Jared Baxter / Mbed 2 deprecated Impedance_Fast_Circuitry_print_V_I

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Dependencies:   mbed-dsp mbed

Fork of Impedance_Fast_Circuitry by Jared Baxter

dma.cpp@41:3e0623d81b9a, 2015-01-30 (annotated)

Committer:
timmey9
Date:
Fri Jan 30 06:59:19 2015 +0000
Revision:
41:3e0623d81b9a
Parent:
40:bd6d8c35e822
Child:
42:52a92a8d2cc7
Added DMA class.  Made changes to ADC.  This code still needs to be tested.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
timmey9 34:44cc9b76a507 1 /*
timmey9 34:44cc9b76a507 2 * dma.c
timmey9 34:44cc9b76a507 3 *
timmey9 34:44cc9b76a507 4 * Created on: Nov 25, 2014
timmey9 34:44cc9b76a507 5 * Author: Manuel Alejandro
timmey9 34:44cc9b76a507 6 */
timmey9 34:44cc9b76a507 7 #include "dma.h"
timmey9 34:44cc9b76a507 8
timmey9 34:44cc9b76a507 9 /* dma_init()
timmey9 34:44cc9b76a507 10 * Initializes the DMA module to read the ADC results every time a conversion has
timmey9 34:44cc9b76a507 11 * finished and stores its value in a buffer
timmey9 34:44cc9b76a507 12 *
timmey9 36:07d8a3143967 13 * @array0 = destination where DMA0 writes
timmey9 36:07d8a3143967 14 * @array1 = destination where DMA1 writes
timmey9 36:07d8a3143967 15 * @array2 = destination where DMA2 writes
timmey9 36:07d8a3143967 16 * @len = the length of array1 and array2, and the number of reads the DMA completes
timmey9 34:44cc9b76a507 17 * */
timmey9 34:44cc9b76a507 18
timmey9 41:3e0623d81b9a 19 DMA::DMA(uint16_t* sample_array1, uint16_t* sample_array2, uint16_t* sample_array3,int len, int* relative_angle)
timmey9 34:44cc9b76a507 20 {
timmey9 41:3e0623d81b9a 21 _array1 = sample_array1;
timmey9 41:3e0623d81b9a 22 _array2 = sample_array2;
timmey9 41:3e0623d81b9a 23 _array3 = sample_array3;
timmey9 41:3e0623d81b9a 24 _len = len;
timmey9 41:3e0623d81b9a 25 _angle = relative_angle;
timmey9 41:3e0623d81b9a 26 init();
timmey9 41:3e0623d81b9a 27 }
timmey9 41:3e0623d81b9a 28
timmey9 41:3e0623d81b9a 29
timmey9 41:3e0623d81b9a 30 void DMA::init()
timmey9 41:3e0623d81b9a 31 {
timmey9 36:07d8a3143967 32 // select round-robin arbitration priority
timmey9 36:07d8a3143967 33 DMA_CR |= DMA_CR_ERCA_MASK;
timmey9 36:07d8a3143967 34
timmey9 34:44cc9b76a507 35 // Enable clock for DMAMUX and DMA
timmey9 34:44cc9b76a507 36 SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
timmey9 34:44cc9b76a507 37 SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
timmey9 34:44cc9b76a507 38
timmey9 34:44cc9b76a507 39 // Enable Channel 0 and set ADC0 as DMA request source
timmey9 36:07d8a3143967 40 DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(40); // see page 95 of user manual
timmey9 36:07d8a3143967 41 DMAMUX_CHCFG1 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(41);
timmey9 37:8bdc71f3e874 42 //DMAMUX_CHCFG2 |= DMAMUX_CHCFG_ENBL_MASK |
timmey9 36:07d8a3143967 43
timmey9 36:07d8a3143967 44
timmey9 34:44cc9b76a507 45 // Enable request signal for channel 0
timmey9 36:07d8a3143967 46 DMA_ERQ = DMA_ERQ_ERQ0_MASK | DMA_ERQ_ERQ1_MASK | DMA_ERQ_ERQ2_MASK;
timmey9 34:44cc9b76a507 47
timmey9 36:07d8a3143967 48 // Set memory address for source and destination for DMA0, DMA1, and DMA2
timmey9 34:44cc9b76a507 49 DMA_TCD0_SADDR = (uint32_t)&ADC0_RA;
timmey9 41:3e0623d81b9a 50 DMA_TCD0_DADDR = (uint32_t) _array1;
timmey9 36:07d8a3143967 51 DMA_TCD1_SADDR = (uint32_t)&ADC1_RA;
timmey9 41:3e0623d81b9a 52 DMA_TCD1_DADDR = (uint32_t) _array2;
timmey9 41:3e0623d81b9a 53 DMA_TCD2_SADDR = (uint32_t) _angle;
timmey9 41:3e0623d81b9a 54 DMA_TCD2_DADDR = (uint32_t) _array3;
timmey9 36:07d8a3143967 55
timmey9 34:44cc9b76a507 56 // Set an offset for source and destination address
timmey9 34:44cc9b76a507 57 DMA_TCD0_SOFF = 0x00; // Source address offset of 2 bits per transaction
timmey9 34:44cc9b76a507 58 DMA_TCD0_DOFF = 0x02; // Destination address offset of 1 bit per transaction
timmey9 36:07d8a3143967 59 DMA_TCD1_SOFF = 0x00; // Source address offset of 2 bits per transaction
timmey9 36:07d8a3143967 60 DMA_TCD1_DOFF = 0x02; // Destination address offset of 1 bit per transaction
timmey9 36:07d8a3143967 61 DMA_TCD2_SOFF = 0x00; // Source address offset of 2 bits per transaction
timmey9 36:07d8a3143967 62 DMA_TCD2_DOFF = 0x02; // Destination address offset of 1 bit per transaction
timmey9 34:44cc9b76a507 63
timmey9 34:44cc9b76a507 64 // Set source and destination data transfer size
timmey9 34:44cc9b76a507 65 DMA_TCD0_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 36:07d8a3143967 66 DMA_TCD1_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 36:07d8a3143967 67 DMA_TCD2_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 34:44cc9b76a507 68
timmey9 34:44cc9b76a507 69 // Number of bytes to be transfered in each service request of the channel
timmey9 34:44cc9b76a507 70 DMA_TCD0_NBYTES_MLNO = 0x02;
timmey9 36:07d8a3143967 71 DMA_TCD1_NBYTES_MLNO = 0x02;
timmey9 36:07d8a3143967 72 DMA_TCD2_NBYTES_MLNO = 0x02;
timmey9 34:44cc9b76a507 73
timmey9 34:44cc9b76a507 74 // Current major iteration count (a single iteration of 5 bytes)
timmey9 41:3e0623d81b9a 75 DMA_TCD0_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(_len);
timmey9 41:3e0623d81b9a 76 DMA_TCD0_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(_len);
timmey9 41:3e0623d81b9a 77 DMA_TCD1_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(_len);
timmey9 41:3e0623d81b9a 78 DMA_TCD1_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(_len);
timmey9 41:3e0623d81b9a 79 DMA_TCD2_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(_len);
timmey9 41:3e0623d81b9a 80 DMA_TCD2_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(_len);
timmey9 34:44cc9b76a507 81
timmey9 34:44cc9b76a507 82 // Adjustment value used to restore the source and destiny address to the initial value
timmey9 36:07d8a3143967 83 // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the address of 'array0')
timmey9 34:44cc9b76a507 84 DMA_TCD0_SLAST = 0x00; // Source address adjustment
timmey9 41:3e0623d81b9a 85 DMA_TCD0_DLASTSGA = -(_len*2); // Destination address adjustment
timmey9 36:07d8a3143967 86 DMA_TCD1_SLAST = 0x00; // Source address adjustment
timmey9 41:3e0623d81b9a 87 DMA_TCD1_DLASTSGA = -(_len*2); // Destination address adjustment
timmey9 36:07d8a3143967 88 DMA_TCD2_SLAST = 0x00; // Source address adjustment
timmey9 41:3e0623d81b9a 89 DMA_TCD2_DLASTSGA = -(_len*2); // Destination address adjustment
timmey9 34:44cc9b76a507 90
timmey9 34:44cc9b76a507 91 // Setup control and status register
timmey9 34:44cc9b76a507 92 DMA_TCD0_CSR = 0;
timmey9 36:07d8a3143967 93 DMA_TCD1_CSR = 0;
timmey9 36:07d8a3143967 94 DMA_TCD2_CSR = 1;
timmey9 39:82dc3daecf32 95
timmey9 40:bd6d8c35e822 96 /*pc.printf("DMA_CR: %08x\r\n", DMA_CR);
timmey9 39:82dc3daecf32 97 pc.printf("DMA_ES: %08x\r\n", DMA_ES);
timmey9 39:82dc3daecf32 98 pc.printf("DMA_ERQ: %08x\r\n", DMA_ERQ);
timmey9 39:82dc3daecf32 99 pc.printf("DMA_EEI: %08x\r\n", DMA_EEI);
timmey9 39:82dc3daecf32 100 pc.printf("DMA_CEEI: %02x\r\n", DMA_CEEI);
timmey9 39:82dc3daecf32 101 pc.printf("DMA_SEEI: %02x\r\n", DMA_SEEI);
timmey9 39:82dc3daecf32 102 pc.printf("DMA_CERQ: %02x\r\n", DMA_CERQ);
timmey9 39:82dc3daecf32 103 pc.printf("DMA_SERQ: %02x\r\n", DMA_SERQ);
timmey9 39:82dc3daecf32 104 pc.printf("DMA_CDNE: %02x\r\n", DMA_CDNE);
timmey9 39:82dc3daecf32 105 pc.printf("DMA_SSRT: %02x\r\n", DMA_SSRT);
timmey9 39:82dc3daecf32 106 pc.printf("DMA_CERR: %02x\r\n", DMA_CERR);
timmey9 39:82dc3daecf32 107 pc.printf("DMA_CINT: %02x\r\n", DMA_CINT);
timmey9 39:82dc3daecf32 108 pc.printf("DMA_INT: %08x\r\n", DMA_INT);
timmey9 39:82dc3daecf32 109 pc.printf("DMA_ERR: %08x\r\n", DMA_ERR);
timmey9 40:bd6d8c35e822 110 pc.printf("DMA_HRS: %08x\r\n", DMA_HRS);*/
timmey9 34:44cc9b76a507 111 }
timmey9 40:bd6d8c35e822 112
timmey9 41:3e0623d81b9a 113 void DMA::reset() {
timmey9 40:bd6d8c35e822 114 // Set memory address for destinations back to the beginning
timmey9 41:3e0623d81b9a 115 init();
timmey9 40:bd6d8c35e822 116 }