Jared Baxter / Mbed 2 deprecated Impedance_Fast_Circuitry

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Dependencies:   mbed-dsp mbed

Fork of DSP_200kHz by Mazzeo Research Group

dma.cpp@36:07d8a3143967, 2015-01-25 (annotated)

Committer:
timmey9
Date:
Sun Jan 25 09:10:24 2015 +0000
Revision:
36:07d8a3143967
Parent:
35:df40c4566826
Child:
37:8bdc71f3e874
DMA0 and DMA1 are working.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
timmey9 34:44cc9b76a507 1 /*
timmey9 34:44cc9b76a507 2 * dma.c
timmey9 34:44cc9b76a507 3 *
timmey9 34:44cc9b76a507 4 * Created on: Nov 25, 2014
timmey9 34:44cc9b76a507 5 * Author: Manuel Alejandro
timmey9 34:44cc9b76a507 6 */
timmey9 34:44cc9b76a507 7 #include "dma.h"
timmey9 34:44cc9b76a507 8
timmey9 34:44cc9b76a507 9 /* dma_init()
timmey9 34:44cc9b76a507 10 * Initializes the DMA module to read the ADC results every time a conversion has
timmey9 34:44cc9b76a507 11 * finished and stores its value in a buffer
timmey9 34:44cc9b76a507 12 *
timmey9 36:07d8a3143967 13 * @array0 = destination where DMA0 writes
timmey9 36:07d8a3143967 14 * @array1 = destination where DMA1 writes
timmey9 36:07d8a3143967 15 * @array2 = destination where DMA2 writes
timmey9 36:07d8a3143967 16 * @len = the length of array1 and array2, and the number of reads the DMA completes
timmey9 34:44cc9b76a507 17 * */
timmey9 34:44cc9b76a507 18
timmey9 36:07d8a3143967 19 void dma_init(uint16_t* array0, uint16_t* array1, uint16_t* array2, int len)
timmey9 34:44cc9b76a507 20 {
timmey9 36:07d8a3143967 21 // select round-robin arbitration priority
timmey9 36:07d8a3143967 22 DMA_CR |= DMA_CR_ERCA_MASK;
timmey9 36:07d8a3143967 23
timmey9 34:44cc9b76a507 24 // Enable clock for DMAMUX and DMA
timmey9 34:44cc9b76a507 25 SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
timmey9 34:44cc9b76a507 26 SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
timmey9 34:44cc9b76a507 27
timmey9 34:44cc9b76a507 28 // Enable Channel 0 and set ADC0 as DMA request source
timmey9 36:07d8a3143967 29 DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(40); // see page 95 of user manual
timmey9 36:07d8a3143967 30 DMAMUX_CHCFG1 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(41);
timmey9 36:07d8a3143967 31 DMAMUX_CHCFG2 |= DMAMUX_CHCFG_ENBL_MASK |
timmey9 36:07d8a3143967 32
timmey9 36:07d8a3143967 33
timmey9 34:44cc9b76a507 34 // Enable request signal for channel 0
timmey9 36:07d8a3143967 35 DMA_ERQ = DMA_ERQ_ERQ0_MASK | DMA_ERQ_ERQ1_MASK | DMA_ERQ_ERQ2_MASK;
timmey9 34:44cc9b76a507 36
timmey9 36:07d8a3143967 37 // Set memory address for source and destination for DMA0, DMA1, and DMA2
timmey9 34:44cc9b76a507 38 DMA_TCD0_SADDR = (uint32_t)&ADC0_RA;
timmey9 36:07d8a3143967 39 DMA_TCD0_DADDR = (uint32_t) array0;
timmey9 36:07d8a3143967 40 DMA_TCD1_SADDR = (uint32_t)&ADC1_RA;
timmey9 36:07d8a3143967 41 DMA_TCD1_DADDR = (uint32_t) array1;
timmey9 36:07d8a3143967 42 DMA_TCD2_SADDR = (uint32_t)&rotary_count;
timmey9 36:07d8a3143967 43 DMA_TCD2_DADDR = (uint32_t) array2;
timmey9 36:07d8a3143967 44
timmey9 34:44cc9b76a507 45 // Set an offset for source and destination address
timmey9 34:44cc9b76a507 46 DMA_TCD0_SOFF = 0x00; // Source address offset of 2 bits per transaction
timmey9 34:44cc9b76a507 47 DMA_TCD0_DOFF = 0x02; // Destination address offset of 1 bit per transaction
timmey9 36:07d8a3143967 48 DMA_TCD1_SOFF = 0x00; // Source address offset of 2 bits per transaction
timmey9 36:07d8a3143967 49 DMA_TCD1_DOFF = 0x02; // Destination address offset of 1 bit per transaction
timmey9 36:07d8a3143967 50 DMA_TCD2_SOFF = 0x00; // Source address offset of 2 bits per transaction
timmey9 36:07d8a3143967 51 DMA_TCD2_DOFF = 0x02; // Destination address offset of 1 bit per transaction
timmey9 34:44cc9b76a507 52
timmey9 34:44cc9b76a507 53 // Set source and destination data transfer size
timmey9 34:44cc9b76a507 54 DMA_TCD0_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 36:07d8a3143967 55 DMA_TCD1_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 36:07d8a3143967 56 DMA_TCD2_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 34:44cc9b76a507 57
timmey9 34:44cc9b76a507 58 // Number of bytes to be transfered in each service request of the channel
timmey9 34:44cc9b76a507 59 DMA_TCD0_NBYTES_MLNO = 0x02;
timmey9 36:07d8a3143967 60 DMA_TCD1_NBYTES_MLNO = 0x02;
timmey9 36:07d8a3143967 61 DMA_TCD2_NBYTES_MLNO = 0x02;
timmey9 34:44cc9b76a507 62
timmey9 34:44cc9b76a507 63 // Current major iteration count (a single iteration of 5 bytes)
timmey9 35:df40c4566826 64 DMA_TCD0_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
timmey9 35:df40c4566826 65 DMA_TCD0_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
timmey9 36:07d8a3143967 66 DMA_TCD1_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
timmey9 36:07d8a3143967 67 DMA_TCD1_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
timmey9 36:07d8a3143967 68 DMA_TCD2_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
timmey9 36:07d8a3143967 69 DMA_TCD2_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
timmey9 34:44cc9b76a507 70
timmey9 34:44cc9b76a507 71 // Adjustment value used to restore the source and destiny address to the initial value
timmey9 36:07d8a3143967 72 // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the address of 'array0')
timmey9 34:44cc9b76a507 73 DMA_TCD0_SLAST = 0x00; // Source address adjustment
timmey9 35:df40c4566826 74 DMA_TCD0_DLASTSGA = -(len*2); // Destination address adjustment
timmey9 36:07d8a3143967 75 DMA_TCD1_SLAST = 0x00; // Source address adjustment
timmey9 36:07d8a3143967 76 DMA_TCD1_DLASTSGA = -(len*2); // Destination address adjustment
timmey9 36:07d8a3143967 77 DMA_TCD2_SLAST = 0x00; // Source address adjustment
timmey9 36:07d8a3143967 78 DMA_TCD2_DLASTSGA = -(len*2); // Destination address adjustment
timmey9 34:44cc9b76a507 79
timmey9 34:44cc9b76a507 80 // Setup control and status register
timmey9 34:44cc9b76a507 81 DMA_TCD0_CSR = 0;
timmey9 36:07d8a3143967 82 DMA_TCD1_CSR = 0;
timmey9 36:07d8a3143967 83 DMA_TCD2_CSR = 1;
timmey9 34:44cc9b76a507 84 }