Diff: dma.cpp

Revision:

36:07d8a3143967

Parent:

35:df40c4566826

Child:

37:8bdc71f3e874

--- a/dma.cpp	Sun Jan 25 06:32:11 2015 +0000
+++ b/dma.cpp	Sun Jan 25 09:10:24 2015 +0000
@@ -10,45 +10,75 @@
  * Initializes the DMA module to read the ADC results every time a conversion has
  * finished and stores its value in a buffer
  * 
- * @buffer = destination where DMA writes
- * @adc_reads = the length of buffer and the number of reads the DMA completes
+ * @array0 = destination where DMA0 writes
+ * @array1 = destination where DMA1 writes
+ * @array2 = destination where DMA2 writes
+ * @len = the length of array1 and array2, and the number of reads the DMA completes
  * */
  
-void dma_init(uint16_t* buffer,int len)
+void dma_init(uint16_t* array0, uint16_t* array1, uint16_t* array2, int len)
 {
+    // select round-robin arbitration priority
+    DMA_CR |= DMA_CR_ERCA_MASK;
+    
     // Enable clock for DMAMUX and DMA
     SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
     SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;    
             
     // Enable Channel 0 and set ADC0 as DMA request source 
-    DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(40);
-
+    DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(40); // see page 95 of user manual
+    DMAMUX_CHCFG1 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(41);
+    DMAMUX_CHCFG2 |= DMAMUX_CHCFG_ENBL_MASK | 
+    
+    
     // Enable request signal for channel 0 
-    DMA_ERQ = DMA_ERQ_ERQ0_MASK;
+    DMA_ERQ = DMA_ERQ_ERQ0_MASK | DMA_ERQ_ERQ1_MASK | DMA_ERQ_ERQ2_MASK;
         
-    // Set memory address for source and destination 
+    // Set memory address for source and destination for DMA0, DMA1, and DMA2
     DMA_TCD0_SADDR = (uint32_t)&ADC0_RA;
-    DMA_TCD0_DADDR = (uint32_t) buffer;
-
+    DMA_TCD0_DADDR = (uint32_t) array0;
+    DMA_TCD1_SADDR = (uint32_t)&ADC1_RA;
+    DMA_TCD1_DADDR = (uint32_t) array1;
+    DMA_TCD2_SADDR = (uint32_t)&rotary_count;
+    DMA_TCD2_DADDR = (uint32_t) array2;
+    
     // Set an offset for source and destination address
     DMA_TCD0_SOFF = 0x00; // Source address offset of 2 bits per transaction
     DMA_TCD0_DOFF = 0x02; // Destination address offset of 1 bit per transaction
+    DMA_TCD1_SOFF = 0x00; // Source address offset of 2 bits per transaction
+    DMA_TCD1_DOFF = 0x02; // Destination address offset of 1 bit per transaction
+    DMA_TCD2_SOFF = 0x00; // Source address offset of 2 bits per transaction
+    DMA_TCD2_DOFF = 0x02; // Destination address offset of 1 bit per transaction
         
     // Set source and destination data transfer size
     DMA_TCD0_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
+    DMA_TCD1_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
+    DMA_TCD2_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
         
     // Number of bytes to be transfered in each service request of the channel
     DMA_TCD0_NBYTES_MLNO = 0x02;
+    DMA_TCD1_NBYTES_MLNO = 0x02;
+    DMA_TCD2_NBYTES_MLNO = 0x02;
         
     // Current major iteration count (a single iteration of 5 bytes)
     DMA_TCD0_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
     DMA_TCD0_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
+    DMA_TCD1_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
+    DMA_TCD1_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
+    DMA_TCD2_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
+    DMA_TCD2_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
     
     // Adjustment value used to restore the source and destiny address to the initial value
-    // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the address of 'buffer')
+    // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the address of 'array0')
     DMA_TCD0_SLAST = 0x00;      // Source address adjustment
     DMA_TCD0_DLASTSGA = -(len*2);  // Destination address adjustment
+    DMA_TCD1_SLAST = 0x00;      // Source address adjustment
+    DMA_TCD1_DLASTSGA = -(len*2);  // Destination address adjustment
+    DMA_TCD2_SLAST = 0x00;      // Source address adjustment
+    DMA_TCD2_DLASTSGA = -(len*2);  // Destination address adjustment
     
     // Setup control and status register
     DMA_TCD0_CSR = 0;
+    DMA_TCD1_CSR = 0;
+    DMA_TCD2_CSR = 1;
 }