Jared Baxter / Mbed 2 deprecated Impedance_Fast_Circuitry

Impedance Fast Circuitry Software

Dependencies:   mbed-dsp mbed

Fork of DSP_200kHz by Mazzeo Research Group

adc.cpp@44:41c262caf898, 2015-01-30 (annotated)

Committer:
timmey9
Date:
Fri Jan 30 14:56:58 2015 +0000
Revision:
44:41c262caf898
Parent:
43:c593a8b9688f
Child:
45:d591d138cdeb
This is before I made changes for posting it online.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
timmey9 39:82dc3daecf32 1 #include "adc.h"
timmey9 40:bd6d8c35e822 2 #include "dma.h"
timmey9 44:41c262caf898 3 /*
timmey9 44:41c262caf898 4 TODO: remove interrupt handlers
timmey9 44:41c262caf898 5 add calibration
timmey9 44:41c262caf898 6 change clock speed (possible with PIT)
timmey9 44:41c262caf898 7
timmey9 44:41c262caf898 8 */
timmey9 40:bd6d8c35e822 9 DigitalOut blah(LED_BLUE);
timmey9 42:52a92a8d2cc7 10 DigitalOut craw(LED_GREEN);
timmey9 40:bd6d8c35e822 11 DigitalOut toggle(PTC16);
timmey9 39:82dc3daecf32 12
timmey9 41:3e0623d81b9a 13 void adc_init(PinName pin)
timmey9 39:82dc3daecf32 14 {
timmey9 39:82dc3daecf32 15 // Turn on the ADC0 and ADC1 clocks
timmey9 39:82dc3daecf32 16 SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK;
timmey9 39:82dc3daecf32 17 SIM_SCGC3 |= SIM_SCGC3_ADC1_MASK;
timmey9 40:bd6d8c35e822 18
timmey9 40:bd6d8c35e822 19 // enable interrupt
timmey9 40:bd6d8c35e822 20 ADC0_SC1A |= ADC_SC1_AIEN_MASK;
timmey9 41:3e0623d81b9a 21 ADC1_SC1A |= ADC_SC1_AIEN_MASK;
timmey9 39:82dc3daecf32 22
timmey9 39:82dc3daecf32 23 // enable the DMA
timmey9 39:82dc3daecf32 24 ADC0->SC2 |= ADC_SC2_DMAEN_MASK;
timmey9 41:3e0623d81b9a 25 ADC1->SC2 |= ADC_SC2_DMAEN_MASK;
timmey9 39:82dc3daecf32 26
timmey9 39:82dc3daecf32 27 // calibrate ADC
timmey9 39:82dc3daecf32 28 ADC0->SC3 = 0; // Reset SC3
timmey9 41:3e0623d81b9a 29 ADC1->SC3 = 0; // Reset SC3
timmey9 39:82dc3daecf32 30 /*do {
timmey9 39:82dc3daecf32 31 ADC0->SC3 |= (1<<7); // start calibration
timmey9 39:82dc3daecf32 32 while(ADC0->SC3&(1<<7)) {} // wait for calibration to complete
timmey9 39:82dc3daecf32 33 if((ADC0->SC3)&(1<<6)) pc.printf("Calibration Failed\r\n");
timmey9 39:82dc3daecf32 34 } while(ADC0->SC3&(1<<6));
timmey9 39:82dc3daecf32 35 */ // the calibration may be failing because ADC0_SC2 has the Vref set to external pins
timmey9 39:82dc3daecf32 36
timmey9 39:82dc3daecf32 37 ADC0->CFG1 |= ADC_CFG1_ADLPC_MASK; // high power mode for faster frequencies
timmey9 41:3e0623d81b9a 38 ADC1->CFG1 |= ADC_CFG1_ADLPC_MASK; // high power mode for faster frequencies
timmey9 39:82dc3daecf32 39
timmey9 39:82dc3daecf32 40 ADCName adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
timmey9 39:82dc3daecf32 41 uint32_t instance = adc >> ADC_INSTANCE_SHIFT;
timmey9 39:82dc3daecf32 42 clock_manager_set_gate(kClockModuleADC, instance, true);
timmey9 39:82dc3daecf32 43 uint32_t bus_clock;
timmey9 39:82dc3daecf32 44 clock_manager_get_frequency(kBusClock, &bus_clock);
timmey9 39:82dc3daecf32 45 uint32_t clkdiv;
timmey9 39:82dc3daecf32 46 for (clkdiv = 0; clkdiv < 4; clkdiv++) {
timmey9 39:82dc3daecf32 47 if ((bus_clock >> clkdiv) <= MAX_FADC)
timmey9 39:82dc3daecf32 48 break;
timmey9 39:82dc3daecf32 49 }
timmey9 39:82dc3daecf32 50 if (clkdiv == 4) {
timmey9 39:82dc3daecf32 51 clkdiv = 0x7; //Set max div
timmey9 39:82dc3daecf32 52 }
timmey9 39:82dc3daecf32 53 // adc is enabled/triggered when reading.
timmey9 39:82dc3daecf32 54 adc_hal_set_clock_source_mode(instance, (adc_clock_source_mode_t)(clkdiv >> 2));
timmey9 39:82dc3daecf32 55 adc_hal_set_clock_divider_mode(instance, (adc_clock_divider_mode_t)(clkdiv & 0x3));
timmey9 39:82dc3daecf32 56 adc_hal_set_reference_voltage_mode(instance, kAdcVoltageVref);
timmey9 39:82dc3daecf32 57 adc_hal_set_resolution_mode(instance, kAdcSingleDiff16);
timmey9 43:c593a8b9688f 58 adc_hal_configure_continuous_conversion(instance, false); // true=continuous conversion mode, false = single conversion mode
timmey9 40:bd6d8c35e822 59 adc_hal_configure_hw_trigger(instance, false); // true=hw trigger, false=sw trigger
timmey9 39:82dc3daecf32 60 adc_hal_configure_hw_average(instance, false);
timmey9 39:82dc3daecf32 61 adc_hal_set_hw_average_mode(instance, kAdcHwAverageCount4);
timmey9 39:82dc3daecf32 62 adc_hal_set_group_mux(instance, kAdcChannelMuxB); // only B channels are avail
timmey9 39:82dc3daecf32 63
timmey9 39:82dc3daecf32 64 pinmap_pinout(pin, PinMap_ADC);
timmey9 41:3e0623d81b9a 65 /*
timmey9 39:82dc3daecf32 66 pc.printf("ADC0_SC1a: %08x\r\n",ADC0_SC1A); // module disabled
timmey9 39:82dc3daecf32 67 pc.printf("ADC0_SC1b: %08x\r\n",ADC0_SC1B); // module disabled
timmey9 39:82dc3daecf32 68 pc.printf("ADC0_CFG1: %08x\r\n",ADC0_CFG1); // alternate clock2 selected, 16-bit 2's complement selected, short sample time, clock divide ration is input/8, low power mode selected
timmey9 39:82dc3daecf32 69 pc.printf("ADC0_CFG2: %08x\r\n",ADC0_CFG2); // ADxxa channels selected
timmey9 39:82dc3daecf32 70 pc.printf("ADC0_RA: %08x\r\n",ADC0_RA);
timmey9 39:82dc3daecf32 71 pc.printf("ADC0_RB: %08x\r\n",ADC0_RB);
timmey9 39:82dc3daecf32 72 pc.printf("ADC0_SC2: %08x\r\n",ADC0_SC2); // hw trigger and dma enabled. Compare function disabled and Vref set to external pin
timmey9 39:82dc3daecf32 73 pc.printf("ADC0_SC3: %08x\r\n\n",ADC0_SC3);
timmey9 41:3e0623d81b9a 74 */
timmey9 40:bd6d8c35e822 75 // Enable the ISR vector
timmey9 41:3e0623d81b9a 76 NVIC_SetVector(ADC0_IRQn, (uint32_t)&ADC0_IRQHandler);
timmey9 41:3e0623d81b9a 77 NVIC_SetVector(ADC1_IRQn, (uint32_t)&ADC1_IRQHandler);
timmey9 40:bd6d8c35e822 78 NVIC_EnableIRQ(ADC0_IRQn);
timmey9 41:3e0623d81b9a 79 NVIC_EnableIRQ(ADC1_IRQn);
timmey9 40:bd6d8c35e822 80 }
timmey9 40:bd6d8c35e822 81
timmey9 41:3e0623d81b9a 82 void adc_start() {
timmey9 40:bd6d8c35e822 83 // reset DMA
timmey9 42:52a92a8d2cc7 84 dma.reset();
timmey9 40:bd6d8c35e822 85
timmey9 40:bd6d8c35e822 86 // set ADC to continuous mode
timmey9 40:bd6d8c35e822 87 ADC0_SC3 |= ADC_SC3_ADCO_MASK;
timmey9 41:3e0623d81b9a 88 ADC1_SC3 |= ADC_SC3_ADCO_MASK;
timmey9 40:bd6d8c35e822 89
timmey9 40:bd6d8c35e822 90 // start ADC conversion (SW trigger)
timmey9 42:52a92a8d2cc7 91 BW_ADC_SC1n_ADCH(0, 0, kAdcChannel13); // This corresponds to starting an ADC conversion on channel 12 of ADC 0 - which is A0 (PTB2)
timmey9 41:3e0623d81b9a 92 BW_ADC_SC1n_ADCH(1, 0, kAdcChannel14); // This corresponds to starting an ADC conversion on channel 14 of ADC 1 - which is A2 (PTB10)
timmey9 40:bd6d8c35e822 93 }
timmey9 40:bd6d8c35e822 94
timmey9 41:3e0623d81b9a 95 void adc_stop() {
timmey9 40:bd6d8c35e822 96 ADC0_SC3 &= ~ADC_SC3_ADCO_MASK; // set to single conversion mode effectively stopping the ADC
timmey9 41:3e0623d81b9a 97 ADC1_SC3 &= ~ADC_SC3_ADCO_MASK; // set to single conversion mode effectively stopping the ADC
timmey9 40:bd6d8c35e822 98 }
timmey9 40:bd6d8c35e822 99
timmey9 40:bd6d8c35e822 100 void ADC0_IRQHandler() {
timmey9 41:3e0623d81b9a 101 //toggle = !toggle;
timmey9 42:52a92a8d2cc7 102 //craw = !craw;
timmey9 41:3e0623d81b9a 103 }
timmey9 41:3e0623d81b9a 104 void ADC1_IRQHandler() {
timmey9 41:3e0623d81b9a 105 //toggle = !toggle;
timmey9 42:52a92a8d2cc7 106 //blah = !blah;
timmey9 39:82dc3daecf32 107 }