Jared Baxter / Mbed 2 deprecated Impedance_Fast_Circuitry

Dependencies:   mbed-dsp mbed

Fork of DSP_200kHz by Mazzeo Research Group

adc.cpp@39:82dc3daecf32, 2015-01-29 (annotated)

Committer:
timmey9
Date:
Thu Jan 29 16:18:54 2015 +0000
Revision:
39:82dc3daecf32
Child:
40:bd6d8c35e822
Cleaned up the code.  PDB still won't work.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
timmey9 39:82dc3daecf32 1 #include "adc.h"
timmey9 39:82dc3daecf32 2
timmey9 39:82dc3daecf32 3 void analog_initialization(PinName pin, Serial &pc)
timmey9 39:82dc3daecf32 4 {
timmey9 39:82dc3daecf32 5
timmey9 39:82dc3daecf32 6 // Turn on the ADC0 and ADC1 clocks
timmey9 39:82dc3daecf32 7 SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK;
timmey9 39:82dc3daecf32 8 SIM_SCGC3 |= SIM_SCGC3_ADC1_MASK;
timmey9 39:82dc3daecf32 9
timmey9 39:82dc3daecf32 10 ADC0->CFG1 |= ADC_CFG1_ADLPC_MASK; // high power mode for faster frequencies
timmey9 39:82dc3daecf32 11
timmey9 39:82dc3daecf32 12 // Configure System Integration Module for defaults as far as ADC
timmey9 39:82dc3daecf32 13 SIM_SOPT7 &= ~(SIM_SOPT7_ADC1ALTTRGEN_MASK | // selects PDB not ALT trigger
timmey9 39:82dc3daecf32 14 SIM_SOPT7_ADC1PRETRGSEL_MASK |
timmey9 39:82dc3daecf32 15 SIM_SOPT7_ADC0ALTTRGEN_MASK | // selects PDB not ALT trigger
timmey9 39:82dc3daecf32 16 SIM_SOPT7_ADC0ALTTRGEN_MASK) ;
timmey9 39:82dc3daecf32 17 SIM_SOPT7 = SIM_SOPT7_ADC0TRGSEL(0); // applies only in case of ALT trigger, in which case PDB external pin input trigger for ADC
timmey9 39:82dc3daecf32 18 SIM_SOPT7 = SIM_SOPT7_ADC1TRGSEL(0); // same for both ADCs
timmey9 39:82dc3daecf32 19
timmey9 39:82dc3daecf32 20 // enable the DMA
timmey9 39:82dc3daecf32 21 ADC0->SC2 |= ADC_SC2_DMAEN_MASK;
timmey9 39:82dc3daecf32 22 //ADC1->SC2 |= ADC_SC2_DMAEN_MASK;
timmey9 39:82dc3daecf32 23
timmey9 39:82dc3daecf32 24 // calibrate ADC
timmey9 39:82dc3daecf32 25 ADC0->SC3 = 0; // Reset SC3
timmey9 39:82dc3daecf32 26 //ADC1->SC3 = 0; // Reset SC3
timmey9 39:82dc3daecf32 27 /*do {
timmey9 39:82dc3daecf32 28 ADC0->SC3 |= (1<<7); // start calibration
timmey9 39:82dc3daecf32 29 while(ADC0->SC3&(1<<7)) {} // wait for calibration to complete
timmey9 39:82dc3daecf32 30 if((ADC0->SC3)&(1<<6)) pc.printf("Calibration Failed\r\n");
timmey9 39:82dc3daecf32 31 } while(ADC0->SC3&(1<<6));
timmey9 39:82dc3daecf32 32 */ // the calibration may be failing because ADC0_SC2 has the Vref set to external pins
timmey9 39:82dc3daecf32 33
timmey9 39:82dc3daecf32 34 ADC0->CFG1 |= ADC_CFG1_ADLPC_MASK; // high power mode for faster frequencies
timmey9 39:82dc3daecf32 35
timmey9 39:82dc3daecf32 36
timmey9 39:82dc3daecf32 37
timmey9 39:82dc3daecf32 38
timmey9 39:82dc3daecf32 39 ADCName adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
timmey9 39:82dc3daecf32 40 // MBED_ASSERT(adc != (ADCName)NC);
timmey9 39:82dc3daecf32 41
timmey9 39:82dc3daecf32 42 uint32_t instance = adc >> ADC_INSTANCE_SHIFT;
timmey9 39:82dc3daecf32 43
timmey9 39:82dc3daecf32 44 clock_manager_set_gate(kClockModuleADC, instance, true);
timmey9 39:82dc3daecf32 45
timmey9 39:82dc3daecf32 46 uint32_t bus_clock;
timmey9 39:82dc3daecf32 47 clock_manager_get_frequency(kBusClock, &bus_clock);
timmey9 39:82dc3daecf32 48 uint32_t clkdiv;
timmey9 39:82dc3daecf32 49 for (clkdiv = 0; clkdiv < 4; clkdiv++) {
timmey9 39:82dc3daecf32 50 if ((bus_clock >> clkdiv) <= MAX_FADC)
timmey9 39:82dc3daecf32 51 break;
timmey9 39:82dc3daecf32 52 }
timmey9 39:82dc3daecf32 53 if (clkdiv == 4) {
timmey9 39:82dc3daecf32 54 clkdiv = 0x7; //Set max div
timmey9 39:82dc3daecf32 55 }
timmey9 39:82dc3daecf32 56 // adc is enabled/triggered when reading.
timmey9 39:82dc3daecf32 57 adc_hal_set_clock_source_mode(instance, (adc_clock_source_mode_t)(clkdiv >> 2));
timmey9 39:82dc3daecf32 58 adc_hal_set_clock_divider_mode(instance, (adc_clock_divider_mode_t)(clkdiv & 0x3));
timmey9 39:82dc3daecf32 59 adc_hal_set_reference_voltage_mode(instance, kAdcVoltageVref);
timmey9 39:82dc3daecf32 60 adc_hal_set_resolution_mode(instance, kAdcSingleDiff16);
timmey9 39:82dc3daecf32 61 adc_hal_configure_continuous_conversion(instance, false); // true=continuous conversion mode, false = single conversion mode
timmey9 39:82dc3daecf32 62 adc_hal_configure_hw_trigger(instance, true); // true=hw trigger, false=sw trigger
timmey9 39:82dc3daecf32 63 adc_hal_configure_hw_average(instance, false);
timmey9 39:82dc3daecf32 64 adc_hal_set_hw_average_mode(instance, kAdcHwAverageCount4);
timmey9 39:82dc3daecf32 65 adc_hal_set_group_mux(instance, kAdcChannelMuxB); // only B channels are avail
timmey9 39:82dc3daecf32 66
timmey9 39:82dc3daecf32 67 pinmap_pinout(pin, PinMap_ADC);
timmey9 39:82dc3daecf32 68
timmey9 39:82dc3daecf32 69 pc.printf("ADC0_SC1a: %08x\r\n",ADC0_SC1A); // module disabled
timmey9 39:82dc3daecf32 70 pc.printf("ADC0_SC1b: %08x\r\n",ADC0_SC1B); // module disabled
timmey9 39:82dc3daecf32 71 pc.printf("ADC0_CFG1: %08x\r\n",ADC0_CFG1); // alternate clock2 selected, 16-bit 2's complement selected, short sample time, clock divide ration is input/8, low power mode selected
timmey9 39:82dc3daecf32 72 pc.printf("ADC0_CFG2: %08x\r\n",ADC0_CFG2); // ADxxa channels selected
timmey9 39:82dc3daecf32 73 pc.printf("ADC0_RA: %08x\r\n",ADC0_RA);
timmey9 39:82dc3daecf32 74 pc.printf("ADC0_RB: %08x\r\n",ADC0_RB);
timmey9 39:82dc3daecf32 75 pc.printf("ADC0_SC2: %08x\r\n",ADC0_SC2); // hw trigger and dma enabled. Compare function disabled and Vref set to external pin
timmey9 39:82dc3daecf32 76 pc.printf("ADC0_SC3: %08x\r\n\n",ADC0_SC3);
timmey9 39:82dc3daecf32 77 }