Bavo Van Achte / Mbed 2 deprecated MLX90418_I2C_master

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Dependencies:   mbed libscpi

i2c_mbed_fpga.cpp@31:0475756cede6, 2021-06-10 (annotated)

Committer:
bavovanachte
Date:
Thu Jun 10 13:29:48 2021 +0000
Revision:
31:0475756cede6
Parent:
30:b463e1f3cae3 
Implemented; - Word write; - SPEED aliases

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wuliqunyy 0:fe3c7dde9771 1 #include "mbed.h"
wuliqunyy 0:fe3c7dde9771 2 #include "i2c_mbed_fpga.h"
wuliqunyy 16:a0bfe33f8a4a 3
bavovanachte 30:b463e1f3cae3 4 #define COMM_STATE_I2C_IDLE (1u)
bavovanachte 30:b463e1f3cae3 5
bavovanachte 30:b463e1f3cae3 6 void i2c_mbed_fpga::wait_for_idle_state(void)
bavovanachte 30:b463e1f3cae3 7 {
bavovanachte 30:b463e1f3cae3 8 int comm_state = 0;
bavovanachte 30:b463e1f3cae3 9 do {
bavovanachte 30:b463e1f3cae3 10 int tmp;
bavovanachte 30:b463e1f3cae3 11 this->i2c_word_read_simple(I2C_STATE, &tmp);
bavovanachte 30:b463e1f3cae3 12 comm_state = (tmp & I2C_STATE_COMM_STATE_MASK) >> I2C_STATE_COMM_STATE_OFFSET;
bavovanachte 30:b463e1f3cae3 13 wait_us(500);
bavovanachte 30:b463e1f3cae3 14 } while(comm_state != COMM_STATE_I2C_IDLE);
bavovanachte 30:b463e1f3cae3 15 }
bavovanachte 30:b463e1f3cae3 16
bavovanachte 30:b463e1f3cae3 17
bavovanachte 30:b463e1f3cae3 18 /** i2c read from slave DUT using the command interpreter feature
bavovanachte 30:b463e1f3cae3 19 * retun 0 on success, otherwise fails
bavovanachte 30:b463e1f3cae3 20 *
bavovanachte 30:b463e1f3cae3 21 * @param[in] address 16-bit address to read from
bavovanachte 30:b463e1f3cae3 22 * @param[out] return value Pointer to the value read at address
bavovanachte 30:b463e1f3cae3 23 * @retval 0 Read failed
bavovanachte 30:b463e1f3cae3 24 * @retval 1 Read successful
bavovanachte 30:b463e1f3cae3 25 */
bavovanachte 30:b463e1f3cae3 26 int i2c_mbed_fpga::i2c_word_read_interpreter(int address, int* return_value){
bavovanachte 30:b463e1f3cae3 27 int read_value;
bavovanachte 30:b463e1f3cae3 28 int busy;
bavovanachte 30:b463e1f3cae3 29 int ack = 0;
bavovanachte 30:b463e1f3cae3 30 while(i2c_check_busy_flag()) {
bavovanachte 30:b463e1f3cae3 31 /* Wait for the busy flag to clear */
bavovanachte 30:b463e1f3cae3 32 }
bavovanachte 30:b463e1f3cae3 33 ack += this->i2c_word_write_simple(I2C_CMD_INTERPRETER_ADDRESS, (address | 0x1)); /* Write the address with the LSB set to 1 to indicate a read operation */
bavovanachte 30:b463e1f3cae3 34 wait_us(100);
bavovanachte 30:b463e1f3cae3 35 /* Check if the command is finished by polling the LSB of CMD_INTERPRETER_ADDRESS */
bavovanachte 30:b463e1f3cae3 36 do {
bavovanachte 30:b463e1f3cae3 37 ack += this->i2c_word_read_simple(I2C_CMD_INTERPRETER_ADDRESS, &read_value);
bavovanachte 30:b463e1f3cae3 38 if((read_value & 0x1) == 1u) {
bavovanachte 30:b463e1f3cae3 39 busy = true;
bavovanachte 30:b463e1f3cae3 40 } else {
bavovanachte 30:b463e1f3cae3 41 busy = false;
bavovanachte 30:b463e1f3cae3 42 }
bavovanachte 30:b463e1f3cae3 43 wait_us(100);
bavovanachte 30:b463e1f3cae3 44 }
bavovanachte 30:b463e1f3cae3 45 while(busy == true);
bavovanachte 30:b463e1f3cae3 46
bavovanachte 30:b463e1f3cae3 47 /* We know the read command has finished. Read back the value */
bavovanachte 30:b463e1f3cae3 48 ack += this->i2c_word_read_simple(I2C_CMD_INTERPRETER_DATA, &read_value);
bavovanachte 30:b463e1f3cae3 49 *return_value = read_value;
bavovanachte 30:b463e1f3cae3 50 return (ack == 0) ? 0 : 1;
bavovanachte 30:b463e1f3cae3 51 }
bavovanachte 30:b463e1f3cae3 52
bavovanachte 30:b463e1f3cae3 53
bavovanachte 30:b463e1f3cae3 54 bool i2c_mbed_fpga::i2c_check_busy_flag(void){
bavovanachte 30:b463e1f3cae3 55 bool retval = true;
bavovanachte 30:b463e1f3cae3 56 int tmp;
bavovanachte 30:b463e1f3cae3 57 this->i2c_word_read_simple(I2C_STATUS, &tmp);
bavovanachte 30:b463e1f3cae3 58 if((tmp & I2C_STATUS_COMMAND_BUSY_MASK) == 0u) {
bavovanachte 30:b463e1f3cae3 59 retval = false;
bavovanachte 30:b463e1f3cae3 60 }
bavovanachte 30:b463e1f3cae3 61 return retval;
bavovanachte 30:b463e1f3cae3 62 }
bavovanachte 30:b463e1f3cae3 63
bavovanachte 30:b463e1f3cae3 64 /** i2c read from slave DUT
bavovanachte 30:b463e1f3cae3 65 * retun 0 on success, otherwise fails
bavovanachte 30:b463e1f3cae3 66 *
bavovanachte 30:b463e1f3cae3 67 * @param i2c_master specifies the i2c interface
bavovanachte 30:b463e1f3cae3 68 * @param word is 4byte, first 2bytes as addr, the rest 2bytes to store data
bavovanachte 30:b463e1f3cae3 69 */
bavovanachte 30:b463e1f3cae3 70 int i2c_mbed_fpga::i2c_word_read(char *word){
bavovanachte 30:b463e1f3cae3 71 int ack = 0;
bavovanachte 30:b463e1f3cae3 72 ack = i2c_master.write(I2C_SLAVE_ADDR, word, 1, true); //restart
bavovanachte 30:b463e1f3cae3 73 ack += i2c_master.read(I2C_SLAVE_ADDR, word+1, 2, false); //stop bit
bavovanachte 30:b463e1f3cae3 74 wait_us(100);
bavovanachte 30:b463e1f3cae3 75 return (ack == 0) ? 0 : 1;
bavovanachte 30:b463e1f3cae3 76 }
wuliqunyy 0:fe3c7dde9771 77
wuliqunyy 6:019ab407ac3c 78 /** i2c read from slave DUT
wuliqunyy 6:019ab407ac3c 79 * retun 0 on success, otherwise fails
wuliqunyy 6:019ab407ac3c 80 *
wuliqunyy 6:019ab407ac3c 81 * @param i2c_master specifies the i2c interface
wuliqunyy 6:019ab407ac3c 82 * @param word is 4byte, first 2bytes as addr, the rest 2bytes to store data
wuliqunyy 6:019ab407ac3c 83 */
bavovanachte 27:9118d8c2509b 84 int i2c_mbed_fpga::i2c_word_read_simple(char address, int* return_value){
bavovanachte 27:9118d8c2509b 85 int ack = 0;
bavovanachte 27:9118d8c2509b 86 char value[2];
bavovanachte 27:9118d8c2509b 87 ack = i2c_master.write(I2C_SLAVE_ADDR, &address, 1, true); //restart
bavovanachte 27:9118d8c2509b 88 ack += i2c_master.read(I2C_SLAVE_ADDR, value, 2, false); //stop bit
bavovanachte 27:9118d8c2509b 89 *return_value = (int)value[1] | ((int)value[0] << 8);
bavovanachte 27:9118d8c2509b 90 wait_us(100);
bavovanachte 27:9118d8c2509b 91 return (ack == 0) ? 0 : 1;
bavovanachte 27:9118d8c2509b 92 }
bavovanachte 27:9118d8c2509b 93
wuliqunyy 0:fe3c7dde9771 94 /** i2c write to slave DUT
wuliqunyy 6:019ab407ac3c 95 * ==> one time write, not read back check
wuliqunyy 0:fe3c7dde9771 96 *
wuliqunyy 0:fe3c7dde9771 97 * @param i2c_master specifies the i2c interface
wuliqunyy 0:fe3c7dde9771 98 * @param word is considered as 4byte char data
wuliqunyy 0:fe3c7dde9771 99 */
wuliqunyy 5:daab0e0e67e2 100 int i2c_mbed_fpga::i2c_word_write(char *word){
wuliqunyy 6:019ab407ac3c 101 int ack = 0;
wuliqunyy 14:062850afdf38 102 ack = i2c_master.write(I2C_SLAVE_ADDR, word, 3, false);
wuliqunyy 6:019ab407ac3c 103 return ack;
wuliqunyy 0:fe3c7dde9771 104 }
wuliqunyy 0:fe3c7dde9771 105
bavovanachte 30:b463e1f3cae3 106 /** i2c read from slave DUT
bavovanachte 30:b463e1f3cae3 107 * retun 0 on success, otherwise fails
bavovanachte 30:b463e1f3cae3 108 *
bavovanachte 30:b463e1f3cae3 109 * @param i2c_master specifies the i2c interface
bavovanachte 30:b463e1f3cae3 110 * @param word is 4byte, first 2bytes as addr, the rest 2bytes to store data
bavovanachte 30:b463e1f3cae3 111 */
bavovanachte 30:b463e1f3cae3 112 int i2c_mbed_fpga::i2c_word_write_simple(char address, int value){
bavovanachte 30:b463e1f3cae3 113 int ack = 0;
bavovanachte 30:b463e1f3cae3 114 char i2cMessage[3];
bavovanachte 30:b463e1f3cae3 115 *(i2cMessage+0) = (char)(address)& 0xff;
bavovanachte 30:b463e1f3cae3 116 *(i2cMessage+1) = (char)((value >> 8u) & 0xff);
bavovanachte 30:b463e1f3cae3 117 *(i2cMessage+2) = (char)(value & 0xff);
bavovanachte 30:b463e1f3cae3 118 ack = i2c_word_write(i2cMessage);
bavovanachte 30:b463e1f3cae3 119 wait_us(100);
bavovanachte 30:b463e1f3cae3 120 return ack;
bavovanachte 30:b463e1f3cae3 121 }
bavovanachte 30:b463e1f3cae3 122
bavovanachte 31:0475756cede6 123 int i2c_mbed_fpga::i2c_word_write_interpreter(int address, int value){
bavovanachte 31:0475756cede6 124 int read_value;
bavovanachte 31:0475756cede6 125 int busy;
bavovanachte 31:0475756cede6 126 int ack = 0;
bavovanachte 31:0475756cede6 127 while(i2c_check_busy_flag()) {
bavovanachte 31:0475756cede6 128 /* Wait for the busy flag to clear */
bavovanachte 31:0475756cede6 129 }
bavovanachte 31:0475756cede6 130 ack += this->i2c_word_write_simple(I2C_CMD_INTERPRETER_DATA, value);
bavovanachte 31:0475756cede6 131 ack += this->i2c_word_write_simple(I2C_CMD_INTERPRETER_ADDRESS, (address & 0xFFFE)); /* Write the address with the LSB set to 0 to indicate a write operation */
bavovanachte 31:0475756cede6 132 /* Check if the command is finished by polling the LSB of CMD_INTERPRETER_ADDRESS */
bavovanachte 31:0475756cede6 133 do {
bavovanachte 31:0475756cede6 134 ack += this->i2c_word_read_simple(I2C_CMD_INTERPRETER_ADDRESS, &read_value);
bavovanachte 31:0475756cede6 135 if((read_value & 0x1) == 0u) {
bavovanachte 31:0475756cede6 136 busy = true;
bavovanachte 31:0475756cede6 137 } else {
bavovanachte 31:0475756cede6 138 busy = false;
bavovanachte 31:0475756cede6 139 }
bavovanachte 31:0475756cede6 140 wait_us(100);
bavovanachte 31:0475756cede6 141 }
bavovanachte 31:0475756cede6 142 while(busy == true);
bavovanachte 31:0475756cede6 143 return (ack == 0) ? 0 : 1;
bavovanachte 31:0475756cede6 144 }
bavovanachte 31:0475756cede6 145
bavovanachte 30:b463e1f3cae3 146
wuliqunyy 0:fe3c7dde9771 147
wuliqunyy 16:a0bfe33f8a4a 148 /** i2c enter key to open I2C window (for old releases)
wuliqunyy 0:fe3c7dde9771 149 */
wuliqunyy 15:83bbc18cccbc 150 //int i2c_mbed_fpga::i2c_window_open(){
wuliqunyy 15:83bbc18cccbc 151 // char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 152 // *(i2cMessage+0) = (char)(I2C_CUST_ID3)& 0xff;
wuliqunyy 15:83bbc18cccbc 153 // *(i2cMessage+1) = (char)(0xD0)& 0xff;
wuliqunyy 15:83bbc18cccbc 154 // *(i2cMessage+2) = (char)(0xD0)& 0xff;
wuliqunyy 15:83bbc18cccbc 155 // return i2c_word_write(i2cMessage);
wuliqunyy 15:83bbc18cccbc 156 //}
wuliqunyy 15:83bbc18cccbc 157
wuliqunyy 16:a0bfe33f8a4a 158 /** i2c enter key to Start the motor (for old releases)
wuliqunyy 15:83bbc18cccbc 159 */
wuliqunyy 15:83bbc18cccbc 160 //int i2c_mbed_fpga::i2c_motor_start(){
wuliqunyy 15:83bbc18cccbc 161 // char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 162 // *(i2cMessage+0) = (char)(I2C_CUST_ID3)& 0xff;
wuliqunyy 15:83bbc18cccbc 163 // *(i2cMessage+1) = (char)(0xCA)& 0xff;
wuliqunyy 15:83bbc18cccbc 164 // *(i2cMessage+2) = (char)(0xFE)& 0xff;
wuliqunyy 15:83bbc18cccbc 165 // return i2c_word_write(i2cMessage);
wuliqunyy 15:83bbc18cccbc 166 //}
wuliqunyy 15:83bbc18cccbc 167
wuliqunyy 15:83bbc18cccbc 168
wuliqunyy 15:83bbc18cccbc 169 /** i2c enter key to open I2C configuration mode entry
wuliqunyy 15:83bbc18cccbc 170 */
wuliqunyy 15:83bbc18cccbc 171 int i2c_mbed_fpga::i2c_config_mode_entry(){
wuliqunyy 14:062850afdf38 172 char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 173 *(i2cMessage+0) = (char)(I2C_COMMAND_CONTROL)& 0xff;
wuliqunyy 15:83bbc18cccbc 174 *(i2cMessage+1) = (char)(0x1D)& 0xff;
wuliqunyy 15:83bbc18cccbc 175 *(i2cMessage+2) = (char)(0xEA)& 0xff;
wuliqunyy 14:062850afdf38 176 return i2c_word_write(i2cMessage);
wuliqunyy 0:fe3c7dde9771 177 }
wuliqunyy 0:fe3c7dde9771 178
wuliqunyy 16:a0bfe33f8a4a 179 /** i2c enter MLX key to open I2C MLX configuration mode entry
wuliqunyy 16:a0bfe33f8a4a 180 */
wuliqunyy 16:a0bfe33f8a4a 181 int i2c_mbed_fpga::i2c_mlx_mode_entry(){
wuliqunyy 16:a0bfe33f8a4a 182 int ack = 0;
wuliqunyy 16:a0bfe33f8a4a 183 char i2cMessage[3];
bavovanachte 30:b463e1f3cae3 184 *(i2cMessage+0) = (char)(I2C_COMMAND_KEY)& 0xff;
bavovanachte 30:b463e1f3cae3 185 *(i2cMessage+1) = (char)(0x65)& 0xff;
bavovanachte 30:b463e1f3cae3 186 *(i2cMessage+2) = (char)(0xA9)& 0xff;
bavovanachte 30:b463e1f3cae3 187 ack += i2c_word_write(i2cMessage);
wuliqunyy 16:a0bfe33f8a4a 188 *(i2cMessage+0) = (char)(I2C_COMMAND_CONTROL)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 189 *(i2cMessage+1) = (char)(0x35)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 190 *(i2cMessage+2) = (char)(0x4B)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 191 ack += i2c_word_write(i2cMessage);
wuliqunyy 16:a0bfe33f8a4a 192
wuliqunyy 16:a0bfe33f8a4a 193 return ack;
wuliqunyy 16:a0bfe33f8a4a 194 }
wuliqunyy 16:a0bfe33f8a4a 195
wuliqunyy 16:a0bfe33f8a4a 196
wuliqunyy 15:83bbc18cccbc 197 /** i2c ram start up flag set to skip OTP copy
wuliqunyy 0:fe3c7dde9771 198 */
wuliqunyy 15:83bbc18cccbc 199 int i2c_mbed_fpga::i2c_skip_app_copy(){
wuliqunyy 14:062850afdf38 200 char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 201 *(i2cMessage+0) = (char)(I2C_STARTUP_FLAGS_1)& 0xff;
wuliqunyy 15:83bbc18cccbc 202 *(i2cMessage+1) = (char)(0x05)& 0xff;
wuliqunyy 15:83bbc18cccbc 203 *(i2cMessage+2) = (char)(0x00)& 0xff;
wuliqunyy 14:062850afdf38 204 return i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 205 }
wuliqunyy 12:9f8c7f4da5f6 206
wuliqunyy 15:83bbc18cccbc 207 /** i2c soft reset
wuliqunyy 15:83bbc18cccbc 208 */
wuliqunyy 15:83bbc18cccbc 209 int i2c_mbed_fpga::i2c_soft_reset(){
wuliqunyy 15:83bbc18cccbc 210 char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 211 *(i2cMessage+0) = (char)(I2C_COMMAND_CONTROL)& 0xff;
wuliqunyy 15:83bbc18cccbc 212 *(i2cMessage+1) = (char)(0xC1)& 0xff;
wuliqunyy 15:83bbc18cccbc 213 *(i2cMessage+2) = (char)(0xA0)& 0xff;
wuliqunyy 15:83bbc18cccbc 214 return i2c_word_write(i2cMessage);
wuliqunyy 15:83bbc18cccbc 215 }
wuliqunyy 15:83bbc18cccbc 216
wuliqunyy 15:83bbc18cccbc 217
wuliqunyy 12:9f8c7f4da5f6 218 /** i2c to set the 50k PWM
wuliqunyy 12:9f8c7f4da5f6 219 */
wuliqunyy 12:9f8c7f4da5f6 220 int i2c_mbed_fpga::i2c_set_50k_pwm(unsigned int pwm50k){
wuliqunyy 15:83bbc18cccbc 221 nv_gen_ctrl_val &= ~NV_PWM_50K_MASK;
wuliqunyy 15:83bbc18cccbc 222 nv_gen_ctrl_val |= pwm50k << NV_PWM_50K_OFFSET;
wuliqunyy 14:062850afdf38 223 char i2cMessage[3];
wuliqunyy 14:062850afdf38 224 *(i2cMessage+0) = (char)(I2C_GEN_CTRL >> 0)& 0xff;
wuliqunyy 14:062850afdf38 225 *(i2cMessage+1) = (char)(nv_gen_ctrl_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 226 *(i2cMessage+2) = (char)(nv_gen_ctrl_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 227 return i2c_word_write(i2cMessage);
wuliqunyy 0:fe3c7dde9771 228 }
wuliqunyy 6:019ab407ac3c 229
wuliqunyy 12:9f8c7f4da5f6 230
wuliqunyy 12:9f8c7f4da5f6 231
wuliqunyy 6:019ab407ac3c 232 /** i2c to set the Postion Pulse width
wuliqunyy 6:019ab407ac3c 233 */
wuliqunyy 6:019ab407ac3c 234 int i2c_mbed_fpga::i2c_set_position_pulse_width(unsigned int mantisaa_2b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 235 nv_positin_val &= ~NV_POSITION_PULSE_TIME_MASK;
wuliqunyy 6:019ab407ac3c 236 nv_positin_val |= ((exponent_3b << 2) | mantisaa_2b) << NV_POSITION_PULSE_TIME_OFFSET;
wuliqunyy 14:062850afdf38 237 char i2cMessage[3];
wuliqunyy 14:062850afdf38 238 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 239 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 240 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 241 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 242 }
wuliqunyy 6:019ab407ac3c 243
wuliqunyy 20:26e934452728 244 /** i2c to set the Postion Flat width
wuliqunyy 20:26e934452728 245 */
wuliqunyy 20:26e934452728 246 int i2c_mbed_fpga::i2c_set_position_flat(unsigned int mantisaa_2b, unsigned int exponent_3b){
wuliqunyy 20:26e934452728 247 nv_positin2_val &= ~NV_POSITION_FLAT_TIME_MASK;
wuliqunyy 20:26e934452728 248 nv_positin2_val |= ((exponent_3b << 2) | mantisaa_2b) << NV_POSITION_FLAT_TIME_OFFSET;
wuliqunyy 20:26e934452728 249 char i2cMessage[3];
wuliqunyy 20:26e934452728 250 *(i2cMessage+0) = (char)(I2C_POSITION2 >> 0)& 0xff;
wuliqunyy 20:26e934452728 251 *(i2cMessage+1) = (char)(nv_positin2_val >> 8)& 0xff;
wuliqunyy 20:26e934452728 252 *(i2cMessage+2) = (char)(nv_positin2_val >> 0)& 0xff;
wuliqunyy 20:26e934452728 253 return i2c_word_write(i2cMessage);
wuliqunyy 20:26e934452728 254 }
wuliqunyy 20:26e934452728 255
wuliqunyy 20:26e934452728 256
wuliqunyy 20:26e934452728 257
wuliqunyy 20:26e934452728 258
wuliqunyy 6:019ab407ac3c 259 /** i2c to set the Postion Pulse duty cycle
wuliqunyy 6:019ab407ac3c 260 */
wuliqunyy 6:019ab407ac3c 261 int i2c_mbed_fpga::i2c_set_position_duty(unsigned int duty_2b){
wuliqunyy 6:019ab407ac3c 262 nv_positin_val &= ~NV_POSITION_DUTY_MASK;
wuliqunyy 6:019ab407ac3c 263 nv_positin_val |= duty_2b << NV_POSITION_DUTY_OFFSET;
wuliqunyy 14:062850afdf38 264 char i2cMessage[3];
wuliqunyy 14:062850afdf38 265 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 266 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 267 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 268 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 269 }
wuliqunyy 6:019ab407ac3c 270
wuliqunyy 6:019ab407ac3c 271 /** i2c to enable the Postion Pulse majority volting
wuliqunyy 6:019ab407ac3c 272 */
wuliqunyy 6:019ab407ac3c 273 int i2c_mbed_fpga::i2c_set_position_maj_vote(unsigned int maj_1b){
wuliqunyy 6:019ab407ac3c 274 nv_positin_val &= ~NV_POSI_MAJO_VOTE_MASK;
wuliqunyy 6:019ab407ac3c 275 nv_positin_val |= maj_1b << NV_POSI_MAJO_VOTE_OFFSET;
wuliqunyy 14:062850afdf38 276 char i2cMessage[3];
wuliqunyy 14:062850afdf38 277 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 278 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 279 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 280 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 281 }
wuliqunyy 6:019ab407ac3c 282
wuliqunyy 6:019ab407ac3c 283 /** i2c to set the anti-cogging rotation direction
wuliqunyy 6:019ab407ac3c 284 */
wuliqunyy 6:019ab407ac3c 285 int i2c_mbed_fpga::i2c_set_position_anti_cog(unsigned int cog_1b){
wuliqunyy 6:019ab407ac3c 286 nv_positin_val &= ~NV_ANTI_COG_MASK;
wuliqunyy 6:019ab407ac3c 287 nv_positin_val |= cog_1b << NV_ANTI_COG_OFFSET;
wuliqunyy 14:062850afdf38 288 char i2cMessage[3];
wuliqunyy 14:062850afdf38 289 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 290 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 291 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 292 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 293 }
wuliqunyy 6:019ab407ac3c 294
wuliqunyy 6:019ab407ac3c 295
wuliqunyy 6:019ab407ac3c 296 /** i2c to set the Start Up Pulse width (pulse train)
wuliqunyy 6:019ab407ac3c 297 */
wuliqunyy 6:019ab407ac3c 298 int i2c_mbed_fpga::i2c_set_start_up_pulse_width(unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 299 nv_start_up_val &= ~NV_START_UP_TIME_MASK;
wuliqunyy 8:2554218db1e6 300 nv_start_up_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_START_UP_TIME_OFFSET;
wuliqunyy 14:062850afdf38 301 char i2cMessage[3];
wuliqunyy 14:062850afdf38 302 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 303 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 304 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 305 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 306 }
wuliqunyy 6:019ab407ac3c 307
wuliqunyy 20:26e934452728 308 /** i2c to set the Start Up Flat width
wuliqunyy 20:26e934452728 309 */
wuliqunyy 20:26e934452728 310 int i2c_mbed_fpga::i2c_set_start_up_flat(unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 20:26e934452728 311 nv_positin2_val &= ~NV_START_UP_FLAT_TIME_MASK;
wuliqunyy 20:26e934452728 312 nv_positin2_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_START_UP_FLAT_TIME_OFFSET;
wuliqunyy 20:26e934452728 313 char i2cMessage[3];
wuliqunyy 20:26e934452728 314 *(i2cMessage+0) = (char)(I2C_POSITION2 >> 0)& 0xff;
wuliqunyy 20:26e934452728 315 *(i2cMessage+1) = (char)(nv_positin2_val >> 8)& 0xff;
wuliqunyy 20:26e934452728 316 *(i2cMessage+2) = (char)(nv_positin2_val >> 0)& 0xff;
wuliqunyy 20:26e934452728 317 return i2c_word_write(i2cMessage);
wuliqunyy 20:26e934452728 318 }
wuliqunyy 20:26e934452728 319
wuliqunyy 20:26e934452728 320
wuliqunyy 20:26e934452728 321
wuliqunyy 6:019ab407ac3c 322 /** i2c to set the Start up Pulse duty cycle (pulse train)
wuliqunyy 6:019ab407ac3c 323 */
wuliqunyy 6:019ab407ac3c 324 int i2c_mbed_fpga::i2c_set_start_up_duty(unsigned int duty_2b){
wuliqunyy 6:019ab407ac3c 325 nv_start_up_val &= ~NV_START_DUTY_MASK;
wuliqunyy 6:019ab407ac3c 326 nv_start_up_val |= duty_2b << NV_START_DUTY_OFFSET;
wuliqunyy 14:062850afdf38 327 char i2cMessage[3];
wuliqunyy 14:062850afdf38 328 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 329 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 330 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 331 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 332 }
wuliqunyy 6:019ab407ac3c 333
wuliqunyy 6:019ab407ac3c 334 /** i2c to set the Start up commutation number of EHPs (pulse train)
wuliqunyy 6:019ab407ac3c 335 */
wuliqunyy 6:019ab407ac3c 336 int i2c_mbed_fpga::i2c_set_start_up_num_comm(unsigned int comm){
wuliqunyy 6:019ab407ac3c 337 nv_start_up_val &= ~NV_COMM_START_NUM_MASK;
wuliqunyy 6:019ab407ac3c 338 nv_start_up_val |= comm << NV_COMM_START_NUM_OFFSET;
wuliqunyy 14:062850afdf38 339 char i2cMessage[3];
wuliqunyy 14:062850afdf38 340 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 341 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 342 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 343 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 344 }
wuliqunyy 6:019ab407ac3c 345
wuliqunyy 6:019ab407ac3c 346 /** i2c to set the Soft Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 347 */
wuliqunyy 6:019ab407ac3c 348 int i2c_mbed_fpga::i2c_set_soft_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b, unsigned int step_size, unsigned int num_steps){
wuliqunyy 6:019ab407ac3c 349 int ack = 0;
wuliqunyy 6:019ab407ac3c 350 nv_start_up_val &= ~NV_SOFT_START_MASK;
wuliqunyy 6:019ab407ac3c 351 nv_start_up_val |= enbale << NV_SOFT_START_OFFSET;
wuliqunyy 6:019ab407ac3c 352 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 353 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 6:019ab407ac3c 354 nv_start_up_val &= ~NV_SOFT_STEP_SIZE_MASK;
wuliqunyy 6:019ab407ac3c 355 nv_start_up_val |= step_size << NV_SOFT_STEP_SIZE_OFFSET;
wuliqunyy 6:019ab407ac3c 356 nv_wind_brake_val &= ~NV_SOFT_NUM_STEP_MASK;
wuliqunyy 6:019ab407ac3c 357 nv_wind_brake_val |= num_steps << NV_SOFT_NUM_STEP_OFFSET;
wuliqunyy 14:062850afdf38 358 char i2cMessage[3];
wuliqunyy 14:062850afdf38 359 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 360 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 361 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 362 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 363 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 364 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 365 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 366 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 367 *(i2cMessage+0) = (char)(I2C_WIND_BRAKE >> 0)& 0xff;
wuliqunyy 14:062850afdf38 368 *(i2cMessage+1) = (char)(nv_wind_brake_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 369 *(i2cMessage+2) = (char)(nv_wind_brake_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 370 ack += i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 371
wuliqunyy 6:019ab407ac3c 372 return ack;
wuliqunyy 6:019ab407ac3c 373 }
wuliqunyy 6:019ab407ac3c 374
wuliqunyy 6:019ab407ac3c 375 /** i2c to set the High Torque Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 376 */
wuliqunyy 6:019ab407ac3c 377 int i2c_mbed_fpga::i2c_set_high_torque_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 378 int ack = 0;
wuliqunyy 6:019ab407ac3c 379 nv_start_up_val &= ~NV_LONG_START_MASK;
wuliqunyy 6:019ab407ac3c 380 nv_start_up_val |= enbale << NV_LONG_START_OFFSET;
wuliqunyy 6:019ab407ac3c 381 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 382 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 14:062850afdf38 383 char i2cMessage[3];
wuliqunyy 14:062850afdf38 384 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 385 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 386 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 387 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 388 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 389 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 390 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 391 ack += i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 392
wuliqunyy 6:019ab407ac3c 393 return ack;
wuliqunyy 6:019ab407ac3c 394 }
wuliqunyy 6:019ab407ac3c 395
wuliqunyy 6:019ab407ac3c 396 /** i2c to set the Single Pulse Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 397 */
wuliqunyy 6:019ab407ac3c 398 int i2c_mbed_fpga::i2c_set_single_pulse_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 399 int ack = 0;
wuliqunyy 6:019ab407ac3c 400 nv_start_up_val &= ~NV_SINGLE_PULSE_START_MASK;
wuliqunyy 6:019ab407ac3c 401 nv_start_up_val |= enbale << NV_SINGLE_PULSE_START_OFFSET;
wuliqunyy 6:019ab407ac3c 402 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 403 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 14:062850afdf38 404 char i2cMessage[3];
wuliqunyy 14:062850afdf38 405 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 406 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 407 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 408 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 409 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 410 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 411 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 412 ack += i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 413
wuliqunyy 6:019ab407ac3c 414 return ack;
wuliqunyy 9:76a0b9f29a2d 415 }
wuliqunyy 9:76a0b9f29a2d 416
wuliqunyy 14:062850afdf38 417 /** i2c to set the rough regulation gain
wuliqunyy 12:9f8c7f4da5f6 418 */
wuliqunyy 17:d7207b1132be 419 int i2c_mbed_fpga::i2c_force_rough_reg(unsigned int reg){
wuliqunyy 17:d7207b1132be 420 int ack = 0;
wuliqunyy 17:d7207b1132be 421 nv_gen_ctrl_val &= ~NV_ROUGH_REG_MASK;
wuliqunyy 17:d7207b1132be 422 nv_gen_ctrl_val |= reg << NV_ROUGH_REG_OFFSET;
wuliqunyy 17:d7207b1132be 423 char i2cMessage[3];
wuliqunyy 17:d7207b1132be 424 *(i2cMessage+0)= (char)(I2C_GEN_CTRL >> 0)& 0xff;
wuliqunyy 17:d7207b1132be 425 *(i2cMessage+1)= (char)(nv_gen_ctrl_val >> 8)& 0xff;
wuliqunyy 17:d7207b1132be 426 *(i2cMessage+2)= (char)(nv_gen_ctrl_val >> 0)& 0xff;
wuliqunyy 17:d7207b1132be 427 ack += i2c_word_write(i2cMessage);
wuliqunyy 17:d7207b1132be 428
wuliqunyy 17:d7207b1132be 429 return ack;
wuliqunyy 17:d7207b1132be 430 }
wuliqunyy 17:d7207b1132be 431
wuliqunyy 17:d7207b1132be 432 /** i2c to set the rough regulation gain
wuliqunyy 17:d7207b1132be 433 */
wuliqunyy 12:9f8c7f4da5f6 434 int i2c_mbed_fpga::i2c_set_rough_gain(unsigned int rough_gain){
wuliqunyy 12:9f8c7f4da5f6 435 int ack = 0;
wuliqunyy 12:9f8c7f4da5f6 436 nv_gen_ctrl_val &= ~NV_ROUGH_GAIN_MASK;
wuliqunyy 12:9f8c7f4da5f6 437 nv_gen_ctrl_val |= rough_gain << NV_ROUGH_GAIN_OFFSET;
wuliqunyy 14:062850afdf38 438 char i2cMessage[3];
wuliqunyy 14:062850afdf38 439 *(i2cMessage+0)= (char)(I2C_GEN_CTRL >> 0)& 0xff;
wuliqunyy 14:062850afdf38 440 *(i2cMessage+1)= (char)(nv_gen_ctrl_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 441 *(i2cMessage+2)= (char)(nv_gen_ctrl_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 442 ack += i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 443
wuliqunyy 12:9f8c7f4da5f6 444 return ack;
wuliqunyy 12:9f8c7f4da5f6 445 }
wuliqunyy 12:9f8c7f4da5f6 446
wuliqunyy 14:062850afdf38 447 /** i2c to set the ehp regulation gain
wuliqunyy 14:062850afdf38 448 */
wuliqunyy 14:062850afdf38 449 int i2c_mbed_fpga::i2c_set_ehp_reg_gain(unsigned int ehp_gain){
wuliqunyy 14:062850afdf38 450 int ack = 0;
wuliqunyy 14:062850afdf38 451 nv_gen_ctrl_val &= ~NV_EHP_REG_GAIN_MASK;
wuliqunyy 14:062850afdf38 452 nv_gen_ctrl_val |= ehp_gain << NV_EHP_REG_GAIN_OFFSET;
wuliqunyy 14:062850afdf38 453 char i2cMessage[3];
wuliqunyy 14:062850afdf38 454 *(i2cMessage+0)= (char)(I2C_GEN_CTRL >> 0)& 0xff;
wuliqunyy 14:062850afdf38 455 *(i2cMessage+1)= (char)(nv_gen_ctrl_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 456 *(i2cMessage+2)= (char)(nv_gen_ctrl_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 457 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 458
wuliqunyy 14:062850afdf38 459 return ack;
wuliqunyy 14:062850afdf38 460 }
wuliqunyy 14:062850afdf38 461
wuliqunyy 14:062850afdf38 462 /** i2c to set the ehp regulation gain
wuliqunyy 14:062850afdf38 463 */
wuliqunyy 14:062850afdf38 464 int i2c_mbed_fpga::i2c_set_fall_time_blank(unsigned int blank_time){
wuliqunyy 14:062850afdf38 465 int ack = 0;
wuliqunyy 15:83bbc18cccbc 466 nv_dig_config_val &= ~NV_FLAT_BLANK_MASK;
wuliqunyy 15:83bbc18cccbc 467 nv_dig_config_val |= blank_time << NV_FLAT_BLANK_OFFSET;
wuliqunyy 14:062850afdf38 468 char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 469 *(i2cMessage+0)= (char)(I2C_DIGITAL_CFG >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 470 *(i2cMessage+1)= (char)(nv_dig_config_val >> 8)& 0xff;
wuliqunyy 15:83bbc18cccbc 471 *(i2cMessage+2)= (char)(nv_dig_config_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 472 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 473
wuliqunyy 14:062850afdf38 474 return ack;
wuliqunyy 14:062850afdf38 475 }
wuliqunyy 12:9f8c7f4da5f6 476
wuliqunyy 12:9f8c7f4da5f6 477
wuliqunyy 12:9f8c7f4da5f6 478 /** i2c to set the current threshold for I_didt
wuliqunyy 12:9f8c7f4da5f6 479 */
wuliqunyy 12:9f8c7f4da5f6 480 int i2c_mbed_fpga::i2c_set_comm_i_thres(unsigned int i_thr_low, unsigned int i_thr_high){
wuliqunyy 12:9f8c7f4da5f6 481 int ack = 0;
wuliqunyy 15:83bbc18cccbc 482 nv_i_zc_th_low_val &= ~NV_I_ZC_TH_LOW_MASK;
wuliqunyy 15:83bbc18cccbc 483 nv_i_zc_th_low_val |= i_thr_low << NV_I_ZC_TH_LOW_OFFSET;
wuliqunyy 15:83bbc18cccbc 484 nv_i_zc_th_high_val &= ~NV_I_ZC_TH_HIGH_MASK;
wuliqunyy 15:83bbc18cccbc 485 nv_i_zc_th_high_val |= i_thr_high << NV_I_ZC_TH_HIGH_OFFSET;
wuliqunyy 14:062850afdf38 486 char i2cMessage[3];
wuliqunyy 20:26e934452728 487 *(i2cMessage+0) = (char)(I2C_I_ZC_TH_LOW_REG >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 488 *(i2cMessage+1) = (char)(nv_i_zc_th_low_val >> 8)& 0xff;
wuliqunyy 15:83bbc18cccbc 489 *(i2cMessage+2) = (char)(nv_i_zc_th_low_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 490 ack += i2c_word_write(i2cMessage);
wuliqunyy 20:26e934452728 491 *(i2cMessage+0) = (char)(I2C_I_ZC_TH_HIGH_REG >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 492 *(i2cMessage+1) = (char)(nv_i_zc_th_high_val >> 8)& 0xff;
wuliqunyy 15:83bbc18cccbc 493 *(i2cMessage+2) = (char)(nv_i_zc_th_high_val >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 494 ack += i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 495 return ack;
wuliqunyy 12:9f8c7f4da5f6 496 }
wuliqunyy 12:9f8c7f4da5f6 497
wuliqunyy 12:9f8c7f4da5f6 498 /** i2c to set the di current threshold for didt
wuliqunyy 12:9f8c7f4da5f6 499 */
wuliqunyy 12:9f8c7f4da5f6 500 int i2c_mbed_fpga::i2c_set_comm_di_thres(unsigned int di_1st, unsigned int di_2nd){
wuliqunyy 12:9f8c7f4da5f6 501 int ack = 0;
wuliqunyy 15:83bbc18cccbc 502 nv_di_th_1st_val &= ~NV_DI_TH_1ST_MASK;
wuliqunyy 15:83bbc18cccbc 503 nv_di_th_1st_val |= di_1st << NV_DI_TH_1ST_OFFSET;
wuliqunyy 15:83bbc18cccbc 504 nv_di_th_2nd_val &= ~NV_DI_TH_2ND_MASK;
wuliqunyy 15:83bbc18cccbc 505 nv_di_th_2nd_val |= di_2nd << NV_DI_TH_2ND_OFFSET;
wuliqunyy 14:062850afdf38 506 char i2cMessage[3];
wuliqunyy 20:26e934452728 507 *(i2cMessage+0) = (char)(I2C_DI_TH_1ST_REG >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 508 *(i2cMessage+1) = (char)(nv_di_th_1st_val >> 8)& 0xff;
wuliqunyy 15:83bbc18cccbc 509 *(i2cMessage+2) = (char)(nv_di_th_1st_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 510 ack += i2c_word_write(i2cMessage);
wuliqunyy 20:26e934452728 511 *(i2cMessage+0) = (char)(I2C_DI_TH_2ND_REG >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 512 *(i2cMessage+1) = (char)(nv_di_th_2nd_val >> 8)& 0xff;
wuliqunyy 15:83bbc18cccbc 513 *(i2cMessage+2) = (char)(nv_di_th_2nd_val >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 514 ack += i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 515 return ack;
wuliqunyy 12:9f8c7f4da5f6 516 }
wuliqunyy 12:9f8c7f4da5f6 517
wuliqunyy 12:9f8c7f4da5f6 518
wuliqunyy 12:9f8c7f4da5f6 519
wuliqunyy 12:9f8c7f4da5f6 520
wuliqunyy 11:b86aea372744 521 /** i2c to clean the I2C controller settins
wuliqunyy 11:b86aea372744 522 */
wuliqunyy 11:b86aea372744 523 int i2c_mbed_fpga::i2c_clear_spd_ctrl(){
wuliqunyy 11:b86aea372744 524 int ack = 0;
wuliqunyy 11:b86aea372744 525 nv_spd_control_1_val = 0;
wuliqunyy 11:b86aea372744 526 nv_spd_control_2_val = 0;
wuliqunyy 14:062850afdf38 527 char i2cMessage[3];
wuliqunyy 14:062850afdf38 528 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_1 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 529 *(i2cMessage+1) = (char)(nv_spd_control_1_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 530 *(i2cMessage+2) = (char)(nv_spd_control_1_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 531 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 532 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_2 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 533 *(i2cMessage+1) = (char)(nv_spd_control_2_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 534 *(i2cMessage+2) = (char)(nv_spd_control_2_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 535 ack += i2c_word_write(i2cMessage);
wuliqunyy 11:b86aea372744 536
wuliqunyy 11:b86aea372744 537 return ack;
wuliqunyy 11:b86aea372744 538 }
wuliqunyy 11:b86aea372744 539
wuliqunyy 14:062850afdf38 540 /** i2c to set the I2C speed input mode
wuliqunyy 14:062850afdf38 541 */
wuliqunyy 14:062850afdf38 542 int i2c_mbed_fpga::i2c_set_input_mode(unsigned int mode){
wuliqunyy 14:062850afdf38 543 int ack = 0;
wuliqunyy 14:062850afdf38 544 nv_application_cfg_val &= ~NV_INPUT_MODE_CFG_MASK;
wuliqunyy 14:062850afdf38 545 nv_application_cfg_val |= mode << NV_INPUT_MODE_CFG_OFFSET;
wuliqunyy 14:062850afdf38 546 char i2cMessage[3];
wuliqunyy 14:062850afdf38 547 *(i2cMessage+0) = (char)(I2C_APPLICATION_CFG >> 0)& 0xff;
wuliqunyy 14:062850afdf38 548 *(i2cMessage+1) = (char)(nv_application_cfg_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 549 *(i2cMessage+2) = (char)(nv_application_cfg_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 550 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 551 return ack;
wuliqunyy 14:062850afdf38 552 }
wuliqunyy 14:062850afdf38 553
wuliqunyy 14:062850afdf38 554
wuliqunyy 11:b86aea372744 555
wuliqunyy 9:76a0b9f29a2d 556 /** i2c to set the open loop mode
wuliqunyy 9:76a0b9f29a2d 557 */
wuliqunyy 9:76a0b9f29a2d 558 int i2c_mbed_fpga::i2c_set_loop_mode(unsigned int openloop){
wuliqunyy 9:76a0b9f29a2d 559 int ack = 0;
wuliqunyy 9:76a0b9f29a2d 560 nv_spd_control_1_val &= ~NV_SPD_LOOP_MODE_MASK;
wuliqunyy 9:76a0b9f29a2d 561 nv_spd_control_1_val |= openloop << NV_SPD_LOOP_MODE_OFFSET;
wuliqunyy 14:062850afdf38 562 char i2cMessage[3];
wuliqunyy 14:062850afdf38 563 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_1 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 564 *(i2cMessage+1) = (char)(nv_spd_control_1_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 565 *(i2cMessage+2) = (char)(nv_spd_control_1_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 566 ack += i2c_word_write(i2cMessage);
wuliqunyy 9:76a0b9f29a2d 567
wuliqunyy 9:76a0b9f29a2d 568 return ack;
wuliqunyy 9:76a0b9f29a2d 569 }
wuliqunyy 9:76a0b9f29a2d 570
wuliqunyy 12:9f8c7f4da5f6 571 /** i2c to set the Single Pulse Start Up (pulse train)
wuliqunyy 12:9f8c7f4da5f6 572 */
wuliqunyy 12:9f8c7f4da5f6 573 int i2c_mbed_fpga::i2c_set_open_loop_duty(unsigned int duty){
wuliqunyy 12:9f8c7f4da5f6 574 int ack = 0;
wuliqunyy 12:9f8c7f4da5f6 575 ram_open_duty_val = duty;
wuliqunyy 14:062850afdf38 576 char i2cMessage[3];
wuliqunyy 14:062850afdf38 577 *(i2cMessage+0) = (char)(I2C_SPEED_DUTY)& 0xff;
wuliqunyy 14:062850afdf38 578 *(i2cMessage+1) = (char)(ram_open_duty_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 579 *(i2cMessage+2) = (char)(ram_open_duty_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 580 ack += i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 581
wuliqunyy 12:9f8c7f4da5f6 582 return ack;
wuliqunyy 12:9f8c7f4da5f6 583 }
wuliqunyy 12:9f8c7f4da5f6 584
wuliqunyy 11:b86aea372744 585 /** i2c to set the speed curve type
wuliqunyy 11:b86aea372744 586 */
wuliqunyy 11:b86aea372744 587 int i2c_mbed_fpga::i2c_set_curve_type(unsigned int curvetype){
wuliqunyy 11:b86aea372744 588 int ack = 0;
wuliqunyy 11:b86aea372744 589 nv_spd_control_1_val &= ~NV_CURVE_MODE_MASK;
wuliqunyy 11:b86aea372744 590 nv_spd_control_1_val |= curvetype << NV_CURVE_MODE_OFFSET;
wuliqunyy 14:062850afdf38 591 char i2cMessage[3];
wuliqunyy 14:062850afdf38 592 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_1 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 593 *(i2cMessage+1) = (char)(nv_spd_control_1_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 594 *(i2cMessage+2) = (char)(nv_spd_control_1_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 595 ack += i2c_word_write(i2cMessage);
wuliqunyy 11:b86aea372744 596
wuliqunyy 11:b86aea372744 597 return ack;
wuliqunyy 11:b86aea372744 598 }
wuliqunyy 11:b86aea372744 599
wuliqunyy 11:b86aea372744 600 /** i2c to set the open dc ini
wuliqunyy 11:b86aea372744 601 */
wuliqunyy 11:b86aea372744 602 int i2c_mbed_fpga::i2c_set_dc_ini(unsigned int ini){
wuliqunyy 11:b86aea372744 603 int ack = 0;
wuliqunyy 11:b86aea372744 604 nv_spd_control_2_val &= ~NV_DC_OPENLOOP_INI_MASK;
wuliqunyy 11:b86aea372744 605 nv_spd_control_2_val |= ini << NV_DC_OPENLOOP_INI_OFFSET;
wuliqunyy 14:062850afdf38 606 char i2cMessage[3];
wuliqunyy 14:062850afdf38 607 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_2 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 608 *(i2cMessage+1) = (char)(nv_spd_control_2_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 609 *(i2cMessage+2) = (char)(nv_spd_control_2_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 610 ack += i2c_word_write(i2cMessage);
wuliqunyy 11:b86aea372744 611
wuliqunyy 11:b86aea372744 612 return ack;
wuliqunyy 11:b86aea372744 613 }
wuliqunyy 11:b86aea372744 614
wuliqunyy 11:b86aea372744 615 /** i2c to set the open dc slew rate
wuliqunyy 11:b86aea372744 616 */
wuliqunyy 11:b86aea372744 617 int i2c_mbed_fpga::i2c_set_dc_sr(unsigned int sr){
wuliqunyy 11:b86aea372744 618 int ack = 0;
wuliqunyy 11:b86aea372744 619 nv_spd_control_2_val &= ~NV_DC_OPENLOOP_SR_MASK;
wuliqunyy 11:b86aea372744 620 nv_spd_control_2_val |= sr << NV_DC_OPENLOOP_SR_OFFSET;
wuliqunyy 14:062850afdf38 621 char i2cMessage[3];
wuliqunyy 14:062850afdf38 622 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_2 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 623 *(i2cMessage+1) = (char)(nv_spd_control_2_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 624 *(i2cMessage+2) = (char)(nv_spd_control_2_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 625 ack += i2c_word_write(i2cMessage);
wuliqunyy 11:b86aea372744 626
wuliqunyy 11:b86aea372744 627 return ack;
wuliqunyy 11:b86aea372744 628 }
wuliqunyy 11:b86aea372744 629
wuliqunyy 16:a0bfe33f8a4a 630 /** i2c to set the target CLIM during start up
wuliqunyy 16:a0bfe33f8a4a 631 */
wuliqunyy 16:a0bfe33f8a4a 632 int i2c_mbed_fpga::i2c_set_clim_start_up(unsigned int clim){
wuliqunyy 16:a0bfe33f8a4a 633 int ack = 0;
wuliqunyy 16:a0bfe33f8a4a 634 nv_clim_user_1_val &= ~NV_TARGET_CLIM_USER_PULSES_MASK;
wuliqunyy 16:a0bfe33f8a4a 635 nv_clim_user_1_val |= clim << NV_TARGET_CLIM_USER_PULSES_OFFSET;
wuliqunyy 16:a0bfe33f8a4a 636 char i2cMessage[3];
wuliqunyy 16:a0bfe33f8a4a 637 *(i2cMessage+0) = (char)(I2C_CLIM_USER_1 >> 0)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 638 *(i2cMessage+1) = (char)(nv_clim_user_1_val >> 8)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 639 *(i2cMessage+2) = (char)(nv_clim_user_1_val >> 0)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 640 ack += i2c_word_write(i2cMessage);
wuliqunyy 16:a0bfe33f8a4a 641
wuliqunyy 16:a0bfe33f8a4a 642 return ack;
wuliqunyy 16:a0bfe33f8a4a 643 }
wuliqunyy 12:9f8c7f4da5f6 644
wuliqunyy 16:a0bfe33f8a4a 645 /** i2c to set the target CLIM during brake
wuliqunyy 16:a0bfe33f8a4a 646 */
wuliqunyy 16:a0bfe33f8a4a 647 int i2c_mbed_fpga::i2c_set_clim_brake(unsigned int clim){
wuliqunyy 16:a0bfe33f8a4a 648 int ack = 0;
wuliqunyy 16:a0bfe33f8a4a 649 nv_clim_user_0_val &= ~NV_TARGET_CLIM_USER_BRAKE_MASK;
wuliqunyy 16:a0bfe33f8a4a 650 nv_clim_user_0_val |= clim << NV_TARGET_CLIM_USER_BRAKE_OFFSET;
wuliqunyy 16:a0bfe33f8a4a 651 char i2cMessage[3];
wuliqunyy 16:a0bfe33f8a4a 652 *(i2cMessage+0) = (char)(I2C_CLIM_USER_0 >> 0)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 653 *(i2cMessage+1) = (char)(nv_clim_user_0_val >> 8)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 654 *(i2cMessage+2) = (char)(nv_clim_user_0_val >> 0)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 655 ack += i2c_word_write(i2cMessage);
wuliqunyy 16:a0bfe33f8a4a 656
wuliqunyy 16:a0bfe33f8a4a 657 return ack;
wuliqunyy 16:a0bfe33f8a4a 658 }
wuliqunyy 16:a0bfe33f8a4a 659
wuliqunyy 16:a0bfe33f8a4a 660 /** i2c to set the target CLIM during run time
wuliqunyy 16:a0bfe33f8a4a 661 */
wuliqunyy 16:a0bfe33f8a4a 662 int i2c_mbed_fpga::i2c_set_clim_run_time(unsigned int clim){
wuliqunyy 16:a0bfe33f8a4a 663 int ack = 0;
wuliqunyy 16:a0bfe33f8a4a 664 nv_clim_user_0_val &= ~NV_TARGET_CLIM_USER_MOTOR_MASK;
wuliqunyy 16:a0bfe33f8a4a 665 nv_clim_user_0_val |= clim << NV_TARGET_CLIM_USER_MOTOR_OFFSET;
wuliqunyy 16:a0bfe33f8a4a 666 char i2cMessage[3];
wuliqunyy 16:a0bfe33f8a4a 667 *(i2cMessage+0) = (char)(I2C_CLIM_USER_0 >> 0)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 668 *(i2cMessage+1) = (char)(nv_clim_user_0_val >> 8)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 669 *(i2cMessage+2) = (char)(nv_clim_user_0_val >> 0)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 670 ack += i2c_word_write(i2cMessage);
wuliqunyy 16:a0bfe33f8a4a 671
wuliqunyy 16:a0bfe33f8a4a 672 return ack;
wuliqunyy 16:a0bfe33f8a4a 673 }
wuliqunyy 16:a0bfe33f8a4a 674
wuliqunyy 16:a0bfe33f8a4a 675
wuliqunyy 22:fd929620e873 676 /** i2c to enbale test debug mode
wuliqunyy 16:a0bfe33f8a4a 677 */
wuliqunyy 22:fd929620e873 678 int i2c_mbed_fpga::i2c_enable_pules_debug_mode(unsigned int enable){
wuliqunyy 22:fd929620e873 679 int ack = 0;
wuliqunyy 22:fd929620e873 680 ram_debug_ctrl_val &= ~0x0001;
wuliqunyy 23:0237430bf3ec 681 ram_debug_ctrl_val |= enable;
wuliqunyy 22:fd929620e873 682 char i2cMessage[3];
wuliqunyy 23:0237430bf3ec 683 // *(i2cMessage+0) = (char)(0x00ea >> 0)& 0xff;
wuliqunyy 23:0237430bf3ec 684 // *(i2cMessage+1) = (char)(ram_debug_ctrl_val >> 8)& 0xff;
wuliqunyy 23:0237430bf3ec 685 // *(i2cMessage+2) = (char)(ram_debug_ctrl_val >> 0)& 0xff;
wuliqunyy 23:0237430bf3ec 686 *(i2cMessage+0) = (char)(0xea);
wuliqunyy 23:0237430bf3ec 687 *(i2cMessage+1) = (char)(0x00);
wuliqunyy 23:0237430bf3ec 688 *(i2cMessage+2) = (char)(0x01);
wuliqunyy 22:fd929620e873 689 ack += i2c_word_write(i2cMessage);
wuliqunyy 22:fd929620e873 690
wuliqunyy 22:fd929620e873 691 return ack;
wuliqunyy 22:fd929620e873 692 }
wuliqunyy 16:a0bfe33f8a4a 693
wuliqunyy 22:fd929620e873 694
wuliqunyy 22:fd929620e873 695