Bavo Van Achte / Mbed 2 deprecated MLX90418_I2C_master

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Dependencies:   mbed libscpi

i2c_mbed_fpga.cpp@9:76a0b9f29a2d, 2021-02-26 (annotated)

Committer:
wuliqunyy
Date:
Fri Feb 26 08:45:13 2021 +0000
Revision:
9:76a0b9f29a2d
Parent:
8:2554218db1e6
Child:
10:a8390614edcc
updated for ganymede14

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wuliqunyy 0:fe3c7dde9771 1 #include "mbed.h"
wuliqunyy 0:fe3c7dde9771 2 #include "i2c_mbed_fpga.h"
wuliqunyy 6:019ab407ac3c 3 DigitalOut led3(LED3);
wuliqunyy 0:fe3c7dde9771 4
wuliqunyy 6:019ab407ac3c 5 /** i2c read from slave DUT
wuliqunyy 6:019ab407ac3c 6 * retun 0 on success, otherwise fails
wuliqunyy 6:019ab407ac3c 7 *
wuliqunyy 6:019ab407ac3c 8 * @param i2c_master specifies the i2c interface
wuliqunyy 6:019ab407ac3c 9 * @param word is 4byte, first 2bytes as addr, the rest 2bytes to store data
wuliqunyy 6:019ab407ac3c 10 */
wuliqunyy 6:019ab407ac3c 11 int i2c_mbed_fpga::i2c_word_read(char *word){
wuliqunyy 6:019ab407ac3c 12 int ack = 0;
wuliqunyy 6:019ab407ac3c 13 ack = i2c_master.write(I2C_SLAVE_ADDR, word, 2, true); //restart
wuliqunyy 6:019ab407ac3c 14 ack += i2c_master.read(I2C_SLAVE_ADDR, word+2, 2, false); //stop bit
wuliqunyy 6:019ab407ac3c 15 wait_us(100);
wuliqunyy 6:019ab407ac3c 16 return (ack == 0) ? 0 : 1;
wuliqunyy 6:019ab407ac3c 17 }
wuliqunyy 0:fe3c7dde9771 18
wuliqunyy 0:fe3c7dde9771 19 /** i2c write to slave DUT
wuliqunyy 6:019ab407ac3c 20 * ==> one time write, not read back check
wuliqunyy 0:fe3c7dde9771 21 *
wuliqunyy 0:fe3c7dde9771 22 * @param i2c_master specifies the i2c interface
wuliqunyy 0:fe3c7dde9771 23 * @param word is considered as 4byte char data
wuliqunyy 0:fe3c7dde9771 24 */
wuliqunyy 5:daab0e0e67e2 25 int i2c_mbed_fpga::i2c_word_write(char *word){
wuliqunyy 6:019ab407ac3c 26 int ack = 0;
wuliqunyy 6:019ab407ac3c 27 ack = i2c_master.write(I2C_SLAVE_ADDR, word, 4, false);
wuliqunyy 5:daab0e0e67e2 28 return ack;
wuliqunyy 0:fe3c7dde9771 29 }
wuliqunyy 0:fe3c7dde9771 30
wuliqunyy 0:fe3c7dde9771 31
wuliqunyy 6:019ab407ac3c 32 /** i2c write to slave DUT
wuliqunyy 6:019ab407ac3c 33 * ==> Safe write with 3 times read back check
wuliqunyy 0:fe3c7dde9771 34 *
wuliqunyy 0:fe3c7dde9771 35 * @param i2c_master specifies the i2c interface
wuliqunyy 6:019ab407ac3c 36 * @param word is considered as 4byte char data
wuliqunyy 0:fe3c7dde9771 37 */
wuliqunyy 6:019ab407ac3c 38 int i2c_mbed_fpga::i2c_word_safe_write(char *word){
wuliqunyy 6:019ab407ac3c 39 int ack = 0;
wuliqunyy 6:019ab407ac3c 40 char readBuff[4];
wuliqunyy 6:019ab407ac3c 41 std::copy(word, word+4, readBuff);
wuliqunyy 6:019ab407ac3c 42 int i = 0;
wuliqunyy 6:019ab407ac3c 43 do{
wuliqunyy 6:019ab407ac3c 44 ack = i2c_master.write(I2C_SLAVE_ADDR, word, 4, false);
wuliqunyy 6:019ab407ac3c 45 wait_us(100);
wuliqunyy 6:019ab407ac3c 46 ack +=i2c_word_read(readBuff);
wuliqunyy 6:019ab407ac3c 47 wait_us(100);
wuliqunyy 6:019ab407ac3c 48 if( *(readBuff+2) == *(word+2) && *(readBuff+3) == *(word+3) ){
wuliqunyy 6:019ab407ac3c 49 ack++;
wuliqunyy 6:019ab407ac3c 50 }
wuliqunyy 6:019ab407ac3c 51 i++;
wuliqunyy 6:019ab407ac3c 52 }while ( ack!=0 && i<3 );
wuliqunyy 6:019ab407ac3c 53 return ack;
wuliqunyy 0:fe3c7dde9771 54 }
wuliqunyy 0:fe3c7dde9771 55
wuliqunyy 0:fe3c7dde9771 56
wuliqunyy 5:daab0e0e67e2 57 /** i2c enter key to open I2C window
wuliqunyy 0:fe3c7dde9771 58 */
wuliqunyy 5:daab0e0e67e2 59 int i2c_mbed_fpga::i2c_window_open(){
wuliqunyy 9:76a0b9f29a2d 60 char i2cKey[4] = {0x13, 0xFA, 0xD0, 0xD0};
wuliqunyy 5:daab0e0e67e2 61 return i2c_word_write(i2cKey);
wuliqunyy 0:fe3c7dde9771 62 }
wuliqunyy 0:fe3c7dde9771 63
wuliqunyy 5:daab0e0e67e2 64 /** i2c enter key to Start the motor
wuliqunyy 0:fe3c7dde9771 65 */
wuliqunyy 5:daab0e0e67e2 66 int i2c_mbed_fpga::i2c_motor_start(){
wuliqunyy 9:76a0b9f29a2d 67 char i2cKey[4] = {0x13, 0xFA, 0xCA, 0xFE};
wuliqunyy 5:daab0e0e67e2 68 return i2c_word_write(i2cKey);
wuliqunyy 0:fe3c7dde9771 69 }
wuliqunyy 6:019ab407ac3c 70
wuliqunyy 6:019ab407ac3c 71 /** i2c to set the Postion Pulse width
wuliqunyy 6:019ab407ac3c 72 */
wuliqunyy 6:019ab407ac3c 73 int i2c_mbed_fpga::i2c_set_position_pulse_width(unsigned int mantisaa_2b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 74 nv_positin_val &= ~NV_POSITION_PULSE_TIME_MASK;
wuliqunyy 6:019ab407ac3c 75 nv_positin_val |= ((exponent_3b << 2) | mantisaa_2b) << NV_POSITION_PULSE_TIME_OFFSET;
wuliqunyy 6:019ab407ac3c 76 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 77 *(i2cMessage+0) = (char)(NVADDR_NV_POSITION >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 78 *(i2cMessage+1) = (char)(NVADDR_NV_POSITION >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 79 *(i2cMessage+2) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 80 *(i2cMessage+3) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 81 return i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 82 }
wuliqunyy 6:019ab407ac3c 83
wuliqunyy 6:019ab407ac3c 84 /** i2c to set the Postion Pulse duty cycle
wuliqunyy 6:019ab407ac3c 85 */
wuliqunyy 6:019ab407ac3c 86 int i2c_mbed_fpga::i2c_set_position_duty(unsigned int duty_2b){
wuliqunyy 6:019ab407ac3c 87 nv_positin_val &= ~NV_POSITION_DUTY_MASK;
wuliqunyy 6:019ab407ac3c 88 nv_positin_val |= duty_2b << NV_POSITION_DUTY_OFFSET;
wuliqunyy 6:019ab407ac3c 89 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 90 *(i2cMessage+0) = (char)(NVADDR_NV_POSITION >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 91 *(i2cMessage+1) = (char)(NVADDR_NV_POSITION >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 92 *(i2cMessage+2) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 93 *(i2cMessage+3) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 94 return i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 95 }
wuliqunyy 6:019ab407ac3c 96
wuliqunyy 6:019ab407ac3c 97 /** i2c to enable the Postion Pulse majority volting
wuliqunyy 6:019ab407ac3c 98 */
wuliqunyy 6:019ab407ac3c 99 int i2c_mbed_fpga::i2c_set_position_maj_vote(unsigned int maj_1b){
wuliqunyy 6:019ab407ac3c 100 nv_positin_val &= ~NV_POSI_MAJO_VOTE_MASK;
wuliqunyy 6:019ab407ac3c 101 nv_positin_val |= maj_1b << NV_POSI_MAJO_VOTE_OFFSET;
wuliqunyy 6:019ab407ac3c 102 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 103 *(i2cMessage+0) = (char)(NVADDR_NV_POSITION >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 104 *(i2cMessage+1) = (char)(NVADDR_NV_POSITION >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 105 *(i2cMessage+2) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 106 *(i2cMessage+3) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 107 return i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 108 }
wuliqunyy 6:019ab407ac3c 109
wuliqunyy 6:019ab407ac3c 110 /** i2c to set the anti-cogging rotation direction
wuliqunyy 6:019ab407ac3c 111 */
wuliqunyy 6:019ab407ac3c 112 int i2c_mbed_fpga::i2c_set_position_anti_cog(unsigned int cog_1b){
wuliqunyy 6:019ab407ac3c 113 nv_positin_val &= ~NV_ANTI_COG_MASK;
wuliqunyy 6:019ab407ac3c 114 nv_positin_val |= cog_1b << NV_ANTI_COG_OFFSET;
wuliqunyy 6:019ab407ac3c 115 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 116 *(i2cMessage+0) = (char)(NVADDR_NV_POSITION >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 117 *(i2cMessage+1) = (char)(NVADDR_NV_POSITION >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 118 *(i2cMessage+2) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 119 *(i2cMessage+3) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 120 return i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 121 }
wuliqunyy 6:019ab407ac3c 122
wuliqunyy 6:019ab407ac3c 123
wuliqunyy 6:019ab407ac3c 124 /** i2c to set the Start Up Pulse width (pulse train)
wuliqunyy 6:019ab407ac3c 125 */
wuliqunyy 6:019ab407ac3c 126 int i2c_mbed_fpga::i2c_set_start_up_pulse_width(unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 127 nv_start_up_val &= ~NV_START_UP_TIME_MASK;
wuliqunyy 8:2554218db1e6 128 nv_start_up_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_START_UP_TIME_OFFSET;
wuliqunyy 6:019ab407ac3c 129 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 130 *(i2cMessage+0) = (char)(NVADDR_NV_START_UP >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 131 *(i2cMessage+1) = (char)(NVADDR_NV_START_UP >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 132 *(i2cMessage+2) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 133 *(i2cMessage+3) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 134 return i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 135 }
wuliqunyy 6:019ab407ac3c 136
wuliqunyy 6:019ab407ac3c 137 /** i2c to set the Start up Pulse duty cycle (pulse train)
wuliqunyy 6:019ab407ac3c 138 */
wuliqunyy 6:019ab407ac3c 139 int i2c_mbed_fpga::i2c_set_start_up_duty(unsigned int duty_2b){
wuliqunyy 6:019ab407ac3c 140 nv_start_up_val &= ~NV_START_DUTY_MASK;
wuliqunyy 6:019ab407ac3c 141 nv_start_up_val |= duty_2b << NV_START_DUTY_OFFSET;
wuliqunyy 6:019ab407ac3c 142 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 143 *(i2cMessage+0) = (char)(NVADDR_NV_START_UP >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 144 *(i2cMessage+1) = (char)(NVADDR_NV_START_UP >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 145 *(i2cMessage+2) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 146 *(i2cMessage+3) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 147 return i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 148 }
wuliqunyy 6:019ab407ac3c 149
wuliqunyy 6:019ab407ac3c 150 /** i2c to set the Start up commutation number of EHPs (pulse train)
wuliqunyy 6:019ab407ac3c 151 */
wuliqunyy 6:019ab407ac3c 152 int i2c_mbed_fpga::i2c_set_start_up_num_comm(unsigned int comm){
wuliqunyy 6:019ab407ac3c 153 nv_start_up_val &= ~NV_COMM_START_NUM_MASK;
wuliqunyy 6:019ab407ac3c 154 nv_start_up_val |= comm << NV_COMM_START_NUM_OFFSET;
wuliqunyy 6:019ab407ac3c 155 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 156 *(i2cMessage+0) = (char)(NVADDR_NV_START_UP >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 157 *(i2cMessage+1) = (char)(NVADDR_NV_START_UP >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 158 *(i2cMessage+2) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 159 *(i2cMessage+3) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 160 return i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 161 }
wuliqunyy 6:019ab407ac3c 162
wuliqunyy 6:019ab407ac3c 163 /** i2c to set the Soft Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 164 */
wuliqunyy 6:019ab407ac3c 165 int i2c_mbed_fpga::i2c_set_soft_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b, unsigned int step_size, unsigned int num_steps){
wuliqunyy 6:019ab407ac3c 166 int ack = 0;
wuliqunyy 6:019ab407ac3c 167 nv_start_up_val &= ~NV_SOFT_START_MASK;
wuliqunyy 6:019ab407ac3c 168 nv_start_up_val |= enbale << NV_SOFT_START_OFFSET;
wuliqunyy 6:019ab407ac3c 169 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 170 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 6:019ab407ac3c 171 nv_start_up_val &= ~NV_SOFT_STEP_SIZE_MASK;
wuliqunyy 6:019ab407ac3c 172 nv_start_up_val |= step_size << NV_SOFT_STEP_SIZE_OFFSET;
wuliqunyy 6:019ab407ac3c 173 nv_wind_brake_val &= ~NV_SOFT_NUM_STEP_MASK;
wuliqunyy 6:019ab407ac3c 174 nv_wind_brake_val |= num_steps << NV_SOFT_NUM_STEP_OFFSET;
wuliqunyy 6:019ab407ac3c 175 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 176 *(i2cMessage+0) = (char)(NVADDR_NV_POSITION >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 177 *(i2cMessage+1) = (char)(NVADDR_NV_POSITION >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 178 *(i2cMessage+2) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 179 *(i2cMessage+3) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 180 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 181
wuliqunyy 9:76a0b9f29a2d 182 *(i2cMessage+0) = (char)(NVADDR_NV_START_UP >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 183 *(i2cMessage+1) = (char)(NVADDR_NV_START_UP >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 184 *(i2cMessage+2) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 185 *(i2cMessage+3) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 186 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 187
wuliqunyy 9:76a0b9f29a2d 188 *(i2cMessage+0) = (char)(NVADDR_NV_WIND_BRAKE >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 189 *(i2cMessage+1) = (char)(NVADDR_NV_WIND_BRAKE >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 190 *(i2cMessage+2) = (char)(nv_wind_brake_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 191 *(i2cMessage+3) = (char)(nv_wind_brake_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 192 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 193
wuliqunyy 6:019ab407ac3c 194 return ack;
wuliqunyy 6:019ab407ac3c 195 }
wuliqunyy 6:019ab407ac3c 196
wuliqunyy 6:019ab407ac3c 197 /** i2c to set the High Torque Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 198 */
wuliqunyy 6:019ab407ac3c 199 int i2c_mbed_fpga::i2c_set_high_torque_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 200 int ack = 0;
wuliqunyy 6:019ab407ac3c 201 nv_start_up_val &= ~NV_LONG_START_MASK;
wuliqunyy 6:019ab407ac3c 202 nv_start_up_val |= enbale << NV_LONG_START_OFFSET;
wuliqunyy 6:019ab407ac3c 203 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 204 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 6:019ab407ac3c 205 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 206 *(i2cMessage+0) = (char)(NVADDR_NV_POSITION >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 207 *(i2cMessage+1) = (char)(NVADDR_NV_POSITION >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 208 *(i2cMessage+2) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 209 *(i2cMessage+3) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 210 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 211
wuliqunyy 9:76a0b9f29a2d 212 *(i2cMessage+0) = (char)(NVADDR_NV_START_UP >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 213 *(i2cMessage+1) = (char)(NVADDR_NV_START_UP >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 214 *(i2cMessage+2) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 215 *(i2cMessage+3) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 216 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 217
wuliqunyy 6:019ab407ac3c 218 return ack;
wuliqunyy 6:019ab407ac3c 219 }
wuliqunyy 6:019ab407ac3c 220
wuliqunyy 6:019ab407ac3c 221 /** i2c to set the Single Pulse Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 222 */
wuliqunyy 6:019ab407ac3c 223 int i2c_mbed_fpga::i2c_set_single_pulse_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 224 int ack = 0;
wuliqunyy 6:019ab407ac3c 225 nv_start_up_val &= ~NV_SINGLE_PULSE_START_MASK;
wuliqunyy 6:019ab407ac3c 226 nv_start_up_val |= enbale << NV_SINGLE_PULSE_START_OFFSET;
wuliqunyy 6:019ab407ac3c 227 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 228 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 6:019ab407ac3c 229 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 230 *(i2cMessage+0) = (char)(NVADDR_NV_POSITION >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 231 *(i2cMessage+1) = (char)(NVADDR_NV_POSITION >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 232 *(i2cMessage+2) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 233 *(i2cMessage+3) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 234 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 235
wuliqunyy 9:76a0b9f29a2d 236 *(i2cMessage+0) = (char)(NVADDR_NV_START_UP >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 237 *(i2cMessage+1) = (char)(NVADDR_NV_START_UP >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 238 *(i2cMessage+2) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 239 *(i2cMessage+3) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 240 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 241
wuliqunyy 6:019ab407ac3c 242 return ack;
wuliqunyy 9:76a0b9f29a2d 243 }
wuliqunyy 9:76a0b9f29a2d 244
wuliqunyy 9:76a0b9f29a2d 245 /** i2c to set the open loop mode
wuliqunyy 9:76a0b9f29a2d 246 */
wuliqunyy 9:76a0b9f29a2d 247 int i2c_mbed_fpga::i2c_set_loop_mode(unsigned int openloop){
wuliqunyy 9:76a0b9f29a2d 248 int ack = 0;
wuliqunyy 9:76a0b9f29a2d 249 nv_spd_control_1_val &= ~NV_SPD_LOOP_MODE_MASK;
wuliqunyy 9:76a0b9f29a2d 250 nv_spd_control_1_val |= openloop << NV_SPD_LOOP_MODE_OFFSET;
wuliqunyy 9:76a0b9f29a2d 251 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 252 *(i2cMessage+0) = (char)(NVADDR_NV_SPD_CTRL_1 >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 253 *(i2cMessage+1) = (char)(NVADDR_NV_SPD_CTRL_1 >> 0)& 0xff;
wuliqunyy 9:76a0b9f29a2d 254 *(i2cMessage+2) = (char)(nv_spd_control_1_val >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 255 *(i2cMessage+3) = (char)(nv_spd_control_1_val >> 0)& 0xff;
wuliqunyy 9:76a0b9f29a2d 256 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 9:76a0b9f29a2d 257
wuliqunyy 9:76a0b9f29a2d 258 return ack;
wuliqunyy 9:76a0b9f29a2d 259 }
wuliqunyy 9:76a0b9f29a2d 260
wuliqunyy 9:76a0b9f29a2d 261 /** i2c to set the Single Pulse Start Up (pulse train)
wuliqunyy 9:76a0b9f29a2d 262 */
wuliqunyy 9:76a0b9f29a2d 263 int i2c_mbed_fpga::i2c_set_open_loop_duty(unsigned int duty){
wuliqunyy 9:76a0b9f29a2d 264 int ack = 0;
wuliqunyy 9:76a0b9f29a2d 265 nv_start_up_val = duty;
wuliqunyy 9:76a0b9f29a2d 266 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 267 *(i2cMessage+0) = (char)(0x10)& 0xff;
wuliqunyy 9:76a0b9f29a2d 268 *(i2cMessage+1) = (char)(0x3e)& 0xff;
wuliqunyy 9:76a0b9f29a2d 269 *(i2cMessage+2) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 270 *(i2cMessage+3) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 9:76a0b9f29a2d 271 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 9:76a0b9f29a2d 272
wuliqunyy 9:76a0b9f29a2d 273
wuliqunyy 9:76a0b9f29a2d 274
wuliqunyy 9:76a0b9f29a2d 275 return ack;
wuliqunyy 9:76a0b9f29a2d 276 }