Bavo Van Achte / Mbed 2 deprecated MLX90418_I2C_master

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Dependencies:   mbed libscpi

i2c_mbed_fpga.cpp@20:26e934452728, 2021-06-04 (annotated)

Committer:
wuliqunyy
Date:
Fri Jun 04 08:21:10 2021 +0000
Revision:
20:26e934452728
Parent:
17:d7207b1132be
Child:
22:fd929620e873
FPGA_V2 release

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wuliqunyy 0:fe3c7dde9771 1 #include "mbed.h"
wuliqunyy 0:fe3c7dde9771 2 #include "i2c_mbed_fpga.h"
wuliqunyy 16:a0bfe33f8a4a 3
wuliqunyy 0:fe3c7dde9771 4
wuliqunyy 6:019ab407ac3c 5 /** i2c read from slave DUT
wuliqunyy 6:019ab407ac3c 6 * retun 0 on success, otherwise fails
wuliqunyy 6:019ab407ac3c 7 *
wuliqunyy 6:019ab407ac3c 8 * @param i2c_master specifies the i2c interface
wuliqunyy 6:019ab407ac3c 9 * @param word is 4byte, first 2bytes as addr, the rest 2bytes to store data
wuliqunyy 6:019ab407ac3c 10 */
wuliqunyy 6:019ab407ac3c 11 int i2c_mbed_fpga::i2c_word_read(char *word){
wuliqunyy 6:019ab407ac3c 12 int ack = 0;
wuliqunyy 14:062850afdf38 13 ack = i2c_master.write(I2C_SLAVE_ADDR, word, 1, true); //restart
wuliqunyy 14:062850afdf38 14 ack += i2c_master.read(I2C_SLAVE_ADDR, word+1, 2, false); //stop bit
wuliqunyy 6:019ab407ac3c 15 wait_us(100);
wuliqunyy 6:019ab407ac3c 16 return (ack == 0) ? 0 : 1;
wuliqunyy 6:019ab407ac3c 17 }
wuliqunyy 0:fe3c7dde9771 18
wuliqunyy 0:fe3c7dde9771 19 /** i2c write to slave DUT
wuliqunyy 6:019ab407ac3c 20 * ==> one time write, not read back check
wuliqunyy 0:fe3c7dde9771 21 *
wuliqunyy 0:fe3c7dde9771 22 * @param i2c_master specifies the i2c interface
wuliqunyy 0:fe3c7dde9771 23 * @param word is considered as 4byte char data
wuliqunyy 0:fe3c7dde9771 24 */
wuliqunyy 5:daab0e0e67e2 25 int i2c_mbed_fpga::i2c_word_write(char *word){
wuliqunyy 6:019ab407ac3c 26 int ack = 0;
wuliqunyy 14:062850afdf38 27 ack = i2c_master.write(I2C_SLAVE_ADDR, word, 3, false);
wuliqunyy 6:019ab407ac3c 28 return ack;
wuliqunyy 0:fe3c7dde9771 29 }
wuliqunyy 0:fe3c7dde9771 30
wuliqunyy 0:fe3c7dde9771 31
wuliqunyy 16:a0bfe33f8a4a 32 /** i2c enter key to open I2C window (for old releases)
wuliqunyy 0:fe3c7dde9771 33 */
wuliqunyy 15:83bbc18cccbc 34 //int i2c_mbed_fpga::i2c_window_open(){
wuliqunyy 15:83bbc18cccbc 35 // char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 36 // *(i2cMessage+0) = (char)(I2C_CUST_ID3)& 0xff;
wuliqunyy 15:83bbc18cccbc 37 // *(i2cMessage+1) = (char)(0xD0)& 0xff;
wuliqunyy 15:83bbc18cccbc 38 // *(i2cMessage+2) = (char)(0xD0)& 0xff;
wuliqunyy 15:83bbc18cccbc 39 // return i2c_word_write(i2cMessage);
wuliqunyy 15:83bbc18cccbc 40 //}
wuliqunyy 15:83bbc18cccbc 41
wuliqunyy 16:a0bfe33f8a4a 42 /** i2c enter key to Start the motor (for old releases)
wuliqunyy 15:83bbc18cccbc 43 */
wuliqunyy 15:83bbc18cccbc 44 //int i2c_mbed_fpga::i2c_motor_start(){
wuliqunyy 15:83bbc18cccbc 45 // char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 46 // *(i2cMessage+0) = (char)(I2C_CUST_ID3)& 0xff;
wuliqunyy 15:83bbc18cccbc 47 // *(i2cMessage+1) = (char)(0xCA)& 0xff;
wuliqunyy 15:83bbc18cccbc 48 // *(i2cMessage+2) = (char)(0xFE)& 0xff;
wuliqunyy 15:83bbc18cccbc 49 // return i2c_word_write(i2cMessage);
wuliqunyy 15:83bbc18cccbc 50 //}
wuliqunyy 15:83bbc18cccbc 51
wuliqunyy 15:83bbc18cccbc 52
wuliqunyy 15:83bbc18cccbc 53 /** i2c enter key to open I2C configuration mode entry
wuliqunyy 15:83bbc18cccbc 54 */
wuliqunyy 15:83bbc18cccbc 55 int i2c_mbed_fpga::i2c_config_mode_entry(){
wuliqunyy 14:062850afdf38 56 char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 57 *(i2cMessage+0) = (char)(I2C_COMMAND_CONTROL)& 0xff;
wuliqunyy 15:83bbc18cccbc 58 *(i2cMessage+1) = (char)(0x1D)& 0xff;
wuliqunyy 15:83bbc18cccbc 59 *(i2cMessage+2) = (char)(0xEA)& 0xff;
wuliqunyy 14:062850afdf38 60 return i2c_word_write(i2cMessage);
wuliqunyy 0:fe3c7dde9771 61 }
wuliqunyy 0:fe3c7dde9771 62
wuliqunyy 16:a0bfe33f8a4a 63 /** i2c enter MLX key to open I2C MLX configuration mode entry
wuliqunyy 16:a0bfe33f8a4a 64 */
wuliqunyy 16:a0bfe33f8a4a 65 int i2c_mbed_fpga::i2c_mlx_mode_entry(){
wuliqunyy 16:a0bfe33f8a4a 66 int ack = 0;
wuliqunyy 16:a0bfe33f8a4a 67 char i2cMessage[3];
wuliqunyy 16:a0bfe33f8a4a 68 *(i2cMessage+0) = (char)(I2C_COMMAND_CONTROL)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 69 *(i2cMessage+1) = (char)(0x35)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 70 *(i2cMessage+2) = (char)(0x4B)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 71 ack += i2c_word_write(i2cMessage);
wuliqunyy 16:a0bfe33f8a4a 72 *(i2cMessage+0) = (char)(I2C_COMMAND_KEY)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 73 *(i2cMessage+1) = (char)(0x65)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 74 *(i2cMessage+2) = (char)(0xA9)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 75 ack += i2c_word_write(i2cMessage);
wuliqunyy 16:a0bfe33f8a4a 76
wuliqunyy 16:a0bfe33f8a4a 77 return ack;
wuliqunyy 16:a0bfe33f8a4a 78 }
wuliqunyy 16:a0bfe33f8a4a 79
wuliqunyy 16:a0bfe33f8a4a 80
wuliqunyy 15:83bbc18cccbc 81 /** i2c ram start up flag set to skip OTP copy
wuliqunyy 0:fe3c7dde9771 82 */
wuliqunyy 15:83bbc18cccbc 83 int i2c_mbed_fpga::i2c_skip_app_copy(){
wuliqunyy 14:062850afdf38 84 char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 85 *(i2cMessage+0) = (char)(I2C_STARTUP_FLAGS_1)& 0xff;
wuliqunyy 15:83bbc18cccbc 86 *(i2cMessage+1) = (char)(0x05)& 0xff;
wuliqunyy 15:83bbc18cccbc 87 *(i2cMessage+2) = (char)(0x00)& 0xff;
wuliqunyy 14:062850afdf38 88 return i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 89 }
wuliqunyy 12:9f8c7f4da5f6 90
wuliqunyy 15:83bbc18cccbc 91 /** i2c soft reset
wuliqunyy 15:83bbc18cccbc 92 */
wuliqunyy 15:83bbc18cccbc 93 int i2c_mbed_fpga::i2c_soft_reset(){
wuliqunyy 15:83bbc18cccbc 94 char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 95 *(i2cMessage+0) = (char)(I2C_COMMAND_CONTROL)& 0xff;
wuliqunyy 15:83bbc18cccbc 96 *(i2cMessage+1) = (char)(0xC1)& 0xff;
wuliqunyy 15:83bbc18cccbc 97 *(i2cMessage+2) = (char)(0xA0)& 0xff;
wuliqunyy 15:83bbc18cccbc 98 return i2c_word_write(i2cMessage);
wuliqunyy 15:83bbc18cccbc 99 }
wuliqunyy 15:83bbc18cccbc 100
wuliqunyy 15:83bbc18cccbc 101
wuliqunyy 12:9f8c7f4da5f6 102 /** i2c to set the 50k PWM
wuliqunyy 12:9f8c7f4da5f6 103 */
wuliqunyy 12:9f8c7f4da5f6 104 int i2c_mbed_fpga::i2c_set_50k_pwm(unsigned int pwm50k){
wuliqunyy 15:83bbc18cccbc 105 nv_gen_ctrl_val &= ~NV_PWM_50K_MASK;
wuliqunyy 15:83bbc18cccbc 106 nv_gen_ctrl_val |= pwm50k << NV_PWM_50K_OFFSET;
wuliqunyy 14:062850afdf38 107 char i2cMessage[3];
wuliqunyy 14:062850afdf38 108 *(i2cMessage+0) = (char)(I2C_GEN_CTRL >> 0)& 0xff;
wuliqunyy 14:062850afdf38 109 *(i2cMessage+1) = (char)(nv_gen_ctrl_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 110 *(i2cMessage+2) = (char)(nv_gen_ctrl_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 111 return i2c_word_write(i2cMessage);
wuliqunyy 0:fe3c7dde9771 112 }
wuliqunyy 6:019ab407ac3c 113
wuliqunyy 12:9f8c7f4da5f6 114
wuliqunyy 12:9f8c7f4da5f6 115
wuliqunyy 6:019ab407ac3c 116 /** i2c to set the Postion Pulse width
wuliqunyy 6:019ab407ac3c 117 */
wuliqunyy 6:019ab407ac3c 118 int i2c_mbed_fpga::i2c_set_position_pulse_width(unsigned int mantisaa_2b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 119 nv_positin_val &= ~NV_POSITION_PULSE_TIME_MASK;
wuliqunyy 6:019ab407ac3c 120 nv_positin_val |= ((exponent_3b << 2) | mantisaa_2b) << NV_POSITION_PULSE_TIME_OFFSET;
wuliqunyy 14:062850afdf38 121 char i2cMessage[3];
wuliqunyy 14:062850afdf38 122 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 123 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 124 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 125 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 126 }
wuliqunyy 6:019ab407ac3c 127
wuliqunyy 20:26e934452728 128 /** i2c to set the Postion Flat width
wuliqunyy 20:26e934452728 129 */
wuliqunyy 20:26e934452728 130 int i2c_mbed_fpga::i2c_set_position_flat(unsigned int mantisaa_2b, unsigned int exponent_3b){
wuliqunyy 20:26e934452728 131 nv_positin2_val &= ~NV_POSITION_FLAT_TIME_MASK;
wuliqunyy 20:26e934452728 132 nv_positin2_val |= ((exponent_3b << 2) | mantisaa_2b) << NV_POSITION_FLAT_TIME_OFFSET;
wuliqunyy 20:26e934452728 133 char i2cMessage[3];
wuliqunyy 20:26e934452728 134 *(i2cMessage+0) = (char)(I2C_POSITION2 >> 0)& 0xff;
wuliqunyy 20:26e934452728 135 *(i2cMessage+1) = (char)(nv_positin2_val >> 8)& 0xff;
wuliqunyy 20:26e934452728 136 *(i2cMessage+2) = (char)(nv_positin2_val >> 0)& 0xff;
wuliqunyy 20:26e934452728 137 return i2c_word_write(i2cMessage);
wuliqunyy 20:26e934452728 138 }
wuliqunyy 20:26e934452728 139
wuliqunyy 20:26e934452728 140
wuliqunyy 20:26e934452728 141
wuliqunyy 20:26e934452728 142
wuliqunyy 6:019ab407ac3c 143 /** i2c to set the Postion Pulse duty cycle
wuliqunyy 6:019ab407ac3c 144 */
wuliqunyy 6:019ab407ac3c 145 int i2c_mbed_fpga::i2c_set_position_duty(unsigned int duty_2b){
wuliqunyy 6:019ab407ac3c 146 nv_positin_val &= ~NV_POSITION_DUTY_MASK;
wuliqunyy 6:019ab407ac3c 147 nv_positin_val |= duty_2b << NV_POSITION_DUTY_OFFSET;
wuliqunyy 14:062850afdf38 148 char i2cMessage[3];
wuliqunyy 14:062850afdf38 149 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 150 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 151 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 152 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 153 }
wuliqunyy 6:019ab407ac3c 154
wuliqunyy 6:019ab407ac3c 155 /** i2c to enable the Postion Pulse majority volting
wuliqunyy 6:019ab407ac3c 156 */
wuliqunyy 6:019ab407ac3c 157 int i2c_mbed_fpga::i2c_set_position_maj_vote(unsigned int maj_1b){
wuliqunyy 6:019ab407ac3c 158 nv_positin_val &= ~NV_POSI_MAJO_VOTE_MASK;
wuliqunyy 6:019ab407ac3c 159 nv_positin_val |= maj_1b << NV_POSI_MAJO_VOTE_OFFSET;
wuliqunyy 14:062850afdf38 160 char i2cMessage[3];
wuliqunyy 14:062850afdf38 161 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 162 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 163 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 164 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 165 }
wuliqunyy 6:019ab407ac3c 166
wuliqunyy 6:019ab407ac3c 167 /** i2c to set the anti-cogging rotation direction
wuliqunyy 6:019ab407ac3c 168 */
wuliqunyy 6:019ab407ac3c 169 int i2c_mbed_fpga::i2c_set_position_anti_cog(unsigned int cog_1b){
wuliqunyy 6:019ab407ac3c 170 nv_positin_val &= ~NV_ANTI_COG_MASK;
wuliqunyy 6:019ab407ac3c 171 nv_positin_val |= cog_1b << NV_ANTI_COG_OFFSET;
wuliqunyy 14:062850afdf38 172 char i2cMessage[3];
wuliqunyy 14:062850afdf38 173 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 174 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 175 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 176 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 177 }
wuliqunyy 6:019ab407ac3c 178
wuliqunyy 6:019ab407ac3c 179
wuliqunyy 6:019ab407ac3c 180 /** i2c to set the Start Up Pulse width (pulse train)
wuliqunyy 6:019ab407ac3c 181 */
wuliqunyy 6:019ab407ac3c 182 int i2c_mbed_fpga::i2c_set_start_up_pulse_width(unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 183 nv_start_up_val &= ~NV_START_UP_TIME_MASK;
wuliqunyy 8:2554218db1e6 184 nv_start_up_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_START_UP_TIME_OFFSET;
wuliqunyy 14:062850afdf38 185 char i2cMessage[3];
wuliqunyy 14:062850afdf38 186 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 187 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 188 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 189 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 190 }
wuliqunyy 6:019ab407ac3c 191
wuliqunyy 20:26e934452728 192 /** i2c to set the Start Up Flat width
wuliqunyy 20:26e934452728 193 */
wuliqunyy 20:26e934452728 194 int i2c_mbed_fpga::i2c_set_start_up_flat(unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 20:26e934452728 195 nv_positin2_val &= ~NV_START_UP_FLAT_TIME_MASK;
wuliqunyy 20:26e934452728 196 nv_positin2_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_START_UP_FLAT_TIME_OFFSET;
wuliqunyy 20:26e934452728 197 char i2cMessage[3];
wuliqunyy 20:26e934452728 198 *(i2cMessage+0) = (char)(I2C_POSITION2 >> 0)& 0xff;
wuliqunyy 20:26e934452728 199 *(i2cMessage+1) = (char)(nv_positin2_val >> 8)& 0xff;
wuliqunyy 20:26e934452728 200 *(i2cMessage+2) = (char)(nv_positin2_val >> 0)& 0xff;
wuliqunyy 20:26e934452728 201 return i2c_word_write(i2cMessage);
wuliqunyy 20:26e934452728 202 }
wuliqunyy 20:26e934452728 203
wuliqunyy 20:26e934452728 204
wuliqunyy 20:26e934452728 205
wuliqunyy 6:019ab407ac3c 206 /** i2c to set the Start up Pulse duty cycle (pulse train)
wuliqunyy 6:019ab407ac3c 207 */
wuliqunyy 6:019ab407ac3c 208 int i2c_mbed_fpga::i2c_set_start_up_duty(unsigned int duty_2b){
wuliqunyy 6:019ab407ac3c 209 nv_start_up_val &= ~NV_START_DUTY_MASK;
wuliqunyy 6:019ab407ac3c 210 nv_start_up_val |= duty_2b << NV_START_DUTY_OFFSET;
wuliqunyy 14:062850afdf38 211 char i2cMessage[3];
wuliqunyy 14:062850afdf38 212 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 213 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 214 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 215 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 216 }
wuliqunyy 6:019ab407ac3c 217
wuliqunyy 6:019ab407ac3c 218 /** i2c to set the Start up commutation number of EHPs (pulse train)
wuliqunyy 6:019ab407ac3c 219 */
wuliqunyy 6:019ab407ac3c 220 int i2c_mbed_fpga::i2c_set_start_up_num_comm(unsigned int comm){
wuliqunyy 6:019ab407ac3c 221 nv_start_up_val &= ~NV_COMM_START_NUM_MASK;
wuliqunyy 6:019ab407ac3c 222 nv_start_up_val |= comm << NV_COMM_START_NUM_OFFSET;
wuliqunyy 14:062850afdf38 223 char i2cMessage[3];
wuliqunyy 14:062850afdf38 224 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 225 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 226 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 227 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 228 }
wuliqunyy 6:019ab407ac3c 229
wuliqunyy 6:019ab407ac3c 230 /** i2c to set the Soft Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 231 */
wuliqunyy 6:019ab407ac3c 232 int i2c_mbed_fpga::i2c_set_soft_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b, unsigned int step_size, unsigned int num_steps){
wuliqunyy 6:019ab407ac3c 233 int ack = 0;
wuliqunyy 6:019ab407ac3c 234 nv_start_up_val &= ~NV_SOFT_START_MASK;
wuliqunyy 6:019ab407ac3c 235 nv_start_up_val |= enbale << NV_SOFT_START_OFFSET;
wuliqunyy 6:019ab407ac3c 236 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 237 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 6:019ab407ac3c 238 nv_start_up_val &= ~NV_SOFT_STEP_SIZE_MASK;
wuliqunyy 6:019ab407ac3c 239 nv_start_up_val |= step_size << NV_SOFT_STEP_SIZE_OFFSET;
wuliqunyy 6:019ab407ac3c 240 nv_wind_brake_val &= ~NV_SOFT_NUM_STEP_MASK;
wuliqunyy 6:019ab407ac3c 241 nv_wind_brake_val |= num_steps << NV_SOFT_NUM_STEP_OFFSET;
wuliqunyy 14:062850afdf38 242 char i2cMessage[3];
wuliqunyy 14:062850afdf38 243 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 244 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 245 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 246 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 247 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 248 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 249 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 250 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 251 *(i2cMessage+0) = (char)(I2C_WIND_BRAKE >> 0)& 0xff;
wuliqunyy 14:062850afdf38 252 *(i2cMessage+1) = (char)(nv_wind_brake_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 253 *(i2cMessage+2) = (char)(nv_wind_brake_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 254 ack += i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 255
wuliqunyy 6:019ab407ac3c 256 return ack;
wuliqunyy 6:019ab407ac3c 257 }
wuliqunyy 6:019ab407ac3c 258
wuliqunyy 6:019ab407ac3c 259 /** i2c to set the High Torque Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 260 */
wuliqunyy 6:019ab407ac3c 261 int i2c_mbed_fpga::i2c_set_high_torque_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 262 int ack = 0;
wuliqunyy 6:019ab407ac3c 263 nv_start_up_val &= ~NV_LONG_START_MASK;
wuliqunyy 6:019ab407ac3c 264 nv_start_up_val |= enbale << NV_LONG_START_OFFSET;
wuliqunyy 6:019ab407ac3c 265 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 266 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 14:062850afdf38 267 char i2cMessage[3];
wuliqunyy 14:062850afdf38 268 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 269 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 270 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 271 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 272 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 273 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 274 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 275 ack += i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 276
wuliqunyy 6:019ab407ac3c 277 return ack;
wuliqunyy 6:019ab407ac3c 278 }
wuliqunyy 6:019ab407ac3c 279
wuliqunyy 6:019ab407ac3c 280 /** i2c to set the Single Pulse Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 281 */
wuliqunyy 6:019ab407ac3c 282 int i2c_mbed_fpga::i2c_set_single_pulse_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 283 int ack = 0;
wuliqunyy 6:019ab407ac3c 284 nv_start_up_val &= ~NV_SINGLE_PULSE_START_MASK;
wuliqunyy 6:019ab407ac3c 285 nv_start_up_val |= enbale << NV_SINGLE_PULSE_START_OFFSET;
wuliqunyy 6:019ab407ac3c 286 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 287 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 14:062850afdf38 288 char i2cMessage[3];
wuliqunyy 14:062850afdf38 289 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 290 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 291 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 292 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 293 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 294 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 295 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 296 ack += i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 297
wuliqunyy 6:019ab407ac3c 298 return ack;
wuliqunyy 9:76a0b9f29a2d 299 }
wuliqunyy 9:76a0b9f29a2d 300
wuliqunyy 14:062850afdf38 301 /** i2c to set the rough regulation gain
wuliqunyy 12:9f8c7f4da5f6 302 */
wuliqunyy 17:d7207b1132be 303 int i2c_mbed_fpga::i2c_force_rough_reg(unsigned int reg){
wuliqunyy 17:d7207b1132be 304 int ack = 0;
wuliqunyy 17:d7207b1132be 305 nv_gen_ctrl_val &= ~NV_ROUGH_REG_MASK;
wuliqunyy 17:d7207b1132be 306 nv_gen_ctrl_val |= reg << NV_ROUGH_REG_OFFSET;
wuliqunyy 17:d7207b1132be 307 char i2cMessage[3];
wuliqunyy 17:d7207b1132be 308 *(i2cMessage+0)= (char)(I2C_GEN_CTRL >> 0)& 0xff;
wuliqunyy 17:d7207b1132be 309 *(i2cMessage+1)= (char)(nv_gen_ctrl_val >> 8)& 0xff;
wuliqunyy 17:d7207b1132be 310 *(i2cMessage+2)= (char)(nv_gen_ctrl_val >> 0)& 0xff;
wuliqunyy 17:d7207b1132be 311 ack += i2c_word_write(i2cMessage);
wuliqunyy 17:d7207b1132be 312
wuliqunyy 17:d7207b1132be 313 return ack;
wuliqunyy 17:d7207b1132be 314 }
wuliqunyy 17:d7207b1132be 315
wuliqunyy 17:d7207b1132be 316 /** i2c to set the rough regulation gain
wuliqunyy 17:d7207b1132be 317 */
wuliqunyy 12:9f8c7f4da5f6 318 int i2c_mbed_fpga::i2c_set_rough_gain(unsigned int rough_gain){
wuliqunyy 12:9f8c7f4da5f6 319 int ack = 0;
wuliqunyy 12:9f8c7f4da5f6 320 nv_gen_ctrl_val &= ~NV_ROUGH_GAIN_MASK;
wuliqunyy 12:9f8c7f4da5f6 321 nv_gen_ctrl_val |= rough_gain << NV_ROUGH_GAIN_OFFSET;
wuliqunyy 14:062850afdf38 322 char i2cMessage[3];
wuliqunyy 14:062850afdf38 323 *(i2cMessage+0)= (char)(I2C_GEN_CTRL >> 0)& 0xff;
wuliqunyy 14:062850afdf38 324 *(i2cMessage+1)= (char)(nv_gen_ctrl_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 325 *(i2cMessage+2)= (char)(nv_gen_ctrl_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 326 ack += i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 327
wuliqunyy 12:9f8c7f4da5f6 328 return ack;
wuliqunyy 12:9f8c7f4da5f6 329 }
wuliqunyy 12:9f8c7f4da5f6 330
wuliqunyy 14:062850afdf38 331 /** i2c to set the ehp regulation gain
wuliqunyy 14:062850afdf38 332 */
wuliqunyy 14:062850afdf38 333 int i2c_mbed_fpga::i2c_set_ehp_reg_gain(unsigned int ehp_gain){
wuliqunyy 14:062850afdf38 334 int ack = 0;
wuliqunyy 14:062850afdf38 335 nv_gen_ctrl_val &= ~NV_EHP_REG_GAIN_MASK;
wuliqunyy 14:062850afdf38 336 nv_gen_ctrl_val |= ehp_gain << NV_EHP_REG_GAIN_OFFSET;
wuliqunyy 14:062850afdf38 337 char i2cMessage[3];
wuliqunyy 14:062850afdf38 338 *(i2cMessage+0)= (char)(I2C_GEN_CTRL >> 0)& 0xff;
wuliqunyy 14:062850afdf38 339 *(i2cMessage+1)= (char)(nv_gen_ctrl_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 340 *(i2cMessage+2)= (char)(nv_gen_ctrl_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 341 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 342
wuliqunyy 14:062850afdf38 343 return ack;
wuliqunyy 14:062850afdf38 344 }
wuliqunyy 14:062850afdf38 345
wuliqunyy 14:062850afdf38 346 /** i2c to set the ehp regulation gain
wuliqunyy 14:062850afdf38 347 */
wuliqunyy 14:062850afdf38 348 int i2c_mbed_fpga::i2c_set_fall_time_blank(unsigned int blank_time){
wuliqunyy 14:062850afdf38 349 int ack = 0;
wuliqunyy 15:83bbc18cccbc 350 nv_dig_config_val &= ~NV_FLAT_BLANK_MASK;
wuliqunyy 15:83bbc18cccbc 351 nv_dig_config_val |= blank_time << NV_FLAT_BLANK_OFFSET;
wuliqunyy 14:062850afdf38 352 char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 353 *(i2cMessage+0)= (char)(I2C_DIGITAL_CFG >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 354 *(i2cMessage+1)= (char)(nv_dig_config_val >> 8)& 0xff;
wuliqunyy 15:83bbc18cccbc 355 *(i2cMessage+2)= (char)(nv_dig_config_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 356 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 357
wuliqunyy 14:062850afdf38 358 return ack;
wuliqunyy 14:062850afdf38 359 }
wuliqunyy 12:9f8c7f4da5f6 360
wuliqunyy 12:9f8c7f4da5f6 361
wuliqunyy 12:9f8c7f4da5f6 362 /** i2c to set the current threshold for I_didt
wuliqunyy 12:9f8c7f4da5f6 363 */
wuliqunyy 12:9f8c7f4da5f6 364 int i2c_mbed_fpga::i2c_set_comm_i_thres(unsigned int i_thr_low, unsigned int i_thr_high){
wuliqunyy 12:9f8c7f4da5f6 365 int ack = 0;
wuliqunyy 15:83bbc18cccbc 366 nv_i_zc_th_low_val &= ~NV_I_ZC_TH_LOW_MASK;
wuliqunyy 15:83bbc18cccbc 367 nv_i_zc_th_low_val |= i_thr_low << NV_I_ZC_TH_LOW_OFFSET;
wuliqunyy 15:83bbc18cccbc 368 nv_i_zc_th_high_val &= ~NV_I_ZC_TH_HIGH_MASK;
wuliqunyy 15:83bbc18cccbc 369 nv_i_zc_th_high_val |= i_thr_high << NV_I_ZC_TH_HIGH_OFFSET;
wuliqunyy 14:062850afdf38 370 char i2cMessage[3];
wuliqunyy 20:26e934452728 371 *(i2cMessage+0) = (char)(I2C_I_ZC_TH_LOW_REG >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 372 *(i2cMessage+1) = (char)(nv_i_zc_th_low_val >> 8)& 0xff;
wuliqunyy 15:83bbc18cccbc 373 *(i2cMessage+2) = (char)(nv_i_zc_th_low_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 374 ack += i2c_word_write(i2cMessage);
wuliqunyy 20:26e934452728 375 *(i2cMessage+0) = (char)(I2C_I_ZC_TH_HIGH_REG >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 376 *(i2cMessage+1) = (char)(nv_i_zc_th_high_val >> 8)& 0xff;
wuliqunyy 15:83bbc18cccbc 377 *(i2cMessage+2) = (char)(nv_i_zc_th_high_val >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 378 ack += i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 379 return ack;
wuliqunyy 12:9f8c7f4da5f6 380 }
wuliqunyy 12:9f8c7f4da5f6 381
wuliqunyy 12:9f8c7f4da5f6 382 /** i2c to set the di current threshold for didt
wuliqunyy 12:9f8c7f4da5f6 383 */
wuliqunyy 12:9f8c7f4da5f6 384 int i2c_mbed_fpga::i2c_set_comm_di_thres(unsigned int di_1st, unsigned int di_2nd){
wuliqunyy 12:9f8c7f4da5f6 385 int ack = 0;
wuliqunyy 15:83bbc18cccbc 386 nv_di_th_1st_val &= ~NV_DI_TH_1ST_MASK;
wuliqunyy 15:83bbc18cccbc 387 nv_di_th_1st_val |= di_1st << NV_DI_TH_1ST_OFFSET;
wuliqunyy 15:83bbc18cccbc 388 nv_di_th_2nd_val &= ~NV_DI_TH_2ND_MASK;
wuliqunyy 15:83bbc18cccbc 389 nv_di_th_2nd_val |= di_2nd << NV_DI_TH_2ND_OFFSET;
wuliqunyy 14:062850afdf38 390 char i2cMessage[3];
wuliqunyy 20:26e934452728 391 *(i2cMessage+0) = (char)(I2C_DI_TH_1ST_REG >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 392 *(i2cMessage+1) = (char)(nv_di_th_1st_val >> 8)& 0xff;
wuliqunyy 15:83bbc18cccbc 393 *(i2cMessage+2) = (char)(nv_di_th_1st_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 394 ack += i2c_word_write(i2cMessage);
wuliqunyy 20:26e934452728 395 *(i2cMessage+0) = (char)(I2C_DI_TH_2ND_REG >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 396 *(i2cMessage+1) = (char)(nv_di_th_2nd_val >> 8)& 0xff;
wuliqunyy 15:83bbc18cccbc 397 *(i2cMessage+2) = (char)(nv_di_th_2nd_val >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 398 ack += i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 399 return ack;
wuliqunyy 12:9f8c7f4da5f6 400 }
wuliqunyy 12:9f8c7f4da5f6 401
wuliqunyy 12:9f8c7f4da5f6 402
wuliqunyy 12:9f8c7f4da5f6 403
wuliqunyy 12:9f8c7f4da5f6 404
wuliqunyy 11:b86aea372744 405 /** i2c to clean the I2C controller settins
wuliqunyy 11:b86aea372744 406 */
wuliqunyy 11:b86aea372744 407 int i2c_mbed_fpga::i2c_clear_spd_ctrl(){
wuliqunyy 11:b86aea372744 408 int ack = 0;
wuliqunyy 11:b86aea372744 409 nv_spd_control_1_val = 0;
wuliqunyy 11:b86aea372744 410 nv_spd_control_2_val = 0;
wuliqunyy 14:062850afdf38 411 char i2cMessage[3];
wuliqunyy 14:062850afdf38 412 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_1 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 413 *(i2cMessage+1) = (char)(nv_spd_control_1_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 414 *(i2cMessage+2) = (char)(nv_spd_control_1_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 415 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 416 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_2 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 417 *(i2cMessage+1) = (char)(nv_spd_control_2_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 418 *(i2cMessage+2) = (char)(nv_spd_control_2_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 419 ack += i2c_word_write(i2cMessage);
wuliqunyy 11:b86aea372744 420
wuliqunyy 11:b86aea372744 421 return ack;
wuliqunyy 11:b86aea372744 422 }
wuliqunyy 11:b86aea372744 423
wuliqunyy 14:062850afdf38 424 /** i2c to set the I2C speed input mode
wuliqunyy 14:062850afdf38 425 */
wuliqunyy 14:062850afdf38 426 int i2c_mbed_fpga::i2c_set_input_mode(unsigned int mode){
wuliqunyy 14:062850afdf38 427 int ack = 0;
wuliqunyy 14:062850afdf38 428 nv_application_cfg_val &= ~NV_INPUT_MODE_CFG_MASK;
wuliqunyy 14:062850afdf38 429 nv_application_cfg_val |= mode << NV_INPUT_MODE_CFG_OFFSET;
wuliqunyy 14:062850afdf38 430 char i2cMessage[3];
wuliqunyy 14:062850afdf38 431 *(i2cMessage+0) = (char)(I2C_APPLICATION_CFG >> 0)& 0xff;
wuliqunyy 14:062850afdf38 432 *(i2cMessage+1) = (char)(nv_application_cfg_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 433 *(i2cMessage+2) = (char)(nv_application_cfg_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 434 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 435 return ack;
wuliqunyy 14:062850afdf38 436 }
wuliqunyy 14:062850afdf38 437
wuliqunyy 14:062850afdf38 438
wuliqunyy 11:b86aea372744 439
wuliqunyy 9:76a0b9f29a2d 440 /** i2c to set the open loop mode
wuliqunyy 9:76a0b9f29a2d 441 */
wuliqunyy 9:76a0b9f29a2d 442 int i2c_mbed_fpga::i2c_set_loop_mode(unsigned int openloop){
wuliqunyy 9:76a0b9f29a2d 443 int ack = 0;
wuliqunyy 9:76a0b9f29a2d 444 nv_spd_control_1_val &= ~NV_SPD_LOOP_MODE_MASK;
wuliqunyy 9:76a0b9f29a2d 445 nv_spd_control_1_val |= openloop << NV_SPD_LOOP_MODE_OFFSET;
wuliqunyy 14:062850afdf38 446 char i2cMessage[3];
wuliqunyy 14:062850afdf38 447 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_1 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 448 *(i2cMessage+1) = (char)(nv_spd_control_1_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 449 *(i2cMessage+2) = (char)(nv_spd_control_1_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 450 ack += i2c_word_write(i2cMessage);
wuliqunyy 9:76a0b9f29a2d 451
wuliqunyy 9:76a0b9f29a2d 452 return ack;
wuliqunyy 9:76a0b9f29a2d 453 }
wuliqunyy 9:76a0b9f29a2d 454
wuliqunyy 12:9f8c7f4da5f6 455 /** i2c to set the Single Pulse Start Up (pulse train)
wuliqunyy 12:9f8c7f4da5f6 456 */
wuliqunyy 12:9f8c7f4da5f6 457 int i2c_mbed_fpga::i2c_set_open_loop_duty(unsigned int duty){
wuliqunyy 12:9f8c7f4da5f6 458 int ack = 0;
wuliqunyy 12:9f8c7f4da5f6 459 ram_open_duty_val = duty;
wuliqunyy 14:062850afdf38 460 char i2cMessage[3];
wuliqunyy 14:062850afdf38 461 *(i2cMessage+0) = (char)(I2C_SPEED_DUTY)& 0xff;
wuliqunyy 14:062850afdf38 462 *(i2cMessage+1) = (char)(ram_open_duty_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 463 *(i2cMessage+2) = (char)(ram_open_duty_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 464 ack += i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 465
wuliqunyy 12:9f8c7f4da5f6 466 return ack;
wuliqunyy 12:9f8c7f4da5f6 467 }
wuliqunyy 12:9f8c7f4da5f6 468
wuliqunyy 11:b86aea372744 469 /** i2c to set the speed curve type
wuliqunyy 11:b86aea372744 470 */
wuliqunyy 11:b86aea372744 471 int i2c_mbed_fpga::i2c_set_curve_type(unsigned int curvetype){
wuliqunyy 11:b86aea372744 472 int ack = 0;
wuliqunyy 11:b86aea372744 473 nv_spd_control_1_val &= ~NV_CURVE_MODE_MASK;
wuliqunyy 11:b86aea372744 474 nv_spd_control_1_val |= curvetype << NV_CURVE_MODE_OFFSET;
wuliqunyy 14:062850afdf38 475 char i2cMessage[3];
wuliqunyy 14:062850afdf38 476 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_1 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 477 *(i2cMessage+1) = (char)(nv_spd_control_1_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 478 *(i2cMessage+2) = (char)(nv_spd_control_1_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 479 ack += i2c_word_write(i2cMessage);
wuliqunyy 11:b86aea372744 480
wuliqunyy 11:b86aea372744 481 return ack;
wuliqunyy 11:b86aea372744 482 }
wuliqunyy 11:b86aea372744 483
wuliqunyy 11:b86aea372744 484 /** i2c to set the open dc ini
wuliqunyy 11:b86aea372744 485 */
wuliqunyy 11:b86aea372744 486 int i2c_mbed_fpga::i2c_set_dc_ini(unsigned int ini){
wuliqunyy 11:b86aea372744 487 int ack = 0;
wuliqunyy 11:b86aea372744 488 nv_spd_control_2_val &= ~NV_DC_OPENLOOP_INI_MASK;
wuliqunyy 11:b86aea372744 489 nv_spd_control_2_val |= ini << NV_DC_OPENLOOP_INI_OFFSET;
wuliqunyy 14:062850afdf38 490 char i2cMessage[3];
wuliqunyy 14:062850afdf38 491 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_2 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 492 *(i2cMessage+1) = (char)(nv_spd_control_2_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 493 *(i2cMessage+2) = (char)(nv_spd_control_2_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 494 ack += i2c_word_write(i2cMessage);
wuliqunyy 11:b86aea372744 495
wuliqunyy 11:b86aea372744 496 return ack;
wuliqunyy 11:b86aea372744 497 }
wuliqunyy 11:b86aea372744 498
wuliqunyy 11:b86aea372744 499 /** i2c to set the open dc slew rate
wuliqunyy 11:b86aea372744 500 */
wuliqunyy 11:b86aea372744 501 int i2c_mbed_fpga::i2c_set_dc_sr(unsigned int sr){
wuliqunyy 11:b86aea372744 502 int ack = 0;
wuliqunyy 11:b86aea372744 503 nv_spd_control_2_val &= ~NV_DC_OPENLOOP_SR_MASK;
wuliqunyy 11:b86aea372744 504 nv_spd_control_2_val |= sr << NV_DC_OPENLOOP_SR_OFFSET;
wuliqunyy 14:062850afdf38 505 char i2cMessage[3];
wuliqunyy 14:062850afdf38 506 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_2 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 507 *(i2cMessage+1) = (char)(nv_spd_control_2_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 508 *(i2cMessage+2) = (char)(nv_spd_control_2_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 509 ack += i2c_word_write(i2cMessage);
wuliqunyy 11:b86aea372744 510
wuliqunyy 11:b86aea372744 511 return ack;
wuliqunyy 11:b86aea372744 512 }
wuliqunyy 11:b86aea372744 513
wuliqunyy 16:a0bfe33f8a4a 514 /** i2c to set the target CLIM during start up
wuliqunyy 16:a0bfe33f8a4a 515 */
wuliqunyy 16:a0bfe33f8a4a 516 int i2c_mbed_fpga::i2c_set_clim_start_up(unsigned int clim){
wuliqunyy 16:a0bfe33f8a4a 517 int ack = 0;
wuliqunyy 16:a0bfe33f8a4a 518 nv_clim_user_1_val &= ~NV_TARGET_CLIM_USER_PULSES_MASK;
wuliqunyy 16:a0bfe33f8a4a 519 nv_clim_user_1_val |= clim << NV_TARGET_CLIM_USER_PULSES_OFFSET;
wuliqunyy 16:a0bfe33f8a4a 520 char i2cMessage[3];
wuliqunyy 16:a0bfe33f8a4a 521 *(i2cMessage+0) = (char)(I2C_CLIM_USER_1 >> 0)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 522 *(i2cMessage+1) = (char)(nv_clim_user_1_val >> 8)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 523 *(i2cMessage+2) = (char)(nv_clim_user_1_val >> 0)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 524 ack += i2c_word_write(i2cMessage);
wuliqunyy 16:a0bfe33f8a4a 525
wuliqunyy 16:a0bfe33f8a4a 526 return ack;
wuliqunyy 16:a0bfe33f8a4a 527 }
wuliqunyy 12:9f8c7f4da5f6 528
wuliqunyy 16:a0bfe33f8a4a 529 /** i2c to set the target CLIM during brake
wuliqunyy 16:a0bfe33f8a4a 530 */
wuliqunyy 16:a0bfe33f8a4a 531 int i2c_mbed_fpga::i2c_set_clim_brake(unsigned int clim){
wuliqunyy 16:a0bfe33f8a4a 532 int ack = 0;
wuliqunyy 16:a0bfe33f8a4a 533 nv_clim_user_0_val &= ~NV_TARGET_CLIM_USER_BRAKE_MASK;
wuliqunyy 16:a0bfe33f8a4a 534 nv_clim_user_0_val |= clim << NV_TARGET_CLIM_USER_BRAKE_OFFSET;
wuliqunyy 16:a0bfe33f8a4a 535 char i2cMessage[3];
wuliqunyy 16:a0bfe33f8a4a 536 *(i2cMessage+0) = (char)(I2C_CLIM_USER_0 >> 0)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 537 *(i2cMessage+1) = (char)(nv_clim_user_0_val >> 8)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 538 *(i2cMessage+2) = (char)(nv_clim_user_0_val >> 0)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 539 ack += i2c_word_write(i2cMessage);
wuliqunyy 16:a0bfe33f8a4a 540
wuliqunyy 16:a0bfe33f8a4a 541 return ack;
wuliqunyy 16:a0bfe33f8a4a 542 }
wuliqunyy 16:a0bfe33f8a4a 543
wuliqunyy 16:a0bfe33f8a4a 544 /** i2c to set the target CLIM during run time
wuliqunyy 16:a0bfe33f8a4a 545 */
wuliqunyy 16:a0bfe33f8a4a 546 int i2c_mbed_fpga::i2c_set_clim_run_time(unsigned int clim){
wuliqunyy 16:a0bfe33f8a4a 547 int ack = 0;
wuliqunyy 16:a0bfe33f8a4a 548 nv_clim_user_0_val &= ~NV_TARGET_CLIM_USER_MOTOR_MASK;
wuliqunyy 16:a0bfe33f8a4a 549 nv_clim_user_0_val |= clim << NV_TARGET_CLIM_USER_MOTOR_OFFSET;
wuliqunyy 16:a0bfe33f8a4a 550 char i2cMessage[3];
wuliqunyy 16:a0bfe33f8a4a 551 *(i2cMessage+0) = (char)(I2C_CLIM_USER_0 >> 0)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 552 *(i2cMessage+1) = (char)(nv_clim_user_0_val >> 8)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 553 *(i2cMessage+2) = (char)(nv_clim_user_0_val >> 0)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 554 ack += i2c_word_write(i2cMessage);
wuliqunyy 16:a0bfe33f8a4a 555
wuliqunyy 16:a0bfe33f8a4a 556 return ack;
wuliqunyy 16:a0bfe33f8a4a 557 }
wuliqunyy 16:a0bfe33f8a4a 558
wuliqunyy 16:a0bfe33f8a4a 559
wuliqunyy 16:a0bfe33f8a4a 560 /** i2c to read I2C_CLIM_CALIB
wuliqunyy 16:a0bfe33f8a4a 561 */
wuliqunyy 16:a0bfe33f8a4a 562