Abdulaziz alsalloum / Project1HomeAlertSystem

Home Alert System

Dependencies:   PWM_Tone_Library DHT

mbed/TARGET_K64F/MK64F12.h@5:569a4894abc1, 2019-03-08 (annotated)

Committer:
aziz111
Date:
Fri Mar 08 17:15:02 2019 +0000
Revision:
5:569a4894abc1
Parent:
3:78f223d34f36 
Final

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ethaderu 3:78f223d34f36 1 /*
ethaderu 3:78f223d34f36 2 ** ###################################################################
ethaderu 3:78f223d34f36 3 ** Processors: MK64FN1M0VDC12
ethaderu 3:78f223d34f36 4 ** MK64FN1M0VLL12
ethaderu 3:78f223d34f36 5 ** MK64FN1M0VLQ12
ethaderu 3:78f223d34f36 6 ** MK64FN1M0VMD12
ethaderu 3:78f223d34f36 7 **
ethaderu 3:78f223d34f36 8 ** Compilers: Keil ARM C/C++ Compiler
ethaderu 3:78f223d34f36 9 ** Freescale C/C++ for Embedded ARM
ethaderu 3:78f223d34f36 10 ** GNU C Compiler
ethaderu 3:78f223d34f36 11 ** GNU C Compiler - CodeSourcery Sourcery G++
ethaderu 3:78f223d34f36 12 ** IAR ANSI C/C++ Compiler for ARM
ethaderu 3:78f223d34f36 13 **
ethaderu 3:78f223d34f36 14 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
ethaderu 3:78f223d34f36 15 ** Version: rev. 2.5, 2014-02-10
ethaderu 3:78f223d34f36 16 ** Build: b140604
ethaderu 3:78f223d34f36 17 **
ethaderu 3:78f223d34f36 18 ** Abstract:
ethaderu 3:78f223d34f36 19 ** CMSIS Peripheral Access Layer for MK64F12
ethaderu 3:78f223d34f36 20 **
ethaderu 3:78f223d34f36 21 ** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc.
ethaderu 3:78f223d34f36 22 ** All rights reserved.
ethaderu 3:78f223d34f36 23 **
ethaderu 3:78f223d34f36 24 ** Redistribution and use in source and binary forms, with or without modification,
ethaderu 3:78f223d34f36 25 ** are permitted provided that the following conditions are met:
ethaderu 3:78f223d34f36 26 **
ethaderu 3:78f223d34f36 27 ** o Redistributions of source code must retain the above copyright notice, this list
ethaderu 3:78f223d34f36 28 ** of conditions and the following disclaimer.
ethaderu 3:78f223d34f36 29 **
ethaderu 3:78f223d34f36 30 ** o Redistributions in binary form must reproduce the above copyright notice, this
ethaderu 3:78f223d34f36 31 ** list of conditions and the following disclaimer in the documentation and/or
ethaderu 3:78f223d34f36 32 ** other materials provided with the distribution.
ethaderu 3:78f223d34f36 33 **
ethaderu 3:78f223d34f36 34 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
ethaderu 3:78f223d34f36 35 ** contributors may be used to endorse or promote products derived from this
ethaderu 3:78f223d34f36 36 ** software without specific prior written permission.
ethaderu 3:78f223d34f36 37 **
ethaderu 3:78f223d34f36 38 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ethaderu 3:78f223d34f36 39 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
ethaderu 3:78f223d34f36 40 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ethaderu 3:78f223d34f36 41 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ethaderu 3:78f223d34f36 42 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
ethaderu 3:78f223d34f36 43 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
ethaderu 3:78f223d34f36 44 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ethaderu 3:78f223d34f36 45 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
ethaderu 3:78f223d34f36 46 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
ethaderu 3:78f223d34f36 47 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ethaderu 3:78f223d34f36 48 **
ethaderu 3:78f223d34f36 49 ** http: www.freescale.com
ethaderu 3:78f223d34f36 50 ** mail: support@freescale.com
ethaderu 3:78f223d34f36 51 **
ethaderu 3:78f223d34f36 52 ** Revisions:
ethaderu 3:78f223d34f36 53 ** - rev. 1.0 (2013-08-12)
ethaderu 3:78f223d34f36 54 ** Initial version.
ethaderu 3:78f223d34f36 55 ** - rev. 2.0 (2013-10-29)
ethaderu 3:78f223d34f36 56 ** Register accessor macros added to the memory map.
ethaderu 3:78f223d34f36 57 ** Symbols for Processor Expert memory map compatibility added to the memory map.
ethaderu 3:78f223d34f36 58 ** Startup file for gcc has been updated according to CMSIS 3.2.
ethaderu 3:78f223d34f36 59 ** System initialization updated.
ethaderu 3:78f223d34f36 60 ** MCG - registers updated.
ethaderu 3:78f223d34f36 61 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
ethaderu 3:78f223d34f36 62 ** - rev. 2.1 (2013-10-30)
ethaderu 3:78f223d34f36 63 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
ethaderu 3:78f223d34f36 64 ** - rev. 2.2 (2013-12-09)
ethaderu 3:78f223d34f36 65 ** DMA - EARS register removed.
ethaderu 3:78f223d34f36 66 ** AIPS0, AIPS1 - MPRA register updated.
ethaderu 3:78f223d34f36 67 ** - rev. 2.3 (2014-01-24)
ethaderu 3:78f223d34f36 68 ** Update according to reference manual rev. 2
ethaderu 3:78f223d34f36 69 ** ENET, MCG, MCM, SIM, USB - registers updated
ethaderu 3:78f223d34f36 70 ** - rev. 2.4 (2014-02-10)
ethaderu 3:78f223d34f36 71 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
ethaderu 3:78f223d34f36 72 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
ethaderu 3:78f223d34f36 73 ** - rev. 2.5 (2014-02-10)
ethaderu 3:78f223d34f36 74 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
ethaderu 3:78f223d34f36 75 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
ethaderu 3:78f223d34f36 76 ** Module access macro module_BASES replaced by module_BASE_PTRS.
ethaderu 3:78f223d34f36 77 **
ethaderu 3:78f223d34f36 78 ** ###################################################################
ethaderu 3:78f223d34f36 79 */
ethaderu 3:78f223d34f36 80
ethaderu 3:78f223d34f36 81 /*!
ethaderu 3:78f223d34f36 82 * @file MK64F12.h
ethaderu 3:78f223d34f36 83 * @version 2.5
ethaderu 3:78f223d34f36 84 * @date 2014-02-10
ethaderu 3:78f223d34f36 85 * @brief CMSIS Peripheral Access Layer for MK64F12
ethaderu 3:78f223d34f36 86 *
ethaderu 3:78f223d34f36 87 * CMSIS Peripheral Access Layer for MK64F12
ethaderu 3:78f223d34f36 88 */
ethaderu 3:78f223d34f36 89
ethaderu 3:78f223d34f36 90
ethaderu 3:78f223d34f36 91 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 92 -- MCU activation
ethaderu 3:78f223d34f36 93 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 94
ethaderu 3:78f223d34f36 95 /* Prevention from multiple including the same memory map */
ethaderu 3:78f223d34f36 96 #if !defined(MK64F12_H_) /* Check if memory map has not been already included */
ethaderu 3:78f223d34f36 97 #define MK64F12_H_
ethaderu 3:78f223d34f36 98 #define MCU_MK64F12
ethaderu 3:78f223d34f36 99
ethaderu 3:78f223d34f36 100 /* Check if another memory map has not been also included */
ethaderu 3:78f223d34f36 101 #if (defined(MCU_ACTIVE))
ethaderu 3:78f223d34f36 102 #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included.
ethaderu 3:78f223d34f36 103 #endif /* (defined(MCU_ACTIVE)) */
ethaderu 3:78f223d34f36 104 #define MCU_ACTIVE
ethaderu 3:78f223d34f36 105
ethaderu 3:78f223d34f36 106 #include <stdint.h>
ethaderu 3:78f223d34f36 107
ethaderu 3:78f223d34f36 108 /** Memory map major version (memory maps with equal major version number are
ethaderu 3:78f223d34f36 109 * compatible) */
ethaderu 3:78f223d34f36 110 #define MCU_MEM_MAP_VERSION 0x0200u
ethaderu 3:78f223d34f36 111 /** Memory map minor version */
ethaderu 3:78f223d34f36 112 #define MCU_MEM_MAP_VERSION_MINOR 0x0005u
ethaderu 3:78f223d34f36 113
ethaderu 3:78f223d34f36 114 /**
ethaderu 3:78f223d34f36 115 * @brief Macro to calculate address of an aliased word in the peripheral
ethaderu 3:78f223d34f36 116 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
ethaderu 3:78f223d34f36 117 * 0x400FFFFF).
ethaderu 3:78f223d34f36 118 * @param Reg Register to access.
ethaderu 3:78f223d34f36 119 * @param Bit Bit number to access.
ethaderu 3:78f223d34f36 120 * @return Address of the aliased word in the peripheral bitband area.
ethaderu 3:78f223d34f36 121 */
ethaderu 3:78f223d34f36 122 #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
ethaderu 3:78f223d34f36 123 /**
ethaderu 3:78f223d34f36 124 * @brief Macro to access a single bit of a peripheral register (bit band region
ethaderu 3:78f223d34f36 125 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
ethaderu 3:78f223d34f36 126 * be used for peripherals with 32bit access allowed.
ethaderu 3:78f223d34f36 127 * @param Reg Register to access.
ethaderu 3:78f223d34f36 128 * @param Bit Bit number to access.
ethaderu 3:78f223d34f36 129 * @return Value of the targeted bit in the bit band region.
ethaderu 3:78f223d34f36 130 */
ethaderu 3:78f223d34f36 131 #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
ethaderu 3:78f223d34f36 132 #define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
ethaderu 3:78f223d34f36 133 /**
ethaderu 3:78f223d34f36 134 * @brief Macro to access a single bit of a peripheral register (bit band region
ethaderu 3:78f223d34f36 135 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
ethaderu 3:78f223d34f36 136 * be used for peripherals with 16bit access allowed.
ethaderu 3:78f223d34f36 137 * @param Reg Register to access.
ethaderu 3:78f223d34f36 138 * @param Bit Bit number to access.
ethaderu 3:78f223d34f36 139 * @return Value of the targeted bit in the bit band region.
ethaderu 3:78f223d34f36 140 */
ethaderu 3:78f223d34f36 141 #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
ethaderu 3:78f223d34f36 142 /**
ethaderu 3:78f223d34f36 143 * @brief Macro to access a single bit of a peripheral register (bit band region
ethaderu 3:78f223d34f36 144 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
ethaderu 3:78f223d34f36 145 * be used for peripherals with 8bit access allowed.
ethaderu 3:78f223d34f36 146 * @param Reg Register to access.
ethaderu 3:78f223d34f36 147 * @param Bit Bit number to access.
ethaderu 3:78f223d34f36 148 * @return Value of the targeted bit in the bit band region.
ethaderu 3:78f223d34f36 149 */
ethaderu 3:78f223d34f36 150 #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
ethaderu 3:78f223d34f36 151
ethaderu 3:78f223d34f36 152 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 153 -- Interrupt vector numbers
ethaderu 3:78f223d34f36 154 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 155
ethaderu 3:78f223d34f36 156 /*!
ethaderu 3:78f223d34f36 157 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
ethaderu 3:78f223d34f36 158 * @{
ethaderu 3:78f223d34f36 159 */
ethaderu 3:78f223d34f36 160
ethaderu 3:78f223d34f36 161 /** Interrupt Number Definitions */
ethaderu 3:78f223d34f36 162 #define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */
ethaderu 3:78f223d34f36 163
ethaderu 3:78f223d34f36 164 typedef enum IRQn {
ethaderu 3:78f223d34f36 165 /* Core interrupts */
ethaderu 3:78f223d34f36 166 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
ethaderu 3:78f223d34f36 167 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
ethaderu 3:78f223d34f36 168 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
ethaderu 3:78f223d34f36 169 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
ethaderu 3:78f223d34f36 170 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
ethaderu 3:78f223d34f36 171 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
ethaderu 3:78f223d34f36 172 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
ethaderu 3:78f223d34f36 173 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
ethaderu 3:78f223d34f36 174 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
ethaderu 3:78f223d34f36 175
ethaderu 3:78f223d34f36 176 /* Device specific interrupts */
ethaderu 3:78f223d34f36 177 DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
ethaderu 3:78f223d34f36 178 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
ethaderu 3:78f223d34f36 179 DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
ethaderu 3:78f223d34f36 180 DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
ethaderu 3:78f223d34f36 181 DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
ethaderu 3:78f223d34f36 182 DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
ethaderu 3:78f223d34f36 183 DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
ethaderu 3:78f223d34f36 184 DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
ethaderu 3:78f223d34f36 185 DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
ethaderu 3:78f223d34f36 186 DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
ethaderu 3:78f223d34f36 187 DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
ethaderu 3:78f223d34f36 188 DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
ethaderu 3:78f223d34f36 189 DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
ethaderu 3:78f223d34f36 190 DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
ethaderu 3:78f223d34f36 191 DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
ethaderu 3:78f223d34f36 192 DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
ethaderu 3:78f223d34f36 193 DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
ethaderu 3:78f223d34f36 194 MCM_IRQn = 17, /**< Normal Interrupt */
ethaderu 3:78f223d34f36 195 FTFE_IRQn = 18, /**< FTFE Command complete interrupt */
ethaderu 3:78f223d34f36 196 Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
ethaderu 3:78f223d34f36 197 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
ethaderu 3:78f223d34f36 198 LLW_IRQn = 21, /**< Low Leakage Wakeup */
ethaderu 3:78f223d34f36 199 Watchdog_IRQn = 22, /**< WDOG Interrupt */
ethaderu 3:78f223d34f36 200 RNG_IRQn = 23, /**< RNG Interrupt */
ethaderu 3:78f223d34f36 201 I2C0_IRQn = 24, /**< I2C0 interrupt */
ethaderu 3:78f223d34f36 202 I2C1_IRQn = 25, /**< I2C1 interrupt */
ethaderu 3:78f223d34f36 203 SPI0_IRQn = 26, /**< SPI0 Interrupt */
ethaderu 3:78f223d34f36 204 SPI1_IRQn = 27, /**< SPI1 Interrupt */
ethaderu 3:78f223d34f36 205 I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
ethaderu 3:78f223d34f36 206 I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
ethaderu 3:78f223d34f36 207 UART0_LON_IRQn = 30, /**< UART0 LON interrupt */
ethaderu 3:78f223d34f36 208 UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
ethaderu 3:78f223d34f36 209 UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
ethaderu 3:78f223d34f36 210 UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
ethaderu 3:78f223d34f36 211 UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
ethaderu 3:78f223d34f36 212 UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
ethaderu 3:78f223d34f36 213 UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
ethaderu 3:78f223d34f36 214 UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */
ethaderu 3:78f223d34f36 215 UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */
ethaderu 3:78f223d34f36 216 ADC0_IRQn = 39, /**< ADC0 interrupt */
ethaderu 3:78f223d34f36 217 CMP0_IRQn = 40, /**< CMP0 interrupt */
ethaderu 3:78f223d34f36 218 CMP1_IRQn = 41, /**< CMP1 interrupt */
ethaderu 3:78f223d34f36 219 FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
ethaderu 3:78f223d34f36 220 FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
ethaderu 3:78f223d34f36 221 FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
ethaderu 3:78f223d34f36 222 CMT_IRQn = 45, /**< CMT interrupt */
ethaderu 3:78f223d34f36 223 RTC_IRQn = 46, /**< RTC interrupt */
ethaderu 3:78f223d34f36 224 RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
ethaderu 3:78f223d34f36 225 PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
ethaderu 3:78f223d34f36 226 PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
ethaderu 3:78f223d34f36 227 PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
ethaderu 3:78f223d34f36 228 PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
ethaderu 3:78f223d34f36 229 PDB0_IRQn = 52, /**< PDB0 Interrupt */
ethaderu 3:78f223d34f36 230 USB0_IRQn = 53, /**< USB0 interrupt */
ethaderu 3:78f223d34f36 231 USBDCD_IRQn = 54, /**< USBDCD Interrupt */
ethaderu 3:78f223d34f36 232 Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
ethaderu 3:78f223d34f36 233 DAC0_IRQn = 56, /**< DAC0 interrupt */
ethaderu 3:78f223d34f36 234 MCG_IRQn = 57, /**< MCG Interrupt */
ethaderu 3:78f223d34f36 235 LPTimer_IRQn = 58, /**< LPTimer interrupt */
ethaderu 3:78f223d34f36 236 PORTA_IRQn = 59, /**< Port A interrupt */
ethaderu 3:78f223d34f36 237 PORTB_IRQn = 60, /**< Port B interrupt */
ethaderu 3:78f223d34f36 238 PORTC_IRQn = 61, /**< Port C interrupt */
ethaderu 3:78f223d34f36 239 PORTD_IRQn = 62, /**< Port D interrupt */
ethaderu 3:78f223d34f36 240 PORTE_IRQn = 63, /**< Port E interrupt */
ethaderu 3:78f223d34f36 241 SWI_IRQn = 64, /**< Software interrupt */
ethaderu 3:78f223d34f36 242 SPI2_IRQn = 65, /**< SPI2 Interrupt */
ethaderu 3:78f223d34f36 243 UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */
ethaderu 3:78f223d34f36 244 UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */
ethaderu 3:78f223d34f36 245 UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */
ethaderu 3:78f223d34f36 246 UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */
ethaderu 3:78f223d34f36 247 CMP2_IRQn = 70, /**< CMP2 interrupt */
ethaderu 3:78f223d34f36 248 FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
ethaderu 3:78f223d34f36 249 DAC1_IRQn = 72, /**< DAC1 interrupt */
ethaderu 3:78f223d34f36 250 ADC1_IRQn = 73, /**< ADC1 interrupt */
ethaderu 3:78f223d34f36 251 I2C2_IRQn = 74, /**< I2C2 interrupt */
ethaderu 3:78f223d34f36 252 CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */
ethaderu 3:78f223d34f36 253 CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */
ethaderu 3:78f223d34f36 254 CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */
ethaderu 3:78f223d34f36 255 CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */
ethaderu 3:78f223d34f36 256 CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */
ethaderu 3:78f223d34f36 257 CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */
ethaderu 3:78f223d34f36 258 SDHC_IRQn = 81, /**< SDHC interrupt */
ethaderu 3:78f223d34f36 259 ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */
ethaderu 3:78f223d34f36 260 ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */
ethaderu 3:78f223d34f36 261 ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */
ethaderu 3:78f223d34f36 262 ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */
ethaderu 3:78f223d34f36 263 } IRQn_Type;
ethaderu 3:78f223d34f36 264
ethaderu 3:78f223d34f36 265 /*!
ethaderu 3:78f223d34f36 266 * @}
ethaderu 3:78f223d34f36 267 */ /* end of group Interrupt_vector_numbers */
ethaderu 3:78f223d34f36 268
ethaderu 3:78f223d34f36 269
ethaderu 3:78f223d34f36 270 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 271 -- Cortex M4 Core Configuration
ethaderu 3:78f223d34f36 272 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 273
ethaderu 3:78f223d34f36 274 /*!
ethaderu 3:78f223d34f36 275 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
ethaderu 3:78f223d34f36 276 * @{
ethaderu 3:78f223d34f36 277 */
ethaderu 3:78f223d34f36 278
ethaderu 3:78f223d34f36 279 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
ethaderu 3:78f223d34f36 280 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
ethaderu 3:78f223d34f36 281 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
ethaderu 3:78f223d34f36 282 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
ethaderu 3:78f223d34f36 283
ethaderu 3:78f223d34f36 284 #include "core_cm4.h" /* Core Peripheral Access Layer */
ethaderu 3:78f223d34f36 285 #include "system_MK64F12.h" /* Device specific configuration file */
ethaderu 3:78f223d34f36 286
ethaderu 3:78f223d34f36 287 /*!
ethaderu 3:78f223d34f36 288 * @}
ethaderu 3:78f223d34f36 289 */ /* end of group Cortex_Core_Configuration */
ethaderu 3:78f223d34f36 290
ethaderu 3:78f223d34f36 291
ethaderu 3:78f223d34f36 292 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 293 -- Device Peripheral Access Layer
ethaderu 3:78f223d34f36 294 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 295
ethaderu 3:78f223d34f36 296 /*!
ethaderu 3:78f223d34f36 297 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
ethaderu 3:78f223d34f36 298 * @{
ethaderu 3:78f223d34f36 299 */
ethaderu 3:78f223d34f36 300
ethaderu 3:78f223d34f36 301
ethaderu 3:78f223d34f36 302 /*
ethaderu 3:78f223d34f36 303 ** Start of section using anonymous unions
ethaderu 3:78f223d34f36 304 */
ethaderu 3:78f223d34f36 305
ethaderu 3:78f223d34f36 306 #if defined(__ARMCC_VERSION)
ethaderu 3:78f223d34f36 307 #pragma push
ethaderu 3:78f223d34f36 308 #pragma anon_unions
ethaderu 3:78f223d34f36 309 #elif defined(__CWCC__)
ethaderu 3:78f223d34f36 310 #pragma push
ethaderu 3:78f223d34f36 311 #pragma cpp_extensions on
ethaderu 3:78f223d34f36 312 #elif defined(__GNUC__)
ethaderu 3:78f223d34f36 313 /* anonymous unions are enabled by default */
ethaderu 3:78f223d34f36 314 #elif defined(__IAR_SYSTEMS_ICC__)
ethaderu 3:78f223d34f36 315 #pragma language=extended
ethaderu 3:78f223d34f36 316 #else
ethaderu 3:78f223d34f36 317 #error Not supported compiler type
ethaderu 3:78f223d34f36 318 #endif
ethaderu 3:78f223d34f36 319
ethaderu 3:78f223d34f36 320 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 321 -- ADC Peripheral Access Layer
ethaderu 3:78f223d34f36 322 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 323
ethaderu 3:78f223d34f36 324 /*!
ethaderu 3:78f223d34f36 325 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
ethaderu 3:78f223d34f36 326 * @{
ethaderu 3:78f223d34f36 327 */
ethaderu 3:78f223d34f36 328
ethaderu 3:78f223d34f36 329 /** ADC - Register Layout Typedef */
ethaderu 3:78f223d34f36 330 typedef struct {
ethaderu 3:78f223d34f36 331 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
ethaderu 3:78f223d34f36 332 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
ethaderu 3:78f223d34f36 333 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
ethaderu 3:78f223d34f36 334 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
ethaderu 3:78f223d34f36 335 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
ethaderu 3:78f223d34f36 336 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
ethaderu 3:78f223d34f36 337 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
ethaderu 3:78f223d34f36 338 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
ethaderu 3:78f223d34f36 339 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
ethaderu 3:78f223d34f36 340 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
ethaderu 3:78f223d34f36 341 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
ethaderu 3:78f223d34f36 342 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
ethaderu 3:78f223d34f36 343 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
ethaderu 3:78f223d34f36 344 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
ethaderu 3:78f223d34f36 345 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
ethaderu 3:78f223d34f36 346 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
ethaderu 3:78f223d34f36 347 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
ethaderu 3:78f223d34f36 348 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
ethaderu 3:78f223d34f36 349 uint8_t RESERVED_0[4];
ethaderu 3:78f223d34f36 350 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
ethaderu 3:78f223d34f36 351 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
ethaderu 3:78f223d34f36 352 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
ethaderu 3:78f223d34f36 353 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
ethaderu 3:78f223d34f36 354 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
ethaderu 3:78f223d34f36 355 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
ethaderu 3:78f223d34f36 356 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
ethaderu 3:78f223d34f36 357 } ADC_Type, *ADC_MemMapPtr;
ethaderu 3:78f223d34f36 358
ethaderu 3:78f223d34f36 359 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 360 -- ADC - Register accessor macros
ethaderu 3:78f223d34f36 361 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 362
ethaderu 3:78f223d34f36 363 /*!
ethaderu 3:78f223d34f36 364 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
ethaderu 3:78f223d34f36 365 * @{
ethaderu 3:78f223d34f36 366 */
ethaderu 3:78f223d34f36 367
ethaderu 3:78f223d34f36 368
ethaderu 3:78f223d34f36 369 /* ADC - Register accessors */
ethaderu 3:78f223d34f36 370 #define ADC_SC1_REG(base,index) ((base)->SC1[index])
ethaderu 3:78f223d34f36 371 #define ADC_CFG1_REG(base) ((base)->CFG1)
ethaderu 3:78f223d34f36 372 #define ADC_CFG2_REG(base) ((base)->CFG2)
ethaderu 3:78f223d34f36 373 #define ADC_R_REG(base,index) ((base)->R[index])
ethaderu 3:78f223d34f36 374 #define ADC_CV1_REG(base) ((base)->CV1)
ethaderu 3:78f223d34f36 375 #define ADC_CV2_REG(base) ((base)->CV2)
ethaderu 3:78f223d34f36 376 #define ADC_SC2_REG(base) ((base)->SC2)
ethaderu 3:78f223d34f36 377 #define ADC_SC3_REG(base) ((base)->SC3)
ethaderu 3:78f223d34f36 378 #define ADC_OFS_REG(base) ((base)->OFS)
ethaderu 3:78f223d34f36 379 #define ADC_PG_REG(base) ((base)->PG)
ethaderu 3:78f223d34f36 380 #define ADC_MG_REG(base) ((base)->MG)
ethaderu 3:78f223d34f36 381 #define ADC_CLPD_REG(base) ((base)->CLPD)
ethaderu 3:78f223d34f36 382 #define ADC_CLPS_REG(base) ((base)->CLPS)
ethaderu 3:78f223d34f36 383 #define ADC_CLP4_REG(base) ((base)->CLP4)
ethaderu 3:78f223d34f36 384 #define ADC_CLP3_REG(base) ((base)->CLP3)
ethaderu 3:78f223d34f36 385 #define ADC_CLP2_REG(base) ((base)->CLP2)
ethaderu 3:78f223d34f36 386 #define ADC_CLP1_REG(base) ((base)->CLP1)
ethaderu 3:78f223d34f36 387 #define ADC_CLP0_REG(base) ((base)->CLP0)
ethaderu 3:78f223d34f36 388 #define ADC_CLMD_REG(base) ((base)->CLMD)
ethaderu 3:78f223d34f36 389 #define ADC_CLMS_REG(base) ((base)->CLMS)
ethaderu 3:78f223d34f36 390 #define ADC_CLM4_REG(base) ((base)->CLM4)
ethaderu 3:78f223d34f36 391 #define ADC_CLM3_REG(base) ((base)->CLM3)
ethaderu 3:78f223d34f36 392 #define ADC_CLM2_REG(base) ((base)->CLM2)
ethaderu 3:78f223d34f36 393 #define ADC_CLM1_REG(base) ((base)->CLM1)
ethaderu 3:78f223d34f36 394 #define ADC_CLM0_REG(base) ((base)->CLM0)
ethaderu 3:78f223d34f36 395
ethaderu 3:78f223d34f36 396 /*!
ethaderu 3:78f223d34f36 397 * @}
ethaderu 3:78f223d34f36 398 */ /* end of group ADC_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 399
ethaderu 3:78f223d34f36 400
ethaderu 3:78f223d34f36 401 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 402 -- ADC Register Masks
ethaderu 3:78f223d34f36 403 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 404
ethaderu 3:78f223d34f36 405 /*!
ethaderu 3:78f223d34f36 406 * @addtogroup ADC_Register_Masks ADC Register Masks
ethaderu 3:78f223d34f36 407 * @{
ethaderu 3:78f223d34f36 408 */
ethaderu 3:78f223d34f36 409
ethaderu 3:78f223d34f36 410 /* SC1 Bit Fields */
ethaderu 3:78f223d34f36 411 #define ADC_SC1_ADCH_MASK 0x1Fu
ethaderu 3:78f223d34f36 412 #define ADC_SC1_ADCH_SHIFT 0
ethaderu 3:78f223d34f36 413 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
ethaderu 3:78f223d34f36 414 #define ADC_SC1_DIFF_MASK 0x20u
ethaderu 3:78f223d34f36 415 #define ADC_SC1_DIFF_SHIFT 5
ethaderu 3:78f223d34f36 416 #define ADC_SC1_AIEN_MASK 0x40u
ethaderu 3:78f223d34f36 417 #define ADC_SC1_AIEN_SHIFT 6
ethaderu 3:78f223d34f36 418 #define ADC_SC1_COCO_MASK 0x80u
ethaderu 3:78f223d34f36 419 #define ADC_SC1_COCO_SHIFT 7
ethaderu 3:78f223d34f36 420 /* CFG1 Bit Fields */
ethaderu 3:78f223d34f36 421 #define ADC_CFG1_ADICLK_MASK 0x3u
ethaderu 3:78f223d34f36 422 #define ADC_CFG1_ADICLK_SHIFT 0
ethaderu 3:78f223d34f36 423 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
ethaderu 3:78f223d34f36 424 #define ADC_CFG1_MODE_MASK 0xCu
ethaderu 3:78f223d34f36 425 #define ADC_CFG1_MODE_SHIFT 2
ethaderu 3:78f223d34f36 426 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
ethaderu 3:78f223d34f36 427 #define ADC_CFG1_ADLSMP_MASK 0x10u
ethaderu 3:78f223d34f36 428 #define ADC_CFG1_ADLSMP_SHIFT 4
ethaderu 3:78f223d34f36 429 #define ADC_CFG1_ADIV_MASK 0x60u
ethaderu 3:78f223d34f36 430 #define ADC_CFG1_ADIV_SHIFT 5
ethaderu 3:78f223d34f36 431 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
ethaderu 3:78f223d34f36 432 #define ADC_CFG1_ADLPC_MASK 0x80u
ethaderu 3:78f223d34f36 433 #define ADC_CFG1_ADLPC_SHIFT 7
ethaderu 3:78f223d34f36 434 /* CFG2 Bit Fields */
ethaderu 3:78f223d34f36 435 #define ADC_CFG2_ADLSTS_MASK 0x3u
ethaderu 3:78f223d34f36 436 #define ADC_CFG2_ADLSTS_SHIFT 0
ethaderu 3:78f223d34f36 437 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
ethaderu 3:78f223d34f36 438 #define ADC_CFG2_ADHSC_MASK 0x4u
ethaderu 3:78f223d34f36 439 #define ADC_CFG2_ADHSC_SHIFT 2
ethaderu 3:78f223d34f36 440 #define ADC_CFG2_ADACKEN_MASK 0x8u
ethaderu 3:78f223d34f36 441 #define ADC_CFG2_ADACKEN_SHIFT 3
ethaderu 3:78f223d34f36 442 #define ADC_CFG2_MUXSEL_MASK 0x10u
ethaderu 3:78f223d34f36 443 #define ADC_CFG2_MUXSEL_SHIFT 4
ethaderu 3:78f223d34f36 444 /* R Bit Fields */
ethaderu 3:78f223d34f36 445 #define ADC_R_D_MASK 0xFFFFu
ethaderu 3:78f223d34f36 446 #define ADC_R_D_SHIFT 0
ethaderu 3:78f223d34f36 447 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
ethaderu 3:78f223d34f36 448 /* CV1 Bit Fields */
ethaderu 3:78f223d34f36 449 #define ADC_CV1_CV_MASK 0xFFFFu
ethaderu 3:78f223d34f36 450 #define ADC_CV1_CV_SHIFT 0
ethaderu 3:78f223d34f36 451 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
ethaderu 3:78f223d34f36 452 /* CV2 Bit Fields */
ethaderu 3:78f223d34f36 453 #define ADC_CV2_CV_MASK 0xFFFFu
ethaderu 3:78f223d34f36 454 #define ADC_CV2_CV_SHIFT 0
ethaderu 3:78f223d34f36 455 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
ethaderu 3:78f223d34f36 456 /* SC2 Bit Fields */
ethaderu 3:78f223d34f36 457 #define ADC_SC2_REFSEL_MASK 0x3u
ethaderu 3:78f223d34f36 458 #define ADC_SC2_REFSEL_SHIFT 0
ethaderu 3:78f223d34f36 459 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
ethaderu 3:78f223d34f36 460 #define ADC_SC2_DMAEN_MASK 0x4u
ethaderu 3:78f223d34f36 461 #define ADC_SC2_DMAEN_SHIFT 2
ethaderu 3:78f223d34f36 462 #define ADC_SC2_ACREN_MASK 0x8u
ethaderu 3:78f223d34f36 463 #define ADC_SC2_ACREN_SHIFT 3
ethaderu 3:78f223d34f36 464 #define ADC_SC2_ACFGT_MASK 0x10u
ethaderu 3:78f223d34f36 465 #define ADC_SC2_ACFGT_SHIFT 4
ethaderu 3:78f223d34f36 466 #define ADC_SC2_ACFE_MASK 0x20u
ethaderu 3:78f223d34f36 467 #define ADC_SC2_ACFE_SHIFT 5
ethaderu 3:78f223d34f36 468 #define ADC_SC2_ADTRG_MASK 0x40u
ethaderu 3:78f223d34f36 469 #define ADC_SC2_ADTRG_SHIFT 6
ethaderu 3:78f223d34f36 470 #define ADC_SC2_ADACT_MASK 0x80u
ethaderu 3:78f223d34f36 471 #define ADC_SC2_ADACT_SHIFT 7
ethaderu 3:78f223d34f36 472 /* SC3 Bit Fields */
ethaderu 3:78f223d34f36 473 #define ADC_SC3_AVGS_MASK 0x3u
ethaderu 3:78f223d34f36 474 #define ADC_SC3_AVGS_SHIFT 0
ethaderu 3:78f223d34f36 475 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
ethaderu 3:78f223d34f36 476 #define ADC_SC3_AVGE_MASK 0x4u
ethaderu 3:78f223d34f36 477 #define ADC_SC3_AVGE_SHIFT 2
ethaderu 3:78f223d34f36 478 #define ADC_SC3_ADCO_MASK 0x8u
ethaderu 3:78f223d34f36 479 #define ADC_SC3_ADCO_SHIFT 3
ethaderu 3:78f223d34f36 480 #define ADC_SC3_CALF_MASK 0x40u
ethaderu 3:78f223d34f36 481 #define ADC_SC3_CALF_SHIFT 6
ethaderu 3:78f223d34f36 482 #define ADC_SC3_CAL_MASK 0x80u
ethaderu 3:78f223d34f36 483 #define ADC_SC3_CAL_SHIFT 7
ethaderu 3:78f223d34f36 484 /* OFS Bit Fields */
ethaderu 3:78f223d34f36 485 #define ADC_OFS_OFS_MASK 0xFFFFu
ethaderu 3:78f223d34f36 486 #define ADC_OFS_OFS_SHIFT 0
ethaderu 3:78f223d34f36 487 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
ethaderu 3:78f223d34f36 488 /* PG Bit Fields */
ethaderu 3:78f223d34f36 489 #define ADC_PG_PG_MASK 0xFFFFu
ethaderu 3:78f223d34f36 490 #define ADC_PG_PG_SHIFT 0
ethaderu 3:78f223d34f36 491 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
ethaderu 3:78f223d34f36 492 /* MG Bit Fields */
ethaderu 3:78f223d34f36 493 #define ADC_MG_MG_MASK 0xFFFFu
ethaderu 3:78f223d34f36 494 #define ADC_MG_MG_SHIFT 0
ethaderu 3:78f223d34f36 495 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
ethaderu 3:78f223d34f36 496 /* CLPD Bit Fields */
ethaderu 3:78f223d34f36 497 #define ADC_CLPD_CLPD_MASK 0x3Fu
ethaderu 3:78f223d34f36 498 #define ADC_CLPD_CLPD_SHIFT 0
ethaderu 3:78f223d34f36 499 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
ethaderu 3:78f223d34f36 500 /* CLPS Bit Fields */
ethaderu 3:78f223d34f36 501 #define ADC_CLPS_CLPS_MASK 0x3Fu
ethaderu 3:78f223d34f36 502 #define ADC_CLPS_CLPS_SHIFT 0
ethaderu 3:78f223d34f36 503 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
ethaderu 3:78f223d34f36 504 /* CLP4 Bit Fields */
ethaderu 3:78f223d34f36 505 #define ADC_CLP4_CLP4_MASK 0x3FFu
ethaderu 3:78f223d34f36 506 #define ADC_CLP4_CLP4_SHIFT 0
ethaderu 3:78f223d34f36 507 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
ethaderu 3:78f223d34f36 508 /* CLP3 Bit Fields */
ethaderu 3:78f223d34f36 509 #define ADC_CLP3_CLP3_MASK 0x1FFu
ethaderu 3:78f223d34f36 510 #define ADC_CLP3_CLP3_SHIFT 0
ethaderu 3:78f223d34f36 511 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
ethaderu 3:78f223d34f36 512 /* CLP2 Bit Fields */
ethaderu 3:78f223d34f36 513 #define ADC_CLP2_CLP2_MASK 0xFFu
ethaderu 3:78f223d34f36 514 #define ADC_CLP2_CLP2_SHIFT 0
ethaderu 3:78f223d34f36 515 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
ethaderu 3:78f223d34f36 516 /* CLP1 Bit Fields */
ethaderu 3:78f223d34f36 517 #define ADC_CLP1_CLP1_MASK 0x7Fu
ethaderu 3:78f223d34f36 518 #define ADC_CLP1_CLP1_SHIFT 0
ethaderu 3:78f223d34f36 519 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
ethaderu 3:78f223d34f36 520 /* CLP0 Bit Fields */
ethaderu 3:78f223d34f36 521 #define ADC_CLP0_CLP0_MASK 0x3Fu
ethaderu 3:78f223d34f36 522 #define ADC_CLP0_CLP0_SHIFT 0
ethaderu 3:78f223d34f36 523 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
ethaderu 3:78f223d34f36 524 /* CLMD Bit Fields */
ethaderu 3:78f223d34f36 525 #define ADC_CLMD_CLMD_MASK 0x3Fu
ethaderu 3:78f223d34f36 526 #define ADC_CLMD_CLMD_SHIFT 0
ethaderu 3:78f223d34f36 527 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
ethaderu 3:78f223d34f36 528 /* CLMS Bit Fields */
ethaderu 3:78f223d34f36 529 #define ADC_CLMS_CLMS_MASK 0x3Fu
ethaderu 3:78f223d34f36 530 #define ADC_CLMS_CLMS_SHIFT 0
ethaderu 3:78f223d34f36 531 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
ethaderu 3:78f223d34f36 532 /* CLM4 Bit Fields */
ethaderu 3:78f223d34f36 533 #define ADC_CLM4_CLM4_MASK 0x3FFu
ethaderu 3:78f223d34f36 534 #define ADC_CLM4_CLM4_SHIFT 0
ethaderu 3:78f223d34f36 535 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
ethaderu 3:78f223d34f36 536 /* CLM3 Bit Fields */
ethaderu 3:78f223d34f36 537 #define ADC_CLM3_CLM3_MASK 0x1FFu
ethaderu 3:78f223d34f36 538 #define ADC_CLM3_CLM3_SHIFT 0
ethaderu 3:78f223d34f36 539 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
ethaderu 3:78f223d34f36 540 /* CLM2 Bit Fields */
ethaderu 3:78f223d34f36 541 #define ADC_CLM2_CLM2_MASK 0xFFu
ethaderu 3:78f223d34f36 542 #define ADC_CLM2_CLM2_SHIFT 0
ethaderu 3:78f223d34f36 543 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
ethaderu 3:78f223d34f36 544 /* CLM1 Bit Fields */
ethaderu 3:78f223d34f36 545 #define ADC_CLM1_CLM1_MASK 0x7Fu
ethaderu 3:78f223d34f36 546 #define ADC_CLM1_CLM1_SHIFT 0
ethaderu 3:78f223d34f36 547 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
ethaderu 3:78f223d34f36 548 /* CLM0 Bit Fields */
ethaderu 3:78f223d34f36 549 #define ADC_CLM0_CLM0_MASK 0x3Fu
ethaderu 3:78f223d34f36 550 #define ADC_CLM0_CLM0_SHIFT 0
ethaderu 3:78f223d34f36 551 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
ethaderu 3:78f223d34f36 552
ethaderu 3:78f223d34f36 553 /*!
ethaderu 3:78f223d34f36 554 * @}
ethaderu 3:78f223d34f36 555 */ /* end of group ADC_Register_Masks */
ethaderu 3:78f223d34f36 556
ethaderu 3:78f223d34f36 557
ethaderu 3:78f223d34f36 558 /* ADC - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 559 /** Peripheral ADC0 base address */
ethaderu 3:78f223d34f36 560 #define ADC0_BASE (0x4003B000u)
ethaderu 3:78f223d34f36 561 /** Peripheral ADC0 base pointer */
ethaderu 3:78f223d34f36 562 #define ADC0 ((ADC_Type *)ADC0_BASE)
ethaderu 3:78f223d34f36 563 #define ADC0_BASE_PTR (ADC0)
ethaderu 3:78f223d34f36 564 /** Peripheral ADC1 base address */
ethaderu 3:78f223d34f36 565 #define ADC1_BASE (0x400BB000u)
ethaderu 3:78f223d34f36 566 /** Peripheral ADC1 base pointer */
ethaderu 3:78f223d34f36 567 #define ADC1 ((ADC_Type *)ADC1_BASE)
ethaderu 3:78f223d34f36 568 #define ADC1_BASE_PTR (ADC1)
ethaderu 3:78f223d34f36 569 /** Array initializer of ADC peripheral base addresses */
ethaderu 3:78f223d34f36 570 #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
ethaderu 3:78f223d34f36 571 /** Array initializer of ADC peripheral base pointers */
ethaderu 3:78f223d34f36 572 #define ADC_BASE_PTRS { ADC0, ADC1 }
ethaderu 3:78f223d34f36 573 /** Interrupt vectors for the ADC peripheral type */
ethaderu 3:78f223d34f36 574 #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
ethaderu 3:78f223d34f36 575
ethaderu 3:78f223d34f36 576 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 577 -- ADC - Register accessor macros
ethaderu 3:78f223d34f36 578 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 579
ethaderu 3:78f223d34f36 580 /*!
ethaderu 3:78f223d34f36 581 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
ethaderu 3:78f223d34f36 582 * @{
ethaderu 3:78f223d34f36 583 */
ethaderu 3:78f223d34f36 584
ethaderu 3:78f223d34f36 585
ethaderu 3:78f223d34f36 586 /* ADC - Register instance definitions */
ethaderu 3:78f223d34f36 587 /* ADC0 */
ethaderu 3:78f223d34f36 588 #define ADC0_SC1A ADC_SC1_REG(ADC0,0)
ethaderu 3:78f223d34f36 589 #define ADC0_SC1B ADC_SC1_REG(ADC0,1)
ethaderu 3:78f223d34f36 590 #define ADC0_CFG1 ADC_CFG1_REG(ADC0)
ethaderu 3:78f223d34f36 591 #define ADC0_CFG2 ADC_CFG2_REG(ADC0)
ethaderu 3:78f223d34f36 592 #define ADC0_RA ADC_R_REG(ADC0,0)
ethaderu 3:78f223d34f36 593 #define ADC0_RB ADC_R_REG(ADC0,1)
ethaderu 3:78f223d34f36 594 #define ADC0_CV1 ADC_CV1_REG(ADC0)
ethaderu 3:78f223d34f36 595 #define ADC0_CV2 ADC_CV2_REG(ADC0)
ethaderu 3:78f223d34f36 596 #define ADC0_SC2 ADC_SC2_REG(ADC0)
ethaderu 3:78f223d34f36 597 #define ADC0_SC3 ADC_SC3_REG(ADC0)
ethaderu 3:78f223d34f36 598 #define ADC0_OFS ADC_OFS_REG(ADC0)
ethaderu 3:78f223d34f36 599 #define ADC0_PG ADC_PG_REG(ADC0)
ethaderu 3:78f223d34f36 600 #define ADC0_MG ADC_MG_REG(ADC0)
ethaderu 3:78f223d34f36 601 #define ADC0_CLPD ADC_CLPD_REG(ADC0)
ethaderu 3:78f223d34f36 602 #define ADC0_CLPS ADC_CLPS_REG(ADC0)
ethaderu 3:78f223d34f36 603 #define ADC0_CLP4 ADC_CLP4_REG(ADC0)
ethaderu 3:78f223d34f36 604 #define ADC0_CLP3 ADC_CLP3_REG(ADC0)
ethaderu 3:78f223d34f36 605 #define ADC0_CLP2 ADC_CLP2_REG(ADC0)
ethaderu 3:78f223d34f36 606 #define ADC0_CLP1 ADC_CLP1_REG(ADC0)
ethaderu 3:78f223d34f36 607 #define ADC0_CLP0 ADC_CLP0_REG(ADC0)
ethaderu 3:78f223d34f36 608 #define ADC0_CLMD ADC_CLMD_REG(ADC0)
ethaderu 3:78f223d34f36 609 #define ADC0_CLMS ADC_CLMS_REG(ADC0)
ethaderu 3:78f223d34f36 610 #define ADC0_CLM4 ADC_CLM4_REG(ADC0)
ethaderu 3:78f223d34f36 611 #define ADC0_CLM3 ADC_CLM3_REG(ADC0)
ethaderu 3:78f223d34f36 612 #define ADC0_CLM2 ADC_CLM2_REG(ADC0)
ethaderu 3:78f223d34f36 613 #define ADC0_CLM1 ADC_CLM1_REG(ADC0)
ethaderu 3:78f223d34f36 614 #define ADC0_CLM0 ADC_CLM0_REG(ADC0)
ethaderu 3:78f223d34f36 615 /* ADC1 */
ethaderu 3:78f223d34f36 616 #define ADC1_SC1A ADC_SC1_REG(ADC1,0)
ethaderu 3:78f223d34f36 617 #define ADC1_SC1B ADC_SC1_REG(ADC1,1)
ethaderu 3:78f223d34f36 618 #define ADC1_CFG1 ADC_CFG1_REG(ADC1)
ethaderu 3:78f223d34f36 619 #define ADC1_CFG2 ADC_CFG2_REG(ADC1)
ethaderu 3:78f223d34f36 620 #define ADC1_RA ADC_R_REG(ADC1,0)
ethaderu 3:78f223d34f36 621 #define ADC1_RB ADC_R_REG(ADC1,1)
ethaderu 3:78f223d34f36 622 #define ADC1_CV1 ADC_CV1_REG(ADC1)
ethaderu 3:78f223d34f36 623 #define ADC1_CV2 ADC_CV2_REG(ADC1)
ethaderu 3:78f223d34f36 624 #define ADC1_SC2 ADC_SC2_REG(ADC1)
ethaderu 3:78f223d34f36 625 #define ADC1_SC3 ADC_SC3_REG(ADC1)
ethaderu 3:78f223d34f36 626 #define ADC1_OFS ADC_OFS_REG(ADC1)
ethaderu 3:78f223d34f36 627 #define ADC1_PG ADC_PG_REG(ADC1)
ethaderu 3:78f223d34f36 628 #define ADC1_MG ADC_MG_REG(ADC1)
ethaderu 3:78f223d34f36 629 #define ADC1_CLPD ADC_CLPD_REG(ADC1)
ethaderu 3:78f223d34f36 630 #define ADC1_CLPS ADC_CLPS_REG(ADC1)
ethaderu 3:78f223d34f36 631 #define ADC1_CLP4 ADC_CLP4_REG(ADC1)
ethaderu 3:78f223d34f36 632 #define ADC1_CLP3 ADC_CLP3_REG(ADC1)
ethaderu 3:78f223d34f36 633 #define ADC1_CLP2 ADC_CLP2_REG(ADC1)
ethaderu 3:78f223d34f36 634 #define ADC1_CLP1 ADC_CLP1_REG(ADC1)
ethaderu 3:78f223d34f36 635 #define ADC1_CLP0 ADC_CLP0_REG(ADC1)
ethaderu 3:78f223d34f36 636 #define ADC1_CLMD ADC_CLMD_REG(ADC1)
ethaderu 3:78f223d34f36 637 #define ADC1_CLMS ADC_CLMS_REG(ADC1)
ethaderu 3:78f223d34f36 638 #define ADC1_CLM4 ADC_CLM4_REG(ADC1)
ethaderu 3:78f223d34f36 639 #define ADC1_CLM3 ADC_CLM3_REG(ADC1)
ethaderu 3:78f223d34f36 640 #define ADC1_CLM2 ADC_CLM2_REG(ADC1)
ethaderu 3:78f223d34f36 641 #define ADC1_CLM1 ADC_CLM1_REG(ADC1)
ethaderu 3:78f223d34f36 642 #define ADC1_CLM0 ADC_CLM0_REG(ADC1)
ethaderu 3:78f223d34f36 643
ethaderu 3:78f223d34f36 644 /* ADC - Register array accessors */
ethaderu 3:78f223d34f36 645 #define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
ethaderu 3:78f223d34f36 646 #define ADC1_SC1(index) ADC_SC1_REG(ADC1,index)
ethaderu 3:78f223d34f36 647 #define ADC0_R(index) ADC_R_REG(ADC0,index)
ethaderu 3:78f223d34f36 648 #define ADC1_R(index) ADC_R_REG(ADC1,index)
ethaderu 3:78f223d34f36 649
ethaderu 3:78f223d34f36 650 /*!
ethaderu 3:78f223d34f36 651 * @}
ethaderu 3:78f223d34f36 652 */ /* end of group ADC_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 653
ethaderu 3:78f223d34f36 654
ethaderu 3:78f223d34f36 655 /*!
ethaderu 3:78f223d34f36 656 * @}
ethaderu 3:78f223d34f36 657 */ /* end of group ADC_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 658
ethaderu 3:78f223d34f36 659
ethaderu 3:78f223d34f36 660 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 661 -- AIPS Peripheral Access Layer
ethaderu 3:78f223d34f36 662 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 663
ethaderu 3:78f223d34f36 664 /*!
ethaderu 3:78f223d34f36 665 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
ethaderu 3:78f223d34f36 666 * @{
ethaderu 3:78f223d34f36 667 */
ethaderu 3:78f223d34f36 668
ethaderu 3:78f223d34f36 669 /** AIPS - Register Layout Typedef */
ethaderu 3:78f223d34f36 670 typedef struct {
ethaderu 3:78f223d34f36 671 __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
ethaderu 3:78f223d34f36 672 uint8_t RESERVED_0[28];
ethaderu 3:78f223d34f36 673 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
ethaderu 3:78f223d34f36 674 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
ethaderu 3:78f223d34f36 675 __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
ethaderu 3:78f223d34f36 676 __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
ethaderu 3:78f223d34f36 677 uint8_t RESERVED_1[16];
ethaderu 3:78f223d34f36 678 __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
ethaderu 3:78f223d34f36 679 __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
ethaderu 3:78f223d34f36 680 __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
ethaderu 3:78f223d34f36 681 __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
ethaderu 3:78f223d34f36 682 __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
ethaderu 3:78f223d34f36 683 __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
ethaderu 3:78f223d34f36 684 __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
ethaderu 3:78f223d34f36 685 __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
ethaderu 3:78f223d34f36 686 __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
ethaderu 3:78f223d34f36 687 __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
ethaderu 3:78f223d34f36 688 __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
ethaderu 3:78f223d34f36 689 __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
ethaderu 3:78f223d34f36 690 uint8_t RESERVED_2[16];
ethaderu 3:78f223d34f36 691 __IO uint32_t PACRU; /**< Peripheral Access Control Register, offset: 0x80 */
ethaderu 3:78f223d34f36 692 } AIPS_Type, *AIPS_MemMapPtr;
ethaderu 3:78f223d34f36 693
ethaderu 3:78f223d34f36 694 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 695 -- AIPS - Register accessor macros
ethaderu 3:78f223d34f36 696 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 697
ethaderu 3:78f223d34f36 698 /*!
ethaderu 3:78f223d34f36 699 * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
ethaderu 3:78f223d34f36 700 * @{
ethaderu 3:78f223d34f36 701 */
ethaderu 3:78f223d34f36 702
ethaderu 3:78f223d34f36 703
ethaderu 3:78f223d34f36 704 /* AIPS - Register accessors */
ethaderu 3:78f223d34f36 705 #define AIPS_MPRA_REG(base) ((base)->MPRA)
ethaderu 3:78f223d34f36 706 #define AIPS_PACRA_REG(base) ((base)->PACRA)
ethaderu 3:78f223d34f36 707 #define AIPS_PACRB_REG(base) ((base)->PACRB)
ethaderu 3:78f223d34f36 708 #define AIPS_PACRC_REG(base) ((base)->PACRC)
ethaderu 3:78f223d34f36 709 #define AIPS_PACRD_REG(base) ((base)->PACRD)
ethaderu 3:78f223d34f36 710 #define AIPS_PACRE_REG(base) ((base)->PACRE)
ethaderu 3:78f223d34f36 711 #define AIPS_PACRF_REG(base) ((base)->PACRF)
ethaderu 3:78f223d34f36 712 #define AIPS_PACRG_REG(base) ((base)->PACRG)
ethaderu 3:78f223d34f36 713 #define AIPS_PACRH_REG(base) ((base)->PACRH)
ethaderu 3:78f223d34f36 714 #define AIPS_PACRI_REG(base) ((base)->PACRI)
ethaderu 3:78f223d34f36 715 #define AIPS_PACRJ_REG(base) ((base)->PACRJ)
ethaderu 3:78f223d34f36 716 #define AIPS_PACRK_REG(base) ((base)->PACRK)
ethaderu 3:78f223d34f36 717 #define AIPS_PACRL_REG(base) ((base)->PACRL)
ethaderu 3:78f223d34f36 718 #define AIPS_PACRM_REG(base) ((base)->PACRM)
ethaderu 3:78f223d34f36 719 #define AIPS_PACRN_REG(base) ((base)->PACRN)
ethaderu 3:78f223d34f36 720 #define AIPS_PACRO_REG(base) ((base)->PACRO)
ethaderu 3:78f223d34f36 721 #define AIPS_PACRP_REG(base) ((base)->PACRP)
ethaderu 3:78f223d34f36 722 #define AIPS_PACRU_REG(base) ((base)->PACRU)
ethaderu 3:78f223d34f36 723
ethaderu 3:78f223d34f36 724 /*!
ethaderu 3:78f223d34f36 725 * @}
ethaderu 3:78f223d34f36 726 */ /* end of group AIPS_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 727
ethaderu 3:78f223d34f36 728
ethaderu 3:78f223d34f36 729 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 730 -- AIPS Register Masks
ethaderu 3:78f223d34f36 731 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 732
ethaderu 3:78f223d34f36 733 /*!
ethaderu 3:78f223d34f36 734 * @addtogroup AIPS_Register_Masks AIPS Register Masks
ethaderu 3:78f223d34f36 735 * @{
ethaderu 3:78f223d34f36 736 */
ethaderu 3:78f223d34f36 737
ethaderu 3:78f223d34f36 738 /* MPRA Bit Fields */
ethaderu 3:78f223d34f36 739 #define AIPS_MPRA_MPL5_MASK 0x100u
ethaderu 3:78f223d34f36 740 #define AIPS_MPRA_MPL5_SHIFT 8
ethaderu 3:78f223d34f36 741 #define AIPS_MPRA_MTW5_MASK 0x200u
ethaderu 3:78f223d34f36 742 #define AIPS_MPRA_MTW5_SHIFT 9
ethaderu 3:78f223d34f36 743 #define AIPS_MPRA_MTR5_MASK 0x400u
ethaderu 3:78f223d34f36 744 #define AIPS_MPRA_MTR5_SHIFT 10
ethaderu 3:78f223d34f36 745 #define AIPS_MPRA_MPL4_MASK 0x1000u
ethaderu 3:78f223d34f36 746 #define AIPS_MPRA_MPL4_SHIFT 12
ethaderu 3:78f223d34f36 747 #define AIPS_MPRA_MTW4_MASK 0x2000u
ethaderu 3:78f223d34f36 748 #define AIPS_MPRA_MTW4_SHIFT 13
ethaderu 3:78f223d34f36 749 #define AIPS_MPRA_MTR4_MASK 0x4000u
ethaderu 3:78f223d34f36 750 #define AIPS_MPRA_MTR4_SHIFT 14
ethaderu 3:78f223d34f36 751 #define AIPS_MPRA_MPL3_MASK 0x10000u
ethaderu 3:78f223d34f36 752 #define AIPS_MPRA_MPL3_SHIFT 16
ethaderu 3:78f223d34f36 753 #define AIPS_MPRA_MTW3_MASK 0x20000u
ethaderu 3:78f223d34f36 754 #define AIPS_MPRA_MTW3_SHIFT 17
ethaderu 3:78f223d34f36 755 #define AIPS_MPRA_MTR3_MASK 0x40000u
ethaderu 3:78f223d34f36 756 #define AIPS_MPRA_MTR3_SHIFT 18
ethaderu 3:78f223d34f36 757 #define AIPS_MPRA_MPL2_MASK 0x100000u
ethaderu 3:78f223d34f36 758 #define AIPS_MPRA_MPL2_SHIFT 20
ethaderu 3:78f223d34f36 759 #define AIPS_MPRA_MTW2_MASK 0x200000u
ethaderu 3:78f223d34f36 760 #define AIPS_MPRA_MTW2_SHIFT 21
ethaderu 3:78f223d34f36 761 #define AIPS_MPRA_MTR2_MASK 0x400000u
ethaderu 3:78f223d34f36 762 #define AIPS_MPRA_MTR2_SHIFT 22
ethaderu 3:78f223d34f36 763 #define AIPS_MPRA_MPL1_MASK 0x1000000u
ethaderu 3:78f223d34f36 764 #define AIPS_MPRA_MPL1_SHIFT 24
ethaderu 3:78f223d34f36 765 #define AIPS_MPRA_MTW1_MASK 0x2000000u
ethaderu 3:78f223d34f36 766 #define AIPS_MPRA_MTW1_SHIFT 25
ethaderu 3:78f223d34f36 767 #define AIPS_MPRA_MTR1_MASK 0x4000000u
ethaderu 3:78f223d34f36 768 #define AIPS_MPRA_MTR1_SHIFT 26
ethaderu 3:78f223d34f36 769 #define AIPS_MPRA_MPL0_MASK 0x10000000u
ethaderu 3:78f223d34f36 770 #define AIPS_MPRA_MPL0_SHIFT 28
ethaderu 3:78f223d34f36 771 #define AIPS_MPRA_MTW0_MASK 0x20000000u
ethaderu 3:78f223d34f36 772 #define AIPS_MPRA_MTW0_SHIFT 29
ethaderu 3:78f223d34f36 773 #define AIPS_MPRA_MTR0_MASK 0x40000000u
ethaderu 3:78f223d34f36 774 #define AIPS_MPRA_MTR0_SHIFT 30
ethaderu 3:78f223d34f36 775 /* PACRA Bit Fields */
ethaderu 3:78f223d34f36 776 #define AIPS_PACRA_TP7_MASK 0x1u
ethaderu 3:78f223d34f36 777 #define AIPS_PACRA_TP7_SHIFT 0
ethaderu 3:78f223d34f36 778 #define AIPS_PACRA_WP7_MASK 0x2u
ethaderu 3:78f223d34f36 779 #define AIPS_PACRA_WP7_SHIFT 1
ethaderu 3:78f223d34f36 780 #define AIPS_PACRA_SP7_MASK 0x4u
ethaderu 3:78f223d34f36 781 #define AIPS_PACRA_SP7_SHIFT 2
ethaderu 3:78f223d34f36 782 #define AIPS_PACRA_TP6_MASK 0x10u
ethaderu 3:78f223d34f36 783 #define AIPS_PACRA_TP6_SHIFT 4
ethaderu 3:78f223d34f36 784 #define AIPS_PACRA_WP6_MASK 0x20u
ethaderu 3:78f223d34f36 785 #define AIPS_PACRA_WP6_SHIFT 5
ethaderu 3:78f223d34f36 786 #define AIPS_PACRA_SP6_MASK 0x40u
ethaderu 3:78f223d34f36 787 #define AIPS_PACRA_SP6_SHIFT 6
ethaderu 3:78f223d34f36 788 #define AIPS_PACRA_TP5_MASK 0x100u
ethaderu 3:78f223d34f36 789 #define AIPS_PACRA_TP5_SHIFT 8
ethaderu 3:78f223d34f36 790 #define AIPS_PACRA_WP5_MASK 0x200u
ethaderu 3:78f223d34f36 791 #define AIPS_PACRA_WP5_SHIFT 9
ethaderu 3:78f223d34f36 792 #define AIPS_PACRA_SP5_MASK 0x400u
ethaderu 3:78f223d34f36 793 #define AIPS_PACRA_SP5_SHIFT 10
ethaderu 3:78f223d34f36 794 #define AIPS_PACRA_TP4_MASK 0x1000u
ethaderu 3:78f223d34f36 795 #define AIPS_PACRA_TP4_SHIFT 12
ethaderu 3:78f223d34f36 796 #define AIPS_PACRA_WP4_MASK 0x2000u
ethaderu 3:78f223d34f36 797 #define AIPS_PACRA_WP4_SHIFT 13
ethaderu 3:78f223d34f36 798 #define AIPS_PACRA_SP4_MASK 0x4000u
ethaderu 3:78f223d34f36 799 #define AIPS_PACRA_SP4_SHIFT 14
ethaderu 3:78f223d34f36 800 #define AIPS_PACRA_TP3_MASK 0x10000u
ethaderu 3:78f223d34f36 801 #define AIPS_PACRA_TP3_SHIFT 16
ethaderu 3:78f223d34f36 802 #define AIPS_PACRA_WP3_MASK 0x20000u
ethaderu 3:78f223d34f36 803 #define AIPS_PACRA_WP3_SHIFT 17
ethaderu 3:78f223d34f36 804 #define AIPS_PACRA_SP3_MASK 0x40000u
ethaderu 3:78f223d34f36 805 #define AIPS_PACRA_SP3_SHIFT 18
ethaderu 3:78f223d34f36 806 #define AIPS_PACRA_TP2_MASK 0x100000u
ethaderu 3:78f223d34f36 807 #define AIPS_PACRA_TP2_SHIFT 20
ethaderu 3:78f223d34f36 808 #define AIPS_PACRA_WP2_MASK 0x200000u
ethaderu 3:78f223d34f36 809 #define AIPS_PACRA_WP2_SHIFT 21
ethaderu 3:78f223d34f36 810 #define AIPS_PACRA_SP2_MASK 0x400000u
ethaderu 3:78f223d34f36 811 #define AIPS_PACRA_SP2_SHIFT 22
ethaderu 3:78f223d34f36 812 #define AIPS_PACRA_TP1_MASK 0x1000000u
ethaderu 3:78f223d34f36 813 #define AIPS_PACRA_TP1_SHIFT 24
ethaderu 3:78f223d34f36 814 #define AIPS_PACRA_WP1_MASK 0x2000000u
ethaderu 3:78f223d34f36 815 #define AIPS_PACRA_WP1_SHIFT 25
ethaderu 3:78f223d34f36 816 #define AIPS_PACRA_SP1_MASK 0x4000000u
ethaderu 3:78f223d34f36 817 #define AIPS_PACRA_SP1_SHIFT 26
ethaderu 3:78f223d34f36 818 #define AIPS_PACRA_TP0_MASK 0x10000000u
ethaderu 3:78f223d34f36 819 #define AIPS_PACRA_TP0_SHIFT 28
ethaderu 3:78f223d34f36 820 #define AIPS_PACRA_WP0_MASK 0x20000000u
ethaderu 3:78f223d34f36 821 #define AIPS_PACRA_WP0_SHIFT 29
ethaderu 3:78f223d34f36 822 #define AIPS_PACRA_SP0_MASK 0x40000000u
ethaderu 3:78f223d34f36 823 #define AIPS_PACRA_SP0_SHIFT 30
ethaderu 3:78f223d34f36 824 /* PACRB Bit Fields */
ethaderu 3:78f223d34f36 825 #define AIPS_PACRB_TP7_MASK 0x1u
ethaderu 3:78f223d34f36 826 #define AIPS_PACRB_TP7_SHIFT 0
ethaderu 3:78f223d34f36 827 #define AIPS_PACRB_WP7_MASK 0x2u
ethaderu 3:78f223d34f36 828 #define AIPS_PACRB_WP7_SHIFT 1
ethaderu 3:78f223d34f36 829 #define AIPS_PACRB_SP7_MASK 0x4u
ethaderu 3:78f223d34f36 830 #define AIPS_PACRB_SP7_SHIFT 2
ethaderu 3:78f223d34f36 831 #define AIPS_PACRB_TP6_MASK 0x10u
ethaderu 3:78f223d34f36 832 #define AIPS_PACRB_TP6_SHIFT 4
ethaderu 3:78f223d34f36 833 #define AIPS_PACRB_WP6_MASK 0x20u
ethaderu 3:78f223d34f36 834 #define AIPS_PACRB_WP6_SHIFT 5
ethaderu 3:78f223d34f36 835 #define AIPS_PACRB_SP6_MASK 0x40u
ethaderu 3:78f223d34f36 836 #define AIPS_PACRB_SP6_SHIFT 6
ethaderu 3:78f223d34f36 837 #define AIPS_PACRB_TP5_MASK 0x100u
ethaderu 3:78f223d34f36 838 #define AIPS_PACRB_TP5_SHIFT 8
ethaderu 3:78f223d34f36 839 #define AIPS_PACRB_WP5_MASK 0x200u
ethaderu 3:78f223d34f36 840 #define AIPS_PACRB_WP5_SHIFT 9
ethaderu 3:78f223d34f36 841 #define AIPS_PACRB_SP5_MASK 0x400u
ethaderu 3:78f223d34f36 842 #define AIPS_PACRB_SP5_SHIFT 10
ethaderu 3:78f223d34f36 843 #define AIPS_PACRB_TP4_MASK 0x1000u
ethaderu 3:78f223d34f36 844 #define AIPS_PACRB_TP4_SHIFT 12
ethaderu 3:78f223d34f36 845 #define AIPS_PACRB_WP4_MASK 0x2000u
ethaderu 3:78f223d34f36 846 #define AIPS_PACRB_WP4_SHIFT 13
ethaderu 3:78f223d34f36 847 #define AIPS_PACRB_SP4_MASK 0x4000u
ethaderu 3:78f223d34f36 848 #define AIPS_PACRB_SP4_SHIFT 14
ethaderu 3:78f223d34f36 849 #define AIPS_PACRB_TP3_MASK 0x10000u
ethaderu 3:78f223d34f36 850 #define AIPS_PACRB_TP3_SHIFT 16
ethaderu 3:78f223d34f36 851 #define AIPS_PACRB_WP3_MASK 0x20000u
ethaderu 3:78f223d34f36 852 #define AIPS_PACRB_WP3_SHIFT 17
ethaderu 3:78f223d34f36 853 #define AIPS_PACRB_SP3_MASK 0x40000u
ethaderu 3:78f223d34f36 854 #define AIPS_PACRB_SP3_SHIFT 18
ethaderu 3:78f223d34f36 855 #define AIPS_PACRB_TP2_MASK 0x100000u
ethaderu 3:78f223d34f36 856 #define AIPS_PACRB_TP2_SHIFT 20
ethaderu 3:78f223d34f36 857 #define AIPS_PACRB_WP2_MASK 0x200000u
ethaderu 3:78f223d34f36 858 #define AIPS_PACRB_WP2_SHIFT 21
ethaderu 3:78f223d34f36 859 #define AIPS_PACRB_SP2_MASK 0x400000u
ethaderu 3:78f223d34f36 860 #define AIPS_PACRB_SP2_SHIFT 22
ethaderu 3:78f223d34f36 861 #define AIPS_PACRB_TP1_MASK 0x1000000u
ethaderu 3:78f223d34f36 862 #define AIPS_PACRB_TP1_SHIFT 24
ethaderu 3:78f223d34f36 863 #define AIPS_PACRB_WP1_MASK 0x2000000u
ethaderu 3:78f223d34f36 864 #define AIPS_PACRB_WP1_SHIFT 25
ethaderu 3:78f223d34f36 865 #define AIPS_PACRB_SP1_MASK 0x4000000u
ethaderu 3:78f223d34f36 866 #define AIPS_PACRB_SP1_SHIFT 26
ethaderu 3:78f223d34f36 867 #define AIPS_PACRB_TP0_MASK 0x10000000u
ethaderu 3:78f223d34f36 868 #define AIPS_PACRB_TP0_SHIFT 28
ethaderu 3:78f223d34f36 869 #define AIPS_PACRB_WP0_MASK 0x20000000u
ethaderu 3:78f223d34f36 870 #define AIPS_PACRB_WP0_SHIFT 29
ethaderu 3:78f223d34f36 871 #define AIPS_PACRB_SP0_MASK 0x40000000u
ethaderu 3:78f223d34f36 872 #define AIPS_PACRB_SP0_SHIFT 30
ethaderu 3:78f223d34f36 873 /* PACRC Bit Fields */
ethaderu 3:78f223d34f36 874 #define AIPS_PACRC_TP7_MASK 0x1u
ethaderu 3:78f223d34f36 875 #define AIPS_PACRC_TP7_SHIFT 0
ethaderu 3:78f223d34f36 876 #define AIPS_PACRC_WP7_MASK 0x2u
ethaderu 3:78f223d34f36 877 #define AIPS_PACRC_WP7_SHIFT 1
ethaderu 3:78f223d34f36 878 #define AIPS_PACRC_SP7_MASK 0x4u
ethaderu 3:78f223d34f36 879 #define AIPS_PACRC_SP7_SHIFT 2
ethaderu 3:78f223d34f36 880 #define AIPS_PACRC_TP6_MASK 0x10u
ethaderu 3:78f223d34f36 881 #define AIPS_PACRC_TP6_SHIFT 4
ethaderu 3:78f223d34f36 882 #define AIPS_PACRC_WP6_MASK 0x20u
ethaderu 3:78f223d34f36 883 #define AIPS_PACRC_WP6_SHIFT 5
ethaderu 3:78f223d34f36 884 #define AIPS_PACRC_SP6_MASK 0x40u
ethaderu 3:78f223d34f36 885 #define AIPS_PACRC_SP6_SHIFT 6
ethaderu 3:78f223d34f36 886 #define AIPS_PACRC_TP5_MASK 0x100u
ethaderu 3:78f223d34f36 887 #define AIPS_PACRC_TP5_SHIFT 8
ethaderu 3:78f223d34f36 888 #define AIPS_PACRC_WP5_MASK 0x200u
ethaderu 3:78f223d34f36 889 #define AIPS_PACRC_WP5_SHIFT 9
ethaderu 3:78f223d34f36 890 #define AIPS_PACRC_SP5_MASK 0x400u
ethaderu 3:78f223d34f36 891 #define AIPS_PACRC_SP5_SHIFT 10
ethaderu 3:78f223d34f36 892 #define AIPS_PACRC_TP4_MASK 0x1000u
ethaderu 3:78f223d34f36 893 #define AIPS_PACRC_TP4_SHIFT 12
ethaderu 3:78f223d34f36 894 #define AIPS_PACRC_WP4_MASK 0x2000u
ethaderu 3:78f223d34f36 895 #define AIPS_PACRC_WP4_SHIFT 13
ethaderu 3:78f223d34f36 896 #define AIPS_PACRC_SP4_MASK 0x4000u
ethaderu 3:78f223d34f36 897 #define AIPS_PACRC_SP4_SHIFT 14
ethaderu 3:78f223d34f36 898 #define AIPS_PACRC_TP3_MASK 0x10000u
ethaderu 3:78f223d34f36 899 #define AIPS_PACRC_TP3_SHIFT 16
ethaderu 3:78f223d34f36 900 #define AIPS_PACRC_WP3_MASK 0x20000u
ethaderu 3:78f223d34f36 901 #define AIPS_PACRC_WP3_SHIFT 17
ethaderu 3:78f223d34f36 902 #define AIPS_PACRC_SP3_MASK 0x40000u
ethaderu 3:78f223d34f36 903 #define AIPS_PACRC_SP3_SHIFT 18
ethaderu 3:78f223d34f36 904 #define AIPS_PACRC_TP2_MASK 0x100000u
ethaderu 3:78f223d34f36 905 #define AIPS_PACRC_TP2_SHIFT 20
ethaderu 3:78f223d34f36 906 #define AIPS_PACRC_WP2_MASK 0x200000u
ethaderu 3:78f223d34f36 907 #define AIPS_PACRC_WP2_SHIFT 21
ethaderu 3:78f223d34f36 908 #define AIPS_PACRC_SP2_MASK 0x400000u
ethaderu 3:78f223d34f36 909 #define AIPS_PACRC_SP2_SHIFT 22
ethaderu 3:78f223d34f36 910 #define AIPS_PACRC_TP1_MASK 0x1000000u
ethaderu 3:78f223d34f36 911 #define AIPS_PACRC_TP1_SHIFT 24
ethaderu 3:78f223d34f36 912 #define AIPS_PACRC_WP1_MASK 0x2000000u
ethaderu 3:78f223d34f36 913 #define AIPS_PACRC_WP1_SHIFT 25
ethaderu 3:78f223d34f36 914 #define AIPS_PACRC_SP1_MASK 0x4000000u
ethaderu 3:78f223d34f36 915 #define AIPS_PACRC_SP1_SHIFT 26
ethaderu 3:78f223d34f36 916 #define AIPS_PACRC_TP0_MASK 0x10000000u
ethaderu 3:78f223d34f36 917 #define AIPS_PACRC_TP0_SHIFT 28
ethaderu 3:78f223d34f36 918 #define AIPS_PACRC_WP0_MASK 0x20000000u
ethaderu 3:78f223d34f36 919 #define AIPS_PACRC_WP0_SHIFT 29
ethaderu 3:78f223d34f36 920 #define AIPS_PACRC_SP0_MASK 0x40000000u
ethaderu 3:78f223d34f36 921 #define AIPS_PACRC_SP0_SHIFT 30
ethaderu 3:78f223d34f36 922 /* PACRD Bit Fields */
ethaderu 3:78f223d34f36 923 #define AIPS_PACRD_TP7_MASK 0x1u
ethaderu 3:78f223d34f36 924 #define AIPS_PACRD_TP7_SHIFT 0
ethaderu 3:78f223d34f36 925 #define AIPS_PACRD_WP7_MASK 0x2u
ethaderu 3:78f223d34f36 926 #define AIPS_PACRD_WP7_SHIFT 1
ethaderu 3:78f223d34f36 927 #define AIPS_PACRD_SP7_MASK 0x4u
ethaderu 3:78f223d34f36 928 #define AIPS_PACRD_SP7_SHIFT 2
ethaderu 3:78f223d34f36 929 #define AIPS_PACRD_TP6_MASK 0x10u
ethaderu 3:78f223d34f36 930 #define AIPS_PACRD_TP6_SHIFT 4
ethaderu 3:78f223d34f36 931 #define AIPS_PACRD_WP6_MASK 0x20u
ethaderu 3:78f223d34f36 932 #define AIPS_PACRD_WP6_SHIFT 5
ethaderu 3:78f223d34f36 933 #define AIPS_PACRD_SP6_MASK 0x40u
ethaderu 3:78f223d34f36 934 #define AIPS_PACRD_SP6_SHIFT 6
ethaderu 3:78f223d34f36 935 #define AIPS_PACRD_TP5_MASK 0x100u
ethaderu 3:78f223d34f36 936 #define AIPS_PACRD_TP5_SHIFT 8
ethaderu 3:78f223d34f36 937 #define AIPS_PACRD_WP5_MASK 0x200u
ethaderu 3:78f223d34f36 938 #define AIPS_PACRD_WP5_SHIFT 9
ethaderu 3:78f223d34f36 939 #define AIPS_PACRD_SP5_MASK 0x400u
ethaderu 3:78f223d34f36 940 #define AIPS_PACRD_SP5_SHIFT 10
ethaderu 3:78f223d34f36 941 #define AIPS_PACRD_TP4_MASK 0x1000u
ethaderu 3:78f223d34f36 942 #define AIPS_PACRD_TP4_SHIFT 12
ethaderu 3:78f223d34f36 943 #define AIPS_PACRD_WP4_MASK 0x2000u
ethaderu 3:78f223d34f36 944 #define AIPS_PACRD_WP4_SHIFT 13
ethaderu 3:78f223d34f36 945 #define AIPS_PACRD_SP4_MASK 0x4000u
ethaderu 3:78f223d34f36 946 #define AIPS_PACRD_SP4_SHIFT 14
ethaderu 3:78f223d34f36 947 #define AIPS_PACRD_TP3_MASK 0x10000u
ethaderu 3:78f223d34f36 948 #define AIPS_PACRD_TP3_SHIFT 16
ethaderu 3:78f223d34f36 949 #define AIPS_PACRD_WP3_MASK 0x20000u
ethaderu 3:78f223d34f36 950 #define AIPS_PACRD_WP3_SHIFT 17
ethaderu 3:78f223d34f36 951 #define AIPS_PACRD_SP3_MASK 0x40000u
ethaderu 3:78f223d34f36 952 #define AIPS_PACRD_SP3_SHIFT 18
ethaderu 3:78f223d34f36 953 #define AIPS_PACRD_TP2_MASK 0x100000u
ethaderu 3:78f223d34f36 954 #define AIPS_PACRD_TP2_SHIFT 20
ethaderu 3:78f223d34f36 955 #define AIPS_PACRD_WP2_MASK 0x200000u
ethaderu 3:78f223d34f36 956 #define AIPS_PACRD_WP2_SHIFT 21
ethaderu 3:78f223d34f36 957 #define AIPS_PACRD_SP2_MASK 0x400000u
ethaderu 3:78f223d34f36 958 #define AIPS_PACRD_SP2_SHIFT 22
ethaderu 3:78f223d34f36 959 #define AIPS_PACRD_TP1_MASK 0x1000000u
ethaderu 3:78f223d34f36 960 #define AIPS_PACRD_TP1_SHIFT 24
ethaderu 3:78f223d34f36 961 #define AIPS_PACRD_WP1_MASK 0x2000000u
ethaderu 3:78f223d34f36 962 #define AIPS_PACRD_WP1_SHIFT 25
ethaderu 3:78f223d34f36 963 #define AIPS_PACRD_SP1_MASK 0x4000000u
ethaderu 3:78f223d34f36 964 #define AIPS_PACRD_SP1_SHIFT 26
ethaderu 3:78f223d34f36 965 #define AIPS_PACRD_TP0_MASK 0x10000000u
ethaderu 3:78f223d34f36 966 #define AIPS_PACRD_TP0_SHIFT 28
ethaderu 3:78f223d34f36 967 #define AIPS_PACRD_WP0_MASK 0x20000000u
ethaderu 3:78f223d34f36 968 #define AIPS_PACRD_WP0_SHIFT 29
ethaderu 3:78f223d34f36 969 #define AIPS_PACRD_SP0_MASK 0x40000000u
ethaderu 3:78f223d34f36 970 #define AIPS_PACRD_SP0_SHIFT 30
ethaderu 3:78f223d34f36 971 /* PACRE Bit Fields */
ethaderu 3:78f223d34f36 972 #define AIPS_PACRE_TP7_MASK 0x1u
ethaderu 3:78f223d34f36 973 #define AIPS_PACRE_TP7_SHIFT 0
ethaderu 3:78f223d34f36 974 #define AIPS_PACRE_WP7_MASK 0x2u
ethaderu 3:78f223d34f36 975 #define AIPS_PACRE_WP7_SHIFT 1
ethaderu 3:78f223d34f36 976 #define AIPS_PACRE_SP7_MASK 0x4u
ethaderu 3:78f223d34f36 977 #define AIPS_PACRE_SP7_SHIFT 2
ethaderu 3:78f223d34f36 978 #define AIPS_PACRE_TP6_MASK 0x10u
ethaderu 3:78f223d34f36 979 #define AIPS_PACRE_TP6_SHIFT 4
ethaderu 3:78f223d34f36 980 #define AIPS_PACRE_WP6_MASK 0x20u
ethaderu 3:78f223d34f36 981 #define AIPS_PACRE_WP6_SHIFT 5
ethaderu 3:78f223d34f36 982 #define AIPS_PACRE_SP6_MASK 0x40u
ethaderu 3:78f223d34f36 983 #define AIPS_PACRE_SP6_SHIFT 6
ethaderu 3:78f223d34f36 984 #define AIPS_PACRE_TP5_MASK 0x100u
ethaderu 3:78f223d34f36 985 #define AIPS_PACRE_TP5_SHIFT 8
ethaderu 3:78f223d34f36 986 #define AIPS_PACRE_WP5_MASK 0x200u
ethaderu 3:78f223d34f36 987 #define AIPS_PACRE_WP5_SHIFT 9
ethaderu 3:78f223d34f36 988 #define AIPS_PACRE_SP5_MASK 0x400u
ethaderu 3:78f223d34f36 989 #define AIPS_PACRE_SP5_SHIFT 10
ethaderu 3:78f223d34f36 990 #define AIPS_PACRE_TP4_MASK 0x1000u
ethaderu 3:78f223d34f36 991 #define AIPS_PACRE_TP4_SHIFT 12
ethaderu 3:78f223d34f36 992 #define AIPS_PACRE_WP4_MASK 0x2000u
ethaderu 3:78f223d34f36 993 #define AIPS_PACRE_WP4_SHIFT 13
ethaderu 3:78f223d34f36 994 #define AIPS_PACRE_SP4_MASK 0x4000u
ethaderu 3:78f223d34f36 995 #define AIPS_PACRE_SP4_SHIFT 14
ethaderu 3:78f223d34f36 996 #define AIPS_PACRE_TP3_MASK 0x10000u
ethaderu 3:78f223d34f36 997 #define AIPS_PACRE_TP3_SHIFT 16
ethaderu 3:78f223d34f36 998 #define AIPS_PACRE_WP3_MASK 0x20000u
ethaderu 3:78f223d34f36 999 #define AIPS_PACRE_WP3_SHIFT 17
ethaderu 3:78f223d34f36 1000 #define AIPS_PACRE_SP3_MASK 0x40000u
ethaderu 3:78f223d34f36 1001 #define AIPS_PACRE_SP3_SHIFT 18
ethaderu 3:78f223d34f36 1002 #define AIPS_PACRE_TP2_MASK 0x100000u
ethaderu 3:78f223d34f36 1003 #define AIPS_PACRE_TP2_SHIFT 20
ethaderu 3:78f223d34f36 1004 #define AIPS_PACRE_WP2_MASK 0x200000u
ethaderu 3:78f223d34f36 1005 #define AIPS_PACRE_WP2_SHIFT 21
ethaderu 3:78f223d34f36 1006 #define AIPS_PACRE_SP2_MASK 0x400000u
ethaderu 3:78f223d34f36 1007 #define AIPS_PACRE_SP2_SHIFT 22
ethaderu 3:78f223d34f36 1008 #define AIPS_PACRE_TP1_MASK 0x1000000u
ethaderu 3:78f223d34f36 1009 #define AIPS_PACRE_TP1_SHIFT 24
ethaderu 3:78f223d34f36 1010 #define AIPS_PACRE_WP1_MASK 0x2000000u
ethaderu 3:78f223d34f36 1011 #define AIPS_PACRE_WP1_SHIFT 25
ethaderu 3:78f223d34f36 1012 #define AIPS_PACRE_SP1_MASK 0x4000000u
ethaderu 3:78f223d34f36 1013 #define AIPS_PACRE_SP1_SHIFT 26
ethaderu 3:78f223d34f36 1014 #define AIPS_PACRE_TP0_MASK 0x10000000u
ethaderu 3:78f223d34f36 1015 #define AIPS_PACRE_TP0_SHIFT 28
ethaderu 3:78f223d34f36 1016 #define AIPS_PACRE_WP0_MASK 0x20000000u
ethaderu 3:78f223d34f36 1017 #define AIPS_PACRE_WP0_SHIFT 29
ethaderu 3:78f223d34f36 1018 #define AIPS_PACRE_SP0_MASK 0x40000000u
ethaderu 3:78f223d34f36 1019 #define AIPS_PACRE_SP0_SHIFT 30
ethaderu 3:78f223d34f36 1020 /* PACRF Bit Fields */
ethaderu 3:78f223d34f36 1021 #define AIPS_PACRF_TP7_MASK 0x1u
ethaderu 3:78f223d34f36 1022 #define AIPS_PACRF_TP7_SHIFT 0
ethaderu 3:78f223d34f36 1023 #define AIPS_PACRF_WP7_MASK 0x2u
ethaderu 3:78f223d34f36 1024 #define AIPS_PACRF_WP7_SHIFT 1
ethaderu 3:78f223d34f36 1025 #define AIPS_PACRF_SP7_MASK 0x4u
ethaderu 3:78f223d34f36 1026 #define AIPS_PACRF_SP7_SHIFT 2
ethaderu 3:78f223d34f36 1027 #define AIPS_PACRF_TP6_MASK 0x10u
ethaderu 3:78f223d34f36 1028 #define AIPS_PACRF_TP6_SHIFT 4
ethaderu 3:78f223d34f36 1029 #define AIPS_PACRF_WP6_MASK 0x20u
ethaderu 3:78f223d34f36 1030 #define AIPS_PACRF_WP6_SHIFT 5
ethaderu 3:78f223d34f36 1031 #define AIPS_PACRF_SP6_MASK 0x40u
ethaderu 3:78f223d34f36 1032 #define AIPS_PACRF_SP6_SHIFT 6
ethaderu 3:78f223d34f36 1033 #define AIPS_PACRF_TP5_MASK 0x100u
ethaderu 3:78f223d34f36 1034 #define AIPS_PACRF_TP5_SHIFT 8
ethaderu 3:78f223d34f36 1035 #define AIPS_PACRF_WP5_MASK 0x200u
ethaderu 3:78f223d34f36 1036 #define AIPS_PACRF_WP5_SHIFT 9
ethaderu 3:78f223d34f36 1037 #define AIPS_PACRF_SP5_MASK 0x400u
ethaderu 3:78f223d34f36 1038 #define AIPS_PACRF_SP5_SHIFT 10
ethaderu 3:78f223d34f36 1039 #define AIPS_PACRF_TP4_MASK 0x1000u
ethaderu 3:78f223d34f36 1040 #define AIPS_PACRF_TP4_SHIFT 12
ethaderu 3:78f223d34f36 1041 #define AIPS_PACRF_WP4_MASK 0x2000u
ethaderu 3:78f223d34f36 1042 #define AIPS_PACRF_WP4_SHIFT 13
ethaderu 3:78f223d34f36 1043 #define AIPS_PACRF_SP4_MASK 0x4000u
ethaderu 3:78f223d34f36 1044 #define AIPS_PACRF_SP4_SHIFT 14
ethaderu 3:78f223d34f36 1045 #define AIPS_PACRF_TP3_MASK 0x10000u
ethaderu 3:78f223d34f36 1046 #define AIPS_PACRF_TP3_SHIFT 16
ethaderu 3:78f223d34f36 1047 #define AIPS_PACRF_WP3_MASK 0x20000u
ethaderu 3:78f223d34f36 1048 #define AIPS_PACRF_WP3_SHIFT 17
ethaderu 3:78f223d34f36 1049 #define AIPS_PACRF_SP3_MASK 0x40000u
ethaderu 3:78f223d34f36 1050 #define AIPS_PACRF_SP3_SHIFT 18
ethaderu 3:78f223d34f36 1051 #define AIPS_PACRF_TP2_MASK 0x100000u
ethaderu 3:78f223d34f36 1052 #define AIPS_PACRF_TP2_SHIFT 20
ethaderu 3:78f223d34f36 1053 #define AIPS_PACRF_WP2_MASK 0x200000u
ethaderu 3:78f223d34f36 1054 #define AIPS_PACRF_WP2_SHIFT 21
ethaderu 3:78f223d34f36 1055 #define AIPS_PACRF_SP2_MASK 0x400000u
ethaderu 3:78f223d34f36 1056 #define AIPS_PACRF_SP2_SHIFT 22
ethaderu 3:78f223d34f36 1057 #define AIPS_PACRF_TP1_MASK 0x1000000u
ethaderu 3:78f223d34f36 1058 #define AIPS_PACRF_TP1_SHIFT 24
ethaderu 3:78f223d34f36 1059 #define AIPS_PACRF_WP1_MASK 0x2000000u
ethaderu 3:78f223d34f36 1060 #define AIPS_PACRF_WP1_SHIFT 25
ethaderu 3:78f223d34f36 1061 #define AIPS_PACRF_SP1_MASK 0x4000000u
ethaderu 3:78f223d34f36 1062 #define AIPS_PACRF_SP1_SHIFT 26
ethaderu 3:78f223d34f36 1063 #define AIPS_PACRF_TP0_MASK 0x10000000u
ethaderu 3:78f223d34f36 1064 #define AIPS_PACRF_TP0_SHIFT 28
ethaderu 3:78f223d34f36 1065 #define AIPS_PACRF_WP0_MASK 0x20000000u
ethaderu 3:78f223d34f36 1066 #define AIPS_PACRF_WP0_SHIFT 29
ethaderu 3:78f223d34f36 1067 #define AIPS_PACRF_SP0_MASK 0x40000000u
ethaderu 3:78f223d34f36 1068 #define AIPS_PACRF_SP0_SHIFT 30
ethaderu 3:78f223d34f36 1069 /* PACRG Bit Fields */
ethaderu 3:78f223d34f36 1070 #define AIPS_PACRG_TP7_MASK 0x1u
ethaderu 3:78f223d34f36 1071 #define AIPS_PACRG_TP7_SHIFT 0
ethaderu 3:78f223d34f36 1072 #define AIPS_PACRG_WP7_MASK 0x2u
ethaderu 3:78f223d34f36 1073 #define AIPS_PACRG_WP7_SHIFT 1
ethaderu 3:78f223d34f36 1074 #define AIPS_PACRG_SP7_MASK 0x4u
ethaderu 3:78f223d34f36 1075 #define AIPS_PACRG_SP7_SHIFT 2
ethaderu 3:78f223d34f36 1076 #define AIPS_PACRG_TP6_MASK 0x10u
ethaderu 3:78f223d34f36 1077 #define AIPS_PACRG_TP6_SHIFT 4
ethaderu 3:78f223d34f36 1078 #define AIPS_PACRG_WP6_MASK 0x20u
ethaderu 3:78f223d34f36 1079 #define AIPS_PACRG_WP6_SHIFT 5
ethaderu 3:78f223d34f36 1080 #define AIPS_PACRG_SP6_MASK 0x40u
ethaderu 3:78f223d34f36 1081 #define AIPS_PACRG_SP6_SHIFT 6
ethaderu 3:78f223d34f36 1082 #define AIPS_PACRG_TP5_MASK 0x100u
ethaderu 3:78f223d34f36 1083 #define AIPS_PACRG_TP5_SHIFT 8
ethaderu 3:78f223d34f36 1084 #define AIPS_PACRG_WP5_MASK 0x200u
ethaderu 3:78f223d34f36 1085 #define AIPS_PACRG_WP5_SHIFT 9
ethaderu 3:78f223d34f36 1086 #define AIPS_PACRG_SP5_MASK 0x400u
ethaderu 3:78f223d34f36 1087 #define AIPS_PACRG_SP5_SHIFT 10
ethaderu 3:78f223d34f36 1088 #define AIPS_PACRG_TP4_MASK 0x1000u
ethaderu 3:78f223d34f36 1089 #define AIPS_PACRG_TP4_SHIFT 12
ethaderu 3:78f223d34f36 1090 #define AIPS_PACRG_WP4_MASK 0x2000u
ethaderu 3:78f223d34f36 1091 #define AIPS_PACRG_WP4_SHIFT 13
ethaderu 3:78f223d34f36 1092 #define AIPS_PACRG_SP4_MASK 0x4000u
ethaderu 3:78f223d34f36 1093 #define AIPS_PACRG_SP4_SHIFT 14
ethaderu 3:78f223d34f36 1094 #define AIPS_PACRG_TP3_MASK 0x10000u
ethaderu 3:78f223d34f36 1095 #define AIPS_PACRG_TP3_SHIFT 16
ethaderu 3:78f223d34f36 1096 #define AIPS_PACRG_WP3_MASK 0x20000u
ethaderu 3:78f223d34f36 1097 #define AIPS_PACRG_WP3_SHIFT 17
ethaderu 3:78f223d34f36 1098 #define AIPS_PACRG_SP3_MASK 0x40000u
ethaderu 3:78f223d34f36 1099 #define AIPS_PACRG_SP3_SHIFT 18
ethaderu 3:78f223d34f36 1100 #define AIPS_PACRG_TP2_MASK 0x100000u
ethaderu 3:78f223d34f36 1101 #define AIPS_PACRG_TP2_SHIFT 20
ethaderu 3:78f223d34f36 1102 #define AIPS_PACRG_WP2_MASK 0x200000u
ethaderu 3:78f223d34f36 1103 #define AIPS_PACRG_WP2_SHIFT 21
ethaderu 3:78f223d34f36 1104 #define AIPS_PACRG_SP2_MASK 0x400000u
ethaderu 3:78f223d34f36 1105 #define AIPS_PACRG_SP2_SHIFT 22
ethaderu 3:78f223d34f36 1106 #define AIPS_PACRG_TP1_MASK 0x1000000u
ethaderu 3:78f223d34f36 1107 #define AIPS_PACRG_TP1_SHIFT 24
ethaderu 3:78f223d34f36 1108 #define AIPS_PACRG_WP1_MASK 0x2000000u
ethaderu 3:78f223d34f36 1109 #define AIPS_PACRG_WP1_SHIFT 25
ethaderu 3:78f223d34f36 1110 #define AIPS_PACRG_SP1_MASK 0x4000000u
ethaderu 3:78f223d34f36 1111 #define AIPS_PACRG_SP1_SHIFT 26
ethaderu 3:78f223d34f36 1112 #define AIPS_PACRG_TP0_MASK 0x10000000u
ethaderu 3:78f223d34f36 1113 #define AIPS_PACRG_TP0_SHIFT 28
ethaderu 3:78f223d34f36 1114 #define AIPS_PACRG_WP0_MASK 0x20000000u
ethaderu 3:78f223d34f36 1115 #define AIPS_PACRG_WP0_SHIFT 29
ethaderu 3:78f223d34f36 1116 #define AIPS_PACRG_SP0_MASK 0x40000000u
ethaderu 3:78f223d34f36 1117 #define AIPS_PACRG_SP0_SHIFT 30
ethaderu 3:78f223d34f36 1118 /* PACRH Bit Fields */
ethaderu 3:78f223d34f36 1119 #define AIPS_PACRH_TP7_MASK 0x1u
ethaderu 3:78f223d34f36 1120 #define AIPS_PACRH_TP7_SHIFT 0
ethaderu 3:78f223d34f36 1121 #define AIPS_PACRH_WP7_MASK 0x2u
ethaderu 3:78f223d34f36 1122 #define AIPS_PACRH_WP7_SHIFT 1
ethaderu 3:78f223d34f36 1123 #define AIPS_PACRH_SP7_MASK 0x4u
ethaderu 3:78f223d34f36 1124 #define AIPS_PACRH_SP7_SHIFT 2
ethaderu 3:78f223d34f36 1125 #define AIPS_PACRH_TP6_MASK 0x10u
ethaderu 3:78f223d34f36 1126 #define AIPS_PACRH_TP6_SHIFT 4
ethaderu 3:78f223d34f36 1127 #define AIPS_PACRH_WP6_MASK 0x20u
ethaderu 3:78f223d34f36 1128 #define AIPS_PACRH_WP6_SHIFT 5
ethaderu 3:78f223d34f36 1129 #define AIPS_PACRH_SP6_MASK 0x40u
ethaderu 3:78f223d34f36 1130 #define AIPS_PACRH_SP6_SHIFT 6
ethaderu 3:78f223d34f36 1131 #define AIPS_PACRH_TP5_MASK 0x100u
ethaderu 3:78f223d34f36 1132 #define AIPS_PACRH_TP5_SHIFT 8
ethaderu 3:78f223d34f36 1133 #define AIPS_PACRH_WP5_MASK 0x200u
ethaderu 3:78f223d34f36 1134 #define AIPS_PACRH_WP5_SHIFT 9
ethaderu 3:78f223d34f36 1135 #define AIPS_PACRH_SP5_MASK 0x400u
ethaderu 3:78f223d34f36 1136 #define AIPS_PACRH_SP5_SHIFT 10
ethaderu 3:78f223d34f36 1137 #define AIPS_PACRH_TP4_MASK 0x1000u
ethaderu 3:78f223d34f36 1138 #define AIPS_PACRH_TP4_SHIFT 12
ethaderu 3:78f223d34f36 1139 #define AIPS_PACRH_WP4_MASK 0x2000u
ethaderu 3:78f223d34f36 1140 #define AIPS_PACRH_WP4_SHIFT 13
ethaderu 3:78f223d34f36 1141 #define AIPS_PACRH_SP4_MASK 0x4000u
ethaderu 3:78f223d34f36 1142 #define AIPS_PACRH_SP4_SHIFT 14
ethaderu 3:78f223d34f36 1143 #define AIPS_PACRH_TP3_MASK 0x10000u
ethaderu 3:78f223d34f36 1144 #define AIPS_PACRH_TP3_SHIFT 16
ethaderu 3:78f223d34f36 1145 #define AIPS_PACRH_WP3_MASK 0x20000u
ethaderu 3:78f223d34f36 1146 #define AIPS_PACRH_WP3_SHIFT 17
ethaderu 3:78f223d34f36 1147 #define AIPS_PACRH_SP3_MASK 0x40000u
ethaderu 3:78f223d34f36 1148 #define AIPS_PACRH_SP3_SHIFT 18
ethaderu 3:78f223d34f36 1149 #define AIPS_PACRH_TP2_MASK 0x100000u
ethaderu 3:78f223d34f36 1150 #define AIPS_PACRH_TP2_SHIFT 20
ethaderu 3:78f223d34f36 1151 #define AIPS_PACRH_WP2_MASK 0x200000u
ethaderu 3:78f223d34f36 1152 #define AIPS_PACRH_WP2_SHIFT 21
ethaderu 3:78f223d34f36 1153 #define AIPS_PACRH_SP2_MASK 0x400000u
ethaderu 3:78f223d34f36 1154 #define AIPS_PACRH_SP2_SHIFT 22
ethaderu 3:78f223d34f36 1155 #define AIPS_PACRH_TP1_MASK 0x1000000u
ethaderu 3:78f223d34f36 1156 #define AIPS_PACRH_TP1_SHIFT 24
ethaderu 3:78f223d34f36 1157 #define AIPS_PACRH_WP1_MASK 0x2000000u
ethaderu 3:78f223d34f36 1158 #define AIPS_PACRH_WP1_SHIFT 25
ethaderu 3:78f223d34f36 1159 #define AIPS_PACRH_SP1_MASK 0x4000000u
ethaderu 3:78f223d34f36 1160 #define AIPS_PACRH_SP1_SHIFT 26
ethaderu 3:78f223d34f36 1161 #define AIPS_PACRH_TP0_MASK 0x10000000u
ethaderu 3:78f223d34f36 1162 #define AIPS_PACRH_TP0_SHIFT 28
ethaderu 3:78f223d34f36 1163 #define AIPS_PACRH_WP0_MASK 0x20000000u
ethaderu 3:78f223d34f36 1164 #define AIPS_PACRH_WP0_SHIFT 29
ethaderu 3:78f223d34f36 1165 #define AIPS_PACRH_SP0_MASK 0x40000000u
ethaderu 3:78f223d34f36 1166 #define AIPS_PACRH_SP0_SHIFT 30
ethaderu 3:78f223d34f36 1167 /* PACRI Bit Fields */
ethaderu 3:78f223d34f36 1168 #define AIPS_PACRI_TP7_MASK 0x1u
ethaderu 3:78f223d34f36 1169 #define AIPS_PACRI_TP7_SHIFT 0
ethaderu 3:78f223d34f36 1170 #define AIPS_PACRI_WP7_MASK 0x2u
ethaderu 3:78f223d34f36 1171 #define AIPS_PACRI_WP7_SHIFT 1
ethaderu 3:78f223d34f36 1172 #define AIPS_PACRI_SP7_MASK 0x4u
ethaderu 3:78f223d34f36 1173 #define AIPS_PACRI_SP7_SHIFT 2
ethaderu 3:78f223d34f36 1174 #define AIPS_PACRI_TP6_MASK 0x10u
ethaderu 3:78f223d34f36 1175 #define AIPS_PACRI_TP6_SHIFT 4
ethaderu 3:78f223d34f36 1176 #define AIPS_PACRI_WP6_MASK 0x20u
ethaderu 3:78f223d34f36 1177 #define AIPS_PACRI_WP6_SHIFT 5
ethaderu 3:78f223d34f36 1178 #define AIPS_PACRI_SP6_MASK 0x40u
ethaderu 3:78f223d34f36 1179 #define AIPS_PACRI_SP6_SHIFT 6
ethaderu 3:78f223d34f36 1180 #define AIPS_PACRI_TP5_MASK 0x100u
ethaderu 3:78f223d34f36 1181 #define AIPS_PACRI_TP5_SHIFT 8
ethaderu 3:78f223d34f36 1182 #define AIPS_PACRI_WP5_MASK 0x200u
ethaderu 3:78f223d34f36 1183 #define AIPS_PACRI_WP5_SHIFT 9
ethaderu 3:78f223d34f36 1184 #define AIPS_PACRI_SP5_MASK 0x400u
ethaderu 3:78f223d34f36 1185 #define AIPS_PACRI_SP5_SHIFT 10
ethaderu 3:78f223d34f36 1186 #define AIPS_PACRI_TP4_MASK 0x1000u
ethaderu 3:78f223d34f36 1187 #define AIPS_PACRI_TP4_SHIFT 12
ethaderu 3:78f223d34f36 1188 #define AIPS_PACRI_WP4_MASK 0x2000u
ethaderu 3:78f223d34f36 1189 #define AIPS_PACRI_WP4_SHIFT 13
ethaderu 3:78f223d34f36 1190 #define AIPS_PACRI_SP4_MASK 0x4000u
ethaderu 3:78f223d34f36 1191 #define AIPS_PACRI_SP4_SHIFT 14
ethaderu 3:78f223d34f36 1192 #define AIPS_PACRI_TP3_MASK 0x10000u
ethaderu 3:78f223d34f36 1193 #define AIPS_PACRI_TP3_SHIFT 16
ethaderu 3:78f223d34f36 1194 #define AIPS_PACRI_WP3_MASK 0x20000u
ethaderu 3:78f223d34f36 1195 #define AIPS_PACRI_WP3_SHIFT 17
ethaderu 3:78f223d34f36 1196 #define AIPS_PACRI_SP3_MASK 0x40000u
ethaderu 3:78f223d34f36 1197 #define AIPS_PACRI_SP3_SHIFT 18
ethaderu 3:78f223d34f36 1198 #define AIPS_PACRI_TP2_MASK 0x100000u
ethaderu 3:78f223d34f36 1199 #define AIPS_PACRI_TP2_SHIFT 20
ethaderu 3:78f223d34f36 1200 #define AIPS_PACRI_WP2_MASK 0x200000u
ethaderu 3:78f223d34f36 1201 #define AIPS_PACRI_WP2_SHIFT 21
ethaderu 3:78f223d34f36 1202 #define AIPS_PACRI_SP2_MASK 0x400000u
ethaderu 3:78f223d34f36 1203 #define AIPS_PACRI_SP2_SHIFT 22
ethaderu 3:78f223d34f36 1204 #define AIPS_PACRI_TP1_MASK 0x1000000u
ethaderu 3:78f223d34f36 1205 #define AIPS_PACRI_TP1_SHIFT 24
ethaderu 3:78f223d34f36 1206 #define AIPS_PACRI_WP1_MASK 0x2000000u
ethaderu 3:78f223d34f36 1207 #define AIPS_PACRI_WP1_SHIFT 25
ethaderu 3:78f223d34f36 1208 #define AIPS_PACRI_SP1_MASK 0x4000000u
ethaderu 3:78f223d34f36 1209 #define AIPS_PACRI_SP1_SHIFT 26
ethaderu 3:78f223d34f36 1210 #define AIPS_PACRI_TP0_MASK 0x10000000u
ethaderu 3:78f223d34f36 1211 #define AIPS_PACRI_TP0_SHIFT 28
ethaderu 3:78f223d34f36 1212 #define AIPS_PACRI_WP0_MASK 0x20000000u
ethaderu 3:78f223d34f36 1213 #define AIPS_PACRI_WP0_SHIFT 29
ethaderu 3:78f223d34f36 1214 #define AIPS_PACRI_SP0_MASK 0x40000000u
ethaderu 3:78f223d34f36 1215 #define AIPS_PACRI_SP0_SHIFT 30
ethaderu 3:78f223d34f36 1216 /* PACRJ Bit Fields */
ethaderu 3:78f223d34f36 1217 #define AIPS_PACRJ_TP7_MASK 0x1u
ethaderu 3:78f223d34f36 1218 #define AIPS_PACRJ_TP7_SHIFT 0
ethaderu 3:78f223d34f36 1219 #define AIPS_PACRJ_WP7_MASK 0x2u
ethaderu 3:78f223d34f36 1220 #define AIPS_PACRJ_WP7_SHIFT 1
ethaderu 3:78f223d34f36 1221 #define AIPS_PACRJ_SP7_MASK 0x4u
ethaderu 3:78f223d34f36 1222 #define AIPS_PACRJ_SP7_SHIFT 2
ethaderu 3:78f223d34f36 1223 #define AIPS_PACRJ_TP6_MASK 0x10u
ethaderu 3:78f223d34f36 1224 #define AIPS_PACRJ_TP6_SHIFT 4
ethaderu 3:78f223d34f36 1225 #define AIPS_PACRJ_WP6_MASK 0x20u
ethaderu 3:78f223d34f36 1226 #define AIPS_PACRJ_WP6_SHIFT 5
ethaderu 3:78f223d34f36 1227 #define AIPS_PACRJ_SP6_MASK 0x40u
ethaderu 3:78f223d34f36 1228 #define AIPS_PACRJ_SP6_SHIFT 6
ethaderu 3:78f223d34f36 1229 #define AIPS_PACRJ_TP5_MASK 0x100u
ethaderu 3:78f223d34f36 1230 #define AIPS_PACRJ_TP5_SHIFT 8
ethaderu 3:78f223d34f36 1231 #define AIPS_PACRJ_WP5_MASK 0x200u
ethaderu 3:78f223d34f36 1232 #define AIPS_PACRJ_WP5_SHIFT 9
ethaderu 3:78f223d34f36 1233 #define AIPS_PACRJ_SP5_MASK 0x400u
ethaderu 3:78f223d34f36 1234 #define AIPS_PACRJ_SP5_SHIFT 10
ethaderu 3:78f223d34f36 1235 #define AIPS_PACRJ_TP4_MASK 0x1000u
ethaderu 3:78f223d34f36 1236 #define AIPS_PACRJ_TP4_SHIFT 12
ethaderu 3:78f223d34f36 1237 #define AIPS_PACRJ_WP4_MASK 0x2000u
ethaderu 3:78f223d34f36 1238 #define AIPS_PACRJ_WP4_SHIFT 13
ethaderu 3:78f223d34f36 1239 #define AIPS_PACRJ_SP4_MASK 0x4000u
ethaderu 3:78f223d34f36 1240 #define AIPS_PACRJ_SP4_SHIFT 14
ethaderu 3:78f223d34f36 1241 #define AIPS_PACRJ_TP3_MASK 0x10000u
ethaderu 3:78f223d34f36 1242 #define AIPS_PACRJ_TP3_SHIFT 16
ethaderu 3:78f223d34f36 1243 #define AIPS_PACRJ_WP3_MASK 0x20000u
ethaderu 3:78f223d34f36 1244 #define AIPS_PACRJ_WP3_SHIFT 17
ethaderu 3:78f223d34f36 1245 #define AIPS_PACRJ_SP3_MASK 0x40000u
ethaderu 3:78f223d34f36 1246 #define AIPS_PACRJ_SP3_SHIFT 18
ethaderu 3:78f223d34f36 1247 #define AIPS_PACRJ_TP2_MASK 0x100000u
ethaderu 3:78f223d34f36 1248 #define AIPS_PACRJ_TP2_SHIFT 20
ethaderu 3:78f223d34f36 1249 #define AIPS_PACRJ_WP2_MASK 0x200000u
ethaderu 3:78f223d34f36 1250 #define AIPS_PACRJ_WP2_SHIFT 21
ethaderu 3:78f223d34f36 1251 #define AIPS_PACRJ_SP2_MASK 0x400000u
ethaderu 3:78f223d34f36 1252 #define AIPS_PACRJ_SP2_SHIFT 22
ethaderu 3:78f223d34f36 1253 #define AIPS_PACRJ_TP1_MASK 0x1000000u
ethaderu 3:78f223d34f36 1254 #define AIPS_PACRJ_TP1_SHIFT 24
ethaderu 3:78f223d34f36 1255 #define AIPS_PACRJ_WP1_MASK 0x2000000u
ethaderu 3:78f223d34f36 1256 #define AIPS_PACRJ_WP1_SHIFT 25
ethaderu 3:78f223d34f36 1257 #define AIPS_PACRJ_SP1_MASK 0x4000000u
ethaderu 3:78f223d34f36 1258 #define AIPS_PACRJ_SP1_SHIFT 26
ethaderu 3:78f223d34f36 1259 #define AIPS_PACRJ_TP0_MASK 0x10000000u
ethaderu 3:78f223d34f36 1260 #define AIPS_PACRJ_TP0_SHIFT 28
ethaderu 3:78f223d34f36 1261 #define AIPS_PACRJ_WP0_MASK 0x20000000u
ethaderu 3:78f223d34f36 1262 #define AIPS_PACRJ_WP0_SHIFT 29
ethaderu 3:78f223d34f36 1263 #define AIPS_PACRJ_SP0_MASK 0x40000000u
ethaderu 3:78f223d34f36 1264 #define AIPS_PACRJ_SP0_SHIFT 30
ethaderu 3:78f223d34f36 1265 /* PACRK Bit Fields */
ethaderu 3:78f223d34f36 1266 #define AIPS_PACRK_TP7_MASK 0x1u
ethaderu 3:78f223d34f36 1267 #define AIPS_PACRK_TP7_SHIFT 0
ethaderu 3:78f223d34f36 1268 #define AIPS_PACRK_WP7_MASK 0x2u
ethaderu 3:78f223d34f36 1269 #define AIPS_PACRK_WP7_SHIFT 1
ethaderu 3:78f223d34f36 1270 #define AIPS_PACRK_SP7_MASK 0x4u
ethaderu 3:78f223d34f36 1271 #define AIPS_PACRK_SP7_SHIFT 2
ethaderu 3:78f223d34f36 1272 #define AIPS_PACRK_TP6_MASK 0x10u
ethaderu 3:78f223d34f36 1273 #define AIPS_PACRK_TP6_SHIFT 4
ethaderu 3:78f223d34f36 1274 #define AIPS_PACRK_WP6_MASK 0x20u
ethaderu 3:78f223d34f36 1275 #define AIPS_PACRK_WP6_SHIFT 5
ethaderu 3:78f223d34f36 1276 #define AIPS_PACRK_SP6_MASK 0x40u
ethaderu 3:78f223d34f36 1277 #define AIPS_PACRK_SP6_SHIFT 6
ethaderu 3:78f223d34f36 1278 #define AIPS_PACRK_TP5_MASK 0x100u
ethaderu 3:78f223d34f36 1279 #define AIPS_PACRK_TP5_SHIFT 8
ethaderu 3:78f223d34f36 1280 #define AIPS_PACRK_WP5_MASK 0x200u
ethaderu 3:78f223d34f36 1281 #define AIPS_PACRK_WP5_SHIFT 9
ethaderu 3:78f223d34f36 1282 #define AIPS_PACRK_SP5_MASK 0x400u
ethaderu 3:78f223d34f36 1283 #define AIPS_PACRK_SP5_SHIFT 10
ethaderu 3:78f223d34f36 1284 #define AIPS_PACRK_TP4_MASK 0x1000u
ethaderu 3:78f223d34f36 1285 #define AIPS_PACRK_TP4_SHIFT 12
ethaderu 3:78f223d34f36 1286 #define AIPS_PACRK_WP4_MASK 0x2000u
ethaderu 3:78f223d34f36 1287 #define AIPS_PACRK_WP4_SHIFT 13
ethaderu 3:78f223d34f36 1288 #define AIPS_PACRK_SP4_MASK 0x4000u
ethaderu 3:78f223d34f36 1289 #define AIPS_PACRK_SP4_SHIFT 14
ethaderu 3:78f223d34f36 1290 #define AIPS_PACRK_TP3_MASK 0x10000u
ethaderu 3:78f223d34f36 1291 #define AIPS_PACRK_TP3_SHIFT 16
ethaderu 3:78f223d34f36 1292 #define AIPS_PACRK_WP3_MASK 0x20000u
ethaderu 3:78f223d34f36 1293 #define AIPS_PACRK_WP3_SHIFT 17
ethaderu 3:78f223d34f36 1294 #define AIPS_PACRK_SP3_MASK 0x40000u
ethaderu 3:78f223d34f36 1295 #define AIPS_PACRK_SP3_SHIFT 18
ethaderu 3:78f223d34f36 1296 #define AIPS_PACRK_TP2_MASK 0x100000u
ethaderu 3:78f223d34f36 1297 #define AIPS_PACRK_TP2_SHIFT 20
ethaderu 3:78f223d34f36 1298 #define AIPS_PACRK_WP2_MASK 0x200000u
ethaderu 3:78f223d34f36 1299 #define AIPS_PACRK_WP2_SHIFT 21
ethaderu 3:78f223d34f36 1300 #define AIPS_PACRK_SP2_MASK 0x400000u
ethaderu 3:78f223d34f36 1301 #define AIPS_PACRK_SP2_SHIFT 22
ethaderu 3:78f223d34f36 1302 #define AIPS_PACRK_TP1_MASK 0x1000000u
ethaderu 3:78f223d34f36 1303 #define AIPS_PACRK_TP1_SHIFT 24
ethaderu 3:78f223d34f36 1304 #define AIPS_PACRK_WP1_MASK 0x2000000u
ethaderu 3:78f223d34f36 1305 #define AIPS_PACRK_WP1_SHIFT 25
ethaderu 3:78f223d34f36 1306 #define AIPS_PACRK_SP1_MASK 0x4000000u
ethaderu 3:78f223d34f36 1307 #define AIPS_PACRK_SP1_SHIFT 26
ethaderu 3:78f223d34f36 1308 #define AIPS_PACRK_TP0_MASK 0x10000000u
ethaderu 3:78f223d34f36 1309 #define AIPS_PACRK_TP0_SHIFT 28
ethaderu 3:78f223d34f36 1310 #define AIPS_PACRK_WP0_MASK 0x20000000u
ethaderu 3:78f223d34f36 1311 #define AIPS_PACRK_WP0_SHIFT 29
ethaderu 3:78f223d34f36 1312 #define AIPS_PACRK_SP0_MASK 0x40000000u
ethaderu 3:78f223d34f36 1313 #define AIPS_PACRK_SP0_SHIFT 30
ethaderu 3:78f223d34f36 1314 /* PACRL Bit Fields */
ethaderu 3:78f223d34f36 1315 #define AIPS_PACRL_TP7_MASK 0x1u
ethaderu 3:78f223d34f36 1316 #define AIPS_PACRL_TP7_SHIFT 0
ethaderu 3:78f223d34f36 1317 #define AIPS_PACRL_WP7_MASK 0x2u
ethaderu 3:78f223d34f36 1318 #define AIPS_PACRL_WP7_SHIFT 1
ethaderu 3:78f223d34f36 1319 #define AIPS_PACRL_SP7_MASK 0x4u
ethaderu 3:78f223d34f36 1320 #define AIPS_PACRL_SP7_SHIFT 2
ethaderu 3:78f223d34f36 1321 #define AIPS_PACRL_TP6_MASK 0x10u
ethaderu 3:78f223d34f36 1322 #define AIPS_PACRL_TP6_SHIFT 4
ethaderu 3:78f223d34f36 1323 #define AIPS_PACRL_WP6_MASK 0x20u
ethaderu 3:78f223d34f36 1324 #define AIPS_PACRL_WP6_SHIFT 5
ethaderu 3:78f223d34f36 1325 #define AIPS_PACRL_SP6_MASK 0x40u
ethaderu 3:78f223d34f36 1326 #define AIPS_PACRL_SP6_SHIFT 6
ethaderu 3:78f223d34f36 1327 #define AIPS_PACRL_TP5_MASK 0x100u
ethaderu 3:78f223d34f36 1328 #define AIPS_PACRL_TP5_SHIFT 8
ethaderu 3:78f223d34f36 1329 #define AIPS_PACRL_WP5_MASK 0x200u
ethaderu 3:78f223d34f36 1330 #define AIPS_PACRL_WP5_SHIFT 9
ethaderu 3:78f223d34f36 1331 #define AIPS_PACRL_SP5_MASK 0x400u
ethaderu 3:78f223d34f36 1332 #define AIPS_PACRL_SP5_SHIFT 10
ethaderu 3:78f223d34f36 1333 #define AIPS_PACRL_TP4_MASK 0x1000u
ethaderu 3:78f223d34f36 1334 #define AIPS_PACRL_TP4_SHIFT 12
ethaderu 3:78f223d34f36 1335 #define AIPS_PACRL_WP4_MASK 0x2000u
ethaderu 3:78f223d34f36 1336 #define AIPS_PACRL_WP4_SHIFT 13
ethaderu 3:78f223d34f36 1337 #define AIPS_PACRL_SP4_MASK 0x4000u
ethaderu 3:78f223d34f36 1338 #define AIPS_PACRL_SP4_SHIFT 14
ethaderu 3:78f223d34f36 1339 #define AIPS_PACRL_TP3_MASK 0x10000u
ethaderu 3:78f223d34f36 1340 #define AIPS_PACRL_TP3_SHIFT 16
ethaderu 3:78f223d34f36 1341 #define AIPS_PACRL_WP3_MASK 0x20000u
ethaderu 3:78f223d34f36 1342 #define AIPS_PACRL_WP3_SHIFT 17
ethaderu 3:78f223d34f36 1343 #define AIPS_PACRL_SP3_MASK 0x40000u
ethaderu 3:78f223d34f36 1344 #define AIPS_PACRL_SP3_SHIFT 18
ethaderu 3:78f223d34f36 1345 #define AIPS_PACRL_TP2_MASK 0x100000u
ethaderu 3:78f223d34f36 1346 #define AIPS_PACRL_TP2_SHIFT 20
ethaderu 3:78f223d34f36 1347 #define AIPS_PACRL_WP2_MASK 0x200000u
ethaderu 3:78f223d34f36 1348 #define AIPS_PACRL_WP2_SHIFT 21
ethaderu 3:78f223d34f36 1349 #define AIPS_PACRL_SP2_MASK 0x400000u
ethaderu 3:78f223d34f36 1350 #define AIPS_PACRL_SP2_SHIFT 22
ethaderu 3:78f223d34f36 1351 #define AIPS_PACRL_TP1_MASK 0x1000000u
ethaderu 3:78f223d34f36 1352 #define AIPS_PACRL_TP1_SHIFT 24
ethaderu 3:78f223d34f36 1353 #define AIPS_PACRL_WP1_MASK 0x2000000u
ethaderu 3:78f223d34f36 1354 #define AIPS_PACRL_WP1_SHIFT 25
ethaderu 3:78f223d34f36 1355 #define AIPS_PACRL_SP1_MASK 0x4000000u
ethaderu 3:78f223d34f36 1356 #define AIPS_PACRL_SP1_SHIFT 26
ethaderu 3:78f223d34f36 1357 #define AIPS_PACRL_TP0_MASK 0x10000000u
ethaderu 3:78f223d34f36 1358 #define AIPS_PACRL_TP0_SHIFT 28
ethaderu 3:78f223d34f36 1359 #define AIPS_PACRL_WP0_MASK 0x20000000u
ethaderu 3:78f223d34f36 1360 #define AIPS_PACRL_WP0_SHIFT 29
ethaderu 3:78f223d34f36 1361 #define AIPS_PACRL_SP0_MASK 0x40000000u
ethaderu 3:78f223d34f36 1362 #define AIPS_PACRL_SP0_SHIFT 30
ethaderu 3:78f223d34f36 1363 /* PACRM Bit Fields */
ethaderu 3:78f223d34f36 1364 #define AIPS_PACRM_TP7_MASK 0x1u
ethaderu 3:78f223d34f36 1365 #define AIPS_PACRM_TP7_SHIFT 0
ethaderu 3:78f223d34f36 1366 #define AIPS_PACRM_WP7_MASK 0x2u
ethaderu 3:78f223d34f36 1367 #define AIPS_PACRM_WP7_SHIFT 1
ethaderu 3:78f223d34f36 1368 #define AIPS_PACRM_SP7_MASK 0x4u
ethaderu 3:78f223d34f36 1369 #define AIPS_PACRM_SP7_SHIFT 2
ethaderu 3:78f223d34f36 1370 #define AIPS_PACRM_TP6_MASK 0x10u
ethaderu 3:78f223d34f36 1371 #define AIPS_PACRM_TP6_SHIFT 4
ethaderu 3:78f223d34f36 1372 #define AIPS_PACRM_WP6_MASK 0x20u
ethaderu 3:78f223d34f36 1373 #define AIPS_PACRM_WP6_SHIFT 5
ethaderu 3:78f223d34f36 1374 #define AIPS_PACRM_SP6_MASK 0x40u
ethaderu 3:78f223d34f36 1375 #define AIPS_PACRM_SP6_SHIFT 6
ethaderu 3:78f223d34f36 1376 #define AIPS_PACRM_TP5_MASK 0x100u
ethaderu 3:78f223d34f36 1377 #define AIPS_PACRM_TP5_SHIFT 8
ethaderu 3:78f223d34f36 1378 #define AIPS_PACRM_WP5_MASK 0x200u
ethaderu 3:78f223d34f36 1379 #define AIPS_PACRM_WP5_SHIFT 9
ethaderu 3:78f223d34f36 1380 #define AIPS_PACRM_SP5_MASK 0x400u
ethaderu 3:78f223d34f36 1381 #define AIPS_PACRM_SP5_SHIFT 10
ethaderu 3:78f223d34f36 1382 #define AIPS_PACRM_TP4_MASK 0x1000u
ethaderu 3:78f223d34f36 1383 #define AIPS_PACRM_TP4_SHIFT 12
ethaderu 3:78f223d34f36 1384 #define AIPS_PACRM_WP4_MASK 0x2000u
ethaderu 3:78f223d34f36 1385 #define AIPS_PACRM_WP4_SHIFT 13
ethaderu 3:78f223d34f36 1386 #define AIPS_PACRM_SP4_MASK 0x4000u
ethaderu 3:78f223d34f36 1387 #define AIPS_PACRM_SP4_SHIFT 14
ethaderu 3:78f223d34f36 1388 #define AIPS_PACRM_TP3_MASK 0x10000u
ethaderu 3:78f223d34f36 1389 #define AIPS_PACRM_TP3_SHIFT 16
ethaderu 3:78f223d34f36 1390 #define AIPS_PACRM_WP3_MASK 0x20000u
ethaderu 3:78f223d34f36 1391 #define AIPS_PACRM_WP3_SHIFT 17
ethaderu 3:78f223d34f36 1392 #define AIPS_PACRM_SP3_MASK 0x40000u
ethaderu 3:78f223d34f36 1393 #define AIPS_PACRM_SP3_SHIFT 18
ethaderu 3:78f223d34f36 1394 #define AIPS_PACRM_TP2_MASK 0x100000u
ethaderu 3:78f223d34f36 1395 #define AIPS_PACRM_TP2_SHIFT 20
ethaderu 3:78f223d34f36 1396 #define AIPS_PACRM_WP2_MASK 0x200000u
ethaderu 3:78f223d34f36 1397 #define AIPS_PACRM_WP2_SHIFT 21
ethaderu 3:78f223d34f36 1398 #define AIPS_PACRM_SP2_MASK 0x400000u
ethaderu 3:78f223d34f36 1399 #define AIPS_PACRM_SP2_SHIFT 22
ethaderu 3:78f223d34f36 1400 #define AIPS_PACRM_TP1_MASK 0x1000000u
ethaderu 3:78f223d34f36 1401 #define AIPS_PACRM_TP1_SHIFT 24
ethaderu 3:78f223d34f36 1402 #define AIPS_PACRM_WP1_MASK 0x2000000u
ethaderu 3:78f223d34f36 1403 #define AIPS_PACRM_WP1_SHIFT 25
ethaderu 3:78f223d34f36 1404 #define AIPS_PACRM_SP1_MASK 0x4000000u
ethaderu 3:78f223d34f36 1405 #define AIPS_PACRM_SP1_SHIFT 26
ethaderu 3:78f223d34f36 1406 #define AIPS_PACRM_TP0_MASK 0x10000000u
ethaderu 3:78f223d34f36 1407 #define AIPS_PACRM_TP0_SHIFT 28
ethaderu 3:78f223d34f36 1408 #define AIPS_PACRM_WP0_MASK 0x20000000u
ethaderu 3:78f223d34f36 1409 #define AIPS_PACRM_WP0_SHIFT 29
ethaderu 3:78f223d34f36 1410 #define AIPS_PACRM_SP0_MASK 0x40000000u
ethaderu 3:78f223d34f36 1411 #define AIPS_PACRM_SP0_SHIFT 30
ethaderu 3:78f223d34f36 1412 /* PACRN Bit Fields */
ethaderu 3:78f223d34f36 1413 #define AIPS_PACRN_TP7_MASK 0x1u
ethaderu 3:78f223d34f36 1414 #define AIPS_PACRN_TP7_SHIFT 0
ethaderu 3:78f223d34f36 1415 #define AIPS_PACRN_WP7_MASK 0x2u
ethaderu 3:78f223d34f36 1416 #define AIPS_PACRN_WP7_SHIFT 1
ethaderu 3:78f223d34f36 1417 #define AIPS_PACRN_SP7_MASK 0x4u
ethaderu 3:78f223d34f36 1418 #define AIPS_PACRN_SP7_SHIFT 2
ethaderu 3:78f223d34f36 1419 #define AIPS_PACRN_TP6_MASK 0x10u
ethaderu 3:78f223d34f36 1420 #define AIPS_PACRN_TP6_SHIFT 4
ethaderu 3:78f223d34f36 1421 #define AIPS_PACRN_WP6_MASK 0x20u
ethaderu 3:78f223d34f36 1422 #define AIPS_PACRN_WP6_SHIFT 5
ethaderu 3:78f223d34f36 1423 #define AIPS_PACRN_SP6_MASK 0x40u
ethaderu 3:78f223d34f36 1424 #define AIPS_PACRN_SP6_SHIFT 6
ethaderu 3:78f223d34f36 1425 #define AIPS_PACRN_TP5_MASK 0x100u
ethaderu 3:78f223d34f36 1426 #define AIPS_PACRN_TP5_SHIFT 8
ethaderu 3:78f223d34f36 1427 #define AIPS_PACRN_WP5_MASK 0x200u
ethaderu 3:78f223d34f36 1428 #define AIPS_PACRN_WP5_SHIFT 9
ethaderu 3:78f223d34f36 1429 #define AIPS_PACRN_SP5_MASK 0x400u
ethaderu 3:78f223d34f36 1430 #define AIPS_PACRN_SP5_SHIFT 10
ethaderu 3:78f223d34f36 1431 #define AIPS_PACRN_TP4_MASK 0x1000u
ethaderu 3:78f223d34f36 1432 #define AIPS_PACRN_TP4_SHIFT 12
ethaderu 3:78f223d34f36 1433 #define AIPS_PACRN_WP4_MASK 0x2000u
ethaderu 3:78f223d34f36 1434 #define AIPS_PACRN_WP4_SHIFT 13
ethaderu 3:78f223d34f36 1435 #define AIPS_PACRN_SP4_MASK 0x4000u
ethaderu 3:78f223d34f36 1436 #define AIPS_PACRN_SP4_SHIFT 14
ethaderu 3:78f223d34f36 1437 #define AIPS_PACRN_TP3_MASK 0x10000u
ethaderu 3:78f223d34f36 1438 #define AIPS_PACRN_TP3_SHIFT 16
ethaderu 3:78f223d34f36 1439 #define AIPS_PACRN_WP3_MASK 0x20000u
ethaderu 3:78f223d34f36 1440 #define AIPS_PACRN_WP3_SHIFT 17
ethaderu 3:78f223d34f36 1441 #define AIPS_PACRN_SP3_MASK 0x40000u
ethaderu 3:78f223d34f36 1442 #define AIPS_PACRN_SP3_SHIFT 18
ethaderu 3:78f223d34f36 1443 #define AIPS_PACRN_TP2_MASK 0x100000u
ethaderu 3:78f223d34f36 1444 #define AIPS_PACRN_TP2_SHIFT 20
ethaderu 3:78f223d34f36 1445 #define AIPS_PACRN_WP2_MASK 0x200000u
ethaderu 3:78f223d34f36 1446 #define AIPS_PACRN_WP2_SHIFT 21
ethaderu 3:78f223d34f36 1447 #define AIPS_PACRN_SP2_MASK 0x400000u
ethaderu 3:78f223d34f36 1448 #define AIPS_PACRN_SP2_SHIFT 22
ethaderu 3:78f223d34f36 1449 #define AIPS_PACRN_TP1_MASK 0x1000000u
ethaderu 3:78f223d34f36 1450 #define AIPS_PACRN_TP1_SHIFT 24
ethaderu 3:78f223d34f36 1451 #define AIPS_PACRN_WP1_MASK 0x2000000u
ethaderu 3:78f223d34f36 1452 #define AIPS_PACRN_WP1_SHIFT 25
ethaderu 3:78f223d34f36 1453 #define AIPS_PACRN_SP1_MASK 0x4000000u
ethaderu 3:78f223d34f36 1454 #define AIPS_PACRN_SP1_SHIFT 26
ethaderu 3:78f223d34f36 1455 #define AIPS_PACRN_TP0_MASK 0x10000000u
ethaderu 3:78f223d34f36 1456 #define AIPS_PACRN_TP0_SHIFT 28
ethaderu 3:78f223d34f36 1457 #define AIPS_PACRN_WP0_MASK 0x20000000u
ethaderu 3:78f223d34f36 1458 #define AIPS_PACRN_WP0_SHIFT 29
ethaderu 3:78f223d34f36 1459 #define AIPS_PACRN_SP0_MASK 0x40000000u
ethaderu 3:78f223d34f36 1460 #define AIPS_PACRN_SP0_SHIFT 30
ethaderu 3:78f223d34f36 1461 /* PACRO Bit Fields */
ethaderu 3:78f223d34f36 1462 #define AIPS_PACRO_TP7_MASK 0x1u
ethaderu 3:78f223d34f36 1463 #define AIPS_PACRO_TP7_SHIFT 0
ethaderu 3:78f223d34f36 1464 #define AIPS_PACRO_WP7_MASK 0x2u
ethaderu 3:78f223d34f36 1465 #define AIPS_PACRO_WP7_SHIFT 1
ethaderu 3:78f223d34f36 1466 #define AIPS_PACRO_SP7_MASK 0x4u
ethaderu 3:78f223d34f36 1467 #define AIPS_PACRO_SP7_SHIFT 2
ethaderu 3:78f223d34f36 1468 #define AIPS_PACRO_TP6_MASK 0x10u
ethaderu 3:78f223d34f36 1469 #define AIPS_PACRO_TP6_SHIFT 4
ethaderu 3:78f223d34f36 1470 #define AIPS_PACRO_WP6_MASK 0x20u
ethaderu 3:78f223d34f36 1471 #define AIPS_PACRO_WP6_SHIFT 5
ethaderu 3:78f223d34f36 1472 #define AIPS_PACRO_SP6_MASK 0x40u
ethaderu 3:78f223d34f36 1473 #define AIPS_PACRO_SP6_SHIFT 6
ethaderu 3:78f223d34f36 1474 #define AIPS_PACRO_TP5_MASK 0x100u
ethaderu 3:78f223d34f36 1475 #define AIPS_PACRO_TP5_SHIFT 8
ethaderu 3:78f223d34f36 1476 #define AIPS_PACRO_WP5_MASK 0x200u
ethaderu 3:78f223d34f36 1477 #define AIPS_PACRO_WP5_SHIFT 9
ethaderu 3:78f223d34f36 1478 #define AIPS_PACRO_SP5_MASK 0x400u
ethaderu 3:78f223d34f36 1479 #define AIPS_PACRO_SP5_SHIFT 10
ethaderu 3:78f223d34f36 1480 #define AIPS_PACRO_TP4_MASK 0x1000u
ethaderu 3:78f223d34f36 1481 #define AIPS_PACRO_TP4_SHIFT 12
ethaderu 3:78f223d34f36 1482 #define AIPS_PACRO_WP4_MASK 0x2000u
ethaderu 3:78f223d34f36 1483 #define AIPS_PACRO_WP4_SHIFT 13
ethaderu 3:78f223d34f36 1484 #define AIPS_PACRO_SP4_MASK 0x4000u
ethaderu 3:78f223d34f36 1485 #define AIPS_PACRO_SP4_SHIFT 14
ethaderu 3:78f223d34f36 1486 #define AIPS_PACRO_TP3_MASK 0x10000u
ethaderu 3:78f223d34f36 1487 #define AIPS_PACRO_TP3_SHIFT 16
ethaderu 3:78f223d34f36 1488 #define AIPS_PACRO_WP3_MASK 0x20000u
ethaderu 3:78f223d34f36 1489 #define AIPS_PACRO_WP3_SHIFT 17
ethaderu 3:78f223d34f36 1490 #define AIPS_PACRO_SP3_MASK 0x40000u
ethaderu 3:78f223d34f36 1491 #define AIPS_PACRO_SP3_SHIFT 18
ethaderu 3:78f223d34f36 1492 #define AIPS_PACRO_TP2_MASK 0x100000u
ethaderu 3:78f223d34f36 1493 #define AIPS_PACRO_TP2_SHIFT 20
ethaderu 3:78f223d34f36 1494 #define AIPS_PACRO_WP2_MASK 0x200000u
ethaderu 3:78f223d34f36 1495 #define AIPS_PACRO_WP2_SHIFT 21
ethaderu 3:78f223d34f36 1496 #define AIPS_PACRO_SP2_MASK 0x400000u
ethaderu 3:78f223d34f36 1497 #define AIPS_PACRO_SP2_SHIFT 22
ethaderu 3:78f223d34f36 1498 #define AIPS_PACRO_TP1_MASK 0x1000000u
ethaderu 3:78f223d34f36 1499 #define AIPS_PACRO_TP1_SHIFT 24
ethaderu 3:78f223d34f36 1500 #define AIPS_PACRO_WP1_MASK 0x2000000u
ethaderu 3:78f223d34f36 1501 #define AIPS_PACRO_WP1_SHIFT 25
ethaderu 3:78f223d34f36 1502 #define AIPS_PACRO_SP1_MASK 0x4000000u
ethaderu 3:78f223d34f36 1503 #define AIPS_PACRO_SP1_SHIFT 26
ethaderu 3:78f223d34f36 1504 #define AIPS_PACRO_TP0_MASK 0x10000000u
ethaderu 3:78f223d34f36 1505 #define AIPS_PACRO_TP0_SHIFT 28
ethaderu 3:78f223d34f36 1506 #define AIPS_PACRO_WP0_MASK 0x20000000u
ethaderu 3:78f223d34f36 1507 #define AIPS_PACRO_WP0_SHIFT 29
ethaderu 3:78f223d34f36 1508 #define AIPS_PACRO_SP0_MASK 0x40000000u
ethaderu 3:78f223d34f36 1509 #define AIPS_PACRO_SP0_SHIFT 30
ethaderu 3:78f223d34f36 1510 /* PACRP Bit Fields */
ethaderu 3:78f223d34f36 1511 #define AIPS_PACRP_TP7_MASK 0x1u
ethaderu 3:78f223d34f36 1512 #define AIPS_PACRP_TP7_SHIFT 0
ethaderu 3:78f223d34f36 1513 #define AIPS_PACRP_WP7_MASK 0x2u
ethaderu 3:78f223d34f36 1514 #define AIPS_PACRP_WP7_SHIFT 1
ethaderu 3:78f223d34f36 1515 #define AIPS_PACRP_SP7_MASK 0x4u
ethaderu 3:78f223d34f36 1516 #define AIPS_PACRP_SP7_SHIFT 2
ethaderu 3:78f223d34f36 1517 #define AIPS_PACRP_TP6_MASK 0x10u
ethaderu 3:78f223d34f36 1518 #define AIPS_PACRP_TP6_SHIFT 4
ethaderu 3:78f223d34f36 1519 #define AIPS_PACRP_WP6_MASK 0x20u
ethaderu 3:78f223d34f36 1520 #define AIPS_PACRP_WP6_SHIFT 5
ethaderu 3:78f223d34f36 1521 #define AIPS_PACRP_SP6_MASK 0x40u
ethaderu 3:78f223d34f36 1522 #define AIPS_PACRP_SP6_SHIFT 6
ethaderu 3:78f223d34f36 1523 #define AIPS_PACRP_TP5_MASK 0x100u
ethaderu 3:78f223d34f36 1524 #define AIPS_PACRP_TP5_SHIFT 8
ethaderu 3:78f223d34f36 1525 #define AIPS_PACRP_WP5_MASK 0x200u
ethaderu 3:78f223d34f36 1526 #define AIPS_PACRP_WP5_SHIFT 9
ethaderu 3:78f223d34f36 1527 #define AIPS_PACRP_SP5_MASK 0x400u
ethaderu 3:78f223d34f36 1528 #define AIPS_PACRP_SP5_SHIFT 10
ethaderu 3:78f223d34f36 1529 #define AIPS_PACRP_TP4_MASK 0x1000u
ethaderu 3:78f223d34f36 1530 #define AIPS_PACRP_TP4_SHIFT 12
ethaderu 3:78f223d34f36 1531 #define AIPS_PACRP_WP4_MASK 0x2000u
ethaderu 3:78f223d34f36 1532 #define AIPS_PACRP_WP4_SHIFT 13
ethaderu 3:78f223d34f36 1533 #define AIPS_PACRP_SP4_MASK 0x4000u
ethaderu 3:78f223d34f36 1534 #define AIPS_PACRP_SP4_SHIFT 14
ethaderu 3:78f223d34f36 1535 #define AIPS_PACRP_TP3_MASK 0x10000u
ethaderu 3:78f223d34f36 1536 #define AIPS_PACRP_TP3_SHIFT 16
ethaderu 3:78f223d34f36 1537 #define AIPS_PACRP_WP3_MASK 0x20000u
ethaderu 3:78f223d34f36 1538 #define AIPS_PACRP_WP3_SHIFT 17
ethaderu 3:78f223d34f36 1539 #define AIPS_PACRP_SP3_MASK 0x40000u
ethaderu 3:78f223d34f36 1540 #define AIPS_PACRP_SP3_SHIFT 18
ethaderu 3:78f223d34f36 1541 #define AIPS_PACRP_TP2_MASK 0x100000u
ethaderu 3:78f223d34f36 1542 #define AIPS_PACRP_TP2_SHIFT 20
ethaderu 3:78f223d34f36 1543 #define AIPS_PACRP_WP2_MASK 0x200000u
ethaderu 3:78f223d34f36 1544 #define AIPS_PACRP_WP2_SHIFT 21
ethaderu 3:78f223d34f36 1545 #define AIPS_PACRP_SP2_MASK 0x400000u
ethaderu 3:78f223d34f36 1546 #define AIPS_PACRP_SP2_SHIFT 22
ethaderu 3:78f223d34f36 1547 #define AIPS_PACRP_TP1_MASK 0x1000000u
ethaderu 3:78f223d34f36 1548 #define AIPS_PACRP_TP1_SHIFT 24
ethaderu 3:78f223d34f36 1549 #define AIPS_PACRP_WP1_MASK 0x2000000u
ethaderu 3:78f223d34f36 1550 #define AIPS_PACRP_WP1_SHIFT 25
ethaderu 3:78f223d34f36 1551 #define AIPS_PACRP_SP1_MASK 0x4000000u
ethaderu 3:78f223d34f36 1552 #define AIPS_PACRP_SP1_SHIFT 26
ethaderu 3:78f223d34f36 1553 #define AIPS_PACRP_TP0_MASK 0x10000000u
ethaderu 3:78f223d34f36 1554 #define AIPS_PACRP_TP0_SHIFT 28
ethaderu 3:78f223d34f36 1555 #define AIPS_PACRP_WP0_MASK 0x20000000u
ethaderu 3:78f223d34f36 1556 #define AIPS_PACRP_WP0_SHIFT 29
ethaderu 3:78f223d34f36 1557 #define AIPS_PACRP_SP0_MASK 0x40000000u
ethaderu 3:78f223d34f36 1558 #define AIPS_PACRP_SP0_SHIFT 30
ethaderu 3:78f223d34f36 1559 /* PACRU Bit Fields */
ethaderu 3:78f223d34f36 1560 #define AIPS_PACRU_TP1_MASK 0x1000000u
ethaderu 3:78f223d34f36 1561 #define AIPS_PACRU_TP1_SHIFT 24
ethaderu 3:78f223d34f36 1562 #define AIPS_PACRU_WP1_MASK 0x2000000u
ethaderu 3:78f223d34f36 1563 #define AIPS_PACRU_WP1_SHIFT 25
ethaderu 3:78f223d34f36 1564 #define AIPS_PACRU_SP1_MASK 0x4000000u
ethaderu 3:78f223d34f36 1565 #define AIPS_PACRU_SP1_SHIFT 26
ethaderu 3:78f223d34f36 1566 #define AIPS_PACRU_TP0_MASK 0x10000000u
ethaderu 3:78f223d34f36 1567 #define AIPS_PACRU_TP0_SHIFT 28
ethaderu 3:78f223d34f36 1568 #define AIPS_PACRU_WP0_MASK 0x20000000u
ethaderu 3:78f223d34f36 1569 #define AIPS_PACRU_WP0_SHIFT 29
ethaderu 3:78f223d34f36 1570 #define AIPS_PACRU_SP0_MASK 0x40000000u
ethaderu 3:78f223d34f36 1571 #define AIPS_PACRU_SP0_SHIFT 30
ethaderu 3:78f223d34f36 1572
ethaderu 3:78f223d34f36 1573 /*!
ethaderu 3:78f223d34f36 1574 * @}
ethaderu 3:78f223d34f36 1575 */ /* end of group AIPS_Register_Masks */
ethaderu 3:78f223d34f36 1576
ethaderu 3:78f223d34f36 1577
ethaderu 3:78f223d34f36 1578 /* AIPS - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 1579 /** Peripheral AIPS0 base address */
ethaderu 3:78f223d34f36 1580 #define AIPS0_BASE (0x40000000u)
ethaderu 3:78f223d34f36 1581 /** Peripheral AIPS0 base pointer */
ethaderu 3:78f223d34f36 1582 #define AIPS0 ((AIPS_Type *)AIPS0_BASE)
ethaderu 3:78f223d34f36 1583 #define AIPS0_BASE_PTR (AIPS0)
ethaderu 3:78f223d34f36 1584 /** Peripheral AIPS1 base address */
ethaderu 3:78f223d34f36 1585 #define AIPS1_BASE (0x40080000u)
ethaderu 3:78f223d34f36 1586 /** Peripheral AIPS1 base pointer */
ethaderu 3:78f223d34f36 1587 #define AIPS1 ((AIPS_Type *)AIPS1_BASE)
ethaderu 3:78f223d34f36 1588 #define AIPS1_BASE_PTR (AIPS1)
ethaderu 3:78f223d34f36 1589 /** Array initializer of AIPS peripheral base addresses */
ethaderu 3:78f223d34f36 1590 #define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
ethaderu 3:78f223d34f36 1591 /** Array initializer of AIPS peripheral base pointers */
ethaderu 3:78f223d34f36 1592 #define AIPS_BASE_PTRS { AIPS0, AIPS1 }
ethaderu 3:78f223d34f36 1593
ethaderu 3:78f223d34f36 1594 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 1595 -- AIPS - Register accessor macros
ethaderu 3:78f223d34f36 1596 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 1597
ethaderu 3:78f223d34f36 1598 /*!
ethaderu 3:78f223d34f36 1599 * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
ethaderu 3:78f223d34f36 1600 * @{
ethaderu 3:78f223d34f36 1601 */
ethaderu 3:78f223d34f36 1602
ethaderu 3:78f223d34f36 1603
ethaderu 3:78f223d34f36 1604 /* AIPS - Register instance definitions */
ethaderu 3:78f223d34f36 1605 /* AIPS0 */
ethaderu 3:78f223d34f36 1606 #define AIPS0_MPRA AIPS_MPRA_REG(AIPS0)
ethaderu 3:78f223d34f36 1607 #define AIPS0_PACRA AIPS_PACRA_REG(AIPS0)
ethaderu 3:78f223d34f36 1608 #define AIPS0_PACRB AIPS_PACRB_REG(AIPS0)
ethaderu 3:78f223d34f36 1609 #define AIPS0_PACRC AIPS_PACRC_REG(AIPS0)
ethaderu 3:78f223d34f36 1610 #define AIPS0_PACRD AIPS_PACRD_REG(AIPS0)
ethaderu 3:78f223d34f36 1611 #define AIPS0_PACRE AIPS_PACRE_REG(AIPS0)
ethaderu 3:78f223d34f36 1612 #define AIPS0_PACRF AIPS_PACRF_REG(AIPS0)
ethaderu 3:78f223d34f36 1613 #define AIPS0_PACRG AIPS_PACRG_REG(AIPS0)
ethaderu 3:78f223d34f36 1614 #define AIPS0_PACRH AIPS_PACRH_REG(AIPS0)
ethaderu 3:78f223d34f36 1615 #define AIPS0_PACRI AIPS_PACRI_REG(AIPS0)
ethaderu 3:78f223d34f36 1616 #define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0)
ethaderu 3:78f223d34f36 1617 #define AIPS0_PACRK AIPS_PACRK_REG(AIPS0)
ethaderu 3:78f223d34f36 1618 #define AIPS0_PACRL AIPS_PACRL_REG(AIPS0)
ethaderu 3:78f223d34f36 1619 #define AIPS0_PACRM AIPS_PACRM_REG(AIPS0)
ethaderu 3:78f223d34f36 1620 #define AIPS0_PACRN AIPS_PACRN_REG(AIPS0)
ethaderu 3:78f223d34f36 1621 #define AIPS0_PACRO AIPS_PACRO_REG(AIPS0)
ethaderu 3:78f223d34f36 1622 #define AIPS0_PACRP AIPS_PACRP_REG(AIPS0)
ethaderu 3:78f223d34f36 1623 #define AIPS0_PACRU AIPS_PACRU_REG(AIPS0)
ethaderu 3:78f223d34f36 1624 /* AIPS1 */
ethaderu 3:78f223d34f36 1625 #define AIPS1_MPRA AIPS_MPRA_REG(AIPS1)
ethaderu 3:78f223d34f36 1626 #define AIPS1_PACRA AIPS_PACRA_REG(AIPS1)
ethaderu 3:78f223d34f36 1627 #define AIPS1_PACRB AIPS_PACRB_REG(AIPS1)
ethaderu 3:78f223d34f36 1628 #define AIPS1_PACRC AIPS_PACRC_REG(AIPS1)
ethaderu 3:78f223d34f36 1629 #define AIPS1_PACRD AIPS_PACRD_REG(AIPS1)
ethaderu 3:78f223d34f36 1630 #define AIPS1_PACRE AIPS_PACRE_REG(AIPS1)
ethaderu 3:78f223d34f36 1631 #define AIPS1_PACRF AIPS_PACRF_REG(AIPS1)
ethaderu 3:78f223d34f36 1632 #define AIPS1_PACRG AIPS_PACRG_REG(AIPS1)
ethaderu 3:78f223d34f36 1633 #define AIPS1_PACRH AIPS_PACRH_REG(AIPS1)
ethaderu 3:78f223d34f36 1634 #define AIPS1_PACRI AIPS_PACRI_REG(AIPS1)
ethaderu 3:78f223d34f36 1635 #define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1)
ethaderu 3:78f223d34f36 1636 #define AIPS1_PACRK AIPS_PACRK_REG(AIPS1)
ethaderu 3:78f223d34f36 1637 #define AIPS1_PACRL AIPS_PACRL_REG(AIPS1)
ethaderu 3:78f223d34f36 1638 #define AIPS1_PACRM AIPS_PACRM_REG(AIPS1)
ethaderu 3:78f223d34f36 1639 #define AIPS1_PACRN AIPS_PACRN_REG(AIPS1)
ethaderu 3:78f223d34f36 1640 #define AIPS1_PACRO AIPS_PACRO_REG(AIPS1)
ethaderu 3:78f223d34f36 1641 #define AIPS1_PACRP AIPS_PACRP_REG(AIPS1)
ethaderu 3:78f223d34f36 1642 #define AIPS1_PACRU AIPS_PACRU_REG(AIPS1)
ethaderu 3:78f223d34f36 1643
ethaderu 3:78f223d34f36 1644 /*!
ethaderu 3:78f223d34f36 1645 * @}
ethaderu 3:78f223d34f36 1646 */ /* end of group AIPS_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 1647
ethaderu 3:78f223d34f36 1648
ethaderu 3:78f223d34f36 1649 /*!
ethaderu 3:78f223d34f36 1650 * @}
ethaderu 3:78f223d34f36 1651 */ /* end of group AIPS_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 1652
ethaderu 3:78f223d34f36 1653
ethaderu 3:78f223d34f36 1654 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 1655 -- AXBS Peripheral Access Layer
ethaderu 3:78f223d34f36 1656 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 1657
ethaderu 3:78f223d34f36 1658 /*!
ethaderu 3:78f223d34f36 1659 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
ethaderu 3:78f223d34f36 1660 * @{
ethaderu 3:78f223d34f36 1661 */
ethaderu 3:78f223d34f36 1662
ethaderu 3:78f223d34f36 1663 /** AXBS - Register Layout Typedef */
ethaderu 3:78f223d34f36 1664 typedef struct {
ethaderu 3:78f223d34f36 1665 struct { /* offset: 0x0, array step: 0x100 */
ethaderu 3:78f223d34f36 1666 __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
ethaderu 3:78f223d34f36 1667 uint8_t RESERVED_0[12];
ethaderu 3:78f223d34f36 1668 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
ethaderu 3:78f223d34f36 1669 uint8_t RESERVED_1[236];
ethaderu 3:78f223d34f36 1670 } SLAVE[5];
ethaderu 3:78f223d34f36 1671 uint8_t RESERVED_0[768];
ethaderu 3:78f223d34f36 1672 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
ethaderu 3:78f223d34f36 1673 uint8_t RESERVED_1[252];
ethaderu 3:78f223d34f36 1674 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
ethaderu 3:78f223d34f36 1675 uint8_t RESERVED_2[252];
ethaderu 3:78f223d34f36 1676 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
ethaderu 3:78f223d34f36 1677 uint8_t RESERVED_3[252];
ethaderu 3:78f223d34f36 1678 __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
ethaderu 3:78f223d34f36 1679 uint8_t RESERVED_4[252];
ethaderu 3:78f223d34f36 1680 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
ethaderu 3:78f223d34f36 1681 uint8_t RESERVED_5[252];
ethaderu 3:78f223d34f36 1682 __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
ethaderu 3:78f223d34f36 1683 } AXBS_Type, *AXBS_MemMapPtr;
ethaderu 3:78f223d34f36 1684
ethaderu 3:78f223d34f36 1685 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 1686 -- AXBS - Register accessor macros
ethaderu 3:78f223d34f36 1687 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 1688
ethaderu 3:78f223d34f36 1689 /*!
ethaderu 3:78f223d34f36 1690 * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
ethaderu 3:78f223d34f36 1691 * @{
ethaderu 3:78f223d34f36 1692 */
ethaderu 3:78f223d34f36 1693
ethaderu 3:78f223d34f36 1694
ethaderu 3:78f223d34f36 1695 /* AXBS - Register accessors */
ethaderu 3:78f223d34f36 1696 #define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS)
ethaderu 3:78f223d34f36 1697 #define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS)
ethaderu 3:78f223d34f36 1698 #define AXBS_MGPCR0_REG(base) ((base)->MGPCR0)
ethaderu 3:78f223d34f36 1699 #define AXBS_MGPCR1_REG(base) ((base)->MGPCR1)
ethaderu 3:78f223d34f36 1700 #define AXBS_MGPCR2_REG(base) ((base)->MGPCR2)
ethaderu 3:78f223d34f36 1701 #define AXBS_MGPCR3_REG(base) ((base)->MGPCR3)
ethaderu 3:78f223d34f36 1702 #define AXBS_MGPCR4_REG(base) ((base)->MGPCR4)
ethaderu 3:78f223d34f36 1703 #define AXBS_MGPCR5_REG(base) ((base)->MGPCR5)
ethaderu 3:78f223d34f36 1704
ethaderu 3:78f223d34f36 1705 /*!
ethaderu 3:78f223d34f36 1706 * @}
ethaderu 3:78f223d34f36 1707 */ /* end of group AXBS_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 1708
ethaderu 3:78f223d34f36 1709
ethaderu 3:78f223d34f36 1710 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 1711 -- AXBS Register Masks
ethaderu 3:78f223d34f36 1712 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 1713
ethaderu 3:78f223d34f36 1714 /*!
ethaderu 3:78f223d34f36 1715 * @addtogroup AXBS_Register_Masks AXBS Register Masks
ethaderu 3:78f223d34f36 1716 * @{
ethaderu 3:78f223d34f36 1717 */
ethaderu 3:78f223d34f36 1718
ethaderu 3:78f223d34f36 1719 /* PRS Bit Fields */
ethaderu 3:78f223d34f36 1720 #define AXBS_PRS_M0_MASK 0x7u
ethaderu 3:78f223d34f36 1721 #define AXBS_PRS_M0_SHIFT 0
ethaderu 3:78f223d34f36 1722 #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
ethaderu 3:78f223d34f36 1723 #define AXBS_PRS_M1_MASK 0x70u
ethaderu 3:78f223d34f36 1724 #define AXBS_PRS_M1_SHIFT 4
ethaderu 3:78f223d34f36 1725 #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
ethaderu 3:78f223d34f36 1726 #define AXBS_PRS_M2_MASK 0x700u
ethaderu 3:78f223d34f36 1727 #define AXBS_PRS_M2_SHIFT 8
ethaderu 3:78f223d34f36 1728 #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
ethaderu 3:78f223d34f36 1729 #define AXBS_PRS_M3_MASK 0x7000u
ethaderu 3:78f223d34f36 1730 #define AXBS_PRS_M3_SHIFT 12
ethaderu 3:78f223d34f36 1731 #define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
ethaderu 3:78f223d34f36 1732 #define AXBS_PRS_M4_MASK 0x70000u
ethaderu 3:78f223d34f36 1733 #define AXBS_PRS_M4_SHIFT 16
ethaderu 3:78f223d34f36 1734 #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
ethaderu 3:78f223d34f36 1735 #define AXBS_PRS_M5_MASK 0x700000u
ethaderu 3:78f223d34f36 1736 #define AXBS_PRS_M5_SHIFT 20
ethaderu 3:78f223d34f36 1737 #define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
ethaderu 3:78f223d34f36 1738 /* CRS Bit Fields */
ethaderu 3:78f223d34f36 1739 #define AXBS_CRS_PARK_MASK 0x7u
ethaderu 3:78f223d34f36 1740 #define AXBS_CRS_PARK_SHIFT 0
ethaderu 3:78f223d34f36 1741 #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
ethaderu 3:78f223d34f36 1742 #define AXBS_CRS_PCTL_MASK 0x30u
ethaderu 3:78f223d34f36 1743 #define AXBS_CRS_PCTL_SHIFT 4
ethaderu 3:78f223d34f36 1744 #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
ethaderu 3:78f223d34f36 1745 #define AXBS_CRS_ARB_MASK 0x300u
ethaderu 3:78f223d34f36 1746 #define AXBS_CRS_ARB_SHIFT 8
ethaderu 3:78f223d34f36 1747 #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
ethaderu 3:78f223d34f36 1748 #define AXBS_CRS_HLP_MASK 0x40000000u
ethaderu 3:78f223d34f36 1749 #define AXBS_CRS_HLP_SHIFT 30
ethaderu 3:78f223d34f36 1750 #define AXBS_CRS_RO_MASK 0x80000000u
ethaderu 3:78f223d34f36 1751 #define AXBS_CRS_RO_SHIFT 31
ethaderu 3:78f223d34f36 1752 /* MGPCR0 Bit Fields */
ethaderu 3:78f223d34f36 1753 #define AXBS_MGPCR0_AULB_MASK 0x7u
ethaderu 3:78f223d34f36 1754 #define AXBS_MGPCR0_AULB_SHIFT 0
ethaderu 3:78f223d34f36 1755 #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
ethaderu 3:78f223d34f36 1756 /* MGPCR1 Bit Fields */
ethaderu 3:78f223d34f36 1757 #define AXBS_MGPCR1_AULB_MASK 0x7u
ethaderu 3:78f223d34f36 1758 #define AXBS_MGPCR1_AULB_SHIFT 0
ethaderu 3:78f223d34f36 1759 #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
ethaderu 3:78f223d34f36 1760 /* MGPCR2 Bit Fields */
ethaderu 3:78f223d34f36 1761 #define AXBS_MGPCR2_AULB_MASK 0x7u
ethaderu 3:78f223d34f36 1762 #define AXBS_MGPCR2_AULB_SHIFT 0
ethaderu 3:78f223d34f36 1763 #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
ethaderu 3:78f223d34f36 1764 /* MGPCR3 Bit Fields */
ethaderu 3:78f223d34f36 1765 #define AXBS_MGPCR3_AULB_MASK 0x7u
ethaderu 3:78f223d34f36 1766 #define AXBS_MGPCR3_AULB_SHIFT 0
ethaderu 3:78f223d34f36 1767 #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
ethaderu 3:78f223d34f36 1768 /* MGPCR4 Bit Fields */
ethaderu 3:78f223d34f36 1769 #define AXBS_MGPCR4_AULB_MASK 0x7u
ethaderu 3:78f223d34f36 1770 #define AXBS_MGPCR4_AULB_SHIFT 0
ethaderu 3:78f223d34f36 1771 #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
ethaderu 3:78f223d34f36 1772 /* MGPCR5 Bit Fields */
ethaderu 3:78f223d34f36 1773 #define AXBS_MGPCR5_AULB_MASK 0x7u
ethaderu 3:78f223d34f36 1774 #define AXBS_MGPCR5_AULB_SHIFT 0
ethaderu 3:78f223d34f36 1775 #define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
ethaderu 3:78f223d34f36 1776
ethaderu 3:78f223d34f36 1777 /*!
ethaderu 3:78f223d34f36 1778 * @}
ethaderu 3:78f223d34f36 1779 */ /* end of group AXBS_Register_Masks */
ethaderu 3:78f223d34f36 1780
ethaderu 3:78f223d34f36 1781
ethaderu 3:78f223d34f36 1782 /* AXBS - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 1783 /** Peripheral AXBS base address */
ethaderu 3:78f223d34f36 1784 #define AXBS_BASE (0x40004000u)
ethaderu 3:78f223d34f36 1785 /** Peripheral AXBS base pointer */
ethaderu 3:78f223d34f36 1786 #define AXBS ((AXBS_Type *)AXBS_BASE)
ethaderu 3:78f223d34f36 1787 #define AXBS_BASE_PTR (AXBS)
ethaderu 3:78f223d34f36 1788 /** Array initializer of AXBS peripheral base addresses */
ethaderu 3:78f223d34f36 1789 #define AXBS_BASE_ADDRS { AXBS_BASE }
ethaderu 3:78f223d34f36 1790 /** Array initializer of AXBS peripheral base pointers */
ethaderu 3:78f223d34f36 1791 #define AXBS_BASE_PTRS { AXBS }
ethaderu 3:78f223d34f36 1792
ethaderu 3:78f223d34f36 1793 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 1794 -- AXBS - Register accessor macros
ethaderu 3:78f223d34f36 1795 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 1796
ethaderu 3:78f223d34f36 1797 /*!
ethaderu 3:78f223d34f36 1798 * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
ethaderu 3:78f223d34f36 1799 * @{
ethaderu 3:78f223d34f36 1800 */
ethaderu 3:78f223d34f36 1801
ethaderu 3:78f223d34f36 1802
ethaderu 3:78f223d34f36 1803 /* AXBS - Register instance definitions */
ethaderu 3:78f223d34f36 1804 /* AXBS */
ethaderu 3:78f223d34f36 1805 #define AXBS_PRS0 AXBS_PRS_REG(AXBS,0)
ethaderu 3:78f223d34f36 1806 #define AXBS_CRS0 AXBS_CRS_REG(AXBS,0)
ethaderu 3:78f223d34f36 1807 #define AXBS_PRS1 AXBS_PRS_REG(AXBS,1)
ethaderu 3:78f223d34f36 1808 #define AXBS_CRS1 AXBS_CRS_REG(AXBS,1)
ethaderu 3:78f223d34f36 1809 #define AXBS_PRS2 AXBS_PRS_REG(AXBS,2)
ethaderu 3:78f223d34f36 1810 #define AXBS_CRS2 AXBS_CRS_REG(AXBS,2)
ethaderu 3:78f223d34f36 1811 #define AXBS_PRS3 AXBS_PRS_REG(AXBS,3)
ethaderu 3:78f223d34f36 1812 #define AXBS_CRS3 AXBS_CRS_REG(AXBS,3)
ethaderu 3:78f223d34f36 1813 #define AXBS_PRS4 AXBS_PRS_REG(AXBS,4)
ethaderu 3:78f223d34f36 1814 #define AXBS_CRS4 AXBS_CRS_REG(AXBS,4)
ethaderu 3:78f223d34f36 1815 #define AXBS_MGPCR0 AXBS_MGPCR0_REG(AXBS)
ethaderu 3:78f223d34f36 1816 #define AXBS_MGPCR1 AXBS_MGPCR1_REG(AXBS)
ethaderu 3:78f223d34f36 1817 #define AXBS_MGPCR2 AXBS_MGPCR2_REG(AXBS)
ethaderu 3:78f223d34f36 1818 #define AXBS_MGPCR3 AXBS_MGPCR3_REG(AXBS)
ethaderu 3:78f223d34f36 1819 #define AXBS_MGPCR4 AXBS_MGPCR4_REG(AXBS)
ethaderu 3:78f223d34f36 1820 #define AXBS_MGPCR5 AXBS_MGPCR5_REG(AXBS)
ethaderu 3:78f223d34f36 1821
ethaderu 3:78f223d34f36 1822 /* AXBS - Register array accessors */
ethaderu 3:78f223d34f36 1823 #define AXBS_PRS(index) AXBS_PRS_REG(AXBS,index)
ethaderu 3:78f223d34f36 1824 #define AXBS_CRS(index) AXBS_CRS_REG(AXBS,index)
ethaderu 3:78f223d34f36 1825
ethaderu 3:78f223d34f36 1826 /*!
ethaderu 3:78f223d34f36 1827 * @}
ethaderu 3:78f223d34f36 1828 */ /* end of group AXBS_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 1829
ethaderu 3:78f223d34f36 1830
ethaderu 3:78f223d34f36 1831 /*!
ethaderu 3:78f223d34f36 1832 * @}
ethaderu 3:78f223d34f36 1833 */ /* end of group AXBS_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 1834
ethaderu 3:78f223d34f36 1835
ethaderu 3:78f223d34f36 1836 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 1837 -- CAN Peripheral Access Layer
ethaderu 3:78f223d34f36 1838 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 1839
ethaderu 3:78f223d34f36 1840 /*!
ethaderu 3:78f223d34f36 1841 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
ethaderu 3:78f223d34f36 1842 * @{
ethaderu 3:78f223d34f36 1843 */
ethaderu 3:78f223d34f36 1844
ethaderu 3:78f223d34f36 1845 /** CAN - Register Layout Typedef */
ethaderu 3:78f223d34f36 1846 typedef struct {
ethaderu 3:78f223d34f36 1847 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
ethaderu 3:78f223d34f36 1848 __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
ethaderu 3:78f223d34f36 1849 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
ethaderu 3:78f223d34f36 1850 uint8_t RESERVED_0[4];
ethaderu 3:78f223d34f36 1851 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
ethaderu 3:78f223d34f36 1852 __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
ethaderu 3:78f223d34f36 1853 __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
ethaderu 3:78f223d34f36 1854 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
ethaderu 3:78f223d34f36 1855 __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
ethaderu 3:78f223d34f36 1856 uint8_t RESERVED_1[4];
ethaderu 3:78f223d34f36 1857 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
ethaderu 3:78f223d34f36 1858 uint8_t RESERVED_2[4];
ethaderu 3:78f223d34f36 1859 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
ethaderu 3:78f223d34f36 1860 __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
ethaderu 3:78f223d34f36 1861 __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
ethaderu 3:78f223d34f36 1862 uint8_t RESERVED_3[8];
ethaderu 3:78f223d34f36 1863 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
ethaderu 3:78f223d34f36 1864 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
ethaderu 3:78f223d34f36 1865 __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
ethaderu 3:78f223d34f36 1866 uint8_t RESERVED_4[48];
ethaderu 3:78f223d34f36 1867 struct { /* offset: 0x80, array step: 0x10 */
ethaderu 3:78f223d34f36 1868 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
ethaderu 3:78f223d34f36 1869 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
ethaderu 3:78f223d34f36 1870 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
ethaderu 3:78f223d34f36 1871 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
ethaderu 3:78f223d34f36 1872 } MB[16];
ethaderu 3:78f223d34f36 1873 uint8_t RESERVED_5[1792];
ethaderu 3:78f223d34f36 1874 __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
ethaderu 3:78f223d34f36 1875 } CAN_Type, *CAN_MemMapPtr;
ethaderu 3:78f223d34f36 1876
ethaderu 3:78f223d34f36 1877 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 1878 -- CAN - Register accessor macros
ethaderu 3:78f223d34f36 1879 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 1880
ethaderu 3:78f223d34f36 1881 /*!
ethaderu 3:78f223d34f36 1882 * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
ethaderu 3:78f223d34f36 1883 * @{
ethaderu 3:78f223d34f36 1884 */
ethaderu 3:78f223d34f36 1885
ethaderu 3:78f223d34f36 1886
ethaderu 3:78f223d34f36 1887 /* CAN - Register accessors */
ethaderu 3:78f223d34f36 1888 #define CAN_MCR_REG(base) ((base)->MCR)
ethaderu 3:78f223d34f36 1889 #define CAN_CTRL1_REG(base) ((base)->CTRL1)
ethaderu 3:78f223d34f36 1890 #define CAN_TIMER_REG(base) ((base)->TIMER)
ethaderu 3:78f223d34f36 1891 #define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK)
ethaderu 3:78f223d34f36 1892 #define CAN_RX14MASK_REG(base) ((base)->RX14MASK)
ethaderu 3:78f223d34f36 1893 #define CAN_RX15MASK_REG(base) ((base)->RX15MASK)
ethaderu 3:78f223d34f36 1894 #define CAN_ECR_REG(base) ((base)->ECR)
ethaderu 3:78f223d34f36 1895 #define CAN_ESR1_REG(base) ((base)->ESR1)
ethaderu 3:78f223d34f36 1896 #define CAN_IMASK1_REG(base) ((base)->IMASK1)
ethaderu 3:78f223d34f36 1897 #define CAN_IFLAG1_REG(base) ((base)->IFLAG1)
ethaderu 3:78f223d34f36 1898 #define CAN_CTRL2_REG(base) ((base)->CTRL2)
ethaderu 3:78f223d34f36 1899 #define CAN_ESR2_REG(base) ((base)->ESR2)
ethaderu 3:78f223d34f36 1900 #define CAN_CRCR_REG(base) ((base)->CRCR)
ethaderu 3:78f223d34f36 1901 #define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK)
ethaderu 3:78f223d34f36 1902 #define CAN_RXFIR_REG(base) ((base)->RXFIR)
ethaderu 3:78f223d34f36 1903 #define CAN_CS_REG(base,index) ((base)->MB[index].CS)
ethaderu 3:78f223d34f36 1904 #define CAN_ID_REG(base,index) ((base)->MB[index].ID)
ethaderu 3:78f223d34f36 1905 #define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0)
ethaderu 3:78f223d34f36 1906 #define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1)
ethaderu 3:78f223d34f36 1907 #define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index])
ethaderu 3:78f223d34f36 1908
ethaderu 3:78f223d34f36 1909 /*!
ethaderu 3:78f223d34f36 1910 * @}
ethaderu 3:78f223d34f36 1911 */ /* end of group CAN_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 1912
ethaderu 3:78f223d34f36 1913
ethaderu 3:78f223d34f36 1914 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 1915 -- CAN Register Masks
ethaderu 3:78f223d34f36 1916 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 1917
ethaderu 3:78f223d34f36 1918 /*!
ethaderu 3:78f223d34f36 1919 * @addtogroup CAN_Register_Masks CAN Register Masks
ethaderu 3:78f223d34f36 1920 * @{
ethaderu 3:78f223d34f36 1921 */
ethaderu 3:78f223d34f36 1922
ethaderu 3:78f223d34f36 1923 /* MCR Bit Fields */
ethaderu 3:78f223d34f36 1924 #define CAN_MCR_MAXMB_MASK 0x7Fu
ethaderu 3:78f223d34f36 1925 #define CAN_MCR_MAXMB_SHIFT 0
ethaderu 3:78f223d34f36 1926 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
ethaderu 3:78f223d34f36 1927 #define CAN_MCR_IDAM_MASK 0x300u
ethaderu 3:78f223d34f36 1928 #define CAN_MCR_IDAM_SHIFT 8
ethaderu 3:78f223d34f36 1929 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
ethaderu 3:78f223d34f36 1930 #define CAN_MCR_AEN_MASK 0x1000u
ethaderu 3:78f223d34f36 1931 #define CAN_MCR_AEN_SHIFT 12
ethaderu 3:78f223d34f36 1932 #define CAN_MCR_LPRIOEN_MASK 0x2000u
ethaderu 3:78f223d34f36 1933 #define CAN_MCR_LPRIOEN_SHIFT 13
ethaderu 3:78f223d34f36 1934 #define CAN_MCR_IRMQ_MASK 0x10000u
ethaderu 3:78f223d34f36 1935 #define CAN_MCR_IRMQ_SHIFT 16
ethaderu 3:78f223d34f36 1936 #define CAN_MCR_SRXDIS_MASK 0x20000u
ethaderu 3:78f223d34f36 1937 #define CAN_MCR_SRXDIS_SHIFT 17
ethaderu 3:78f223d34f36 1938 #define CAN_MCR_WAKSRC_MASK 0x80000u
ethaderu 3:78f223d34f36 1939 #define CAN_MCR_WAKSRC_SHIFT 19
ethaderu 3:78f223d34f36 1940 #define CAN_MCR_LPMACK_MASK 0x100000u
ethaderu 3:78f223d34f36 1941 #define CAN_MCR_LPMACK_SHIFT 20
ethaderu 3:78f223d34f36 1942 #define CAN_MCR_WRNEN_MASK 0x200000u
ethaderu 3:78f223d34f36 1943 #define CAN_MCR_WRNEN_SHIFT 21
ethaderu 3:78f223d34f36 1944 #define CAN_MCR_SLFWAK_MASK 0x400000u
ethaderu 3:78f223d34f36 1945 #define CAN_MCR_SLFWAK_SHIFT 22
ethaderu 3:78f223d34f36 1946 #define CAN_MCR_SUPV_MASK 0x800000u
ethaderu 3:78f223d34f36 1947 #define CAN_MCR_SUPV_SHIFT 23
ethaderu 3:78f223d34f36 1948 #define CAN_MCR_FRZACK_MASK 0x1000000u
ethaderu 3:78f223d34f36 1949 #define CAN_MCR_FRZACK_SHIFT 24
ethaderu 3:78f223d34f36 1950 #define CAN_MCR_SOFTRST_MASK 0x2000000u
ethaderu 3:78f223d34f36 1951 #define CAN_MCR_SOFTRST_SHIFT 25
ethaderu 3:78f223d34f36 1952 #define CAN_MCR_WAKMSK_MASK 0x4000000u
ethaderu 3:78f223d34f36 1953 #define CAN_MCR_WAKMSK_SHIFT 26
ethaderu 3:78f223d34f36 1954 #define CAN_MCR_NOTRDY_MASK 0x8000000u
ethaderu 3:78f223d34f36 1955 #define CAN_MCR_NOTRDY_SHIFT 27
ethaderu 3:78f223d34f36 1956 #define CAN_MCR_HALT_MASK 0x10000000u
ethaderu 3:78f223d34f36 1957 #define CAN_MCR_HALT_SHIFT 28
ethaderu 3:78f223d34f36 1958 #define CAN_MCR_RFEN_MASK 0x20000000u
ethaderu 3:78f223d34f36 1959 #define CAN_MCR_RFEN_SHIFT 29
ethaderu 3:78f223d34f36 1960 #define CAN_MCR_FRZ_MASK 0x40000000u
ethaderu 3:78f223d34f36 1961 #define CAN_MCR_FRZ_SHIFT 30
ethaderu 3:78f223d34f36 1962 #define CAN_MCR_MDIS_MASK 0x80000000u
ethaderu 3:78f223d34f36 1963 #define CAN_MCR_MDIS_SHIFT 31
ethaderu 3:78f223d34f36 1964 /* CTRL1 Bit Fields */
ethaderu 3:78f223d34f36 1965 #define CAN_CTRL1_PROPSEG_MASK 0x7u
ethaderu 3:78f223d34f36 1966 #define CAN_CTRL1_PROPSEG_SHIFT 0
ethaderu 3:78f223d34f36 1967 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
ethaderu 3:78f223d34f36 1968 #define CAN_CTRL1_LOM_MASK 0x8u
ethaderu 3:78f223d34f36 1969 #define CAN_CTRL1_LOM_SHIFT 3
ethaderu 3:78f223d34f36 1970 #define CAN_CTRL1_LBUF_MASK 0x10u
ethaderu 3:78f223d34f36 1971 #define CAN_CTRL1_LBUF_SHIFT 4
ethaderu 3:78f223d34f36 1972 #define CAN_CTRL1_TSYN_MASK 0x20u
ethaderu 3:78f223d34f36 1973 #define CAN_CTRL1_TSYN_SHIFT 5
ethaderu 3:78f223d34f36 1974 #define CAN_CTRL1_BOFFREC_MASK 0x40u
ethaderu 3:78f223d34f36 1975 #define CAN_CTRL1_BOFFREC_SHIFT 6
ethaderu 3:78f223d34f36 1976 #define CAN_CTRL1_SMP_MASK 0x80u
ethaderu 3:78f223d34f36 1977 #define CAN_CTRL1_SMP_SHIFT 7
ethaderu 3:78f223d34f36 1978 #define CAN_CTRL1_RWRNMSK_MASK 0x400u
ethaderu 3:78f223d34f36 1979 #define CAN_CTRL1_RWRNMSK_SHIFT 10
ethaderu 3:78f223d34f36 1980 #define CAN_CTRL1_TWRNMSK_MASK 0x800u
ethaderu 3:78f223d34f36 1981 #define CAN_CTRL1_TWRNMSK_SHIFT 11
ethaderu 3:78f223d34f36 1982 #define CAN_CTRL1_LPB_MASK 0x1000u
ethaderu 3:78f223d34f36 1983 #define CAN_CTRL1_LPB_SHIFT 12
ethaderu 3:78f223d34f36 1984 #define CAN_CTRL1_CLKSRC_MASK 0x2000u
ethaderu 3:78f223d34f36 1985 #define CAN_CTRL1_CLKSRC_SHIFT 13
ethaderu 3:78f223d34f36 1986 #define CAN_CTRL1_ERRMSK_MASK 0x4000u
ethaderu 3:78f223d34f36 1987 #define CAN_CTRL1_ERRMSK_SHIFT 14
ethaderu 3:78f223d34f36 1988 #define CAN_CTRL1_BOFFMSK_MASK 0x8000u
ethaderu 3:78f223d34f36 1989 #define CAN_CTRL1_BOFFMSK_SHIFT 15
ethaderu 3:78f223d34f36 1990 #define CAN_CTRL1_PSEG2_MASK 0x70000u
ethaderu 3:78f223d34f36 1991 #define CAN_CTRL1_PSEG2_SHIFT 16
ethaderu 3:78f223d34f36 1992 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
ethaderu 3:78f223d34f36 1993 #define CAN_CTRL1_PSEG1_MASK 0x380000u
ethaderu 3:78f223d34f36 1994 #define CAN_CTRL1_PSEG1_SHIFT 19
ethaderu 3:78f223d34f36 1995 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
ethaderu 3:78f223d34f36 1996 #define CAN_CTRL1_RJW_MASK 0xC00000u
ethaderu 3:78f223d34f36 1997 #define CAN_CTRL1_RJW_SHIFT 22
ethaderu 3:78f223d34f36 1998 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
ethaderu 3:78f223d34f36 1999 #define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
ethaderu 3:78f223d34f36 2000 #define CAN_CTRL1_PRESDIV_SHIFT 24
ethaderu 3:78f223d34f36 2001 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
ethaderu 3:78f223d34f36 2002 /* TIMER Bit Fields */
ethaderu 3:78f223d34f36 2003 #define CAN_TIMER_TIMER_MASK 0xFFFFu
ethaderu 3:78f223d34f36 2004 #define CAN_TIMER_TIMER_SHIFT 0
ethaderu 3:78f223d34f36 2005 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
ethaderu 3:78f223d34f36 2006 /* RXMGMASK Bit Fields */
ethaderu 3:78f223d34f36 2007 #define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2008 #define CAN_RXMGMASK_MG_SHIFT 0
ethaderu 3:78f223d34f36 2009 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
ethaderu 3:78f223d34f36 2010 /* RX14MASK Bit Fields */
ethaderu 3:78f223d34f36 2011 #define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2012 #define CAN_RX14MASK_RX14M_SHIFT 0
ethaderu 3:78f223d34f36 2013 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
ethaderu 3:78f223d34f36 2014 /* RX15MASK Bit Fields */
ethaderu 3:78f223d34f36 2015 #define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2016 #define CAN_RX15MASK_RX15M_SHIFT 0
ethaderu 3:78f223d34f36 2017 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
ethaderu 3:78f223d34f36 2018 /* ECR Bit Fields */
ethaderu 3:78f223d34f36 2019 #define CAN_ECR_TXERRCNT_MASK 0xFFu
ethaderu 3:78f223d34f36 2020 #define CAN_ECR_TXERRCNT_SHIFT 0
ethaderu 3:78f223d34f36 2021 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
ethaderu 3:78f223d34f36 2022 #define CAN_ECR_RXERRCNT_MASK 0xFF00u
ethaderu 3:78f223d34f36 2023 #define CAN_ECR_RXERRCNT_SHIFT 8
ethaderu 3:78f223d34f36 2024 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
ethaderu 3:78f223d34f36 2025 /* ESR1 Bit Fields */
ethaderu 3:78f223d34f36 2026 #define CAN_ESR1_WAKINT_MASK 0x1u
ethaderu 3:78f223d34f36 2027 #define CAN_ESR1_WAKINT_SHIFT 0
ethaderu 3:78f223d34f36 2028 #define CAN_ESR1_ERRINT_MASK 0x2u
ethaderu 3:78f223d34f36 2029 #define CAN_ESR1_ERRINT_SHIFT 1
ethaderu 3:78f223d34f36 2030 #define CAN_ESR1_BOFFINT_MASK 0x4u
ethaderu 3:78f223d34f36 2031 #define CAN_ESR1_BOFFINT_SHIFT 2
ethaderu 3:78f223d34f36 2032 #define CAN_ESR1_RX_MASK 0x8u
ethaderu 3:78f223d34f36 2033 #define CAN_ESR1_RX_SHIFT 3
ethaderu 3:78f223d34f36 2034 #define CAN_ESR1_FLTCONF_MASK 0x30u
ethaderu 3:78f223d34f36 2035 #define CAN_ESR1_FLTCONF_SHIFT 4
ethaderu 3:78f223d34f36 2036 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
ethaderu 3:78f223d34f36 2037 #define CAN_ESR1_TX_MASK 0x40u
ethaderu 3:78f223d34f36 2038 #define CAN_ESR1_TX_SHIFT 6
ethaderu 3:78f223d34f36 2039 #define CAN_ESR1_IDLE_MASK 0x80u
ethaderu 3:78f223d34f36 2040 #define CAN_ESR1_IDLE_SHIFT 7
ethaderu 3:78f223d34f36 2041 #define CAN_ESR1_RXWRN_MASK 0x100u
ethaderu 3:78f223d34f36 2042 #define CAN_ESR1_RXWRN_SHIFT 8
ethaderu 3:78f223d34f36 2043 #define CAN_ESR1_TXWRN_MASK 0x200u
ethaderu 3:78f223d34f36 2044 #define CAN_ESR1_TXWRN_SHIFT 9
ethaderu 3:78f223d34f36 2045 #define CAN_ESR1_STFERR_MASK 0x400u
ethaderu 3:78f223d34f36 2046 #define CAN_ESR1_STFERR_SHIFT 10
ethaderu 3:78f223d34f36 2047 #define CAN_ESR1_FRMERR_MASK 0x800u
ethaderu 3:78f223d34f36 2048 #define CAN_ESR1_FRMERR_SHIFT 11
ethaderu 3:78f223d34f36 2049 #define CAN_ESR1_CRCERR_MASK 0x1000u
ethaderu 3:78f223d34f36 2050 #define CAN_ESR1_CRCERR_SHIFT 12
ethaderu 3:78f223d34f36 2051 #define CAN_ESR1_ACKERR_MASK 0x2000u
ethaderu 3:78f223d34f36 2052 #define CAN_ESR1_ACKERR_SHIFT 13
ethaderu 3:78f223d34f36 2053 #define CAN_ESR1_BIT0ERR_MASK 0x4000u
ethaderu 3:78f223d34f36 2054 #define CAN_ESR1_BIT0ERR_SHIFT 14
ethaderu 3:78f223d34f36 2055 #define CAN_ESR1_BIT1ERR_MASK 0x8000u
ethaderu 3:78f223d34f36 2056 #define CAN_ESR1_BIT1ERR_SHIFT 15
ethaderu 3:78f223d34f36 2057 #define CAN_ESR1_RWRNINT_MASK 0x10000u
ethaderu 3:78f223d34f36 2058 #define CAN_ESR1_RWRNINT_SHIFT 16
ethaderu 3:78f223d34f36 2059 #define CAN_ESR1_TWRNINT_MASK 0x20000u
ethaderu 3:78f223d34f36 2060 #define CAN_ESR1_TWRNINT_SHIFT 17
ethaderu 3:78f223d34f36 2061 #define CAN_ESR1_SYNCH_MASK 0x40000u
ethaderu 3:78f223d34f36 2062 #define CAN_ESR1_SYNCH_SHIFT 18
ethaderu 3:78f223d34f36 2063 /* IMASK1 Bit Fields */
ethaderu 3:78f223d34f36 2064 #define CAN_IMASK1_BUFLM_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2065 #define CAN_IMASK1_BUFLM_SHIFT 0
ethaderu 3:78f223d34f36 2066 #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
ethaderu 3:78f223d34f36 2067 /* IFLAG1 Bit Fields */
ethaderu 3:78f223d34f36 2068 #define CAN_IFLAG1_BUF0I_MASK 0x1u
ethaderu 3:78f223d34f36 2069 #define CAN_IFLAG1_BUF0I_SHIFT 0
ethaderu 3:78f223d34f36 2070 #define CAN_IFLAG1_BUF4TO1I_MASK 0x1Eu
ethaderu 3:78f223d34f36 2071 #define CAN_IFLAG1_BUF4TO1I_SHIFT 1
ethaderu 3:78f223d34f36 2072 #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
ethaderu 3:78f223d34f36 2073 #define CAN_IFLAG1_BUF5I_MASK 0x20u
ethaderu 3:78f223d34f36 2074 #define CAN_IFLAG1_BUF5I_SHIFT 5
ethaderu 3:78f223d34f36 2075 #define CAN_IFLAG1_BUF6I_MASK 0x40u
ethaderu 3:78f223d34f36 2076 #define CAN_IFLAG1_BUF6I_SHIFT 6
ethaderu 3:78f223d34f36 2077 #define CAN_IFLAG1_BUF7I_MASK 0x80u
ethaderu 3:78f223d34f36 2078 #define CAN_IFLAG1_BUF7I_SHIFT 7
ethaderu 3:78f223d34f36 2079 #define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
ethaderu 3:78f223d34f36 2080 #define CAN_IFLAG1_BUF31TO8I_SHIFT 8
ethaderu 3:78f223d34f36 2081 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
ethaderu 3:78f223d34f36 2082 /* CTRL2 Bit Fields */
ethaderu 3:78f223d34f36 2083 #define CAN_CTRL2_EACEN_MASK 0x10000u
ethaderu 3:78f223d34f36 2084 #define CAN_CTRL2_EACEN_SHIFT 16
ethaderu 3:78f223d34f36 2085 #define CAN_CTRL2_RRS_MASK 0x20000u
ethaderu 3:78f223d34f36 2086 #define CAN_CTRL2_RRS_SHIFT 17
ethaderu 3:78f223d34f36 2087 #define CAN_CTRL2_MRP_MASK 0x40000u
ethaderu 3:78f223d34f36 2088 #define CAN_CTRL2_MRP_SHIFT 18
ethaderu 3:78f223d34f36 2089 #define CAN_CTRL2_TASD_MASK 0xF80000u
ethaderu 3:78f223d34f36 2090 #define CAN_CTRL2_TASD_SHIFT 19
ethaderu 3:78f223d34f36 2091 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
ethaderu 3:78f223d34f36 2092 #define CAN_CTRL2_RFFN_MASK 0xF000000u
ethaderu 3:78f223d34f36 2093 #define CAN_CTRL2_RFFN_SHIFT 24
ethaderu 3:78f223d34f36 2094 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
ethaderu 3:78f223d34f36 2095 #define CAN_CTRL2_WRMFRZ_MASK 0x10000000u
ethaderu 3:78f223d34f36 2096 #define CAN_CTRL2_WRMFRZ_SHIFT 28
ethaderu 3:78f223d34f36 2097 /* ESR2 Bit Fields */
ethaderu 3:78f223d34f36 2098 #define CAN_ESR2_IMB_MASK 0x2000u
ethaderu 3:78f223d34f36 2099 #define CAN_ESR2_IMB_SHIFT 13
ethaderu 3:78f223d34f36 2100 #define CAN_ESR2_VPS_MASK 0x4000u
ethaderu 3:78f223d34f36 2101 #define CAN_ESR2_VPS_SHIFT 14
ethaderu 3:78f223d34f36 2102 #define CAN_ESR2_LPTM_MASK 0x7F0000u
ethaderu 3:78f223d34f36 2103 #define CAN_ESR2_LPTM_SHIFT 16
ethaderu 3:78f223d34f36 2104 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
ethaderu 3:78f223d34f36 2105 /* CRCR Bit Fields */
ethaderu 3:78f223d34f36 2106 #define CAN_CRCR_TXCRC_MASK 0x7FFFu
ethaderu 3:78f223d34f36 2107 #define CAN_CRCR_TXCRC_SHIFT 0
ethaderu 3:78f223d34f36 2108 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
ethaderu 3:78f223d34f36 2109 #define CAN_CRCR_MBCRC_MASK 0x7F0000u
ethaderu 3:78f223d34f36 2110 #define CAN_CRCR_MBCRC_SHIFT 16
ethaderu 3:78f223d34f36 2111 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
ethaderu 3:78f223d34f36 2112 /* RXFGMASK Bit Fields */
ethaderu 3:78f223d34f36 2113 #define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2114 #define CAN_RXFGMASK_FGM_SHIFT 0
ethaderu 3:78f223d34f36 2115 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
ethaderu 3:78f223d34f36 2116 /* RXFIR Bit Fields */
ethaderu 3:78f223d34f36 2117 #define CAN_RXFIR_IDHIT_MASK 0x1FFu
ethaderu 3:78f223d34f36 2118 #define CAN_RXFIR_IDHIT_SHIFT 0
ethaderu 3:78f223d34f36 2119 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
ethaderu 3:78f223d34f36 2120 /* CS Bit Fields */
ethaderu 3:78f223d34f36 2121 #define CAN_CS_TIME_STAMP_MASK 0xFFFFu
ethaderu 3:78f223d34f36 2122 #define CAN_CS_TIME_STAMP_SHIFT 0
ethaderu 3:78f223d34f36 2123 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
ethaderu 3:78f223d34f36 2124 #define CAN_CS_DLC_MASK 0xF0000u
ethaderu 3:78f223d34f36 2125 #define CAN_CS_DLC_SHIFT 16
ethaderu 3:78f223d34f36 2126 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
ethaderu 3:78f223d34f36 2127 #define CAN_CS_RTR_MASK 0x100000u
ethaderu 3:78f223d34f36 2128 #define CAN_CS_RTR_SHIFT 20
ethaderu 3:78f223d34f36 2129 #define CAN_CS_IDE_MASK 0x200000u
ethaderu 3:78f223d34f36 2130 #define CAN_CS_IDE_SHIFT 21
ethaderu 3:78f223d34f36 2131 #define CAN_CS_SRR_MASK 0x400000u
ethaderu 3:78f223d34f36 2132 #define CAN_CS_SRR_SHIFT 22
ethaderu 3:78f223d34f36 2133 #define CAN_CS_CODE_MASK 0xF000000u
ethaderu 3:78f223d34f36 2134 #define CAN_CS_CODE_SHIFT 24
ethaderu 3:78f223d34f36 2135 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
ethaderu 3:78f223d34f36 2136 /* ID Bit Fields */
ethaderu 3:78f223d34f36 2137 #define CAN_ID_EXT_MASK 0x3FFFFu
ethaderu 3:78f223d34f36 2138 #define CAN_ID_EXT_SHIFT 0
ethaderu 3:78f223d34f36 2139 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
ethaderu 3:78f223d34f36 2140 #define CAN_ID_STD_MASK 0x1FFC0000u
ethaderu 3:78f223d34f36 2141 #define CAN_ID_STD_SHIFT 18
ethaderu 3:78f223d34f36 2142 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
ethaderu 3:78f223d34f36 2143 #define CAN_ID_PRIO_MASK 0xE0000000u
ethaderu 3:78f223d34f36 2144 #define CAN_ID_PRIO_SHIFT 29
ethaderu 3:78f223d34f36 2145 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
ethaderu 3:78f223d34f36 2146 /* WORD0 Bit Fields */
ethaderu 3:78f223d34f36 2147 #define CAN_WORD0_DATA_BYTE_3_MASK 0xFFu
ethaderu 3:78f223d34f36 2148 #define CAN_WORD0_DATA_BYTE_3_SHIFT 0
ethaderu 3:78f223d34f36 2149 #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
ethaderu 3:78f223d34f36 2150 #define CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u
ethaderu 3:78f223d34f36 2151 #define CAN_WORD0_DATA_BYTE_2_SHIFT 8
ethaderu 3:78f223d34f36 2152 #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
ethaderu 3:78f223d34f36 2153 #define CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u
ethaderu 3:78f223d34f36 2154 #define CAN_WORD0_DATA_BYTE_1_SHIFT 16
ethaderu 3:78f223d34f36 2155 #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
ethaderu 3:78f223d34f36 2156 #define CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u
ethaderu 3:78f223d34f36 2157 #define CAN_WORD0_DATA_BYTE_0_SHIFT 24
ethaderu 3:78f223d34f36 2158 #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
ethaderu 3:78f223d34f36 2159 /* WORD1 Bit Fields */
ethaderu 3:78f223d34f36 2160 #define CAN_WORD1_DATA_BYTE_7_MASK 0xFFu
ethaderu 3:78f223d34f36 2161 #define CAN_WORD1_DATA_BYTE_7_SHIFT 0
ethaderu 3:78f223d34f36 2162 #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
ethaderu 3:78f223d34f36 2163 #define CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u
ethaderu 3:78f223d34f36 2164 #define CAN_WORD1_DATA_BYTE_6_SHIFT 8
ethaderu 3:78f223d34f36 2165 #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
ethaderu 3:78f223d34f36 2166 #define CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u
ethaderu 3:78f223d34f36 2167 #define CAN_WORD1_DATA_BYTE_5_SHIFT 16
ethaderu 3:78f223d34f36 2168 #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
ethaderu 3:78f223d34f36 2169 #define CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u
ethaderu 3:78f223d34f36 2170 #define CAN_WORD1_DATA_BYTE_4_SHIFT 24
ethaderu 3:78f223d34f36 2171 #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
ethaderu 3:78f223d34f36 2172 /* RXIMR Bit Fields */
ethaderu 3:78f223d34f36 2173 #define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2174 #define CAN_RXIMR_MI_SHIFT 0
ethaderu 3:78f223d34f36 2175 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
ethaderu 3:78f223d34f36 2176
ethaderu 3:78f223d34f36 2177 /*!
ethaderu 3:78f223d34f36 2178 * @}
ethaderu 3:78f223d34f36 2179 */ /* end of group CAN_Register_Masks */
ethaderu 3:78f223d34f36 2180
ethaderu 3:78f223d34f36 2181
ethaderu 3:78f223d34f36 2182 /* CAN - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 2183 /** Peripheral CAN0 base address */
ethaderu 3:78f223d34f36 2184 #define CAN0_BASE (0x40024000u)
ethaderu 3:78f223d34f36 2185 /** Peripheral CAN0 base pointer */
ethaderu 3:78f223d34f36 2186 #define CAN0 ((CAN_Type *)CAN0_BASE)
ethaderu 3:78f223d34f36 2187 #define CAN0_BASE_PTR (CAN0)
ethaderu 3:78f223d34f36 2188 /** Array initializer of CAN peripheral base addresses */
ethaderu 3:78f223d34f36 2189 #define CAN_BASE_ADDRS { CAN0_BASE }
ethaderu 3:78f223d34f36 2190 /** Array initializer of CAN peripheral base pointers */
ethaderu 3:78f223d34f36 2191 #define CAN_BASE_PTRS { CAN0 }
ethaderu 3:78f223d34f36 2192 /** Interrupt vectors for the CAN peripheral type */
ethaderu 3:78f223d34f36 2193 #define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn }
ethaderu 3:78f223d34f36 2194 #define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn }
ethaderu 3:78f223d34f36 2195 #define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn }
ethaderu 3:78f223d34f36 2196 #define CAN_Error_IRQS { CAN0_Error_IRQn }
ethaderu 3:78f223d34f36 2197 #define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn }
ethaderu 3:78f223d34f36 2198 #define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn }
ethaderu 3:78f223d34f36 2199
ethaderu 3:78f223d34f36 2200 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 2201 -- CAN - Register accessor macros
ethaderu 3:78f223d34f36 2202 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 2203
ethaderu 3:78f223d34f36 2204 /*!
ethaderu 3:78f223d34f36 2205 * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
ethaderu 3:78f223d34f36 2206 * @{
ethaderu 3:78f223d34f36 2207 */
ethaderu 3:78f223d34f36 2208
ethaderu 3:78f223d34f36 2209
ethaderu 3:78f223d34f36 2210 /* CAN - Register instance definitions */
ethaderu 3:78f223d34f36 2211 /* CAN0 */
ethaderu 3:78f223d34f36 2212 #define CAN0_MCR CAN_MCR_REG(CAN0)
ethaderu 3:78f223d34f36 2213 #define CAN0_CTRL1 CAN_CTRL1_REG(CAN0)
ethaderu 3:78f223d34f36 2214 #define CAN0_TIMER CAN_TIMER_REG(CAN0)
ethaderu 3:78f223d34f36 2215 #define CAN0_RXMGMASK CAN_RXMGMASK_REG(CAN0)
ethaderu 3:78f223d34f36 2216 #define CAN0_RX14MASK CAN_RX14MASK_REG(CAN0)
ethaderu 3:78f223d34f36 2217 #define CAN0_RX15MASK CAN_RX15MASK_REG(CAN0)
ethaderu 3:78f223d34f36 2218 #define CAN0_ECR CAN_ECR_REG(CAN0)
ethaderu 3:78f223d34f36 2219 #define CAN0_ESR1 CAN_ESR1_REG(CAN0)
ethaderu 3:78f223d34f36 2220 #define CAN0_IMASK1 CAN_IMASK1_REG(CAN0)
ethaderu 3:78f223d34f36 2221 #define CAN0_IFLAG1 CAN_IFLAG1_REG(CAN0)
ethaderu 3:78f223d34f36 2222 #define CAN0_CTRL2 CAN_CTRL2_REG(CAN0)
ethaderu 3:78f223d34f36 2223 #define CAN0_ESR2 CAN_ESR2_REG(CAN0)
ethaderu 3:78f223d34f36 2224 #define CAN0_CRCR CAN_CRCR_REG(CAN0)
ethaderu 3:78f223d34f36 2225 #define CAN0_RXFGMASK CAN_RXFGMASK_REG(CAN0)
ethaderu 3:78f223d34f36 2226 #define CAN0_RXFIR CAN_RXFIR_REG(CAN0)
ethaderu 3:78f223d34f36 2227 #define CAN0_CS0 CAN_CS_REG(CAN0,0)
ethaderu 3:78f223d34f36 2228 #define CAN0_ID0 CAN_ID_REG(CAN0,0)
ethaderu 3:78f223d34f36 2229 #define CAN0_WORD00 CAN_WORD0_REG(CAN0,0)
ethaderu 3:78f223d34f36 2230 #define CAN0_WORD10 CAN_WORD1_REG(CAN0,0)
ethaderu 3:78f223d34f36 2231 #define CAN0_CS1 CAN_CS_REG(CAN0,1)
ethaderu 3:78f223d34f36 2232 #define CAN0_ID1 CAN_ID_REG(CAN0,1)
ethaderu 3:78f223d34f36 2233 #define CAN0_WORD01 CAN_WORD0_REG(CAN0,1)
ethaderu 3:78f223d34f36 2234 #define CAN0_WORD11 CAN_WORD1_REG(CAN0,1)
ethaderu 3:78f223d34f36 2235 #define CAN0_CS2 CAN_CS_REG(CAN0,2)
ethaderu 3:78f223d34f36 2236 #define CAN0_ID2 CAN_ID_REG(CAN0,2)
ethaderu 3:78f223d34f36 2237 #define CAN0_WORD02 CAN_WORD0_REG(CAN0,2)
ethaderu 3:78f223d34f36 2238 #define CAN0_WORD12 CAN_WORD1_REG(CAN0,2)
ethaderu 3:78f223d34f36 2239 #define CAN0_CS3 CAN_CS_REG(CAN0,3)
ethaderu 3:78f223d34f36 2240 #define CAN0_ID3 CAN_ID_REG(CAN0,3)
ethaderu 3:78f223d34f36 2241 #define CAN0_WORD03 CAN_WORD0_REG(CAN0,3)
ethaderu 3:78f223d34f36 2242 #define CAN0_WORD13 CAN_WORD1_REG(CAN0,3)
ethaderu 3:78f223d34f36 2243 #define CAN0_CS4 CAN_CS_REG(CAN0,4)
ethaderu 3:78f223d34f36 2244 #define CAN0_ID4 CAN_ID_REG(CAN0,4)
ethaderu 3:78f223d34f36 2245 #define CAN0_WORD04 CAN_WORD0_REG(CAN0,4)
ethaderu 3:78f223d34f36 2246 #define CAN0_WORD14 CAN_WORD1_REG(CAN0,4)
ethaderu 3:78f223d34f36 2247 #define CAN0_CS5 CAN_CS_REG(CAN0,5)
ethaderu 3:78f223d34f36 2248 #define CAN0_ID5 CAN_ID_REG(CAN0,5)
ethaderu 3:78f223d34f36 2249 #define CAN0_WORD05 CAN_WORD0_REG(CAN0,5)
ethaderu 3:78f223d34f36 2250 #define CAN0_WORD15 CAN_WORD1_REG(CAN0,5)
ethaderu 3:78f223d34f36 2251 #define CAN0_CS6 CAN_CS_REG(CAN0,6)
ethaderu 3:78f223d34f36 2252 #define CAN0_ID6 CAN_ID_REG(CAN0,6)
ethaderu 3:78f223d34f36 2253 #define CAN0_WORD06 CAN_WORD0_REG(CAN0,6)
ethaderu 3:78f223d34f36 2254 #define CAN0_WORD16 CAN_WORD1_REG(CAN0,6)
ethaderu 3:78f223d34f36 2255 #define CAN0_CS7 CAN_CS_REG(CAN0,7)
ethaderu 3:78f223d34f36 2256 #define CAN0_ID7 CAN_ID_REG(CAN0,7)
ethaderu 3:78f223d34f36 2257 #define CAN0_WORD07 CAN_WORD0_REG(CAN0,7)
ethaderu 3:78f223d34f36 2258 #define CAN0_WORD17 CAN_WORD1_REG(CAN0,7)
ethaderu 3:78f223d34f36 2259 #define CAN0_CS8 CAN_CS_REG(CAN0,8)
ethaderu 3:78f223d34f36 2260 #define CAN0_ID8 CAN_ID_REG(CAN0,8)
ethaderu 3:78f223d34f36 2261 #define CAN0_WORD08 CAN_WORD0_REG(CAN0,8)
ethaderu 3:78f223d34f36 2262 #define CAN0_WORD18 CAN_WORD1_REG(CAN0,8)
ethaderu 3:78f223d34f36 2263 #define CAN0_CS9 CAN_CS_REG(CAN0,9)
ethaderu 3:78f223d34f36 2264 #define CAN0_ID9 CAN_ID_REG(CAN0,9)
ethaderu 3:78f223d34f36 2265 #define CAN0_WORD09 CAN_WORD0_REG(CAN0,9)
ethaderu 3:78f223d34f36 2266 #define CAN0_WORD19 CAN_WORD1_REG(CAN0,9)
ethaderu 3:78f223d34f36 2267 #define CAN0_CS10 CAN_CS_REG(CAN0,10)
ethaderu 3:78f223d34f36 2268 #define CAN0_ID10 CAN_ID_REG(CAN0,10)
ethaderu 3:78f223d34f36 2269 #define CAN0_WORD010 CAN_WORD0_REG(CAN0,10)
ethaderu 3:78f223d34f36 2270 #define CAN0_WORD110 CAN_WORD1_REG(CAN0,10)
ethaderu 3:78f223d34f36 2271 #define CAN0_CS11 CAN_CS_REG(CAN0,11)
ethaderu 3:78f223d34f36 2272 #define CAN0_ID11 CAN_ID_REG(CAN0,11)
ethaderu 3:78f223d34f36 2273 #define CAN0_WORD011 CAN_WORD0_REG(CAN0,11)
ethaderu 3:78f223d34f36 2274 #define CAN0_WORD111 CAN_WORD1_REG(CAN0,11)
ethaderu 3:78f223d34f36 2275 #define CAN0_CS12 CAN_CS_REG(CAN0,12)
ethaderu 3:78f223d34f36 2276 #define CAN0_ID12 CAN_ID_REG(CAN0,12)
ethaderu 3:78f223d34f36 2277 #define CAN0_WORD012 CAN_WORD0_REG(CAN0,12)
ethaderu 3:78f223d34f36 2278 #define CAN0_WORD112 CAN_WORD1_REG(CAN0,12)
ethaderu 3:78f223d34f36 2279 #define CAN0_CS13 CAN_CS_REG(CAN0,13)
ethaderu 3:78f223d34f36 2280 #define CAN0_ID13 CAN_ID_REG(CAN0,13)
ethaderu 3:78f223d34f36 2281 #define CAN0_WORD013 CAN_WORD0_REG(CAN0,13)
ethaderu 3:78f223d34f36 2282 #define CAN0_WORD113 CAN_WORD1_REG(CAN0,13)
ethaderu 3:78f223d34f36 2283 #define CAN0_CS14 CAN_CS_REG(CAN0,14)
ethaderu 3:78f223d34f36 2284 #define CAN0_ID14 CAN_ID_REG(CAN0,14)
ethaderu 3:78f223d34f36 2285 #define CAN0_WORD014 CAN_WORD0_REG(CAN0,14)
ethaderu 3:78f223d34f36 2286 #define CAN0_WORD114 CAN_WORD1_REG(CAN0,14)
ethaderu 3:78f223d34f36 2287 #define CAN0_CS15 CAN_CS_REG(CAN0,15)
ethaderu 3:78f223d34f36 2288 #define CAN0_ID15 CAN_ID_REG(CAN0,15)
ethaderu 3:78f223d34f36 2289 #define CAN0_WORD015 CAN_WORD0_REG(CAN0,15)
ethaderu 3:78f223d34f36 2290 #define CAN0_WORD115 CAN_WORD1_REG(CAN0,15)
ethaderu 3:78f223d34f36 2291 #define CAN0_RXIMR0 CAN_RXIMR_REG(CAN0,0)
ethaderu 3:78f223d34f36 2292 #define CAN0_RXIMR1 CAN_RXIMR_REG(CAN0,1)
ethaderu 3:78f223d34f36 2293 #define CAN0_RXIMR2 CAN_RXIMR_REG(CAN0,2)
ethaderu 3:78f223d34f36 2294 #define CAN0_RXIMR3 CAN_RXIMR_REG(CAN0,3)
ethaderu 3:78f223d34f36 2295 #define CAN0_RXIMR4 CAN_RXIMR_REG(CAN0,4)
ethaderu 3:78f223d34f36 2296 #define CAN0_RXIMR5 CAN_RXIMR_REG(CAN0,5)
ethaderu 3:78f223d34f36 2297 #define CAN0_RXIMR6 CAN_RXIMR_REG(CAN0,6)
ethaderu 3:78f223d34f36 2298 #define CAN0_RXIMR7 CAN_RXIMR_REG(CAN0,7)
ethaderu 3:78f223d34f36 2299 #define CAN0_RXIMR8 CAN_RXIMR_REG(CAN0,8)
ethaderu 3:78f223d34f36 2300 #define CAN0_RXIMR9 CAN_RXIMR_REG(CAN0,9)
ethaderu 3:78f223d34f36 2301 #define CAN0_RXIMR10 CAN_RXIMR_REG(CAN0,10)
ethaderu 3:78f223d34f36 2302 #define CAN0_RXIMR11 CAN_RXIMR_REG(CAN0,11)
ethaderu 3:78f223d34f36 2303 #define CAN0_RXIMR12 CAN_RXIMR_REG(CAN0,12)
ethaderu 3:78f223d34f36 2304 #define CAN0_RXIMR13 CAN_RXIMR_REG(CAN0,13)
ethaderu 3:78f223d34f36 2305 #define CAN0_RXIMR14 CAN_RXIMR_REG(CAN0,14)
ethaderu 3:78f223d34f36 2306 #define CAN0_RXIMR15 CAN_RXIMR_REG(CAN0,15)
ethaderu 3:78f223d34f36 2307
ethaderu 3:78f223d34f36 2308 /* CAN - Register array accessors */
ethaderu 3:78f223d34f36 2309 #define CAN0_CS(index) CAN_CS_REG(CAN0,index)
ethaderu 3:78f223d34f36 2310 #define CAN0_ID(index) CAN_ID_REG(CAN0,index)
ethaderu 3:78f223d34f36 2311 #define CAN0_WORD0(index) CAN_WORD0_REG(CAN0,index)
ethaderu 3:78f223d34f36 2312 #define CAN0_WORD1(index) CAN_WORD1_REG(CAN0,index)
ethaderu 3:78f223d34f36 2313 #define CAN0_RXIMR(index) CAN_RXIMR_REG(CAN0,index)
ethaderu 3:78f223d34f36 2314
ethaderu 3:78f223d34f36 2315 /*!
ethaderu 3:78f223d34f36 2316 * @}
ethaderu 3:78f223d34f36 2317 */ /* end of group CAN_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 2318
ethaderu 3:78f223d34f36 2319
ethaderu 3:78f223d34f36 2320 /*!
ethaderu 3:78f223d34f36 2321 * @}
ethaderu 3:78f223d34f36 2322 */ /* end of group CAN_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 2323
ethaderu 3:78f223d34f36 2324
ethaderu 3:78f223d34f36 2325 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 2326 -- CAU Peripheral Access Layer
ethaderu 3:78f223d34f36 2327 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 2328
ethaderu 3:78f223d34f36 2329 /*!
ethaderu 3:78f223d34f36 2330 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
ethaderu 3:78f223d34f36 2331 * @{
ethaderu 3:78f223d34f36 2332 */
ethaderu 3:78f223d34f36 2333
ethaderu 3:78f223d34f36 2334 /** CAU - Register Layout Typedef */
ethaderu 3:78f223d34f36 2335 typedef struct {
ethaderu 3:78f223d34f36 2336 __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
ethaderu 3:78f223d34f36 2337 uint8_t RESERVED_0[2048];
ethaderu 3:78f223d34f36 2338 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
ethaderu 3:78f223d34f36 2339 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
ethaderu 3:78f223d34f36 2340 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
ethaderu 3:78f223d34f36 2341 uint8_t RESERVED_1[20];
ethaderu 3:78f223d34f36 2342 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
ethaderu 3:78f223d34f36 2343 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
ethaderu 3:78f223d34f36 2344 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
ethaderu 3:78f223d34f36 2345 uint8_t RESERVED_2[20];
ethaderu 3:78f223d34f36 2346 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
ethaderu 3:78f223d34f36 2347 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
ethaderu 3:78f223d34f36 2348 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
ethaderu 3:78f223d34f36 2349 uint8_t RESERVED_3[20];
ethaderu 3:78f223d34f36 2350 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
ethaderu 3:78f223d34f36 2351 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
ethaderu 3:78f223d34f36 2352 __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
ethaderu 3:78f223d34f36 2353 uint8_t RESERVED_4[84];
ethaderu 3:78f223d34f36 2354 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
ethaderu 3:78f223d34f36 2355 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
ethaderu 3:78f223d34f36 2356 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
ethaderu 3:78f223d34f36 2357 uint8_t RESERVED_5[20];
ethaderu 3:78f223d34f36 2358 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
ethaderu 3:78f223d34f36 2359 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
ethaderu 3:78f223d34f36 2360 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
ethaderu 3:78f223d34f36 2361 uint8_t RESERVED_6[276];
ethaderu 3:78f223d34f36 2362 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
ethaderu 3:78f223d34f36 2363 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
ethaderu 3:78f223d34f36 2364 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
ethaderu 3:78f223d34f36 2365 uint8_t RESERVED_7[20];
ethaderu 3:78f223d34f36 2366 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
ethaderu 3:78f223d34f36 2367 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
ethaderu 3:78f223d34f36 2368 __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
ethaderu 3:78f223d34f36 2369 } CAU_Type, *CAU_MemMapPtr;
ethaderu 3:78f223d34f36 2370
ethaderu 3:78f223d34f36 2371 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 2372 -- CAU - Register accessor macros
ethaderu 3:78f223d34f36 2373 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 2374
ethaderu 3:78f223d34f36 2375 /*!
ethaderu 3:78f223d34f36 2376 * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
ethaderu 3:78f223d34f36 2377 * @{
ethaderu 3:78f223d34f36 2378 */
ethaderu 3:78f223d34f36 2379
ethaderu 3:78f223d34f36 2380
ethaderu 3:78f223d34f36 2381 /* CAU - Register accessors */
ethaderu 3:78f223d34f36 2382 #define CAU_DIRECT_REG(base,index) ((base)->DIRECT[index])
ethaderu 3:78f223d34f36 2383 #define CAU_LDR_CASR_REG(base) ((base)->LDR_CASR)
ethaderu 3:78f223d34f36 2384 #define CAU_LDR_CAA_REG(base) ((base)->LDR_CAA)
ethaderu 3:78f223d34f36 2385 #define CAU_LDR_CA_REG(base,index) ((base)->LDR_CA[index])
ethaderu 3:78f223d34f36 2386 #define CAU_STR_CASR_REG(base) ((base)->STR_CASR)
ethaderu 3:78f223d34f36 2387 #define CAU_STR_CAA_REG(base) ((base)->STR_CAA)
ethaderu 3:78f223d34f36 2388 #define CAU_STR_CA_REG(base,index) ((base)->STR_CA[index])
ethaderu 3:78f223d34f36 2389 #define CAU_ADR_CASR_REG(base) ((base)->ADR_CASR)
ethaderu 3:78f223d34f36 2390 #define CAU_ADR_CAA_REG(base) ((base)->ADR_CAA)
ethaderu 3:78f223d34f36 2391 #define CAU_ADR_CA_REG(base,index) ((base)->ADR_CA[index])
ethaderu 3:78f223d34f36 2392 #define CAU_RADR_CASR_REG(base) ((base)->RADR_CASR)
ethaderu 3:78f223d34f36 2393 #define CAU_RADR_CAA_REG(base) ((base)->RADR_CAA)
ethaderu 3:78f223d34f36 2394 #define CAU_RADR_CA_REG(base,index) ((base)->RADR_CA[index])
ethaderu 3:78f223d34f36 2395 #define CAU_XOR_CASR_REG(base) ((base)->XOR_CASR)
ethaderu 3:78f223d34f36 2396 #define CAU_XOR_CAA_REG(base) ((base)->XOR_CAA)
ethaderu 3:78f223d34f36 2397 #define CAU_XOR_CA_REG(base,index) ((base)->XOR_CA[index])
ethaderu 3:78f223d34f36 2398 #define CAU_ROTL_CASR_REG(base) ((base)->ROTL_CASR)
ethaderu 3:78f223d34f36 2399 #define CAU_ROTL_CAA_REG(base) ((base)->ROTL_CAA)
ethaderu 3:78f223d34f36 2400 #define CAU_ROTL_CA_REG(base,index) ((base)->ROTL_CA[index])
ethaderu 3:78f223d34f36 2401 #define CAU_AESC_CASR_REG(base) ((base)->AESC_CASR)
ethaderu 3:78f223d34f36 2402 #define CAU_AESC_CAA_REG(base) ((base)->AESC_CAA)
ethaderu 3:78f223d34f36 2403 #define CAU_AESC_CA_REG(base,index) ((base)->AESC_CA[index])
ethaderu 3:78f223d34f36 2404 #define CAU_AESIC_CASR_REG(base) ((base)->AESIC_CASR)
ethaderu 3:78f223d34f36 2405 #define CAU_AESIC_CAA_REG(base) ((base)->AESIC_CAA)
ethaderu 3:78f223d34f36 2406 #define CAU_AESIC_CA_REG(base,index) ((base)->AESIC_CA[index])
ethaderu 3:78f223d34f36 2407
ethaderu 3:78f223d34f36 2408 /*!
ethaderu 3:78f223d34f36 2409 * @}
ethaderu 3:78f223d34f36 2410 */ /* end of group CAU_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 2411
ethaderu 3:78f223d34f36 2412
ethaderu 3:78f223d34f36 2413 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 2414 -- CAU Register Masks
ethaderu 3:78f223d34f36 2415 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 2416
ethaderu 3:78f223d34f36 2417 /*!
ethaderu 3:78f223d34f36 2418 * @addtogroup CAU_Register_Masks CAU Register Masks
ethaderu 3:78f223d34f36 2419 * @{
ethaderu 3:78f223d34f36 2420 */
ethaderu 3:78f223d34f36 2421
ethaderu 3:78f223d34f36 2422 /* DIRECT Bit Fields */
ethaderu 3:78f223d34f36 2423 #define CAU_DIRECT_CAU_DIRECT0_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2424 #define CAU_DIRECT_CAU_DIRECT0_SHIFT 0
ethaderu 3:78f223d34f36 2425 #define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT0_SHIFT))&CAU_DIRECT_CAU_DIRECT0_MASK)
ethaderu 3:78f223d34f36 2426 #define CAU_DIRECT_CAU_DIRECT1_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2427 #define CAU_DIRECT_CAU_DIRECT1_SHIFT 0
ethaderu 3:78f223d34f36 2428 #define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT1_SHIFT))&CAU_DIRECT_CAU_DIRECT1_MASK)
ethaderu 3:78f223d34f36 2429 #define CAU_DIRECT_CAU_DIRECT2_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2430 #define CAU_DIRECT_CAU_DIRECT2_SHIFT 0
ethaderu 3:78f223d34f36 2431 #define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT2_SHIFT))&CAU_DIRECT_CAU_DIRECT2_MASK)
ethaderu 3:78f223d34f36 2432 #define CAU_DIRECT_CAU_DIRECT3_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2433 #define CAU_DIRECT_CAU_DIRECT3_SHIFT 0
ethaderu 3:78f223d34f36 2434 #define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT3_SHIFT))&CAU_DIRECT_CAU_DIRECT3_MASK)
ethaderu 3:78f223d34f36 2435 #define CAU_DIRECT_CAU_DIRECT4_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2436 #define CAU_DIRECT_CAU_DIRECT4_SHIFT 0
ethaderu 3:78f223d34f36 2437 #define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT4_SHIFT))&CAU_DIRECT_CAU_DIRECT4_MASK)
ethaderu 3:78f223d34f36 2438 #define CAU_DIRECT_CAU_DIRECT5_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2439 #define CAU_DIRECT_CAU_DIRECT5_SHIFT 0
ethaderu 3:78f223d34f36 2440 #define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT5_SHIFT))&CAU_DIRECT_CAU_DIRECT5_MASK)
ethaderu 3:78f223d34f36 2441 #define CAU_DIRECT_CAU_DIRECT6_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2442 #define CAU_DIRECT_CAU_DIRECT6_SHIFT 0
ethaderu 3:78f223d34f36 2443 #define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT6_SHIFT))&CAU_DIRECT_CAU_DIRECT6_MASK)
ethaderu 3:78f223d34f36 2444 #define CAU_DIRECT_CAU_DIRECT7_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2445 #define CAU_DIRECT_CAU_DIRECT7_SHIFT 0
ethaderu 3:78f223d34f36 2446 #define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT7_SHIFT))&CAU_DIRECT_CAU_DIRECT7_MASK)
ethaderu 3:78f223d34f36 2447 #define CAU_DIRECT_CAU_DIRECT8_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2448 #define CAU_DIRECT_CAU_DIRECT8_SHIFT 0
ethaderu 3:78f223d34f36 2449 #define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT8_SHIFT))&CAU_DIRECT_CAU_DIRECT8_MASK)
ethaderu 3:78f223d34f36 2450 #define CAU_DIRECT_CAU_DIRECT9_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2451 #define CAU_DIRECT_CAU_DIRECT9_SHIFT 0
ethaderu 3:78f223d34f36 2452 #define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT9_SHIFT))&CAU_DIRECT_CAU_DIRECT9_MASK)
ethaderu 3:78f223d34f36 2453 #define CAU_DIRECT_CAU_DIRECT10_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2454 #define CAU_DIRECT_CAU_DIRECT10_SHIFT 0
ethaderu 3:78f223d34f36 2455 #define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT10_SHIFT))&CAU_DIRECT_CAU_DIRECT10_MASK)
ethaderu 3:78f223d34f36 2456 #define CAU_DIRECT_CAU_DIRECT11_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2457 #define CAU_DIRECT_CAU_DIRECT11_SHIFT 0
ethaderu 3:78f223d34f36 2458 #define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT11_SHIFT))&CAU_DIRECT_CAU_DIRECT11_MASK)
ethaderu 3:78f223d34f36 2459 #define CAU_DIRECT_CAU_DIRECT12_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2460 #define CAU_DIRECT_CAU_DIRECT12_SHIFT 0
ethaderu 3:78f223d34f36 2461 #define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT12_SHIFT))&CAU_DIRECT_CAU_DIRECT12_MASK)
ethaderu 3:78f223d34f36 2462 #define CAU_DIRECT_CAU_DIRECT13_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2463 #define CAU_DIRECT_CAU_DIRECT13_SHIFT 0
ethaderu 3:78f223d34f36 2464 #define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT13_SHIFT))&CAU_DIRECT_CAU_DIRECT13_MASK)
ethaderu 3:78f223d34f36 2465 #define CAU_DIRECT_CAU_DIRECT14_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2466 #define CAU_DIRECT_CAU_DIRECT14_SHIFT 0
ethaderu 3:78f223d34f36 2467 #define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT14_SHIFT))&CAU_DIRECT_CAU_DIRECT14_MASK)
ethaderu 3:78f223d34f36 2468 #define CAU_DIRECT_CAU_DIRECT15_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2469 #define CAU_DIRECT_CAU_DIRECT15_SHIFT 0
ethaderu 3:78f223d34f36 2470 #define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT15_SHIFT))&CAU_DIRECT_CAU_DIRECT15_MASK)
ethaderu 3:78f223d34f36 2471 /* LDR_CASR Bit Fields */
ethaderu 3:78f223d34f36 2472 #define CAU_LDR_CASR_IC_MASK 0x1u
ethaderu 3:78f223d34f36 2473 #define CAU_LDR_CASR_IC_SHIFT 0
ethaderu 3:78f223d34f36 2474 #define CAU_LDR_CASR_DPE_MASK 0x2u
ethaderu 3:78f223d34f36 2475 #define CAU_LDR_CASR_DPE_SHIFT 1
ethaderu 3:78f223d34f36 2476 #define CAU_LDR_CASR_VER_MASK 0xF0000000u
ethaderu 3:78f223d34f36 2477 #define CAU_LDR_CASR_VER_SHIFT 28
ethaderu 3:78f223d34f36 2478 #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
ethaderu 3:78f223d34f36 2479 /* LDR_CAA Bit Fields */
ethaderu 3:78f223d34f36 2480 #define CAU_LDR_CAA_ACC_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2481 #define CAU_LDR_CAA_ACC_SHIFT 0
ethaderu 3:78f223d34f36 2482 #define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CAA_ACC_SHIFT))&CAU_LDR_CAA_ACC_MASK)
ethaderu 3:78f223d34f36 2483 /* LDR_CA Bit Fields */
ethaderu 3:78f223d34f36 2484 #define CAU_LDR_CA_CA0_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2485 #define CAU_LDR_CA_CA0_SHIFT 0
ethaderu 3:78f223d34f36 2486 #define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA0_SHIFT))&CAU_LDR_CA_CA0_MASK)
ethaderu 3:78f223d34f36 2487 #define CAU_LDR_CA_CA1_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2488 #define CAU_LDR_CA_CA1_SHIFT 0
ethaderu 3:78f223d34f36 2489 #define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA1_SHIFT))&CAU_LDR_CA_CA1_MASK)
ethaderu 3:78f223d34f36 2490 #define CAU_LDR_CA_CA2_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2491 #define CAU_LDR_CA_CA2_SHIFT 0
ethaderu 3:78f223d34f36 2492 #define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA2_SHIFT))&CAU_LDR_CA_CA2_MASK)
ethaderu 3:78f223d34f36 2493 #define CAU_LDR_CA_CA3_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2494 #define CAU_LDR_CA_CA3_SHIFT 0
ethaderu 3:78f223d34f36 2495 #define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA3_SHIFT))&CAU_LDR_CA_CA3_MASK)
ethaderu 3:78f223d34f36 2496 #define CAU_LDR_CA_CA4_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2497 #define CAU_LDR_CA_CA4_SHIFT 0
ethaderu 3:78f223d34f36 2498 #define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA4_SHIFT))&CAU_LDR_CA_CA4_MASK)
ethaderu 3:78f223d34f36 2499 #define CAU_LDR_CA_CA5_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2500 #define CAU_LDR_CA_CA5_SHIFT 0
ethaderu 3:78f223d34f36 2501 #define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA5_SHIFT))&CAU_LDR_CA_CA5_MASK)
ethaderu 3:78f223d34f36 2502 #define CAU_LDR_CA_CA6_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2503 #define CAU_LDR_CA_CA6_SHIFT 0
ethaderu 3:78f223d34f36 2504 #define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA6_SHIFT))&CAU_LDR_CA_CA6_MASK)
ethaderu 3:78f223d34f36 2505 #define CAU_LDR_CA_CA7_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2506 #define CAU_LDR_CA_CA7_SHIFT 0
ethaderu 3:78f223d34f36 2507 #define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA7_SHIFT))&CAU_LDR_CA_CA7_MASK)
ethaderu 3:78f223d34f36 2508 #define CAU_LDR_CA_CA8_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2509 #define CAU_LDR_CA_CA8_SHIFT 0
ethaderu 3:78f223d34f36 2510 #define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA8_SHIFT))&CAU_LDR_CA_CA8_MASK)
ethaderu 3:78f223d34f36 2511 /* STR_CASR Bit Fields */
ethaderu 3:78f223d34f36 2512 #define CAU_STR_CASR_IC_MASK 0x1u
ethaderu 3:78f223d34f36 2513 #define CAU_STR_CASR_IC_SHIFT 0
ethaderu 3:78f223d34f36 2514 #define CAU_STR_CASR_DPE_MASK 0x2u
ethaderu 3:78f223d34f36 2515 #define CAU_STR_CASR_DPE_SHIFT 1
ethaderu 3:78f223d34f36 2516 #define CAU_STR_CASR_VER_MASK 0xF0000000u
ethaderu 3:78f223d34f36 2517 #define CAU_STR_CASR_VER_SHIFT 28
ethaderu 3:78f223d34f36 2518 #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
ethaderu 3:78f223d34f36 2519 /* STR_CAA Bit Fields */
ethaderu 3:78f223d34f36 2520 #define CAU_STR_CAA_ACC_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2521 #define CAU_STR_CAA_ACC_SHIFT 0
ethaderu 3:78f223d34f36 2522 #define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CAA_ACC_SHIFT))&CAU_STR_CAA_ACC_MASK)
ethaderu 3:78f223d34f36 2523 /* STR_CA Bit Fields */
ethaderu 3:78f223d34f36 2524 #define CAU_STR_CA_CA0_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2525 #define CAU_STR_CA_CA0_SHIFT 0
ethaderu 3:78f223d34f36 2526 #define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA0_SHIFT))&CAU_STR_CA_CA0_MASK)
ethaderu 3:78f223d34f36 2527 #define CAU_STR_CA_CA1_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2528 #define CAU_STR_CA_CA1_SHIFT 0
ethaderu 3:78f223d34f36 2529 #define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA1_SHIFT))&CAU_STR_CA_CA1_MASK)
ethaderu 3:78f223d34f36 2530 #define CAU_STR_CA_CA2_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2531 #define CAU_STR_CA_CA2_SHIFT 0
ethaderu 3:78f223d34f36 2532 #define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA2_SHIFT))&CAU_STR_CA_CA2_MASK)
ethaderu 3:78f223d34f36 2533 #define CAU_STR_CA_CA3_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2534 #define CAU_STR_CA_CA3_SHIFT 0
ethaderu 3:78f223d34f36 2535 #define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA3_SHIFT))&CAU_STR_CA_CA3_MASK)
ethaderu 3:78f223d34f36 2536 #define CAU_STR_CA_CA4_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2537 #define CAU_STR_CA_CA4_SHIFT 0
ethaderu 3:78f223d34f36 2538 #define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA4_SHIFT))&CAU_STR_CA_CA4_MASK)
ethaderu 3:78f223d34f36 2539 #define CAU_STR_CA_CA5_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2540 #define CAU_STR_CA_CA5_SHIFT 0
ethaderu 3:78f223d34f36 2541 #define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA5_SHIFT))&CAU_STR_CA_CA5_MASK)
ethaderu 3:78f223d34f36 2542 #define CAU_STR_CA_CA6_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2543 #define CAU_STR_CA_CA6_SHIFT 0
ethaderu 3:78f223d34f36 2544 #define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA6_SHIFT))&CAU_STR_CA_CA6_MASK)
ethaderu 3:78f223d34f36 2545 #define CAU_STR_CA_CA7_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2546 #define CAU_STR_CA_CA7_SHIFT 0
ethaderu 3:78f223d34f36 2547 #define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA7_SHIFT))&CAU_STR_CA_CA7_MASK)
ethaderu 3:78f223d34f36 2548 #define CAU_STR_CA_CA8_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2549 #define CAU_STR_CA_CA8_SHIFT 0
ethaderu 3:78f223d34f36 2550 #define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA8_SHIFT))&CAU_STR_CA_CA8_MASK)
ethaderu 3:78f223d34f36 2551 /* ADR_CASR Bit Fields */
ethaderu 3:78f223d34f36 2552 #define CAU_ADR_CASR_IC_MASK 0x1u
ethaderu 3:78f223d34f36 2553 #define CAU_ADR_CASR_IC_SHIFT 0
ethaderu 3:78f223d34f36 2554 #define CAU_ADR_CASR_DPE_MASK 0x2u
ethaderu 3:78f223d34f36 2555 #define CAU_ADR_CASR_DPE_SHIFT 1
ethaderu 3:78f223d34f36 2556 #define CAU_ADR_CASR_VER_MASK 0xF0000000u
ethaderu 3:78f223d34f36 2557 #define CAU_ADR_CASR_VER_SHIFT 28
ethaderu 3:78f223d34f36 2558 #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
ethaderu 3:78f223d34f36 2559 /* ADR_CAA Bit Fields */
ethaderu 3:78f223d34f36 2560 #define CAU_ADR_CAA_ACC_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2561 #define CAU_ADR_CAA_ACC_SHIFT 0
ethaderu 3:78f223d34f36 2562 #define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CAA_ACC_SHIFT))&CAU_ADR_CAA_ACC_MASK)
ethaderu 3:78f223d34f36 2563 /* ADR_CA Bit Fields */
ethaderu 3:78f223d34f36 2564 #define CAU_ADR_CA_CA0_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2565 #define CAU_ADR_CA_CA0_SHIFT 0
ethaderu 3:78f223d34f36 2566 #define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA0_SHIFT))&CAU_ADR_CA_CA0_MASK)
ethaderu 3:78f223d34f36 2567 #define CAU_ADR_CA_CA1_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2568 #define CAU_ADR_CA_CA1_SHIFT 0
ethaderu 3:78f223d34f36 2569 #define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA1_SHIFT))&CAU_ADR_CA_CA1_MASK)
ethaderu 3:78f223d34f36 2570 #define CAU_ADR_CA_CA2_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2571 #define CAU_ADR_CA_CA2_SHIFT 0
ethaderu 3:78f223d34f36 2572 #define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA2_SHIFT))&CAU_ADR_CA_CA2_MASK)
ethaderu 3:78f223d34f36 2573 #define CAU_ADR_CA_CA3_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2574 #define CAU_ADR_CA_CA3_SHIFT 0
ethaderu 3:78f223d34f36 2575 #define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA3_SHIFT))&CAU_ADR_CA_CA3_MASK)
ethaderu 3:78f223d34f36 2576 #define CAU_ADR_CA_CA4_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2577 #define CAU_ADR_CA_CA4_SHIFT 0
ethaderu 3:78f223d34f36 2578 #define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA4_SHIFT))&CAU_ADR_CA_CA4_MASK)
ethaderu 3:78f223d34f36 2579 #define CAU_ADR_CA_CA5_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2580 #define CAU_ADR_CA_CA5_SHIFT 0
ethaderu 3:78f223d34f36 2581 #define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA5_SHIFT))&CAU_ADR_CA_CA5_MASK)
ethaderu 3:78f223d34f36 2582 #define CAU_ADR_CA_CA6_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2583 #define CAU_ADR_CA_CA6_SHIFT 0
ethaderu 3:78f223d34f36 2584 #define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA6_SHIFT))&CAU_ADR_CA_CA6_MASK)
ethaderu 3:78f223d34f36 2585 #define CAU_ADR_CA_CA7_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2586 #define CAU_ADR_CA_CA7_SHIFT 0
ethaderu 3:78f223d34f36 2587 #define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA7_SHIFT))&CAU_ADR_CA_CA7_MASK)
ethaderu 3:78f223d34f36 2588 #define CAU_ADR_CA_CA8_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2589 #define CAU_ADR_CA_CA8_SHIFT 0
ethaderu 3:78f223d34f36 2590 #define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA8_SHIFT))&CAU_ADR_CA_CA8_MASK)
ethaderu 3:78f223d34f36 2591 /* RADR_CASR Bit Fields */
ethaderu 3:78f223d34f36 2592 #define CAU_RADR_CASR_IC_MASK 0x1u
ethaderu 3:78f223d34f36 2593 #define CAU_RADR_CASR_IC_SHIFT 0
ethaderu 3:78f223d34f36 2594 #define CAU_RADR_CASR_DPE_MASK 0x2u
ethaderu 3:78f223d34f36 2595 #define CAU_RADR_CASR_DPE_SHIFT 1
ethaderu 3:78f223d34f36 2596 #define CAU_RADR_CASR_VER_MASK 0xF0000000u
ethaderu 3:78f223d34f36 2597 #define CAU_RADR_CASR_VER_SHIFT 28
ethaderu 3:78f223d34f36 2598 #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
ethaderu 3:78f223d34f36 2599 /* RADR_CAA Bit Fields */
ethaderu 3:78f223d34f36 2600 #define CAU_RADR_CAA_ACC_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2601 #define CAU_RADR_CAA_ACC_SHIFT 0
ethaderu 3:78f223d34f36 2602 #define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CAA_ACC_SHIFT))&CAU_RADR_CAA_ACC_MASK)
ethaderu 3:78f223d34f36 2603 /* RADR_CA Bit Fields */
ethaderu 3:78f223d34f36 2604 #define CAU_RADR_CA_CA0_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2605 #define CAU_RADR_CA_CA0_SHIFT 0
ethaderu 3:78f223d34f36 2606 #define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA0_SHIFT))&CAU_RADR_CA_CA0_MASK)
ethaderu 3:78f223d34f36 2607 #define CAU_RADR_CA_CA1_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2608 #define CAU_RADR_CA_CA1_SHIFT 0
ethaderu 3:78f223d34f36 2609 #define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA1_SHIFT))&CAU_RADR_CA_CA1_MASK)
ethaderu 3:78f223d34f36 2610 #define CAU_RADR_CA_CA2_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2611 #define CAU_RADR_CA_CA2_SHIFT 0
ethaderu 3:78f223d34f36 2612 #define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA2_SHIFT))&CAU_RADR_CA_CA2_MASK)
ethaderu 3:78f223d34f36 2613 #define CAU_RADR_CA_CA3_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2614 #define CAU_RADR_CA_CA3_SHIFT 0
ethaderu 3:78f223d34f36 2615 #define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA3_SHIFT))&CAU_RADR_CA_CA3_MASK)
ethaderu 3:78f223d34f36 2616 #define CAU_RADR_CA_CA4_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2617 #define CAU_RADR_CA_CA4_SHIFT 0
ethaderu 3:78f223d34f36 2618 #define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA4_SHIFT))&CAU_RADR_CA_CA4_MASK)
ethaderu 3:78f223d34f36 2619 #define CAU_RADR_CA_CA5_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2620 #define CAU_RADR_CA_CA5_SHIFT 0
ethaderu 3:78f223d34f36 2621 #define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA5_SHIFT))&CAU_RADR_CA_CA5_MASK)
ethaderu 3:78f223d34f36 2622 #define CAU_RADR_CA_CA6_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2623 #define CAU_RADR_CA_CA6_SHIFT 0
ethaderu 3:78f223d34f36 2624 #define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA6_SHIFT))&CAU_RADR_CA_CA6_MASK)
ethaderu 3:78f223d34f36 2625 #define CAU_RADR_CA_CA7_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2626 #define CAU_RADR_CA_CA7_SHIFT 0
ethaderu 3:78f223d34f36 2627 #define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA7_SHIFT))&CAU_RADR_CA_CA7_MASK)
ethaderu 3:78f223d34f36 2628 #define CAU_RADR_CA_CA8_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2629 #define CAU_RADR_CA_CA8_SHIFT 0
ethaderu 3:78f223d34f36 2630 #define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA8_SHIFT))&CAU_RADR_CA_CA8_MASK)
ethaderu 3:78f223d34f36 2631 /* XOR_CASR Bit Fields */
ethaderu 3:78f223d34f36 2632 #define CAU_XOR_CASR_IC_MASK 0x1u
ethaderu 3:78f223d34f36 2633 #define CAU_XOR_CASR_IC_SHIFT 0
ethaderu 3:78f223d34f36 2634 #define CAU_XOR_CASR_DPE_MASK 0x2u
ethaderu 3:78f223d34f36 2635 #define CAU_XOR_CASR_DPE_SHIFT 1
ethaderu 3:78f223d34f36 2636 #define CAU_XOR_CASR_VER_MASK 0xF0000000u
ethaderu 3:78f223d34f36 2637 #define CAU_XOR_CASR_VER_SHIFT 28
ethaderu 3:78f223d34f36 2638 #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
ethaderu 3:78f223d34f36 2639 /* XOR_CAA Bit Fields */
ethaderu 3:78f223d34f36 2640 #define CAU_XOR_CAA_ACC_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2641 #define CAU_XOR_CAA_ACC_SHIFT 0
ethaderu 3:78f223d34f36 2642 #define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CAA_ACC_SHIFT))&CAU_XOR_CAA_ACC_MASK)
ethaderu 3:78f223d34f36 2643 /* XOR_CA Bit Fields */
ethaderu 3:78f223d34f36 2644 #define CAU_XOR_CA_CA0_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2645 #define CAU_XOR_CA_CA0_SHIFT 0
ethaderu 3:78f223d34f36 2646 #define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA0_SHIFT))&CAU_XOR_CA_CA0_MASK)
ethaderu 3:78f223d34f36 2647 #define CAU_XOR_CA_CA1_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2648 #define CAU_XOR_CA_CA1_SHIFT 0
ethaderu 3:78f223d34f36 2649 #define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA1_SHIFT))&CAU_XOR_CA_CA1_MASK)
ethaderu 3:78f223d34f36 2650 #define CAU_XOR_CA_CA2_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2651 #define CAU_XOR_CA_CA2_SHIFT 0
ethaderu 3:78f223d34f36 2652 #define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA2_SHIFT))&CAU_XOR_CA_CA2_MASK)
ethaderu 3:78f223d34f36 2653 #define CAU_XOR_CA_CA3_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2654 #define CAU_XOR_CA_CA3_SHIFT 0
ethaderu 3:78f223d34f36 2655 #define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA3_SHIFT))&CAU_XOR_CA_CA3_MASK)
ethaderu 3:78f223d34f36 2656 #define CAU_XOR_CA_CA4_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2657 #define CAU_XOR_CA_CA4_SHIFT 0
ethaderu 3:78f223d34f36 2658 #define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA4_SHIFT))&CAU_XOR_CA_CA4_MASK)
ethaderu 3:78f223d34f36 2659 #define CAU_XOR_CA_CA5_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2660 #define CAU_XOR_CA_CA5_SHIFT 0
ethaderu 3:78f223d34f36 2661 #define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA5_SHIFT))&CAU_XOR_CA_CA5_MASK)
ethaderu 3:78f223d34f36 2662 #define CAU_XOR_CA_CA6_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2663 #define CAU_XOR_CA_CA6_SHIFT 0
ethaderu 3:78f223d34f36 2664 #define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA6_SHIFT))&CAU_XOR_CA_CA6_MASK)
ethaderu 3:78f223d34f36 2665 #define CAU_XOR_CA_CA7_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2666 #define CAU_XOR_CA_CA7_SHIFT 0
ethaderu 3:78f223d34f36 2667 #define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA7_SHIFT))&CAU_XOR_CA_CA7_MASK)
ethaderu 3:78f223d34f36 2668 #define CAU_XOR_CA_CA8_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2669 #define CAU_XOR_CA_CA8_SHIFT 0
ethaderu 3:78f223d34f36 2670 #define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA8_SHIFT))&CAU_XOR_CA_CA8_MASK)
ethaderu 3:78f223d34f36 2671 /* ROTL_CASR Bit Fields */
ethaderu 3:78f223d34f36 2672 #define CAU_ROTL_CASR_IC_MASK 0x1u
ethaderu 3:78f223d34f36 2673 #define CAU_ROTL_CASR_IC_SHIFT 0
ethaderu 3:78f223d34f36 2674 #define CAU_ROTL_CASR_DPE_MASK 0x2u
ethaderu 3:78f223d34f36 2675 #define CAU_ROTL_CASR_DPE_SHIFT 1
ethaderu 3:78f223d34f36 2676 #define CAU_ROTL_CASR_VER_MASK 0xF0000000u
ethaderu 3:78f223d34f36 2677 #define CAU_ROTL_CASR_VER_SHIFT 28
ethaderu 3:78f223d34f36 2678 #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
ethaderu 3:78f223d34f36 2679 /* ROTL_CAA Bit Fields */
ethaderu 3:78f223d34f36 2680 #define CAU_ROTL_CAA_ACC_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2681 #define CAU_ROTL_CAA_ACC_SHIFT 0
ethaderu 3:78f223d34f36 2682 #define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CAA_ACC_SHIFT))&CAU_ROTL_CAA_ACC_MASK)
ethaderu 3:78f223d34f36 2683 /* ROTL_CA Bit Fields */
ethaderu 3:78f223d34f36 2684 #define CAU_ROTL_CA_CA0_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2685 #define CAU_ROTL_CA_CA0_SHIFT 0
ethaderu 3:78f223d34f36 2686 #define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA0_SHIFT))&CAU_ROTL_CA_CA0_MASK)
ethaderu 3:78f223d34f36 2687 #define CAU_ROTL_CA_CA1_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2688 #define CAU_ROTL_CA_CA1_SHIFT 0
ethaderu 3:78f223d34f36 2689 #define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA1_SHIFT))&CAU_ROTL_CA_CA1_MASK)
ethaderu 3:78f223d34f36 2690 #define CAU_ROTL_CA_CA2_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2691 #define CAU_ROTL_CA_CA2_SHIFT 0
ethaderu 3:78f223d34f36 2692 #define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA2_SHIFT))&CAU_ROTL_CA_CA2_MASK)
ethaderu 3:78f223d34f36 2693 #define CAU_ROTL_CA_CA3_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2694 #define CAU_ROTL_CA_CA3_SHIFT 0
ethaderu 3:78f223d34f36 2695 #define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA3_SHIFT))&CAU_ROTL_CA_CA3_MASK)
ethaderu 3:78f223d34f36 2696 #define CAU_ROTL_CA_CA4_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2697 #define CAU_ROTL_CA_CA4_SHIFT 0
ethaderu 3:78f223d34f36 2698 #define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA4_SHIFT))&CAU_ROTL_CA_CA4_MASK)
ethaderu 3:78f223d34f36 2699 #define CAU_ROTL_CA_CA5_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2700 #define CAU_ROTL_CA_CA5_SHIFT 0
ethaderu 3:78f223d34f36 2701 #define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA5_SHIFT))&CAU_ROTL_CA_CA5_MASK)
ethaderu 3:78f223d34f36 2702 #define CAU_ROTL_CA_CA6_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2703 #define CAU_ROTL_CA_CA6_SHIFT 0
ethaderu 3:78f223d34f36 2704 #define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA6_SHIFT))&CAU_ROTL_CA_CA6_MASK)
ethaderu 3:78f223d34f36 2705 #define CAU_ROTL_CA_CA7_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2706 #define CAU_ROTL_CA_CA7_SHIFT 0
ethaderu 3:78f223d34f36 2707 #define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA7_SHIFT))&CAU_ROTL_CA_CA7_MASK)
ethaderu 3:78f223d34f36 2708 #define CAU_ROTL_CA_CA8_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2709 #define CAU_ROTL_CA_CA8_SHIFT 0
ethaderu 3:78f223d34f36 2710 #define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA8_SHIFT))&CAU_ROTL_CA_CA8_MASK)
ethaderu 3:78f223d34f36 2711 /* AESC_CASR Bit Fields */
ethaderu 3:78f223d34f36 2712 #define CAU_AESC_CASR_IC_MASK 0x1u
ethaderu 3:78f223d34f36 2713 #define CAU_AESC_CASR_IC_SHIFT 0
ethaderu 3:78f223d34f36 2714 #define CAU_AESC_CASR_DPE_MASK 0x2u
ethaderu 3:78f223d34f36 2715 #define CAU_AESC_CASR_DPE_SHIFT 1
ethaderu 3:78f223d34f36 2716 #define CAU_AESC_CASR_VER_MASK 0xF0000000u
ethaderu 3:78f223d34f36 2717 #define CAU_AESC_CASR_VER_SHIFT 28
ethaderu 3:78f223d34f36 2718 #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
ethaderu 3:78f223d34f36 2719 /* AESC_CAA Bit Fields */
ethaderu 3:78f223d34f36 2720 #define CAU_AESC_CAA_ACC_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2721 #define CAU_AESC_CAA_ACC_SHIFT 0
ethaderu 3:78f223d34f36 2722 #define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CAA_ACC_SHIFT))&CAU_AESC_CAA_ACC_MASK)
ethaderu 3:78f223d34f36 2723 /* AESC_CA Bit Fields */
ethaderu 3:78f223d34f36 2724 #define CAU_AESC_CA_CA0_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2725 #define CAU_AESC_CA_CA0_SHIFT 0
ethaderu 3:78f223d34f36 2726 #define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA0_SHIFT))&CAU_AESC_CA_CA0_MASK)
ethaderu 3:78f223d34f36 2727 #define CAU_AESC_CA_CA1_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2728 #define CAU_AESC_CA_CA1_SHIFT 0
ethaderu 3:78f223d34f36 2729 #define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA1_SHIFT))&CAU_AESC_CA_CA1_MASK)
ethaderu 3:78f223d34f36 2730 #define CAU_AESC_CA_CA2_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2731 #define CAU_AESC_CA_CA2_SHIFT 0
ethaderu 3:78f223d34f36 2732 #define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA2_SHIFT))&CAU_AESC_CA_CA2_MASK)
ethaderu 3:78f223d34f36 2733 #define CAU_AESC_CA_CA3_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2734 #define CAU_AESC_CA_CA3_SHIFT 0
ethaderu 3:78f223d34f36 2735 #define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA3_SHIFT))&CAU_AESC_CA_CA3_MASK)
ethaderu 3:78f223d34f36 2736 #define CAU_AESC_CA_CA4_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2737 #define CAU_AESC_CA_CA4_SHIFT 0
ethaderu 3:78f223d34f36 2738 #define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA4_SHIFT))&CAU_AESC_CA_CA4_MASK)
ethaderu 3:78f223d34f36 2739 #define CAU_AESC_CA_CA5_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2740 #define CAU_AESC_CA_CA5_SHIFT 0
ethaderu 3:78f223d34f36 2741 #define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA5_SHIFT))&CAU_AESC_CA_CA5_MASK)
ethaderu 3:78f223d34f36 2742 #define CAU_AESC_CA_CA6_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2743 #define CAU_AESC_CA_CA6_SHIFT 0
ethaderu 3:78f223d34f36 2744 #define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA6_SHIFT))&CAU_AESC_CA_CA6_MASK)
ethaderu 3:78f223d34f36 2745 #define CAU_AESC_CA_CA7_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2746 #define CAU_AESC_CA_CA7_SHIFT 0
ethaderu 3:78f223d34f36 2747 #define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA7_SHIFT))&CAU_AESC_CA_CA7_MASK)
ethaderu 3:78f223d34f36 2748 #define CAU_AESC_CA_CA8_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2749 #define CAU_AESC_CA_CA8_SHIFT 0
ethaderu 3:78f223d34f36 2750 #define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA8_SHIFT))&CAU_AESC_CA_CA8_MASK)
ethaderu 3:78f223d34f36 2751 /* AESIC_CASR Bit Fields */
ethaderu 3:78f223d34f36 2752 #define CAU_AESIC_CASR_IC_MASK 0x1u
ethaderu 3:78f223d34f36 2753 #define CAU_AESIC_CASR_IC_SHIFT 0
ethaderu 3:78f223d34f36 2754 #define CAU_AESIC_CASR_DPE_MASK 0x2u
ethaderu 3:78f223d34f36 2755 #define CAU_AESIC_CASR_DPE_SHIFT 1
ethaderu 3:78f223d34f36 2756 #define CAU_AESIC_CASR_VER_MASK 0xF0000000u
ethaderu 3:78f223d34f36 2757 #define CAU_AESIC_CASR_VER_SHIFT 28
ethaderu 3:78f223d34f36 2758 #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
ethaderu 3:78f223d34f36 2759 /* AESIC_CAA Bit Fields */
ethaderu 3:78f223d34f36 2760 #define CAU_AESIC_CAA_ACC_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2761 #define CAU_AESIC_CAA_ACC_SHIFT 0
ethaderu 3:78f223d34f36 2762 #define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CAA_ACC_SHIFT))&CAU_AESIC_CAA_ACC_MASK)
ethaderu 3:78f223d34f36 2763 /* AESIC_CA Bit Fields */
ethaderu 3:78f223d34f36 2764 #define CAU_AESIC_CA_CA0_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2765 #define CAU_AESIC_CA_CA0_SHIFT 0
ethaderu 3:78f223d34f36 2766 #define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA0_SHIFT))&CAU_AESIC_CA_CA0_MASK)
ethaderu 3:78f223d34f36 2767 #define CAU_AESIC_CA_CA1_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2768 #define CAU_AESIC_CA_CA1_SHIFT 0
ethaderu 3:78f223d34f36 2769 #define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA1_SHIFT))&CAU_AESIC_CA_CA1_MASK)
ethaderu 3:78f223d34f36 2770 #define CAU_AESIC_CA_CA2_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2771 #define CAU_AESIC_CA_CA2_SHIFT 0
ethaderu 3:78f223d34f36 2772 #define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA2_SHIFT))&CAU_AESIC_CA_CA2_MASK)
ethaderu 3:78f223d34f36 2773 #define CAU_AESIC_CA_CA3_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2774 #define CAU_AESIC_CA_CA3_SHIFT 0
ethaderu 3:78f223d34f36 2775 #define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA3_SHIFT))&CAU_AESIC_CA_CA3_MASK)
ethaderu 3:78f223d34f36 2776 #define CAU_AESIC_CA_CA4_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2777 #define CAU_AESIC_CA_CA4_SHIFT 0
ethaderu 3:78f223d34f36 2778 #define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA4_SHIFT))&CAU_AESIC_CA_CA4_MASK)
ethaderu 3:78f223d34f36 2779 #define CAU_AESIC_CA_CA5_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2780 #define CAU_AESIC_CA_CA5_SHIFT 0
ethaderu 3:78f223d34f36 2781 #define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA5_SHIFT))&CAU_AESIC_CA_CA5_MASK)
ethaderu 3:78f223d34f36 2782 #define CAU_AESIC_CA_CA6_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2783 #define CAU_AESIC_CA_CA6_SHIFT 0
ethaderu 3:78f223d34f36 2784 #define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA6_SHIFT))&CAU_AESIC_CA_CA6_MASK)
ethaderu 3:78f223d34f36 2785 #define CAU_AESIC_CA_CA7_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2786 #define CAU_AESIC_CA_CA7_SHIFT 0
ethaderu 3:78f223d34f36 2787 #define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA7_SHIFT))&CAU_AESIC_CA_CA7_MASK)
ethaderu 3:78f223d34f36 2788 #define CAU_AESIC_CA_CA8_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 2789 #define CAU_AESIC_CA_CA8_SHIFT 0
ethaderu 3:78f223d34f36 2790 #define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA8_SHIFT))&CAU_AESIC_CA_CA8_MASK)
ethaderu 3:78f223d34f36 2791
ethaderu 3:78f223d34f36 2792 /*!
ethaderu 3:78f223d34f36 2793 * @}
ethaderu 3:78f223d34f36 2794 */ /* end of group CAU_Register_Masks */
ethaderu 3:78f223d34f36 2795
ethaderu 3:78f223d34f36 2796
ethaderu 3:78f223d34f36 2797 /* CAU - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 2798 /** Peripheral CAU base address */
ethaderu 3:78f223d34f36 2799 #define CAU_BASE (0xE0081000u)
ethaderu 3:78f223d34f36 2800 /** Peripheral CAU base pointer */
ethaderu 3:78f223d34f36 2801 #define CAU ((CAU_Type *)CAU_BASE)
ethaderu 3:78f223d34f36 2802 #define CAU_BASE_PTR (CAU)
ethaderu 3:78f223d34f36 2803 /** Array initializer of CAU peripheral base addresses */
ethaderu 3:78f223d34f36 2804 #define CAU_BASE_ADDRS { CAU_BASE }
ethaderu 3:78f223d34f36 2805 /** Array initializer of CAU peripheral base pointers */
ethaderu 3:78f223d34f36 2806 #define CAU_BASE_PTRS { CAU }
ethaderu 3:78f223d34f36 2807
ethaderu 3:78f223d34f36 2808 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 2809 -- CAU - Register accessor macros
ethaderu 3:78f223d34f36 2810 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 2811
ethaderu 3:78f223d34f36 2812 /*!
ethaderu 3:78f223d34f36 2813 * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
ethaderu 3:78f223d34f36 2814 * @{
ethaderu 3:78f223d34f36 2815 */
ethaderu 3:78f223d34f36 2816
ethaderu 3:78f223d34f36 2817
ethaderu 3:78f223d34f36 2818 /* CAU - Register instance definitions */
ethaderu 3:78f223d34f36 2819 /* CAU */
ethaderu 3:78f223d34f36 2820 #define CAU_DIRECT0 CAU_DIRECT_REG(CAU,0)
ethaderu 3:78f223d34f36 2821 #define CAU_DIRECT1 CAU_DIRECT_REG(CAU,1)
ethaderu 3:78f223d34f36 2822 #define CAU_DIRECT2 CAU_DIRECT_REG(CAU,2)
ethaderu 3:78f223d34f36 2823 #define CAU_DIRECT3 CAU_DIRECT_REG(CAU,3)
ethaderu 3:78f223d34f36 2824 #define CAU_DIRECT4 CAU_DIRECT_REG(CAU,4)
ethaderu 3:78f223d34f36 2825 #define CAU_DIRECT5 CAU_DIRECT_REG(CAU,5)
ethaderu 3:78f223d34f36 2826 #define CAU_DIRECT6 CAU_DIRECT_REG(CAU,6)
ethaderu 3:78f223d34f36 2827 #define CAU_DIRECT7 CAU_DIRECT_REG(CAU,7)
ethaderu 3:78f223d34f36 2828 #define CAU_DIRECT8 CAU_DIRECT_REG(CAU,8)
ethaderu 3:78f223d34f36 2829 #define CAU_DIRECT9 CAU_DIRECT_REG(CAU,9)
ethaderu 3:78f223d34f36 2830 #define CAU_DIRECT10 CAU_DIRECT_REG(CAU,10)
ethaderu 3:78f223d34f36 2831 #define CAU_DIRECT11 CAU_DIRECT_REG(CAU,11)
ethaderu 3:78f223d34f36 2832 #define CAU_DIRECT12 CAU_DIRECT_REG(CAU,12)
ethaderu 3:78f223d34f36 2833 #define CAU_DIRECT13 CAU_DIRECT_REG(CAU,13)
ethaderu 3:78f223d34f36 2834 #define CAU_DIRECT14 CAU_DIRECT_REG(CAU,14)
ethaderu 3:78f223d34f36 2835 #define CAU_DIRECT15 CAU_DIRECT_REG(CAU,15)
ethaderu 3:78f223d34f36 2836 #define CAU_LDR_CASR CAU_LDR_CASR_REG(CAU)
ethaderu 3:78f223d34f36 2837 #define CAU_LDR_CAA CAU_LDR_CAA_REG(CAU)
ethaderu 3:78f223d34f36 2838 #define CAU_LDR_CA0 CAU_LDR_CA_REG(CAU,0)
ethaderu 3:78f223d34f36 2839 #define CAU_LDR_CA1 CAU_LDR_CA_REG(CAU,1)
ethaderu 3:78f223d34f36 2840 #define CAU_LDR_CA2 CAU_LDR_CA_REG(CAU,2)
ethaderu 3:78f223d34f36 2841 #define CAU_LDR_CA3 CAU_LDR_CA_REG(CAU,3)
ethaderu 3:78f223d34f36 2842 #define CAU_LDR_CA4 CAU_LDR_CA_REG(CAU,4)
ethaderu 3:78f223d34f36 2843 #define CAU_LDR_CA5 CAU_LDR_CA_REG(CAU,5)
ethaderu 3:78f223d34f36 2844 #define CAU_LDR_CA6 CAU_LDR_CA_REG(CAU,6)
ethaderu 3:78f223d34f36 2845 #define CAU_LDR_CA7 CAU_LDR_CA_REG(CAU,7)
ethaderu 3:78f223d34f36 2846 #define CAU_LDR_CA8 CAU_LDR_CA_REG(CAU,8)
ethaderu 3:78f223d34f36 2847 #define CAU_STR_CASR CAU_STR_CASR_REG(CAU)
ethaderu 3:78f223d34f36 2848 #define CAU_STR_CAA CAU_STR_CAA_REG(CAU)
ethaderu 3:78f223d34f36 2849 #define CAU_STR_CA0 CAU_STR_CA_REG(CAU,0)
ethaderu 3:78f223d34f36 2850 #define CAU_STR_CA1 CAU_STR_CA_REG(CAU,1)
ethaderu 3:78f223d34f36 2851 #define CAU_STR_CA2 CAU_STR_CA_REG(CAU,2)
ethaderu 3:78f223d34f36 2852 #define CAU_STR_CA3 CAU_STR_CA_REG(CAU,3)
ethaderu 3:78f223d34f36 2853 #define CAU_STR_CA4 CAU_STR_CA_REG(CAU,4)
ethaderu 3:78f223d34f36 2854 #define CAU_STR_CA5 CAU_STR_CA_REG(CAU,5)
ethaderu 3:78f223d34f36 2855 #define CAU_STR_CA6 CAU_STR_CA_REG(CAU,6)
ethaderu 3:78f223d34f36 2856 #define CAU_STR_CA7 CAU_STR_CA_REG(CAU,7)
ethaderu 3:78f223d34f36 2857 #define CAU_STR_CA8 CAU_STR_CA_REG(CAU,8)
ethaderu 3:78f223d34f36 2858 #define CAU_ADR_CASR CAU_ADR_CASR_REG(CAU)
ethaderu 3:78f223d34f36 2859 #define CAU_ADR_CAA CAU_ADR_CAA_REG(CAU)
ethaderu 3:78f223d34f36 2860 #define CAU_ADR_CA0 CAU_ADR_CA_REG(CAU,0)
ethaderu 3:78f223d34f36 2861 #define CAU_ADR_CA1 CAU_ADR_CA_REG(CAU,1)
ethaderu 3:78f223d34f36 2862 #define CAU_ADR_CA2 CAU_ADR_CA_REG(CAU,2)
ethaderu 3:78f223d34f36 2863 #define CAU_ADR_CA3 CAU_ADR_CA_REG(CAU,3)
ethaderu 3:78f223d34f36 2864 #define CAU_ADR_CA4 CAU_ADR_CA_REG(CAU,4)
ethaderu 3:78f223d34f36 2865 #define CAU_ADR_CA5 CAU_ADR_CA_REG(CAU,5)
ethaderu 3:78f223d34f36 2866 #define CAU_ADR_CA6 CAU_ADR_CA_REG(CAU,6)
ethaderu 3:78f223d34f36 2867 #define CAU_ADR_CA7 CAU_ADR_CA_REG(CAU,7)
ethaderu 3:78f223d34f36 2868 #define CAU_ADR_CA8 CAU_ADR_CA_REG(CAU,8)
ethaderu 3:78f223d34f36 2869 #define CAU_RADR_CASR CAU_RADR_CASR_REG(CAU)
ethaderu 3:78f223d34f36 2870 #define CAU_RADR_CAA CAU_RADR_CAA_REG(CAU)
ethaderu 3:78f223d34f36 2871 #define CAU_RADR_CA0 CAU_RADR_CA_REG(CAU,0)
ethaderu 3:78f223d34f36 2872 #define CAU_RADR_CA1 CAU_RADR_CA_REG(CAU,1)
ethaderu 3:78f223d34f36 2873 #define CAU_RADR_CA2 CAU_RADR_CA_REG(CAU,2)
ethaderu 3:78f223d34f36 2874 #define CAU_RADR_CA3 CAU_RADR_CA_REG(CAU,3)
ethaderu 3:78f223d34f36 2875 #define CAU_RADR_CA4 CAU_RADR_CA_REG(CAU,4)
ethaderu 3:78f223d34f36 2876 #define CAU_RADR_CA5 CAU_RADR_CA_REG(CAU,5)
ethaderu 3:78f223d34f36 2877 #define CAU_RADR_CA6 CAU_RADR_CA_REG(CAU,6)
ethaderu 3:78f223d34f36 2878 #define CAU_RADR_CA7 CAU_RADR_CA_REG(CAU,7)
ethaderu 3:78f223d34f36 2879 #define CAU_RADR_CA8 CAU_RADR_CA_REG(CAU,8)
ethaderu 3:78f223d34f36 2880 #define CAU_XOR_CASR CAU_XOR_CASR_REG(CAU)
ethaderu 3:78f223d34f36 2881 #define CAU_XOR_CAA CAU_XOR_CAA_REG(CAU)
ethaderu 3:78f223d34f36 2882 #define CAU_XOR_CA0 CAU_XOR_CA_REG(CAU,0)
ethaderu 3:78f223d34f36 2883 #define CAU_XOR_CA1 CAU_XOR_CA_REG(CAU,1)
ethaderu 3:78f223d34f36 2884 #define CAU_XOR_CA2 CAU_XOR_CA_REG(CAU,2)
ethaderu 3:78f223d34f36 2885 #define CAU_XOR_CA3 CAU_XOR_CA_REG(CAU,3)
ethaderu 3:78f223d34f36 2886 #define CAU_XOR_CA4 CAU_XOR_CA_REG(CAU,4)
ethaderu 3:78f223d34f36 2887 #define CAU_XOR_CA5 CAU_XOR_CA_REG(CAU,5)
ethaderu 3:78f223d34f36 2888 #define CAU_XOR_CA6 CAU_XOR_CA_REG(CAU,6)
ethaderu 3:78f223d34f36 2889 #define CAU_XOR_CA7 CAU_XOR_CA_REG(CAU,7)
ethaderu 3:78f223d34f36 2890 #define CAU_XOR_CA8 CAU_XOR_CA_REG(CAU,8)
ethaderu 3:78f223d34f36 2891 #define CAU_ROTL_CASR CAU_ROTL_CASR_REG(CAU)
ethaderu 3:78f223d34f36 2892 #define CAU_ROTL_CAA CAU_ROTL_CAA_REG(CAU)
ethaderu 3:78f223d34f36 2893 #define CAU_ROTL_CA0 CAU_ROTL_CA_REG(CAU,0)
ethaderu 3:78f223d34f36 2894 #define CAU_ROTL_CA1 CAU_ROTL_CA_REG(CAU,1)
ethaderu 3:78f223d34f36 2895 #define CAU_ROTL_CA2 CAU_ROTL_CA_REG(CAU,2)
ethaderu 3:78f223d34f36 2896 #define CAU_ROTL_CA3 CAU_ROTL_CA_REG(CAU,3)
ethaderu 3:78f223d34f36 2897 #define CAU_ROTL_CA4 CAU_ROTL_CA_REG(CAU,4)
ethaderu 3:78f223d34f36 2898 #define CAU_ROTL_CA5 CAU_ROTL_CA_REG(CAU,5)
ethaderu 3:78f223d34f36 2899 #define CAU_ROTL_CA6 CAU_ROTL_CA_REG(CAU,6)
ethaderu 3:78f223d34f36 2900 #define CAU_ROTL_CA7 CAU_ROTL_CA_REG(CAU,7)
ethaderu 3:78f223d34f36 2901 #define CAU_ROTL_CA8 CAU_ROTL_CA_REG(CAU,8)
ethaderu 3:78f223d34f36 2902 #define CAU_AESC_CASR CAU_AESC_CASR_REG(CAU)
ethaderu 3:78f223d34f36 2903 #define CAU_AESC_CAA CAU_AESC_CAA_REG(CAU)
ethaderu 3:78f223d34f36 2904 #define CAU_AESC_CA0 CAU_AESC_CA_REG(CAU,0)
ethaderu 3:78f223d34f36 2905 #define CAU_AESC_CA1 CAU_AESC_CA_REG(CAU,1)
ethaderu 3:78f223d34f36 2906 #define CAU_AESC_CA2 CAU_AESC_CA_REG(CAU,2)
ethaderu 3:78f223d34f36 2907 #define CAU_AESC_CA3 CAU_AESC_CA_REG(CAU,3)
ethaderu 3:78f223d34f36 2908 #define CAU_AESC_CA4 CAU_AESC_CA_REG(CAU,4)
ethaderu 3:78f223d34f36 2909 #define CAU_AESC_CA5 CAU_AESC_CA_REG(CAU,5)
ethaderu 3:78f223d34f36 2910 #define CAU_AESC_CA6 CAU_AESC_CA_REG(CAU,6)
ethaderu 3:78f223d34f36 2911 #define CAU_AESC_CA7 CAU_AESC_CA_REG(CAU,7)
ethaderu 3:78f223d34f36 2912 #define CAU_AESC_CA8 CAU_AESC_CA_REG(CAU,8)
ethaderu 3:78f223d34f36 2913 #define CAU_AESIC_CASR CAU_AESIC_CASR_REG(CAU)
ethaderu 3:78f223d34f36 2914 #define CAU_AESIC_CAA CAU_AESIC_CAA_REG(CAU)
ethaderu 3:78f223d34f36 2915 #define CAU_AESIC_CA0 CAU_AESIC_CA_REG(CAU,0)
ethaderu 3:78f223d34f36 2916 #define CAU_AESIC_CA1 CAU_AESIC_CA_REG(CAU,1)
ethaderu 3:78f223d34f36 2917 #define CAU_AESIC_CA2 CAU_AESIC_CA_REG(CAU,2)
ethaderu 3:78f223d34f36 2918 #define CAU_AESIC_CA3 CAU_AESIC_CA_REG(CAU,3)
ethaderu 3:78f223d34f36 2919 #define CAU_AESIC_CA4 CAU_AESIC_CA_REG(CAU,4)
ethaderu 3:78f223d34f36 2920 #define CAU_AESIC_CA5 CAU_AESIC_CA_REG(CAU,5)
ethaderu 3:78f223d34f36 2921 #define CAU_AESIC_CA6 CAU_AESIC_CA_REG(CAU,6)
ethaderu 3:78f223d34f36 2922 #define CAU_AESIC_CA7 CAU_AESIC_CA_REG(CAU,7)
ethaderu 3:78f223d34f36 2923 #define CAU_AESIC_CA8 CAU_AESIC_CA_REG(CAU,8)
ethaderu 3:78f223d34f36 2924
ethaderu 3:78f223d34f36 2925 /* CAU - Register array accessors */
ethaderu 3:78f223d34f36 2926 #define CAU_DIRECT(index) CAU_DIRECT_REG(CAU,index)
ethaderu 3:78f223d34f36 2927 #define CAU_LDR_CA(index) CAU_LDR_CA_REG(CAU,index)
ethaderu 3:78f223d34f36 2928 #define CAU_STR_CA(index) CAU_STR_CA_REG(CAU,index)
ethaderu 3:78f223d34f36 2929 #define CAU_ADR_CA(index) CAU_ADR_CA_REG(CAU,index)
ethaderu 3:78f223d34f36 2930 #define CAU_RADR_CA(index) CAU_RADR_CA_REG(CAU,index)
ethaderu 3:78f223d34f36 2931 #define CAU_XOR_CA(index) CAU_XOR_CA_REG(CAU,index)
ethaderu 3:78f223d34f36 2932 #define CAU_ROTL_CA(index) CAU_ROTL_CA_REG(CAU,index)
ethaderu 3:78f223d34f36 2933 #define CAU_AESC_CA(index) CAU_AESC_CA_REG(CAU,index)
ethaderu 3:78f223d34f36 2934 #define CAU_AESIC_CA(index) CAU_AESIC_CA_REG(CAU,index)
ethaderu 3:78f223d34f36 2935
ethaderu 3:78f223d34f36 2936 /*!
ethaderu 3:78f223d34f36 2937 * @}
ethaderu 3:78f223d34f36 2938 */ /* end of group CAU_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 2939
ethaderu 3:78f223d34f36 2940
ethaderu 3:78f223d34f36 2941 /*!
ethaderu 3:78f223d34f36 2942 * @}
ethaderu 3:78f223d34f36 2943 */ /* end of group CAU_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 2944
ethaderu 3:78f223d34f36 2945
ethaderu 3:78f223d34f36 2946 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 2947 -- CMP Peripheral Access Layer
ethaderu 3:78f223d34f36 2948 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 2949
ethaderu 3:78f223d34f36 2950 /*!
ethaderu 3:78f223d34f36 2951 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
ethaderu 3:78f223d34f36 2952 * @{
ethaderu 3:78f223d34f36 2953 */
ethaderu 3:78f223d34f36 2954
ethaderu 3:78f223d34f36 2955 /** CMP - Register Layout Typedef */
ethaderu 3:78f223d34f36 2956 typedef struct {
ethaderu 3:78f223d34f36 2957 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
ethaderu 3:78f223d34f36 2958 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
ethaderu 3:78f223d34f36 2959 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
ethaderu 3:78f223d34f36 2960 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
ethaderu 3:78f223d34f36 2961 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
ethaderu 3:78f223d34f36 2962 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
ethaderu 3:78f223d34f36 2963 } CMP_Type, *CMP_MemMapPtr;
ethaderu 3:78f223d34f36 2964
ethaderu 3:78f223d34f36 2965 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 2966 -- CMP - Register accessor macros
ethaderu 3:78f223d34f36 2967 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 2968
ethaderu 3:78f223d34f36 2969 /*!
ethaderu 3:78f223d34f36 2970 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
ethaderu 3:78f223d34f36 2971 * @{
ethaderu 3:78f223d34f36 2972 */
ethaderu 3:78f223d34f36 2973
ethaderu 3:78f223d34f36 2974
ethaderu 3:78f223d34f36 2975 /* CMP - Register accessors */
ethaderu 3:78f223d34f36 2976 #define CMP_CR0_REG(base) ((base)->CR0)
ethaderu 3:78f223d34f36 2977 #define CMP_CR1_REG(base) ((base)->CR1)
ethaderu 3:78f223d34f36 2978 #define CMP_FPR_REG(base) ((base)->FPR)
ethaderu 3:78f223d34f36 2979 #define CMP_SCR_REG(base) ((base)->SCR)
ethaderu 3:78f223d34f36 2980 #define CMP_DACCR_REG(base) ((base)->DACCR)
ethaderu 3:78f223d34f36 2981 #define CMP_MUXCR_REG(base) ((base)->MUXCR)
ethaderu 3:78f223d34f36 2982
ethaderu 3:78f223d34f36 2983 /*!
ethaderu 3:78f223d34f36 2984 * @}
ethaderu 3:78f223d34f36 2985 */ /* end of group CMP_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 2986
ethaderu 3:78f223d34f36 2987
ethaderu 3:78f223d34f36 2988 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 2989 -- CMP Register Masks
ethaderu 3:78f223d34f36 2990 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 2991
ethaderu 3:78f223d34f36 2992 /*!
ethaderu 3:78f223d34f36 2993 * @addtogroup CMP_Register_Masks CMP Register Masks
ethaderu 3:78f223d34f36 2994 * @{
ethaderu 3:78f223d34f36 2995 */
ethaderu 3:78f223d34f36 2996
ethaderu 3:78f223d34f36 2997 /* CR0 Bit Fields */
ethaderu 3:78f223d34f36 2998 #define CMP_CR0_HYSTCTR_MASK 0x3u
ethaderu 3:78f223d34f36 2999 #define CMP_CR0_HYSTCTR_SHIFT 0
ethaderu 3:78f223d34f36 3000 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
ethaderu 3:78f223d34f36 3001 #define CMP_CR0_FILTER_CNT_MASK 0x70u
ethaderu 3:78f223d34f36 3002 #define CMP_CR0_FILTER_CNT_SHIFT 4
ethaderu 3:78f223d34f36 3003 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
ethaderu 3:78f223d34f36 3004 /* CR1 Bit Fields */
ethaderu 3:78f223d34f36 3005 #define CMP_CR1_EN_MASK 0x1u
ethaderu 3:78f223d34f36 3006 #define CMP_CR1_EN_SHIFT 0
ethaderu 3:78f223d34f36 3007 #define CMP_CR1_OPE_MASK 0x2u
ethaderu 3:78f223d34f36 3008 #define CMP_CR1_OPE_SHIFT 1
ethaderu 3:78f223d34f36 3009 #define CMP_CR1_COS_MASK 0x4u
ethaderu 3:78f223d34f36 3010 #define CMP_CR1_COS_SHIFT 2
ethaderu 3:78f223d34f36 3011 #define CMP_CR1_INV_MASK 0x8u
ethaderu 3:78f223d34f36 3012 #define CMP_CR1_INV_SHIFT 3
ethaderu 3:78f223d34f36 3013 #define CMP_CR1_PMODE_MASK 0x10u
ethaderu 3:78f223d34f36 3014 #define CMP_CR1_PMODE_SHIFT 4
ethaderu 3:78f223d34f36 3015 #define CMP_CR1_WE_MASK 0x40u
ethaderu 3:78f223d34f36 3016 #define CMP_CR1_WE_SHIFT 6
ethaderu 3:78f223d34f36 3017 #define CMP_CR1_SE_MASK 0x80u
ethaderu 3:78f223d34f36 3018 #define CMP_CR1_SE_SHIFT 7
ethaderu 3:78f223d34f36 3019 /* FPR Bit Fields */
ethaderu 3:78f223d34f36 3020 #define CMP_FPR_FILT_PER_MASK 0xFFu
ethaderu 3:78f223d34f36 3021 #define CMP_FPR_FILT_PER_SHIFT 0
ethaderu 3:78f223d34f36 3022 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
ethaderu 3:78f223d34f36 3023 /* SCR Bit Fields */
ethaderu 3:78f223d34f36 3024 #define CMP_SCR_COUT_MASK 0x1u
ethaderu 3:78f223d34f36 3025 #define CMP_SCR_COUT_SHIFT 0
ethaderu 3:78f223d34f36 3026 #define CMP_SCR_CFF_MASK 0x2u
ethaderu 3:78f223d34f36 3027 #define CMP_SCR_CFF_SHIFT 1
ethaderu 3:78f223d34f36 3028 #define CMP_SCR_CFR_MASK 0x4u
ethaderu 3:78f223d34f36 3029 #define CMP_SCR_CFR_SHIFT 2
ethaderu 3:78f223d34f36 3030 #define CMP_SCR_IEF_MASK 0x8u
ethaderu 3:78f223d34f36 3031 #define CMP_SCR_IEF_SHIFT 3
ethaderu 3:78f223d34f36 3032 #define CMP_SCR_IER_MASK 0x10u
ethaderu 3:78f223d34f36 3033 #define CMP_SCR_IER_SHIFT 4
ethaderu 3:78f223d34f36 3034 #define CMP_SCR_DMAEN_MASK 0x40u
ethaderu 3:78f223d34f36 3035 #define CMP_SCR_DMAEN_SHIFT 6
ethaderu 3:78f223d34f36 3036 /* DACCR Bit Fields */
ethaderu 3:78f223d34f36 3037 #define CMP_DACCR_VOSEL_MASK 0x3Fu
ethaderu 3:78f223d34f36 3038 #define CMP_DACCR_VOSEL_SHIFT 0
ethaderu 3:78f223d34f36 3039 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
ethaderu 3:78f223d34f36 3040 #define CMP_DACCR_VRSEL_MASK 0x40u
ethaderu 3:78f223d34f36 3041 #define CMP_DACCR_VRSEL_SHIFT 6
ethaderu 3:78f223d34f36 3042 #define CMP_DACCR_DACEN_MASK 0x80u
ethaderu 3:78f223d34f36 3043 #define CMP_DACCR_DACEN_SHIFT 7
ethaderu 3:78f223d34f36 3044 /* MUXCR Bit Fields */
ethaderu 3:78f223d34f36 3045 #define CMP_MUXCR_MSEL_MASK 0x7u
ethaderu 3:78f223d34f36 3046 #define CMP_MUXCR_MSEL_SHIFT 0
ethaderu 3:78f223d34f36 3047 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
ethaderu 3:78f223d34f36 3048 #define CMP_MUXCR_PSEL_MASK 0x38u
ethaderu 3:78f223d34f36 3049 #define CMP_MUXCR_PSEL_SHIFT 3
ethaderu 3:78f223d34f36 3050 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
ethaderu 3:78f223d34f36 3051 #define CMP_MUXCR_PSTM_MASK 0x80u
ethaderu 3:78f223d34f36 3052 #define CMP_MUXCR_PSTM_SHIFT 7
ethaderu 3:78f223d34f36 3053
ethaderu 3:78f223d34f36 3054 /*!
ethaderu 3:78f223d34f36 3055 * @}
ethaderu 3:78f223d34f36 3056 */ /* end of group CMP_Register_Masks */
ethaderu 3:78f223d34f36 3057
ethaderu 3:78f223d34f36 3058
ethaderu 3:78f223d34f36 3059 /* CMP - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 3060 /** Peripheral CMP0 base address */
ethaderu 3:78f223d34f36 3061 #define CMP0_BASE (0x40073000u)
ethaderu 3:78f223d34f36 3062 /** Peripheral CMP0 base pointer */
ethaderu 3:78f223d34f36 3063 #define CMP0 ((CMP_Type *)CMP0_BASE)
ethaderu 3:78f223d34f36 3064 #define CMP0_BASE_PTR (CMP0)
ethaderu 3:78f223d34f36 3065 /** Peripheral CMP1 base address */
ethaderu 3:78f223d34f36 3066 #define CMP1_BASE (0x40073008u)
ethaderu 3:78f223d34f36 3067 /** Peripheral CMP1 base pointer */
ethaderu 3:78f223d34f36 3068 #define CMP1 ((CMP_Type *)CMP1_BASE)
ethaderu 3:78f223d34f36 3069 #define CMP1_BASE_PTR (CMP1)
ethaderu 3:78f223d34f36 3070 /** Peripheral CMP2 base address */
ethaderu 3:78f223d34f36 3071 #define CMP2_BASE (0x40073010u)
ethaderu 3:78f223d34f36 3072 /** Peripheral CMP2 base pointer */
ethaderu 3:78f223d34f36 3073 #define CMP2 ((CMP_Type *)CMP2_BASE)
ethaderu 3:78f223d34f36 3074 #define CMP2_BASE_PTR (CMP2)
ethaderu 3:78f223d34f36 3075 /** Array initializer of CMP peripheral base addresses */
ethaderu 3:78f223d34f36 3076 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
ethaderu 3:78f223d34f36 3077 /** Array initializer of CMP peripheral base pointers */
ethaderu 3:78f223d34f36 3078 #define CMP_BASE_PTRS { CMP0, CMP1, CMP2 }
ethaderu 3:78f223d34f36 3079 /** Interrupt vectors for the CMP peripheral type */
ethaderu 3:78f223d34f36 3080 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
ethaderu 3:78f223d34f36 3081
ethaderu 3:78f223d34f36 3082 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 3083 -- CMP - Register accessor macros
ethaderu 3:78f223d34f36 3084 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 3085
ethaderu 3:78f223d34f36 3086 /*!
ethaderu 3:78f223d34f36 3087 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
ethaderu 3:78f223d34f36 3088 * @{
ethaderu 3:78f223d34f36 3089 */
ethaderu 3:78f223d34f36 3090
ethaderu 3:78f223d34f36 3091
ethaderu 3:78f223d34f36 3092 /* CMP - Register instance definitions */
ethaderu 3:78f223d34f36 3093 /* CMP0 */
ethaderu 3:78f223d34f36 3094 #define CMP0_CR0 CMP_CR0_REG(CMP0)
ethaderu 3:78f223d34f36 3095 #define CMP0_CR1 CMP_CR1_REG(CMP0)
ethaderu 3:78f223d34f36 3096 #define CMP0_FPR CMP_FPR_REG(CMP0)
ethaderu 3:78f223d34f36 3097 #define CMP0_SCR CMP_SCR_REG(CMP0)
ethaderu 3:78f223d34f36 3098 #define CMP0_DACCR CMP_DACCR_REG(CMP0)
ethaderu 3:78f223d34f36 3099 #define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
ethaderu 3:78f223d34f36 3100 /* CMP1 */
ethaderu 3:78f223d34f36 3101 #define CMP1_CR0 CMP_CR0_REG(CMP1)
ethaderu 3:78f223d34f36 3102 #define CMP1_CR1 CMP_CR1_REG(CMP1)
ethaderu 3:78f223d34f36 3103 #define CMP1_FPR CMP_FPR_REG(CMP1)
ethaderu 3:78f223d34f36 3104 #define CMP1_SCR CMP_SCR_REG(CMP1)
ethaderu 3:78f223d34f36 3105 #define CMP1_DACCR CMP_DACCR_REG(CMP1)
ethaderu 3:78f223d34f36 3106 #define CMP1_MUXCR CMP_MUXCR_REG(CMP1)
ethaderu 3:78f223d34f36 3107 /* CMP2 */
ethaderu 3:78f223d34f36 3108 #define CMP2_CR0 CMP_CR0_REG(CMP2)
ethaderu 3:78f223d34f36 3109 #define CMP2_CR1 CMP_CR1_REG(CMP2)
ethaderu 3:78f223d34f36 3110 #define CMP2_FPR CMP_FPR_REG(CMP2)
ethaderu 3:78f223d34f36 3111 #define CMP2_SCR CMP_SCR_REG(CMP2)
ethaderu 3:78f223d34f36 3112 #define CMP2_DACCR CMP_DACCR_REG(CMP2)
ethaderu 3:78f223d34f36 3113 #define CMP2_MUXCR CMP_MUXCR_REG(CMP2)
ethaderu 3:78f223d34f36 3114
ethaderu 3:78f223d34f36 3115 /*!
ethaderu 3:78f223d34f36 3116 * @}
ethaderu 3:78f223d34f36 3117 */ /* end of group CMP_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 3118
ethaderu 3:78f223d34f36 3119
ethaderu 3:78f223d34f36 3120 /*!
ethaderu 3:78f223d34f36 3121 * @}
ethaderu 3:78f223d34f36 3122 */ /* end of group CMP_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 3123
ethaderu 3:78f223d34f36 3124
ethaderu 3:78f223d34f36 3125 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 3126 -- CMT Peripheral Access Layer
ethaderu 3:78f223d34f36 3127 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 3128
ethaderu 3:78f223d34f36 3129 /*!
ethaderu 3:78f223d34f36 3130 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
ethaderu 3:78f223d34f36 3131 * @{
ethaderu 3:78f223d34f36 3132 */
ethaderu 3:78f223d34f36 3133
ethaderu 3:78f223d34f36 3134 /** CMT - Register Layout Typedef */
ethaderu 3:78f223d34f36 3135 typedef struct {
ethaderu 3:78f223d34f36 3136 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
ethaderu 3:78f223d34f36 3137 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
ethaderu 3:78f223d34f36 3138 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
ethaderu 3:78f223d34f36 3139 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
ethaderu 3:78f223d34f36 3140 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
ethaderu 3:78f223d34f36 3141 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
ethaderu 3:78f223d34f36 3142 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
ethaderu 3:78f223d34f36 3143 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
ethaderu 3:78f223d34f36 3144 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
ethaderu 3:78f223d34f36 3145 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
ethaderu 3:78f223d34f36 3146 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
ethaderu 3:78f223d34f36 3147 __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
ethaderu 3:78f223d34f36 3148 } CMT_Type, *CMT_MemMapPtr;
ethaderu 3:78f223d34f36 3149
ethaderu 3:78f223d34f36 3150 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 3151 -- CMT - Register accessor macros
ethaderu 3:78f223d34f36 3152 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 3153
ethaderu 3:78f223d34f36 3154 /*!
ethaderu 3:78f223d34f36 3155 * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
ethaderu 3:78f223d34f36 3156 * @{
ethaderu 3:78f223d34f36 3157 */
ethaderu 3:78f223d34f36 3158
ethaderu 3:78f223d34f36 3159
ethaderu 3:78f223d34f36 3160 /* CMT - Register accessors */
ethaderu 3:78f223d34f36 3161 #define CMT_CGH1_REG(base) ((base)->CGH1)
ethaderu 3:78f223d34f36 3162 #define CMT_CGL1_REG(base) ((base)->CGL1)
ethaderu 3:78f223d34f36 3163 #define CMT_CGH2_REG(base) ((base)->CGH2)
ethaderu 3:78f223d34f36 3164 #define CMT_CGL2_REG(base) ((base)->CGL2)
ethaderu 3:78f223d34f36 3165 #define CMT_OC_REG(base) ((base)->OC)
ethaderu 3:78f223d34f36 3166 #define CMT_MSC_REG(base) ((base)->MSC)
ethaderu 3:78f223d34f36 3167 #define CMT_CMD1_REG(base) ((base)->CMD1)
ethaderu 3:78f223d34f36 3168 #define CMT_CMD2_REG(base) ((base)->CMD2)
ethaderu 3:78f223d34f36 3169 #define CMT_CMD3_REG(base) ((base)->CMD3)
ethaderu 3:78f223d34f36 3170 #define CMT_CMD4_REG(base) ((base)->CMD4)
ethaderu 3:78f223d34f36 3171 #define CMT_PPS_REG(base) ((base)->PPS)
ethaderu 3:78f223d34f36 3172 #define CMT_DMA_REG(base) ((base)->DMA)
ethaderu 3:78f223d34f36 3173
ethaderu 3:78f223d34f36 3174 /*!
ethaderu 3:78f223d34f36 3175 * @}
ethaderu 3:78f223d34f36 3176 */ /* end of group CMT_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 3177
ethaderu 3:78f223d34f36 3178
ethaderu 3:78f223d34f36 3179 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 3180 -- CMT Register Masks
ethaderu 3:78f223d34f36 3181 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 3182
ethaderu 3:78f223d34f36 3183 /*!
ethaderu 3:78f223d34f36 3184 * @addtogroup CMT_Register_Masks CMT Register Masks
ethaderu 3:78f223d34f36 3185 * @{
ethaderu 3:78f223d34f36 3186 */
ethaderu 3:78f223d34f36 3187
ethaderu 3:78f223d34f36 3188 /* CGH1 Bit Fields */
ethaderu 3:78f223d34f36 3189 #define CMT_CGH1_PH_MASK 0xFFu
ethaderu 3:78f223d34f36 3190 #define CMT_CGH1_PH_SHIFT 0
ethaderu 3:78f223d34f36 3191 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
ethaderu 3:78f223d34f36 3192 /* CGL1 Bit Fields */
ethaderu 3:78f223d34f36 3193 #define CMT_CGL1_PL_MASK 0xFFu
ethaderu 3:78f223d34f36 3194 #define CMT_CGL1_PL_SHIFT 0
ethaderu 3:78f223d34f36 3195 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
ethaderu 3:78f223d34f36 3196 /* CGH2 Bit Fields */
ethaderu 3:78f223d34f36 3197 #define CMT_CGH2_SH_MASK 0xFFu
ethaderu 3:78f223d34f36 3198 #define CMT_CGH2_SH_SHIFT 0
ethaderu 3:78f223d34f36 3199 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
ethaderu 3:78f223d34f36 3200 /* CGL2 Bit Fields */
ethaderu 3:78f223d34f36 3201 #define CMT_CGL2_SL_MASK 0xFFu
ethaderu 3:78f223d34f36 3202 #define CMT_CGL2_SL_SHIFT 0
ethaderu 3:78f223d34f36 3203 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
ethaderu 3:78f223d34f36 3204 /* OC Bit Fields */
ethaderu 3:78f223d34f36 3205 #define CMT_OC_IROPEN_MASK 0x20u
ethaderu 3:78f223d34f36 3206 #define CMT_OC_IROPEN_SHIFT 5
ethaderu 3:78f223d34f36 3207 #define CMT_OC_CMTPOL_MASK 0x40u
ethaderu 3:78f223d34f36 3208 #define CMT_OC_CMTPOL_SHIFT 6
ethaderu 3:78f223d34f36 3209 #define CMT_OC_IROL_MASK 0x80u
ethaderu 3:78f223d34f36 3210 #define CMT_OC_IROL_SHIFT 7
ethaderu 3:78f223d34f36 3211 /* MSC Bit Fields */
ethaderu 3:78f223d34f36 3212 #define CMT_MSC_MCGEN_MASK 0x1u
ethaderu 3:78f223d34f36 3213 #define CMT_MSC_MCGEN_SHIFT 0
ethaderu 3:78f223d34f36 3214 #define CMT_MSC_EOCIE_MASK 0x2u
ethaderu 3:78f223d34f36 3215 #define CMT_MSC_EOCIE_SHIFT 1
ethaderu 3:78f223d34f36 3216 #define CMT_MSC_FSK_MASK 0x4u
ethaderu 3:78f223d34f36 3217 #define CMT_MSC_FSK_SHIFT 2
ethaderu 3:78f223d34f36 3218 #define CMT_MSC_BASE_MASK 0x8u
ethaderu 3:78f223d34f36 3219 #define CMT_MSC_BASE_SHIFT 3
ethaderu 3:78f223d34f36 3220 #define CMT_MSC_EXSPC_MASK 0x10u
ethaderu 3:78f223d34f36 3221 #define CMT_MSC_EXSPC_SHIFT 4
ethaderu 3:78f223d34f36 3222 #define CMT_MSC_CMTDIV_MASK 0x60u
ethaderu 3:78f223d34f36 3223 #define CMT_MSC_CMTDIV_SHIFT 5
ethaderu 3:78f223d34f36 3224 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
ethaderu 3:78f223d34f36 3225 #define CMT_MSC_EOCF_MASK 0x80u
ethaderu 3:78f223d34f36 3226 #define CMT_MSC_EOCF_SHIFT 7
ethaderu 3:78f223d34f36 3227 /* CMD1 Bit Fields */
ethaderu 3:78f223d34f36 3228 #define CMT_CMD1_MB_MASK 0xFFu
ethaderu 3:78f223d34f36 3229 #define CMT_CMD1_MB_SHIFT 0
ethaderu 3:78f223d34f36 3230 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
ethaderu 3:78f223d34f36 3231 /* CMD2 Bit Fields */
ethaderu 3:78f223d34f36 3232 #define CMT_CMD2_MB_MASK 0xFFu
ethaderu 3:78f223d34f36 3233 #define CMT_CMD2_MB_SHIFT 0
ethaderu 3:78f223d34f36 3234 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
ethaderu 3:78f223d34f36 3235 /* CMD3 Bit Fields */
ethaderu 3:78f223d34f36 3236 #define CMT_CMD3_SB_MASK 0xFFu
ethaderu 3:78f223d34f36 3237 #define CMT_CMD3_SB_SHIFT 0
ethaderu 3:78f223d34f36 3238 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
ethaderu 3:78f223d34f36 3239 /* CMD4 Bit Fields */
ethaderu 3:78f223d34f36 3240 #define CMT_CMD4_SB_MASK 0xFFu
ethaderu 3:78f223d34f36 3241 #define CMT_CMD4_SB_SHIFT 0
ethaderu 3:78f223d34f36 3242 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
ethaderu 3:78f223d34f36 3243 /* PPS Bit Fields */
ethaderu 3:78f223d34f36 3244 #define CMT_PPS_PPSDIV_MASK 0xFu
ethaderu 3:78f223d34f36 3245 #define CMT_PPS_PPSDIV_SHIFT 0
ethaderu 3:78f223d34f36 3246 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
ethaderu 3:78f223d34f36 3247 /* DMA Bit Fields */
ethaderu 3:78f223d34f36 3248 #define CMT_DMA_DMA_MASK 0x1u
ethaderu 3:78f223d34f36 3249 #define CMT_DMA_DMA_SHIFT 0
ethaderu 3:78f223d34f36 3250
ethaderu 3:78f223d34f36 3251 /*!
ethaderu 3:78f223d34f36 3252 * @}
ethaderu 3:78f223d34f36 3253 */ /* end of group CMT_Register_Masks */
ethaderu 3:78f223d34f36 3254
ethaderu 3:78f223d34f36 3255
ethaderu 3:78f223d34f36 3256 /* CMT - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 3257 /** Peripheral CMT base address */
ethaderu 3:78f223d34f36 3258 #define CMT_BASE (0x40062000u)
ethaderu 3:78f223d34f36 3259 /** Peripheral CMT base pointer */
ethaderu 3:78f223d34f36 3260 #define CMT ((CMT_Type *)CMT_BASE)
ethaderu 3:78f223d34f36 3261 #define CMT_BASE_PTR (CMT)
ethaderu 3:78f223d34f36 3262 /** Array initializer of CMT peripheral base addresses */
ethaderu 3:78f223d34f36 3263 #define CMT_BASE_ADDRS { CMT_BASE }
ethaderu 3:78f223d34f36 3264 /** Array initializer of CMT peripheral base pointers */
ethaderu 3:78f223d34f36 3265 #define CMT_BASE_PTRS { CMT }
ethaderu 3:78f223d34f36 3266 /** Interrupt vectors for the CMT peripheral type */
ethaderu 3:78f223d34f36 3267 #define CMT_IRQS { CMT_IRQn }
ethaderu 3:78f223d34f36 3268
ethaderu 3:78f223d34f36 3269 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 3270 -- CMT - Register accessor macros
ethaderu 3:78f223d34f36 3271 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 3272
ethaderu 3:78f223d34f36 3273 /*!
ethaderu 3:78f223d34f36 3274 * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
ethaderu 3:78f223d34f36 3275 * @{
ethaderu 3:78f223d34f36 3276 */
ethaderu 3:78f223d34f36 3277
ethaderu 3:78f223d34f36 3278
ethaderu 3:78f223d34f36 3279 /* CMT - Register instance definitions */
ethaderu 3:78f223d34f36 3280 /* CMT */
ethaderu 3:78f223d34f36 3281 #define CMT_CGH1 CMT_CGH1_REG(CMT)
ethaderu 3:78f223d34f36 3282 #define CMT_CGL1 CMT_CGL1_REG(CMT)
ethaderu 3:78f223d34f36 3283 #define CMT_CGH2 CMT_CGH2_REG(CMT)
ethaderu 3:78f223d34f36 3284 #define CMT_CGL2 CMT_CGL2_REG(CMT)
ethaderu 3:78f223d34f36 3285 #define CMT_OC CMT_OC_REG(CMT)
ethaderu 3:78f223d34f36 3286 #define CMT_MSC CMT_MSC_REG(CMT)
ethaderu 3:78f223d34f36 3287 #define CMT_CMD1 CMT_CMD1_REG(CMT)
ethaderu 3:78f223d34f36 3288 #define CMT_CMD2 CMT_CMD2_REG(CMT)
ethaderu 3:78f223d34f36 3289 #define CMT_CMD3 CMT_CMD3_REG(CMT)
ethaderu 3:78f223d34f36 3290 #define CMT_CMD4 CMT_CMD4_REG(CMT)
ethaderu 3:78f223d34f36 3291 #define CMT_PPS CMT_PPS_REG(CMT)
ethaderu 3:78f223d34f36 3292 #define CMT_DMA CMT_DMA_REG(CMT)
ethaderu 3:78f223d34f36 3293
ethaderu 3:78f223d34f36 3294 /*!
ethaderu 3:78f223d34f36 3295 * @}
ethaderu 3:78f223d34f36 3296 */ /* end of group CMT_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 3297
ethaderu 3:78f223d34f36 3298
ethaderu 3:78f223d34f36 3299 /*!
ethaderu 3:78f223d34f36 3300 * @}
ethaderu 3:78f223d34f36 3301 */ /* end of group CMT_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 3302
ethaderu 3:78f223d34f36 3303
ethaderu 3:78f223d34f36 3304 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 3305 -- CRC Peripheral Access Layer
ethaderu 3:78f223d34f36 3306 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 3307
ethaderu 3:78f223d34f36 3308 /*!
ethaderu 3:78f223d34f36 3309 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
ethaderu 3:78f223d34f36 3310 * @{
ethaderu 3:78f223d34f36 3311 */
ethaderu 3:78f223d34f36 3312
ethaderu 3:78f223d34f36 3313 /** CRC - Register Layout Typedef */
ethaderu 3:78f223d34f36 3314 typedef struct {
ethaderu 3:78f223d34f36 3315 union { /* offset: 0x0 */
ethaderu 3:78f223d34f36 3316 struct { /* offset: 0x0 */
ethaderu 3:78f223d34f36 3317 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
ethaderu 3:78f223d34f36 3318 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
ethaderu 3:78f223d34f36 3319 } ACCESS16BIT;
ethaderu 3:78f223d34f36 3320 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
ethaderu 3:78f223d34f36 3321 struct { /* offset: 0x0 */
ethaderu 3:78f223d34f36 3322 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
ethaderu 3:78f223d34f36 3323 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
ethaderu 3:78f223d34f36 3324 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
ethaderu 3:78f223d34f36 3325 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
ethaderu 3:78f223d34f36 3326 } ACCESS8BIT;
ethaderu 3:78f223d34f36 3327 };
ethaderu 3:78f223d34f36 3328 union { /* offset: 0x4 */
ethaderu 3:78f223d34f36 3329 struct { /* offset: 0x4 */
ethaderu 3:78f223d34f36 3330 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
ethaderu 3:78f223d34f36 3331 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
ethaderu 3:78f223d34f36 3332 } GPOLY_ACCESS16BIT;
ethaderu 3:78f223d34f36 3333 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
ethaderu 3:78f223d34f36 3334 struct { /* offset: 0x4 */
ethaderu 3:78f223d34f36 3335 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
ethaderu 3:78f223d34f36 3336 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
ethaderu 3:78f223d34f36 3337 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
ethaderu 3:78f223d34f36 3338 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
ethaderu 3:78f223d34f36 3339 } GPOLY_ACCESS8BIT;
ethaderu 3:78f223d34f36 3340 };
ethaderu 3:78f223d34f36 3341 union { /* offset: 0x8 */
ethaderu 3:78f223d34f36 3342 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
ethaderu 3:78f223d34f36 3343 struct { /* offset: 0x8 */
ethaderu 3:78f223d34f36 3344 uint8_t RESERVED_0[3];
ethaderu 3:78f223d34f36 3345 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
ethaderu 3:78f223d34f36 3346 } CTRL_ACCESS8BIT;
ethaderu 3:78f223d34f36 3347 };
ethaderu 3:78f223d34f36 3348 } CRC_Type, *CRC_MemMapPtr;
ethaderu 3:78f223d34f36 3349
ethaderu 3:78f223d34f36 3350 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 3351 -- CRC - Register accessor macros
ethaderu 3:78f223d34f36 3352 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 3353
ethaderu 3:78f223d34f36 3354 /*!
ethaderu 3:78f223d34f36 3355 * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
ethaderu 3:78f223d34f36 3356 * @{
ethaderu 3:78f223d34f36 3357 */
ethaderu 3:78f223d34f36 3358
ethaderu 3:78f223d34f36 3359
ethaderu 3:78f223d34f36 3360 /* CRC - Register accessors */
ethaderu 3:78f223d34f36 3361 #define CRC_DATAL_REG(base) ((base)->ACCESS16BIT.DATAL)
ethaderu 3:78f223d34f36 3362 #define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH)
ethaderu 3:78f223d34f36 3363 #define CRC_DATA_REG(base) ((base)->DATA)
ethaderu 3:78f223d34f36 3364 #define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL)
ethaderu 3:78f223d34f36 3365 #define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU)
ethaderu 3:78f223d34f36 3366 #define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL)
ethaderu 3:78f223d34f36 3367 #define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU)
ethaderu 3:78f223d34f36 3368 #define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
ethaderu 3:78f223d34f36 3369 #define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
ethaderu 3:78f223d34f36 3370 #define CRC_GPOLY_REG(base) ((base)->GPOLY)
ethaderu 3:78f223d34f36 3371 #define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
ethaderu 3:78f223d34f36 3372 #define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
ethaderu 3:78f223d34f36 3373 #define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
ethaderu 3:78f223d34f36 3374 #define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
ethaderu 3:78f223d34f36 3375 #define CRC_CTRL_REG(base) ((base)->CTRL)
ethaderu 3:78f223d34f36 3376 #define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
ethaderu 3:78f223d34f36 3377
ethaderu 3:78f223d34f36 3378 /*!
ethaderu 3:78f223d34f36 3379 * @}
ethaderu 3:78f223d34f36 3380 */ /* end of group CRC_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 3381
ethaderu 3:78f223d34f36 3382
ethaderu 3:78f223d34f36 3383 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 3384 -- CRC Register Masks
ethaderu 3:78f223d34f36 3385 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 3386
ethaderu 3:78f223d34f36 3387 /*!
ethaderu 3:78f223d34f36 3388 * @addtogroup CRC_Register_Masks CRC Register Masks
ethaderu 3:78f223d34f36 3389 * @{
ethaderu 3:78f223d34f36 3390 */
ethaderu 3:78f223d34f36 3391
ethaderu 3:78f223d34f36 3392 /* DATAL Bit Fields */
ethaderu 3:78f223d34f36 3393 #define CRC_DATAL_DATAL_MASK 0xFFFFu
ethaderu 3:78f223d34f36 3394 #define CRC_DATAL_DATAL_SHIFT 0
ethaderu 3:78f223d34f36 3395 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
ethaderu 3:78f223d34f36 3396 /* DATAH Bit Fields */
ethaderu 3:78f223d34f36 3397 #define CRC_DATAH_DATAH_MASK 0xFFFFu
ethaderu 3:78f223d34f36 3398 #define CRC_DATAH_DATAH_SHIFT 0
ethaderu 3:78f223d34f36 3399 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
ethaderu 3:78f223d34f36 3400 /* DATA Bit Fields */
ethaderu 3:78f223d34f36 3401 #define CRC_DATA_LL_MASK 0xFFu
ethaderu 3:78f223d34f36 3402 #define CRC_DATA_LL_SHIFT 0
ethaderu 3:78f223d34f36 3403 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
ethaderu 3:78f223d34f36 3404 #define CRC_DATA_LU_MASK 0xFF00u
ethaderu 3:78f223d34f36 3405 #define CRC_DATA_LU_SHIFT 8
ethaderu 3:78f223d34f36 3406 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
ethaderu 3:78f223d34f36 3407 #define CRC_DATA_HL_MASK 0xFF0000u
ethaderu 3:78f223d34f36 3408 #define CRC_DATA_HL_SHIFT 16
ethaderu 3:78f223d34f36 3409 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
ethaderu 3:78f223d34f36 3410 #define CRC_DATA_HU_MASK 0xFF000000u
ethaderu 3:78f223d34f36 3411 #define CRC_DATA_HU_SHIFT 24
ethaderu 3:78f223d34f36 3412 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
ethaderu 3:78f223d34f36 3413 /* DATALL Bit Fields */
ethaderu 3:78f223d34f36 3414 #define CRC_DATALL_DATALL_MASK 0xFFu
ethaderu 3:78f223d34f36 3415 #define CRC_DATALL_DATALL_SHIFT 0
ethaderu 3:78f223d34f36 3416 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
ethaderu 3:78f223d34f36 3417 /* DATALU Bit Fields */
ethaderu 3:78f223d34f36 3418 #define CRC_DATALU_DATALU_MASK 0xFFu
ethaderu 3:78f223d34f36 3419 #define CRC_DATALU_DATALU_SHIFT 0
ethaderu 3:78f223d34f36 3420 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
ethaderu 3:78f223d34f36 3421 /* DATAHL Bit Fields */
ethaderu 3:78f223d34f36 3422 #define CRC_DATAHL_DATAHL_MASK 0xFFu
ethaderu 3:78f223d34f36 3423 #define CRC_DATAHL_DATAHL_SHIFT 0
ethaderu 3:78f223d34f36 3424 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
ethaderu 3:78f223d34f36 3425 /* DATAHU Bit Fields */
ethaderu 3:78f223d34f36 3426 #define CRC_DATAHU_DATAHU_MASK 0xFFu
ethaderu 3:78f223d34f36 3427 #define CRC_DATAHU_DATAHU_SHIFT 0
ethaderu 3:78f223d34f36 3428 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
ethaderu 3:78f223d34f36 3429 /* GPOLYL Bit Fields */
ethaderu 3:78f223d34f36 3430 #define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
ethaderu 3:78f223d34f36 3431 #define CRC_GPOLYL_GPOLYL_SHIFT 0
ethaderu 3:78f223d34f36 3432 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
ethaderu 3:78f223d34f36 3433 /* GPOLYH Bit Fields */
ethaderu 3:78f223d34f36 3434 #define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
ethaderu 3:78f223d34f36 3435 #define CRC_GPOLYH_GPOLYH_SHIFT 0
ethaderu 3:78f223d34f36 3436 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
ethaderu 3:78f223d34f36 3437 /* GPOLY Bit Fields */
ethaderu 3:78f223d34f36 3438 #define CRC_GPOLY_LOW_MASK 0xFFFFu
ethaderu 3:78f223d34f36 3439 #define CRC_GPOLY_LOW_SHIFT 0
ethaderu 3:78f223d34f36 3440 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
ethaderu 3:78f223d34f36 3441 #define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
ethaderu 3:78f223d34f36 3442 #define CRC_GPOLY_HIGH_SHIFT 16
ethaderu 3:78f223d34f36 3443 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
ethaderu 3:78f223d34f36 3444 /* GPOLYLL Bit Fields */
ethaderu 3:78f223d34f36 3445 #define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
ethaderu 3:78f223d34f36 3446 #define CRC_GPOLYLL_GPOLYLL_SHIFT 0
ethaderu 3:78f223d34f36 3447 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
ethaderu 3:78f223d34f36 3448 /* GPOLYLU Bit Fields */
ethaderu 3:78f223d34f36 3449 #define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
ethaderu 3:78f223d34f36 3450 #define CRC_GPOLYLU_GPOLYLU_SHIFT 0
ethaderu 3:78f223d34f36 3451 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
ethaderu 3:78f223d34f36 3452 /* GPOLYHL Bit Fields */
ethaderu 3:78f223d34f36 3453 #define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
ethaderu 3:78f223d34f36 3454 #define CRC_GPOLYHL_GPOLYHL_SHIFT 0
ethaderu 3:78f223d34f36 3455 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
ethaderu 3:78f223d34f36 3456 /* GPOLYHU Bit Fields */
ethaderu 3:78f223d34f36 3457 #define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
ethaderu 3:78f223d34f36 3458 #define CRC_GPOLYHU_GPOLYHU_SHIFT 0
ethaderu 3:78f223d34f36 3459 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
ethaderu 3:78f223d34f36 3460 /* CTRL Bit Fields */
ethaderu 3:78f223d34f36 3461 #define CRC_CTRL_TCRC_MASK 0x1000000u
ethaderu 3:78f223d34f36 3462 #define CRC_CTRL_TCRC_SHIFT 24
ethaderu 3:78f223d34f36 3463 #define CRC_CTRL_WAS_MASK 0x2000000u
ethaderu 3:78f223d34f36 3464 #define CRC_CTRL_WAS_SHIFT 25
ethaderu 3:78f223d34f36 3465 #define CRC_CTRL_FXOR_MASK 0x4000000u
ethaderu 3:78f223d34f36 3466 #define CRC_CTRL_FXOR_SHIFT 26
ethaderu 3:78f223d34f36 3467 #define CRC_CTRL_TOTR_MASK 0x30000000u
ethaderu 3:78f223d34f36 3468 #define CRC_CTRL_TOTR_SHIFT 28
ethaderu 3:78f223d34f36 3469 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
ethaderu 3:78f223d34f36 3470 #define CRC_CTRL_TOT_MASK 0xC0000000u
ethaderu 3:78f223d34f36 3471 #define CRC_CTRL_TOT_SHIFT 30
ethaderu 3:78f223d34f36 3472 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
ethaderu 3:78f223d34f36 3473 /* CTRLHU Bit Fields */
ethaderu 3:78f223d34f36 3474 #define CRC_CTRLHU_TCRC_MASK 0x1u
ethaderu 3:78f223d34f36 3475 #define CRC_CTRLHU_TCRC_SHIFT 0
ethaderu 3:78f223d34f36 3476 #define CRC_CTRLHU_WAS_MASK 0x2u
ethaderu 3:78f223d34f36 3477 #define CRC_CTRLHU_WAS_SHIFT 1
ethaderu 3:78f223d34f36 3478 #define CRC_CTRLHU_FXOR_MASK 0x4u
ethaderu 3:78f223d34f36 3479 #define CRC_CTRLHU_FXOR_SHIFT 2
ethaderu 3:78f223d34f36 3480 #define CRC_CTRLHU_TOTR_MASK 0x30u
ethaderu 3:78f223d34f36 3481 #define CRC_CTRLHU_TOTR_SHIFT 4
ethaderu 3:78f223d34f36 3482 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
ethaderu 3:78f223d34f36 3483 #define CRC_CTRLHU_TOT_MASK 0xC0u
ethaderu 3:78f223d34f36 3484 #define CRC_CTRLHU_TOT_SHIFT 6
ethaderu 3:78f223d34f36 3485 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
ethaderu 3:78f223d34f36 3486
ethaderu 3:78f223d34f36 3487 /*!
ethaderu 3:78f223d34f36 3488 * @}
ethaderu 3:78f223d34f36 3489 */ /* end of group CRC_Register_Masks */
ethaderu 3:78f223d34f36 3490
ethaderu 3:78f223d34f36 3491
ethaderu 3:78f223d34f36 3492 /* CRC - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 3493 /** Peripheral CRC base address */
ethaderu 3:78f223d34f36 3494 #define CRC_BASE (0x40032000u)
ethaderu 3:78f223d34f36 3495 /** Peripheral CRC base pointer */
ethaderu 3:78f223d34f36 3496 #define CRC0 ((CRC_Type *)CRC_BASE)
ethaderu 3:78f223d34f36 3497 #define CRC_BASE_PTR (CRC0)
ethaderu 3:78f223d34f36 3498 /** Array initializer of CRC peripheral base addresses */
ethaderu 3:78f223d34f36 3499 #define CRC_BASE_ADDRS { CRC_BASE }
ethaderu 3:78f223d34f36 3500 /** Array initializer of CRC peripheral base pointers */
ethaderu 3:78f223d34f36 3501 #define CRC_BASE_PTRS { CRC0 }
ethaderu 3:78f223d34f36 3502
ethaderu 3:78f223d34f36 3503 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 3504 -- CRC - Register accessor macros
ethaderu 3:78f223d34f36 3505 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 3506
ethaderu 3:78f223d34f36 3507 /*!
ethaderu 3:78f223d34f36 3508 * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
ethaderu 3:78f223d34f36 3509 * @{
ethaderu 3:78f223d34f36 3510 */
ethaderu 3:78f223d34f36 3511
ethaderu 3:78f223d34f36 3512
ethaderu 3:78f223d34f36 3513 /* CRC - Register instance definitions */
ethaderu 3:78f223d34f36 3514 /* CRC */
ethaderu 3:78f223d34f36 3515 #define CRC_DATA CRC_DATA_REG(CRC0)
ethaderu 3:78f223d34f36 3516 #define CRC_DATAL CRC_DATAL_REG(CRC0)
ethaderu 3:78f223d34f36 3517 #define CRC_DATALL CRC_DATALL_REG(CRC0)
ethaderu 3:78f223d34f36 3518 #define CRC_DATALU CRC_DATALU_REG(CRC0)
ethaderu 3:78f223d34f36 3519 #define CRC_DATAH CRC_DATAH_REG(CRC0)
ethaderu 3:78f223d34f36 3520 #define CRC_DATAHL CRC_DATAHL_REG(CRC0)
ethaderu 3:78f223d34f36 3521 #define CRC_DATAHU CRC_DATAHU_REG(CRC0)
ethaderu 3:78f223d34f36 3522 #define CRC_GPOLY CRC_GPOLY_REG(CRC0)
ethaderu 3:78f223d34f36 3523 #define CRC_GPOLYL CRC_GPOLYL_REG(CRC0)
ethaderu 3:78f223d34f36 3524 #define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC0)
ethaderu 3:78f223d34f36 3525 #define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC0)
ethaderu 3:78f223d34f36 3526 #define CRC_GPOLYH CRC_GPOLYH_REG(CRC0)
ethaderu 3:78f223d34f36 3527 #define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC0)
ethaderu 3:78f223d34f36 3528 #define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC0)
ethaderu 3:78f223d34f36 3529 #define CRC_CTRL CRC_CTRL_REG(CRC0)
ethaderu 3:78f223d34f36 3530 #define CRC_CTRLHU CRC_CTRLHU_REG(CRC0)
ethaderu 3:78f223d34f36 3531
ethaderu 3:78f223d34f36 3532 /*!
ethaderu 3:78f223d34f36 3533 * @}
ethaderu 3:78f223d34f36 3534 */ /* end of group CRC_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 3535
ethaderu 3:78f223d34f36 3536
ethaderu 3:78f223d34f36 3537 /*!
ethaderu 3:78f223d34f36 3538 * @}
ethaderu 3:78f223d34f36 3539 */ /* end of group CRC_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 3540
ethaderu 3:78f223d34f36 3541
ethaderu 3:78f223d34f36 3542 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 3543 -- DAC Peripheral Access Layer
ethaderu 3:78f223d34f36 3544 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 3545
ethaderu 3:78f223d34f36 3546 /*!
ethaderu 3:78f223d34f36 3547 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
ethaderu 3:78f223d34f36 3548 * @{
ethaderu 3:78f223d34f36 3549 */
ethaderu 3:78f223d34f36 3550
ethaderu 3:78f223d34f36 3551 /** DAC - Register Layout Typedef */
ethaderu 3:78f223d34f36 3552 typedef struct {
ethaderu 3:78f223d34f36 3553 struct { /* offset: 0x0, array step: 0x2 */
ethaderu 3:78f223d34f36 3554 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
ethaderu 3:78f223d34f36 3555 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
ethaderu 3:78f223d34f36 3556 } DAT[16];
ethaderu 3:78f223d34f36 3557 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
ethaderu 3:78f223d34f36 3558 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
ethaderu 3:78f223d34f36 3559 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
ethaderu 3:78f223d34f36 3560 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
ethaderu 3:78f223d34f36 3561 } DAC_Type, *DAC_MemMapPtr;
ethaderu 3:78f223d34f36 3562
ethaderu 3:78f223d34f36 3563 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 3564 -- DAC - Register accessor macros
ethaderu 3:78f223d34f36 3565 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 3566
ethaderu 3:78f223d34f36 3567 /*!
ethaderu 3:78f223d34f36 3568 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
ethaderu 3:78f223d34f36 3569 * @{
ethaderu 3:78f223d34f36 3570 */
ethaderu 3:78f223d34f36 3571
ethaderu 3:78f223d34f36 3572
ethaderu 3:78f223d34f36 3573 /* DAC - Register accessors */
ethaderu 3:78f223d34f36 3574 #define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
ethaderu 3:78f223d34f36 3575 #define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
ethaderu 3:78f223d34f36 3576 #define DAC_SR_REG(base) ((base)->SR)
ethaderu 3:78f223d34f36 3577 #define DAC_C0_REG(base) ((base)->C0)
ethaderu 3:78f223d34f36 3578 #define DAC_C1_REG(base) ((base)->C1)
ethaderu 3:78f223d34f36 3579 #define DAC_C2_REG(base) ((base)->C2)
ethaderu 3:78f223d34f36 3580
ethaderu 3:78f223d34f36 3581 /*!
ethaderu 3:78f223d34f36 3582 * @}
ethaderu 3:78f223d34f36 3583 */ /* end of group DAC_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 3584
ethaderu 3:78f223d34f36 3585
ethaderu 3:78f223d34f36 3586 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 3587 -- DAC Register Masks
ethaderu 3:78f223d34f36 3588 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 3589
ethaderu 3:78f223d34f36 3590 /*!
ethaderu 3:78f223d34f36 3591 * @addtogroup DAC_Register_Masks DAC Register Masks
ethaderu 3:78f223d34f36 3592 * @{
ethaderu 3:78f223d34f36 3593 */
ethaderu 3:78f223d34f36 3594
ethaderu 3:78f223d34f36 3595 /* DATL Bit Fields */
ethaderu 3:78f223d34f36 3596 #define DAC_DATL_DATA0_MASK 0xFFu
ethaderu 3:78f223d34f36 3597 #define DAC_DATL_DATA0_SHIFT 0
ethaderu 3:78f223d34f36 3598 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
ethaderu 3:78f223d34f36 3599 /* DATH Bit Fields */
ethaderu 3:78f223d34f36 3600 #define DAC_DATH_DATA1_MASK 0xFu
ethaderu 3:78f223d34f36 3601 #define DAC_DATH_DATA1_SHIFT 0
ethaderu 3:78f223d34f36 3602 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
ethaderu 3:78f223d34f36 3603 /* SR Bit Fields */
ethaderu 3:78f223d34f36 3604 #define DAC_SR_DACBFRPBF_MASK 0x1u
ethaderu 3:78f223d34f36 3605 #define DAC_SR_DACBFRPBF_SHIFT 0
ethaderu 3:78f223d34f36 3606 #define DAC_SR_DACBFRPTF_MASK 0x2u
ethaderu 3:78f223d34f36 3607 #define DAC_SR_DACBFRPTF_SHIFT 1
ethaderu 3:78f223d34f36 3608 #define DAC_SR_DACBFWMF_MASK 0x4u
ethaderu 3:78f223d34f36 3609 #define DAC_SR_DACBFWMF_SHIFT 2
ethaderu 3:78f223d34f36 3610 /* C0 Bit Fields */
ethaderu 3:78f223d34f36 3611 #define DAC_C0_DACBBIEN_MASK 0x1u
ethaderu 3:78f223d34f36 3612 #define DAC_C0_DACBBIEN_SHIFT 0
ethaderu 3:78f223d34f36 3613 #define DAC_C0_DACBTIEN_MASK 0x2u
ethaderu 3:78f223d34f36 3614 #define DAC_C0_DACBTIEN_SHIFT 1
ethaderu 3:78f223d34f36 3615 #define DAC_C0_DACBWIEN_MASK 0x4u
ethaderu 3:78f223d34f36 3616 #define DAC_C0_DACBWIEN_SHIFT 2
ethaderu 3:78f223d34f36 3617 #define DAC_C0_LPEN_MASK 0x8u
ethaderu 3:78f223d34f36 3618 #define DAC_C0_LPEN_SHIFT 3
ethaderu 3:78f223d34f36 3619 #define DAC_C0_DACSWTRG_MASK 0x10u
ethaderu 3:78f223d34f36 3620 #define DAC_C0_DACSWTRG_SHIFT 4
ethaderu 3:78f223d34f36 3621 #define DAC_C0_DACTRGSEL_MASK 0x20u
ethaderu 3:78f223d34f36 3622 #define DAC_C0_DACTRGSEL_SHIFT 5
ethaderu 3:78f223d34f36 3623 #define DAC_C0_DACRFS_MASK 0x40u
ethaderu 3:78f223d34f36 3624 #define DAC_C0_DACRFS_SHIFT 6
ethaderu 3:78f223d34f36 3625 #define DAC_C0_DACEN_MASK 0x80u
ethaderu 3:78f223d34f36 3626 #define DAC_C0_DACEN_SHIFT 7
ethaderu 3:78f223d34f36 3627 /* C1 Bit Fields */
ethaderu 3:78f223d34f36 3628 #define DAC_C1_DACBFEN_MASK 0x1u
ethaderu 3:78f223d34f36 3629 #define DAC_C1_DACBFEN_SHIFT 0
ethaderu 3:78f223d34f36 3630 #define DAC_C1_DACBFMD_MASK 0x6u
ethaderu 3:78f223d34f36 3631 #define DAC_C1_DACBFMD_SHIFT 1
ethaderu 3:78f223d34f36 3632 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
ethaderu 3:78f223d34f36 3633 #define DAC_C1_DACBFWM_MASK 0x18u
ethaderu 3:78f223d34f36 3634 #define DAC_C1_DACBFWM_SHIFT 3
ethaderu 3:78f223d34f36 3635 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
ethaderu 3:78f223d34f36 3636 #define DAC_C1_DMAEN_MASK 0x80u
ethaderu 3:78f223d34f36 3637 #define DAC_C1_DMAEN_SHIFT 7
ethaderu 3:78f223d34f36 3638 /* C2 Bit Fields */
ethaderu 3:78f223d34f36 3639 #define DAC_C2_DACBFUP_MASK 0xFu
ethaderu 3:78f223d34f36 3640 #define DAC_C2_DACBFUP_SHIFT 0
ethaderu 3:78f223d34f36 3641 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
ethaderu 3:78f223d34f36 3642 #define DAC_C2_DACBFRP_MASK 0xF0u
ethaderu 3:78f223d34f36 3643 #define DAC_C2_DACBFRP_SHIFT 4
ethaderu 3:78f223d34f36 3644 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
ethaderu 3:78f223d34f36 3645
ethaderu 3:78f223d34f36 3646 /*!
ethaderu 3:78f223d34f36 3647 * @}
ethaderu 3:78f223d34f36 3648 */ /* end of group DAC_Register_Masks */
ethaderu 3:78f223d34f36 3649
ethaderu 3:78f223d34f36 3650
ethaderu 3:78f223d34f36 3651 /* DAC - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 3652 /** Peripheral DAC0 base address */
ethaderu 3:78f223d34f36 3653 #define DAC0_BASE (0x400CC000u)
ethaderu 3:78f223d34f36 3654 /** Peripheral DAC0 base pointer */
ethaderu 3:78f223d34f36 3655 #define DAC0 ((DAC_Type *)DAC0_BASE)
ethaderu 3:78f223d34f36 3656 #define DAC0_BASE_PTR (DAC0)
ethaderu 3:78f223d34f36 3657 /** Peripheral DAC1 base address */
ethaderu 3:78f223d34f36 3658 #define DAC1_BASE (0x400CD000u)
ethaderu 3:78f223d34f36 3659 /** Peripheral DAC1 base pointer */
ethaderu 3:78f223d34f36 3660 #define DAC1 ((DAC_Type *)DAC1_BASE)
ethaderu 3:78f223d34f36 3661 #define DAC1_BASE_PTR (DAC1)
ethaderu 3:78f223d34f36 3662 /** Array initializer of DAC peripheral base addresses */
ethaderu 3:78f223d34f36 3663 #define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
ethaderu 3:78f223d34f36 3664 /** Array initializer of DAC peripheral base pointers */
ethaderu 3:78f223d34f36 3665 #define DAC_BASE_PTRS { DAC0, DAC1 }
ethaderu 3:78f223d34f36 3666 /** Interrupt vectors for the DAC peripheral type */
ethaderu 3:78f223d34f36 3667 #define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
ethaderu 3:78f223d34f36 3668
ethaderu 3:78f223d34f36 3669 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 3670 -- DAC - Register accessor macros
ethaderu 3:78f223d34f36 3671 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 3672
ethaderu 3:78f223d34f36 3673 /*!
ethaderu 3:78f223d34f36 3674 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
ethaderu 3:78f223d34f36 3675 * @{
ethaderu 3:78f223d34f36 3676 */
ethaderu 3:78f223d34f36 3677
ethaderu 3:78f223d34f36 3678
ethaderu 3:78f223d34f36 3679 /* DAC - Register instance definitions */
ethaderu 3:78f223d34f36 3680 /* DAC0 */
ethaderu 3:78f223d34f36 3681 #define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
ethaderu 3:78f223d34f36 3682 #define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
ethaderu 3:78f223d34f36 3683 #define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
ethaderu 3:78f223d34f36 3684 #define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
ethaderu 3:78f223d34f36 3685 #define DAC0_DAT2L DAC_DATL_REG(DAC0,2)
ethaderu 3:78f223d34f36 3686 #define DAC0_DAT2H DAC_DATH_REG(DAC0,2)
ethaderu 3:78f223d34f36 3687 #define DAC0_DAT3L DAC_DATL_REG(DAC0,3)
ethaderu 3:78f223d34f36 3688 #define DAC0_DAT3H DAC_DATH_REG(DAC0,3)
ethaderu 3:78f223d34f36 3689 #define DAC0_DAT4L DAC_DATL_REG(DAC0,4)
ethaderu 3:78f223d34f36 3690 #define DAC0_DAT4H DAC_DATH_REG(DAC0,4)
ethaderu 3:78f223d34f36 3691 #define DAC0_DAT5L DAC_DATL_REG(DAC0,5)
ethaderu 3:78f223d34f36 3692 #define DAC0_DAT5H DAC_DATH_REG(DAC0,5)
ethaderu 3:78f223d34f36 3693 #define DAC0_DAT6L DAC_DATL_REG(DAC0,6)
ethaderu 3:78f223d34f36 3694 #define DAC0_DAT6H DAC_DATH_REG(DAC0,6)
ethaderu 3:78f223d34f36 3695 #define DAC0_DAT7L DAC_DATL_REG(DAC0,7)
ethaderu 3:78f223d34f36 3696 #define DAC0_DAT7H DAC_DATH_REG(DAC0,7)
ethaderu 3:78f223d34f36 3697 #define DAC0_DAT8L DAC_DATL_REG(DAC0,8)
ethaderu 3:78f223d34f36 3698 #define DAC0_DAT8H DAC_DATH_REG(DAC0,8)
ethaderu 3:78f223d34f36 3699 #define DAC0_DAT9L DAC_DATL_REG(DAC0,9)
ethaderu 3:78f223d34f36 3700 #define DAC0_DAT9H DAC_DATH_REG(DAC0,9)
ethaderu 3:78f223d34f36 3701 #define DAC0_DAT10L DAC_DATL_REG(DAC0,10)
ethaderu 3:78f223d34f36 3702 #define DAC0_DAT10H DAC_DATH_REG(DAC0,10)
ethaderu 3:78f223d34f36 3703 #define DAC0_DAT11L DAC_DATL_REG(DAC0,11)
ethaderu 3:78f223d34f36 3704 #define DAC0_DAT11H DAC_DATH_REG(DAC0,11)
ethaderu 3:78f223d34f36 3705 #define DAC0_DAT12L DAC_DATL_REG(DAC0,12)
ethaderu 3:78f223d34f36 3706 #define DAC0_DAT12H DAC_DATH_REG(DAC0,12)
ethaderu 3:78f223d34f36 3707 #define DAC0_DAT13L DAC_DATL_REG(DAC0,13)
ethaderu 3:78f223d34f36 3708 #define DAC0_DAT13H DAC_DATH_REG(DAC0,13)
ethaderu 3:78f223d34f36 3709 #define DAC0_DAT14L DAC_DATL_REG(DAC0,14)
ethaderu 3:78f223d34f36 3710 #define DAC0_DAT14H DAC_DATH_REG(DAC0,14)
ethaderu 3:78f223d34f36 3711 #define DAC0_DAT15L DAC_DATL_REG(DAC0,15)
ethaderu 3:78f223d34f36 3712 #define DAC0_DAT15H DAC_DATH_REG(DAC0,15)
ethaderu 3:78f223d34f36 3713 #define DAC0_SR DAC_SR_REG(DAC0)
ethaderu 3:78f223d34f36 3714 #define DAC0_C0 DAC_C0_REG(DAC0)
ethaderu 3:78f223d34f36 3715 #define DAC0_C1 DAC_C1_REG(DAC0)
ethaderu 3:78f223d34f36 3716 #define DAC0_C2 DAC_C2_REG(DAC0)
ethaderu 3:78f223d34f36 3717 /* DAC1 */
ethaderu 3:78f223d34f36 3718 #define DAC1_DAT0L DAC_DATL_REG(DAC1,0)
ethaderu 3:78f223d34f36 3719 #define DAC1_DAT0H DAC_DATH_REG(DAC1,0)
ethaderu 3:78f223d34f36 3720 #define DAC1_DAT1L DAC_DATL_REG(DAC1,1)
ethaderu 3:78f223d34f36 3721 #define DAC1_DAT1H DAC_DATH_REG(DAC1,1)
ethaderu 3:78f223d34f36 3722 #define DAC1_DAT2L DAC_DATL_REG(DAC1,2)
ethaderu 3:78f223d34f36 3723 #define DAC1_DAT2H DAC_DATH_REG(DAC1,2)
ethaderu 3:78f223d34f36 3724 #define DAC1_DAT3L DAC_DATL_REG(DAC1,3)
ethaderu 3:78f223d34f36 3725 #define DAC1_DAT3H DAC_DATH_REG(DAC1,3)
ethaderu 3:78f223d34f36 3726 #define DAC1_DAT4L DAC_DATL_REG(DAC1,4)
ethaderu 3:78f223d34f36 3727 #define DAC1_DAT4H DAC_DATH_REG(DAC1,4)
ethaderu 3:78f223d34f36 3728 #define DAC1_DAT5L DAC_DATL_REG(DAC1,5)
ethaderu 3:78f223d34f36 3729 #define DAC1_DAT5H DAC_DATH_REG(DAC1,5)
ethaderu 3:78f223d34f36 3730 #define DAC1_DAT6L DAC_DATL_REG(DAC1,6)
ethaderu 3:78f223d34f36 3731 #define DAC1_DAT6H DAC_DATH_REG(DAC1,6)
ethaderu 3:78f223d34f36 3732 #define DAC1_DAT7L DAC_DATL_REG(DAC1,7)
ethaderu 3:78f223d34f36 3733 #define DAC1_DAT7H DAC_DATH_REG(DAC1,7)
ethaderu 3:78f223d34f36 3734 #define DAC1_DAT8L DAC_DATL_REG(DAC1,8)
ethaderu 3:78f223d34f36 3735 #define DAC1_DAT8H DAC_DATH_REG(DAC1,8)
ethaderu 3:78f223d34f36 3736 #define DAC1_DAT9L DAC_DATL_REG(DAC1,9)
ethaderu 3:78f223d34f36 3737 #define DAC1_DAT9H DAC_DATH_REG(DAC1,9)
ethaderu 3:78f223d34f36 3738 #define DAC1_DAT10L DAC_DATL_REG(DAC1,10)
ethaderu 3:78f223d34f36 3739 #define DAC1_DAT10H DAC_DATH_REG(DAC1,10)
ethaderu 3:78f223d34f36 3740 #define DAC1_DAT11L DAC_DATL_REG(DAC1,11)
ethaderu 3:78f223d34f36 3741 #define DAC1_DAT11H DAC_DATH_REG(DAC1,11)
ethaderu 3:78f223d34f36 3742 #define DAC1_DAT12L DAC_DATL_REG(DAC1,12)
ethaderu 3:78f223d34f36 3743 #define DAC1_DAT12H DAC_DATH_REG(DAC1,12)
ethaderu 3:78f223d34f36 3744 #define DAC1_DAT13L DAC_DATL_REG(DAC1,13)
ethaderu 3:78f223d34f36 3745 #define DAC1_DAT13H DAC_DATH_REG(DAC1,13)
ethaderu 3:78f223d34f36 3746 #define DAC1_DAT14L DAC_DATL_REG(DAC1,14)
ethaderu 3:78f223d34f36 3747 #define DAC1_DAT14H DAC_DATH_REG(DAC1,14)
ethaderu 3:78f223d34f36 3748 #define DAC1_DAT15L DAC_DATL_REG(DAC1,15)
ethaderu 3:78f223d34f36 3749 #define DAC1_DAT15H DAC_DATH_REG(DAC1,15)
ethaderu 3:78f223d34f36 3750 #define DAC1_SR DAC_SR_REG(DAC1)
ethaderu 3:78f223d34f36 3751 #define DAC1_C0 DAC_C0_REG(DAC1)
ethaderu 3:78f223d34f36 3752 #define DAC1_C1 DAC_C1_REG(DAC1)
ethaderu 3:78f223d34f36 3753 #define DAC1_C2 DAC_C2_REG(DAC1)
ethaderu 3:78f223d34f36 3754
ethaderu 3:78f223d34f36 3755 /* DAC - Register array accessors */
ethaderu 3:78f223d34f36 3756 #define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
ethaderu 3:78f223d34f36 3757 #define DAC1_DATL(index) DAC_DATL_REG(DAC1,index)
ethaderu 3:78f223d34f36 3758 #define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
ethaderu 3:78f223d34f36 3759 #define DAC1_DATH(index) DAC_DATH_REG(DAC1,index)
ethaderu 3:78f223d34f36 3760
ethaderu 3:78f223d34f36 3761 /*!
ethaderu 3:78f223d34f36 3762 * @}
ethaderu 3:78f223d34f36 3763 */ /* end of group DAC_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 3764
ethaderu 3:78f223d34f36 3765
ethaderu 3:78f223d34f36 3766 /*!
ethaderu 3:78f223d34f36 3767 * @}
ethaderu 3:78f223d34f36 3768 */ /* end of group DAC_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 3769
ethaderu 3:78f223d34f36 3770
ethaderu 3:78f223d34f36 3771 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 3772 -- DMA Peripheral Access Layer
ethaderu 3:78f223d34f36 3773 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 3774
ethaderu 3:78f223d34f36 3775 /*!
ethaderu 3:78f223d34f36 3776 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
ethaderu 3:78f223d34f36 3777 * @{
ethaderu 3:78f223d34f36 3778 */
ethaderu 3:78f223d34f36 3779
ethaderu 3:78f223d34f36 3780 /** DMA - Register Layout Typedef */
ethaderu 3:78f223d34f36 3781 typedef struct {
ethaderu 3:78f223d34f36 3782 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
ethaderu 3:78f223d34f36 3783 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
ethaderu 3:78f223d34f36 3784 uint8_t RESERVED_0[4];
ethaderu 3:78f223d34f36 3785 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
ethaderu 3:78f223d34f36 3786 uint8_t RESERVED_1[4];
ethaderu 3:78f223d34f36 3787 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
ethaderu 3:78f223d34f36 3788 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
ethaderu 3:78f223d34f36 3789 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
ethaderu 3:78f223d34f36 3790 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
ethaderu 3:78f223d34f36 3791 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
ethaderu 3:78f223d34f36 3792 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
ethaderu 3:78f223d34f36 3793 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
ethaderu 3:78f223d34f36 3794 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
ethaderu 3:78f223d34f36 3795 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
ethaderu 3:78f223d34f36 3796 uint8_t RESERVED_2[4];
ethaderu 3:78f223d34f36 3797 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
ethaderu 3:78f223d34f36 3798 uint8_t RESERVED_3[4];
ethaderu 3:78f223d34f36 3799 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
ethaderu 3:78f223d34f36 3800 uint8_t RESERVED_4[4];
ethaderu 3:78f223d34f36 3801 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
ethaderu 3:78f223d34f36 3802 uint8_t RESERVED_5[200];
ethaderu 3:78f223d34f36 3803 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
ethaderu 3:78f223d34f36 3804 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
ethaderu 3:78f223d34f36 3805 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
ethaderu 3:78f223d34f36 3806 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
ethaderu 3:78f223d34f36 3807 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
ethaderu 3:78f223d34f36 3808 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
ethaderu 3:78f223d34f36 3809 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
ethaderu 3:78f223d34f36 3810 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
ethaderu 3:78f223d34f36 3811 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
ethaderu 3:78f223d34f36 3812 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
ethaderu 3:78f223d34f36 3813 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
ethaderu 3:78f223d34f36 3814 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
ethaderu 3:78f223d34f36 3815 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
ethaderu 3:78f223d34f36 3816 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
ethaderu 3:78f223d34f36 3817 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
ethaderu 3:78f223d34f36 3818 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
ethaderu 3:78f223d34f36 3819 uint8_t RESERVED_6[3824];
ethaderu 3:78f223d34f36 3820 struct { /* offset: 0x1000, array step: 0x20 */
ethaderu 3:78f223d34f36 3821 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
ethaderu 3:78f223d34f36 3822 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
ethaderu 3:78f223d34f36 3823 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
ethaderu 3:78f223d34f36 3824 union { /* offset: 0x1008, array step: 0x20 */
ethaderu 3:78f223d34f36 3825 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
ethaderu 3:78f223d34f36 3826 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
ethaderu 3:78f223d34f36 3827 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
ethaderu 3:78f223d34f36 3828 };
ethaderu 3:78f223d34f36 3829 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
ethaderu 3:78f223d34f36 3830 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
ethaderu 3:78f223d34f36 3831 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
ethaderu 3:78f223d34f36 3832 union { /* offset: 0x1016, array step: 0x20 */
ethaderu 3:78f223d34f36 3833 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
ethaderu 3:78f223d34f36 3834 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
ethaderu 3:78f223d34f36 3835 };
ethaderu 3:78f223d34f36 3836 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
ethaderu 3:78f223d34f36 3837 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
ethaderu 3:78f223d34f36 3838 union { /* offset: 0x101E, array step: 0x20 */
ethaderu 3:78f223d34f36 3839 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
ethaderu 3:78f223d34f36 3840 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
ethaderu 3:78f223d34f36 3841 };
ethaderu 3:78f223d34f36 3842 } TCD[16];
ethaderu 3:78f223d34f36 3843 } DMA_Type, *DMA_MemMapPtr;
ethaderu 3:78f223d34f36 3844
ethaderu 3:78f223d34f36 3845 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 3846 -- DMA - Register accessor macros
ethaderu 3:78f223d34f36 3847 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 3848
ethaderu 3:78f223d34f36 3849 /*!
ethaderu 3:78f223d34f36 3850 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
ethaderu 3:78f223d34f36 3851 * @{
ethaderu 3:78f223d34f36 3852 */
ethaderu 3:78f223d34f36 3853
ethaderu 3:78f223d34f36 3854
ethaderu 3:78f223d34f36 3855 /* DMA - Register accessors */
ethaderu 3:78f223d34f36 3856 #define DMA_CR_REG(base) ((base)->CR)
ethaderu 3:78f223d34f36 3857 #define DMA_ES_REG(base) ((base)->ES)
ethaderu 3:78f223d34f36 3858 #define DMA_ERQ_REG(base) ((base)->ERQ)
ethaderu 3:78f223d34f36 3859 #define DMA_EEI_REG(base) ((base)->EEI)
ethaderu 3:78f223d34f36 3860 #define DMA_CEEI_REG(base) ((base)->CEEI)
ethaderu 3:78f223d34f36 3861 #define DMA_SEEI_REG(base) ((base)->SEEI)
ethaderu 3:78f223d34f36 3862 #define DMA_CERQ_REG(base) ((base)->CERQ)
ethaderu 3:78f223d34f36 3863 #define DMA_SERQ_REG(base) ((base)->SERQ)
ethaderu 3:78f223d34f36 3864 #define DMA_CDNE_REG(base) ((base)->CDNE)
ethaderu 3:78f223d34f36 3865 #define DMA_SSRT_REG(base) ((base)->SSRT)
ethaderu 3:78f223d34f36 3866 #define DMA_CERR_REG(base) ((base)->CERR)
ethaderu 3:78f223d34f36 3867 #define DMA_CINT_REG(base) ((base)->CINT)
ethaderu 3:78f223d34f36 3868 #define DMA_INT_REG(base) ((base)->INT)
ethaderu 3:78f223d34f36 3869 #define DMA_ERR_REG(base) ((base)->ERR)
ethaderu 3:78f223d34f36 3870 #define DMA_HRS_REG(base) ((base)->HRS)
ethaderu 3:78f223d34f36 3871 #define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
ethaderu 3:78f223d34f36 3872 #define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
ethaderu 3:78f223d34f36 3873 #define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
ethaderu 3:78f223d34f36 3874 #define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
ethaderu 3:78f223d34f36 3875 #define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
ethaderu 3:78f223d34f36 3876 #define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
ethaderu 3:78f223d34f36 3877 #define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
ethaderu 3:78f223d34f36 3878 #define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
ethaderu 3:78f223d34f36 3879 #define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)
ethaderu 3:78f223d34f36 3880 #define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)
ethaderu 3:78f223d34f36 3881 #define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)
ethaderu 3:78f223d34f36 3882 #define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)
ethaderu 3:78f223d34f36 3883 #define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)
ethaderu 3:78f223d34f36 3884 #define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)
ethaderu 3:78f223d34f36 3885 #define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)
ethaderu 3:78f223d34f36 3886 #define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)
ethaderu 3:78f223d34f36 3887 #define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
ethaderu 3:78f223d34f36 3888 #define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
ethaderu 3:78f223d34f36 3889 #define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
ethaderu 3:78f223d34f36 3890 #define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
ethaderu 3:78f223d34f36 3891 #define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
ethaderu 3:78f223d34f36 3892 #define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
ethaderu 3:78f223d34f36 3893 #define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
ethaderu 3:78f223d34f36 3894 #define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
ethaderu 3:78f223d34f36 3895 #define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
ethaderu 3:78f223d34f36 3896 #define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
ethaderu 3:78f223d34f36 3897 #define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
ethaderu 3:78f223d34f36 3898 #define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
ethaderu 3:78f223d34f36 3899 #define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
ethaderu 3:78f223d34f36 3900 #define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
ethaderu 3:78f223d34f36 3901 #define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
ethaderu 3:78f223d34f36 3902
ethaderu 3:78f223d34f36 3903 /*!
ethaderu 3:78f223d34f36 3904 * @}
ethaderu 3:78f223d34f36 3905 */ /* end of group DMA_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 3906
ethaderu 3:78f223d34f36 3907
ethaderu 3:78f223d34f36 3908 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 3909 -- DMA Register Masks
ethaderu 3:78f223d34f36 3910 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 3911
ethaderu 3:78f223d34f36 3912 /*!
ethaderu 3:78f223d34f36 3913 * @addtogroup DMA_Register_Masks DMA Register Masks
ethaderu 3:78f223d34f36 3914 * @{
ethaderu 3:78f223d34f36 3915 */
ethaderu 3:78f223d34f36 3916
ethaderu 3:78f223d34f36 3917 /* CR Bit Fields */
ethaderu 3:78f223d34f36 3918 #define DMA_CR_EDBG_MASK 0x2u
ethaderu 3:78f223d34f36 3919 #define DMA_CR_EDBG_SHIFT 1
ethaderu 3:78f223d34f36 3920 #define DMA_CR_ERCA_MASK 0x4u
ethaderu 3:78f223d34f36 3921 #define DMA_CR_ERCA_SHIFT 2
ethaderu 3:78f223d34f36 3922 #define DMA_CR_HOE_MASK 0x10u
ethaderu 3:78f223d34f36 3923 #define DMA_CR_HOE_SHIFT 4
ethaderu 3:78f223d34f36 3924 #define DMA_CR_HALT_MASK 0x20u
ethaderu 3:78f223d34f36 3925 #define DMA_CR_HALT_SHIFT 5
ethaderu 3:78f223d34f36 3926 #define DMA_CR_CLM_MASK 0x40u
ethaderu 3:78f223d34f36 3927 #define DMA_CR_CLM_SHIFT 6
ethaderu 3:78f223d34f36 3928 #define DMA_CR_EMLM_MASK 0x80u
ethaderu 3:78f223d34f36 3929 #define DMA_CR_EMLM_SHIFT 7
ethaderu 3:78f223d34f36 3930 #define DMA_CR_ECX_MASK 0x10000u
ethaderu 3:78f223d34f36 3931 #define DMA_CR_ECX_SHIFT 16
ethaderu 3:78f223d34f36 3932 #define DMA_CR_CX_MASK 0x20000u
ethaderu 3:78f223d34f36 3933 #define DMA_CR_CX_SHIFT 17
ethaderu 3:78f223d34f36 3934 /* ES Bit Fields */
ethaderu 3:78f223d34f36 3935 #define DMA_ES_DBE_MASK 0x1u
ethaderu 3:78f223d34f36 3936 #define DMA_ES_DBE_SHIFT 0
ethaderu 3:78f223d34f36 3937 #define DMA_ES_SBE_MASK 0x2u
ethaderu 3:78f223d34f36 3938 #define DMA_ES_SBE_SHIFT 1
ethaderu 3:78f223d34f36 3939 #define DMA_ES_SGE_MASK 0x4u
ethaderu 3:78f223d34f36 3940 #define DMA_ES_SGE_SHIFT 2
ethaderu 3:78f223d34f36 3941 #define DMA_ES_NCE_MASK 0x8u
ethaderu 3:78f223d34f36 3942 #define DMA_ES_NCE_SHIFT 3
ethaderu 3:78f223d34f36 3943 #define DMA_ES_DOE_MASK 0x10u
ethaderu 3:78f223d34f36 3944 #define DMA_ES_DOE_SHIFT 4
ethaderu 3:78f223d34f36 3945 #define DMA_ES_DAE_MASK 0x20u
ethaderu 3:78f223d34f36 3946 #define DMA_ES_DAE_SHIFT 5
ethaderu 3:78f223d34f36 3947 #define DMA_ES_SOE_MASK 0x40u
ethaderu 3:78f223d34f36 3948 #define DMA_ES_SOE_SHIFT 6
ethaderu 3:78f223d34f36 3949 #define DMA_ES_SAE_MASK 0x80u
ethaderu 3:78f223d34f36 3950 #define DMA_ES_SAE_SHIFT 7
ethaderu 3:78f223d34f36 3951 #define DMA_ES_ERRCHN_MASK 0xF00u
ethaderu 3:78f223d34f36 3952 #define DMA_ES_ERRCHN_SHIFT 8
ethaderu 3:78f223d34f36 3953 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
ethaderu 3:78f223d34f36 3954 #define DMA_ES_CPE_MASK 0x4000u
ethaderu 3:78f223d34f36 3955 #define DMA_ES_CPE_SHIFT 14
ethaderu 3:78f223d34f36 3956 #define DMA_ES_ECX_MASK 0x10000u
ethaderu 3:78f223d34f36 3957 #define DMA_ES_ECX_SHIFT 16
ethaderu 3:78f223d34f36 3958 #define DMA_ES_VLD_MASK 0x80000000u
ethaderu 3:78f223d34f36 3959 #define DMA_ES_VLD_SHIFT 31
ethaderu 3:78f223d34f36 3960 /* ERQ Bit Fields */
ethaderu 3:78f223d34f36 3961 #define DMA_ERQ_ERQ0_MASK 0x1u
ethaderu 3:78f223d34f36 3962 #define DMA_ERQ_ERQ0_SHIFT 0
ethaderu 3:78f223d34f36 3963 #define DMA_ERQ_ERQ1_MASK 0x2u
ethaderu 3:78f223d34f36 3964 #define DMA_ERQ_ERQ1_SHIFT 1
ethaderu 3:78f223d34f36 3965 #define DMA_ERQ_ERQ2_MASK 0x4u
ethaderu 3:78f223d34f36 3966 #define DMA_ERQ_ERQ2_SHIFT 2
ethaderu 3:78f223d34f36 3967 #define DMA_ERQ_ERQ3_MASK 0x8u
ethaderu 3:78f223d34f36 3968 #define DMA_ERQ_ERQ3_SHIFT 3
ethaderu 3:78f223d34f36 3969 #define DMA_ERQ_ERQ4_MASK 0x10u
ethaderu 3:78f223d34f36 3970 #define DMA_ERQ_ERQ4_SHIFT 4
ethaderu 3:78f223d34f36 3971 #define DMA_ERQ_ERQ5_MASK 0x20u
ethaderu 3:78f223d34f36 3972 #define DMA_ERQ_ERQ5_SHIFT 5
ethaderu 3:78f223d34f36 3973 #define DMA_ERQ_ERQ6_MASK 0x40u
ethaderu 3:78f223d34f36 3974 #define DMA_ERQ_ERQ6_SHIFT 6
ethaderu 3:78f223d34f36 3975 #define DMA_ERQ_ERQ7_MASK 0x80u
ethaderu 3:78f223d34f36 3976 #define DMA_ERQ_ERQ7_SHIFT 7
ethaderu 3:78f223d34f36 3977 #define DMA_ERQ_ERQ8_MASK 0x100u
ethaderu 3:78f223d34f36 3978 #define DMA_ERQ_ERQ8_SHIFT 8
ethaderu 3:78f223d34f36 3979 #define DMA_ERQ_ERQ9_MASK 0x200u
ethaderu 3:78f223d34f36 3980 #define DMA_ERQ_ERQ9_SHIFT 9
ethaderu 3:78f223d34f36 3981 #define DMA_ERQ_ERQ10_MASK 0x400u
ethaderu 3:78f223d34f36 3982 #define DMA_ERQ_ERQ10_SHIFT 10
ethaderu 3:78f223d34f36 3983 #define DMA_ERQ_ERQ11_MASK 0x800u
ethaderu 3:78f223d34f36 3984 #define DMA_ERQ_ERQ11_SHIFT 11
ethaderu 3:78f223d34f36 3985 #define DMA_ERQ_ERQ12_MASK 0x1000u
ethaderu 3:78f223d34f36 3986 #define DMA_ERQ_ERQ12_SHIFT 12
ethaderu 3:78f223d34f36 3987 #define DMA_ERQ_ERQ13_MASK 0x2000u
ethaderu 3:78f223d34f36 3988 #define DMA_ERQ_ERQ13_SHIFT 13
ethaderu 3:78f223d34f36 3989 #define DMA_ERQ_ERQ14_MASK 0x4000u
ethaderu 3:78f223d34f36 3990 #define DMA_ERQ_ERQ14_SHIFT 14
ethaderu 3:78f223d34f36 3991 #define DMA_ERQ_ERQ15_MASK 0x8000u
ethaderu 3:78f223d34f36 3992 #define DMA_ERQ_ERQ15_SHIFT 15
ethaderu 3:78f223d34f36 3993 /* EEI Bit Fields */
ethaderu 3:78f223d34f36 3994 #define DMA_EEI_EEI0_MASK 0x1u
ethaderu 3:78f223d34f36 3995 #define DMA_EEI_EEI0_SHIFT 0
ethaderu 3:78f223d34f36 3996 #define DMA_EEI_EEI1_MASK 0x2u
ethaderu 3:78f223d34f36 3997 #define DMA_EEI_EEI1_SHIFT 1
ethaderu 3:78f223d34f36 3998 #define DMA_EEI_EEI2_MASK 0x4u
ethaderu 3:78f223d34f36 3999 #define DMA_EEI_EEI2_SHIFT 2
ethaderu 3:78f223d34f36 4000 #define DMA_EEI_EEI3_MASK 0x8u
ethaderu 3:78f223d34f36 4001 #define DMA_EEI_EEI3_SHIFT 3
ethaderu 3:78f223d34f36 4002 #define DMA_EEI_EEI4_MASK 0x10u
ethaderu 3:78f223d34f36 4003 #define DMA_EEI_EEI4_SHIFT 4
ethaderu 3:78f223d34f36 4004 #define DMA_EEI_EEI5_MASK 0x20u
ethaderu 3:78f223d34f36 4005 #define DMA_EEI_EEI5_SHIFT 5
ethaderu 3:78f223d34f36 4006 #define DMA_EEI_EEI6_MASK 0x40u
ethaderu 3:78f223d34f36 4007 #define DMA_EEI_EEI6_SHIFT 6
ethaderu 3:78f223d34f36 4008 #define DMA_EEI_EEI7_MASK 0x80u
ethaderu 3:78f223d34f36 4009 #define DMA_EEI_EEI7_SHIFT 7
ethaderu 3:78f223d34f36 4010 #define DMA_EEI_EEI8_MASK 0x100u
ethaderu 3:78f223d34f36 4011 #define DMA_EEI_EEI8_SHIFT 8
ethaderu 3:78f223d34f36 4012 #define DMA_EEI_EEI9_MASK 0x200u
ethaderu 3:78f223d34f36 4013 #define DMA_EEI_EEI9_SHIFT 9
ethaderu 3:78f223d34f36 4014 #define DMA_EEI_EEI10_MASK 0x400u
ethaderu 3:78f223d34f36 4015 #define DMA_EEI_EEI10_SHIFT 10
ethaderu 3:78f223d34f36 4016 #define DMA_EEI_EEI11_MASK 0x800u
ethaderu 3:78f223d34f36 4017 #define DMA_EEI_EEI11_SHIFT 11
ethaderu 3:78f223d34f36 4018 #define DMA_EEI_EEI12_MASK 0x1000u
ethaderu 3:78f223d34f36 4019 #define DMA_EEI_EEI12_SHIFT 12
ethaderu 3:78f223d34f36 4020 #define DMA_EEI_EEI13_MASK 0x2000u
ethaderu 3:78f223d34f36 4021 #define DMA_EEI_EEI13_SHIFT 13
ethaderu 3:78f223d34f36 4022 #define DMA_EEI_EEI14_MASK 0x4000u
ethaderu 3:78f223d34f36 4023 #define DMA_EEI_EEI14_SHIFT 14
ethaderu 3:78f223d34f36 4024 #define DMA_EEI_EEI15_MASK 0x8000u
ethaderu 3:78f223d34f36 4025 #define DMA_EEI_EEI15_SHIFT 15
ethaderu 3:78f223d34f36 4026 /* CEEI Bit Fields */
ethaderu 3:78f223d34f36 4027 #define DMA_CEEI_CEEI_MASK 0xFu
ethaderu 3:78f223d34f36 4028 #define DMA_CEEI_CEEI_SHIFT 0
ethaderu 3:78f223d34f36 4029 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
ethaderu 3:78f223d34f36 4030 #define DMA_CEEI_CAEE_MASK 0x40u
ethaderu 3:78f223d34f36 4031 #define DMA_CEEI_CAEE_SHIFT 6
ethaderu 3:78f223d34f36 4032 #define DMA_CEEI_NOP_MASK 0x80u
ethaderu 3:78f223d34f36 4033 #define DMA_CEEI_NOP_SHIFT 7
ethaderu 3:78f223d34f36 4034 /* SEEI Bit Fields */
ethaderu 3:78f223d34f36 4035 #define DMA_SEEI_SEEI_MASK 0xFu
ethaderu 3:78f223d34f36 4036 #define DMA_SEEI_SEEI_SHIFT 0
ethaderu 3:78f223d34f36 4037 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
ethaderu 3:78f223d34f36 4038 #define DMA_SEEI_SAEE_MASK 0x40u
ethaderu 3:78f223d34f36 4039 #define DMA_SEEI_SAEE_SHIFT 6
ethaderu 3:78f223d34f36 4040 #define DMA_SEEI_NOP_MASK 0x80u
ethaderu 3:78f223d34f36 4041 #define DMA_SEEI_NOP_SHIFT 7
ethaderu 3:78f223d34f36 4042 /* CERQ Bit Fields */
ethaderu 3:78f223d34f36 4043 #define DMA_CERQ_CERQ_MASK 0xFu
ethaderu 3:78f223d34f36 4044 #define DMA_CERQ_CERQ_SHIFT 0
ethaderu 3:78f223d34f36 4045 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
ethaderu 3:78f223d34f36 4046 #define DMA_CERQ_CAER_MASK 0x40u
ethaderu 3:78f223d34f36 4047 #define DMA_CERQ_CAER_SHIFT 6
ethaderu 3:78f223d34f36 4048 #define DMA_CERQ_NOP_MASK 0x80u
ethaderu 3:78f223d34f36 4049 #define DMA_CERQ_NOP_SHIFT 7
ethaderu 3:78f223d34f36 4050 /* SERQ Bit Fields */
ethaderu 3:78f223d34f36 4051 #define DMA_SERQ_SERQ_MASK 0xFu
ethaderu 3:78f223d34f36 4052 #define DMA_SERQ_SERQ_SHIFT 0
ethaderu 3:78f223d34f36 4053 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
ethaderu 3:78f223d34f36 4054 #define DMA_SERQ_SAER_MASK 0x40u
ethaderu 3:78f223d34f36 4055 #define DMA_SERQ_SAER_SHIFT 6
ethaderu 3:78f223d34f36 4056 #define DMA_SERQ_NOP_MASK 0x80u
ethaderu 3:78f223d34f36 4057 #define DMA_SERQ_NOP_SHIFT 7
ethaderu 3:78f223d34f36 4058 /* CDNE Bit Fields */
ethaderu 3:78f223d34f36 4059 #define DMA_CDNE_CDNE_MASK 0xFu
ethaderu 3:78f223d34f36 4060 #define DMA_CDNE_CDNE_SHIFT 0
ethaderu 3:78f223d34f36 4061 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
ethaderu 3:78f223d34f36 4062 #define DMA_CDNE_CADN_MASK 0x40u
ethaderu 3:78f223d34f36 4063 #define DMA_CDNE_CADN_SHIFT 6
ethaderu 3:78f223d34f36 4064 #define DMA_CDNE_NOP_MASK 0x80u
ethaderu 3:78f223d34f36 4065 #define DMA_CDNE_NOP_SHIFT 7
ethaderu 3:78f223d34f36 4066 /* SSRT Bit Fields */
ethaderu 3:78f223d34f36 4067 #define DMA_SSRT_SSRT_MASK 0xFu
ethaderu 3:78f223d34f36 4068 #define DMA_SSRT_SSRT_SHIFT 0
ethaderu 3:78f223d34f36 4069 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
ethaderu 3:78f223d34f36 4070 #define DMA_SSRT_SAST_MASK 0x40u
ethaderu 3:78f223d34f36 4071 #define DMA_SSRT_SAST_SHIFT 6
ethaderu 3:78f223d34f36 4072 #define DMA_SSRT_NOP_MASK 0x80u
ethaderu 3:78f223d34f36 4073 #define DMA_SSRT_NOP_SHIFT 7
ethaderu 3:78f223d34f36 4074 /* CERR Bit Fields */
ethaderu 3:78f223d34f36 4075 #define DMA_CERR_CERR_MASK 0xFu
ethaderu 3:78f223d34f36 4076 #define DMA_CERR_CERR_SHIFT 0
ethaderu 3:78f223d34f36 4077 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
ethaderu 3:78f223d34f36 4078 #define DMA_CERR_CAEI_MASK 0x40u
ethaderu 3:78f223d34f36 4079 #define DMA_CERR_CAEI_SHIFT 6
ethaderu 3:78f223d34f36 4080 #define DMA_CERR_NOP_MASK 0x80u
ethaderu 3:78f223d34f36 4081 #define DMA_CERR_NOP_SHIFT 7
ethaderu 3:78f223d34f36 4082 /* CINT Bit Fields */
ethaderu 3:78f223d34f36 4083 #define DMA_CINT_CINT_MASK 0xFu
ethaderu 3:78f223d34f36 4084 #define DMA_CINT_CINT_SHIFT 0
ethaderu 3:78f223d34f36 4085 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
ethaderu 3:78f223d34f36 4086 #define DMA_CINT_CAIR_MASK 0x40u
ethaderu 3:78f223d34f36 4087 #define DMA_CINT_CAIR_SHIFT 6
ethaderu 3:78f223d34f36 4088 #define DMA_CINT_NOP_MASK 0x80u
ethaderu 3:78f223d34f36 4089 #define DMA_CINT_NOP_SHIFT 7
ethaderu 3:78f223d34f36 4090 /* INT Bit Fields */
ethaderu 3:78f223d34f36 4091 #define DMA_INT_INT0_MASK 0x1u
ethaderu 3:78f223d34f36 4092 #define DMA_INT_INT0_SHIFT 0
ethaderu 3:78f223d34f36 4093 #define DMA_INT_INT1_MASK 0x2u
ethaderu 3:78f223d34f36 4094 #define DMA_INT_INT1_SHIFT 1
ethaderu 3:78f223d34f36 4095 #define DMA_INT_INT2_MASK 0x4u
ethaderu 3:78f223d34f36 4096 #define DMA_INT_INT2_SHIFT 2
ethaderu 3:78f223d34f36 4097 #define DMA_INT_INT3_MASK 0x8u
ethaderu 3:78f223d34f36 4098 #define DMA_INT_INT3_SHIFT 3
ethaderu 3:78f223d34f36 4099 #define DMA_INT_INT4_MASK 0x10u
ethaderu 3:78f223d34f36 4100 #define DMA_INT_INT4_SHIFT 4
ethaderu 3:78f223d34f36 4101 #define DMA_INT_INT5_MASK 0x20u
ethaderu 3:78f223d34f36 4102 #define DMA_INT_INT5_SHIFT 5
ethaderu 3:78f223d34f36 4103 #define DMA_INT_INT6_MASK 0x40u
ethaderu 3:78f223d34f36 4104 #define DMA_INT_INT6_SHIFT 6
ethaderu 3:78f223d34f36 4105 #define DMA_INT_INT7_MASK 0x80u
ethaderu 3:78f223d34f36 4106 #define DMA_INT_INT7_SHIFT 7
ethaderu 3:78f223d34f36 4107 #define DMA_INT_INT8_MASK 0x100u
ethaderu 3:78f223d34f36 4108 #define DMA_INT_INT8_SHIFT 8
ethaderu 3:78f223d34f36 4109 #define DMA_INT_INT9_MASK 0x200u
ethaderu 3:78f223d34f36 4110 #define DMA_INT_INT9_SHIFT 9
ethaderu 3:78f223d34f36 4111 #define DMA_INT_INT10_MASK 0x400u
ethaderu 3:78f223d34f36 4112 #define DMA_INT_INT10_SHIFT 10
ethaderu 3:78f223d34f36 4113 #define DMA_INT_INT11_MASK 0x800u
ethaderu 3:78f223d34f36 4114 #define DMA_INT_INT11_SHIFT 11
ethaderu 3:78f223d34f36 4115 #define DMA_INT_INT12_MASK 0x1000u
ethaderu 3:78f223d34f36 4116 #define DMA_INT_INT12_SHIFT 12
ethaderu 3:78f223d34f36 4117 #define DMA_INT_INT13_MASK 0x2000u
ethaderu 3:78f223d34f36 4118 #define DMA_INT_INT13_SHIFT 13
ethaderu 3:78f223d34f36 4119 #define DMA_INT_INT14_MASK 0x4000u
ethaderu 3:78f223d34f36 4120 #define DMA_INT_INT14_SHIFT 14
ethaderu 3:78f223d34f36 4121 #define DMA_INT_INT15_MASK 0x8000u
ethaderu 3:78f223d34f36 4122 #define DMA_INT_INT15_SHIFT 15
ethaderu 3:78f223d34f36 4123 /* ERR Bit Fields */
ethaderu 3:78f223d34f36 4124 #define DMA_ERR_ERR0_MASK 0x1u
ethaderu 3:78f223d34f36 4125 #define DMA_ERR_ERR0_SHIFT 0
ethaderu 3:78f223d34f36 4126 #define DMA_ERR_ERR1_MASK 0x2u
ethaderu 3:78f223d34f36 4127 #define DMA_ERR_ERR1_SHIFT 1
ethaderu 3:78f223d34f36 4128 #define DMA_ERR_ERR2_MASK 0x4u
ethaderu 3:78f223d34f36 4129 #define DMA_ERR_ERR2_SHIFT 2
ethaderu 3:78f223d34f36 4130 #define DMA_ERR_ERR3_MASK 0x8u
ethaderu 3:78f223d34f36 4131 #define DMA_ERR_ERR3_SHIFT 3
ethaderu 3:78f223d34f36 4132 #define DMA_ERR_ERR4_MASK 0x10u
ethaderu 3:78f223d34f36 4133 #define DMA_ERR_ERR4_SHIFT 4
ethaderu 3:78f223d34f36 4134 #define DMA_ERR_ERR5_MASK 0x20u
ethaderu 3:78f223d34f36 4135 #define DMA_ERR_ERR5_SHIFT 5
ethaderu 3:78f223d34f36 4136 #define DMA_ERR_ERR6_MASK 0x40u
ethaderu 3:78f223d34f36 4137 #define DMA_ERR_ERR6_SHIFT 6
ethaderu 3:78f223d34f36 4138 #define DMA_ERR_ERR7_MASK 0x80u
ethaderu 3:78f223d34f36 4139 #define DMA_ERR_ERR7_SHIFT 7
ethaderu 3:78f223d34f36 4140 #define DMA_ERR_ERR8_MASK 0x100u
ethaderu 3:78f223d34f36 4141 #define DMA_ERR_ERR8_SHIFT 8
ethaderu 3:78f223d34f36 4142 #define DMA_ERR_ERR9_MASK 0x200u
ethaderu 3:78f223d34f36 4143 #define DMA_ERR_ERR9_SHIFT 9
ethaderu 3:78f223d34f36 4144 #define DMA_ERR_ERR10_MASK 0x400u
ethaderu 3:78f223d34f36 4145 #define DMA_ERR_ERR10_SHIFT 10
ethaderu 3:78f223d34f36 4146 #define DMA_ERR_ERR11_MASK 0x800u
ethaderu 3:78f223d34f36 4147 #define DMA_ERR_ERR11_SHIFT 11
ethaderu 3:78f223d34f36 4148 #define DMA_ERR_ERR12_MASK 0x1000u
ethaderu 3:78f223d34f36 4149 #define DMA_ERR_ERR12_SHIFT 12
ethaderu 3:78f223d34f36 4150 #define DMA_ERR_ERR13_MASK 0x2000u
ethaderu 3:78f223d34f36 4151 #define DMA_ERR_ERR13_SHIFT 13
ethaderu 3:78f223d34f36 4152 #define DMA_ERR_ERR14_MASK 0x4000u
ethaderu 3:78f223d34f36 4153 #define DMA_ERR_ERR14_SHIFT 14
ethaderu 3:78f223d34f36 4154 #define DMA_ERR_ERR15_MASK 0x8000u
ethaderu 3:78f223d34f36 4155 #define DMA_ERR_ERR15_SHIFT 15
ethaderu 3:78f223d34f36 4156 /* HRS Bit Fields */
ethaderu 3:78f223d34f36 4157 #define DMA_HRS_HRS0_MASK 0x1u
ethaderu 3:78f223d34f36 4158 #define DMA_HRS_HRS0_SHIFT 0
ethaderu 3:78f223d34f36 4159 #define DMA_HRS_HRS1_MASK 0x2u
ethaderu 3:78f223d34f36 4160 #define DMA_HRS_HRS1_SHIFT 1
ethaderu 3:78f223d34f36 4161 #define DMA_HRS_HRS2_MASK 0x4u
ethaderu 3:78f223d34f36 4162 #define DMA_HRS_HRS2_SHIFT 2
ethaderu 3:78f223d34f36 4163 #define DMA_HRS_HRS3_MASK 0x8u
ethaderu 3:78f223d34f36 4164 #define DMA_HRS_HRS3_SHIFT 3
ethaderu 3:78f223d34f36 4165 #define DMA_HRS_HRS4_MASK 0x10u
ethaderu 3:78f223d34f36 4166 #define DMA_HRS_HRS4_SHIFT 4
ethaderu 3:78f223d34f36 4167 #define DMA_HRS_HRS5_MASK 0x20u
ethaderu 3:78f223d34f36 4168 #define DMA_HRS_HRS5_SHIFT 5
ethaderu 3:78f223d34f36 4169 #define DMA_HRS_HRS6_MASK 0x40u
ethaderu 3:78f223d34f36 4170 #define DMA_HRS_HRS6_SHIFT 6
ethaderu 3:78f223d34f36 4171 #define DMA_HRS_HRS7_MASK 0x80u
ethaderu 3:78f223d34f36 4172 #define DMA_HRS_HRS7_SHIFT 7
ethaderu 3:78f223d34f36 4173 #define DMA_HRS_HRS8_MASK 0x100u
ethaderu 3:78f223d34f36 4174 #define DMA_HRS_HRS8_SHIFT 8
ethaderu 3:78f223d34f36 4175 #define DMA_HRS_HRS9_MASK 0x200u
ethaderu 3:78f223d34f36 4176 #define DMA_HRS_HRS9_SHIFT 9
ethaderu 3:78f223d34f36 4177 #define DMA_HRS_HRS10_MASK 0x400u
ethaderu 3:78f223d34f36 4178 #define DMA_HRS_HRS10_SHIFT 10
ethaderu 3:78f223d34f36 4179 #define DMA_HRS_HRS11_MASK 0x800u
ethaderu 3:78f223d34f36 4180 #define DMA_HRS_HRS11_SHIFT 11
ethaderu 3:78f223d34f36 4181 #define DMA_HRS_HRS12_MASK 0x1000u
ethaderu 3:78f223d34f36 4182 #define DMA_HRS_HRS12_SHIFT 12
ethaderu 3:78f223d34f36 4183 #define DMA_HRS_HRS13_MASK 0x2000u
ethaderu 3:78f223d34f36 4184 #define DMA_HRS_HRS13_SHIFT 13
ethaderu 3:78f223d34f36 4185 #define DMA_HRS_HRS14_MASK 0x4000u
ethaderu 3:78f223d34f36 4186 #define DMA_HRS_HRS14_SHIFT 14
ethaderu 3:78f223d34f36 4187 #define DMA_HRS_HRS15_MASK 0x8000u
ethaderu 3:78f223d34f36 4188 #define DMA_HRS_HRS15_SHIFT 15
ethaderu 3:78f223d34f36 4189 /* DCHPRI3 Bit Fields */
ethaderu 3:78f223d34f36 4190 #define DMA_DCHPRI3_CHPRI_MASK 0xFu
ethaderu 3:78f223d34f36 4191 #define DMA_DCHPRI3_CHPRI_SHIFT 0
ethaderu 3:78f223d34f36 4192 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
ethaderu 3:78f223d34f36 4193 #define DMA_DCHPRI3_DPA_MASK 0x40u
ethaderu 3:78f223d34f36 4194 #define DMA_DCHPRI3_DPA_SHIFT 6
ethaderu 3:78f223d34f36 4195 #define DMA_DCHPRI3_ECP_MASK 0x80u
ethaderu 3:78f223d34f36 4196 #define DMA_DCHPRI3_ECP_SHIFT 7
ethaderu 3:78f223d34f36 4197 /* DCHPRI2 Bit Fields */
ethaderu 3:78f223d34f36 4198 #define DMA_DCHPRI2_CHPRI_MASK 0xFu
ethaderu 3:78f223d34f36 4199 #define DMA_DCHPRI2_CHPRI_SHIFT 0
ethaderu 3:78f223d34f36 4200 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
ethaderu 3:78f223d34f36 4201 #define DMA_DCHPRI2_DPA_MASK 0x40u
ethaderu 3:78f223d34f36 4202 #define DMA_DCHPRI2_DPA_SHIFT 6
ethaderu 3:78f223d34f36 4203 #define DMA_DCHPRI2_ECP_MASK 0x80u
ethaderu 3:78f223d34f36 4204 #define DMA_DCHPRI2_ECP_SHIFT 7
ethaderu 3:78f223d34f36 4205 /* DCHPRI1 Bit Fields */
ethaderu 3:78f223d34f36 4206 #define DMA_DCHPRI1_CHPRI_MASK 0xFu
ethaderu 3:78f223d34f36 4207 #define DMA_DCHPRI1_CHPRI_SHIFT 0
ethaderu 3:78f223d34f36 4208 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
ethaderu 3:78f223d34f36 4209 #define DMA_DCHPRI1_DPA_MASK 0x40u
ethaderu 3:78f223d34f36 4210 #define DMA_DCHPRI1_DPA_SHIFT 6
ethaderu 3:78f223d34f36 4211 #define DMA_DCHPRI1_ECP_MASK 0x80u
ethaderu 3:78f223d34f36 4212 #define DMA_DCHPRI1_ECP_SHIFT 7
ethaderu 3:78f223d34f36 4213 /* DCHPRI0 Bit Fields */
ethaderu 3:78f223d34f36 4214 #define DMA_DCHPRI0_CHPRI_MASK 0xFu
ethaderu 3:78f223d34f36 4215 #define DMA_DCHPRI0_CHPRI_SHIFT 0
ethaderu 3:78f223d34f36 4216 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
ethaderu 3:78f223d34f36 4217 #define DMA_DCHPRI0_DPA_MASK 0x40u
ethaderu 3:78f223d34f36 4218 #define DMA_DCHPRI0_DPA_SHIFT 6
ethaderu 3:78f223d34f36 4219 #define DMA_DCHPRI0_ECP_MASK 0x80u
ethaderu 3:78f223d34f36 4220 #define DMA_DCHPRI0_ECP_SHIFT 7
ethaderu 3:78f223d34f36 4221 /* DCHPRI7 Bit Fields */
ethaderu 3:78f223d34f36 4222 #define DMA_DCHPRI7_CHPRI_MASK 0xFu
ethaderu 3:78f223d34f36 4223 #define DMA_DCHPRI7_CHPRI_SHIFT 0
ethaderu 3:78f223d34f36 4224 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
ethaderu 3:78f223d34f36 4225 #define DMA_DCHPRI7_DPA_MASK 0x40u
ethaderu 3:78f223d34f36 4226 #define DMA_DCHPRI7_DPA_SHIFT 6
ethaderu 3:78f223d34f36 4227 #define DMA_DCHPRI7_ECP_MASK 0x80u
ethaderu 3:78f223d34f36 4228 #define DMA_DCHPRI7_ECP_SHIFT 7
ethaderu 3:78f223d34f36 4229 /* DCHPRI6 Bit Fields */
ethaderu 3:78f223d34f36 4230 #define DMA_DCHPRI6_CHPRI_MASK 0xFu
ethaderu 3:78f223d34f36 4231 #define DMA_DCHPRI6_CHPRI_SHIFT 0
ethaderu 3:78f223d34f36 4232 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
ethaderu 3:78f223d34f36 4233 #define DMA_DCHPRI6_DPA_MASK 0x40u
ethaderu 3:78f223d34f36 4234 #define DMA_DCHPRI6_DPA_SHIFT 6
ethaderu 3:78f223d34f36 4235 #define DMA_DCHPRI6_ECP_MASK 0x80u
ethaderu 3:78f223d34f36 4236 #define DMA_DCHPRI6_ECP_SHIFT 7
ethaderu 3:78f223d34f36 4237 /* DCHPRI5 Bit Fields */
ethaderu 3:78f223d34f36 4238 #define DMA_DCHPRI5_CHPRI_MASK 0xFu
ethaderu 3:78f223d34f36 4239 #define DMA_DCHPRI5_CHPRI_SHIFT 0
ethaderu 3:78f223d34f36 4240 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
ethaderu 3:78f223d34f36 4241 #define DMA_DCHPRI5_DPA_MASK 0x40u
ethaderu 3:78f223d34f36 4242 #define DMA_DCHPRI5_DPA_SHIFT 6
ethaderu 3:78f223d34f36 4243 #define DMA_DCHPRI5_ECP_MASK 0x80u
ethaderu 3:78f223d34f36 4244 #define DMA_DCHPRI5_ECP_SHIFT 7
ethaderu 3:78f223d34f36 4245 /* DCHPRI4 Bit Fields */
ethaderu 3:78f223d34f36 4246 #define DMA_DCHPRI4_CHPRI_MASK 0xFu
ethaderu 3:78f223d34f36 4247 #define DMA_DCHPRI4_CHPRI_SHIFT 0
ethaderu 3:78f223d34f36 4248 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
ethaderu 3:78f223d34f36 4249 #define DMA_DCHPRI4_DPA_MASK 0x40u
ethaderu 3:78f223d34f36 4250 #define DMA_DCHPRI4_DPA_SHIFT 6
ethaderu 3:78f223d34f36 4251 #define DMA_DCHPRI4_ECP_MASK 0x80u
ethaderu 3:78f223d34f36 4252 #define DMA_DCHPRI4_ECP_SHIFT 7
ethaderu 3:78f223d34f36 4253 /* DCHPRI11 Bit Fields */
ethaderu 3:78f223d34f36 4254 #define DMA_DCHPRI11_CHPRI_MASK 0xFu
ethaderu 3:78f223d34f36 4255 #define DMA_DCHPRI11_CHPRI_SHIFT 0
ethaderu 3:78f223d34f36 4256 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
ethaderu 3:78f223d34f36 4257 #define DMA_DCHPRI11_DPA_MASK 0x40u
ethaderu 3:78f223d34f36 4258 #define DMA_DCHPRI11_DPA_SHIFT 6
ethaderu 3:78f223d34f36 4259 #define DMA_DCHPRI11_ECP_MASK 0x80u
ethaderu 3:78f223d34f36 4260 #define DMA_DCHPRI11_ECP_SHIFT 7
ethaderu 3:78f223d34f36 4261 /* DCHPRI10 Bit Fields */
ethaderu 3:78f223d34f36 4262 #define DMA_DCHPRI10_CHPRI_MASK 0xFu
ethaderu 3:78f223d34f36 4263 #define DMA_DCHPRI10_CHPRI_SHIFT 0
ethaderu 3:78f223d34f36 4264 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
ethaderu 3:78f223d34f36 4265 #define DMA_DCHPRI10_DPA_MASK 0x40u
ethaderu 3:78f223d34f36 4266 #define DMA_DCHPRI10_DPA_SHIFT 6
ethaderu 3:78f223d34f36 4267 #define DMA_DCHPRI10_ECP_MASK 0x80u
ethaderu 3:78f223d34f36 4268 #define DMA_DCHPRI10_ECP_SHIFT 7
ethaderu 3:78f223d34f36 4269 /* DCHPRI9 Bit Fields */
ethaderu 3:78f223d34f36 4270 #define DMA_DCHPRI9_CHPRI_MASK 0xFu
ethaderu 3:78f223d34f36 4271 #define DMA_DCHPRI9_CHPRI_SHIFT 0
ethaderu 3:78f223d34f36 4272 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
ethaderu 3:78f223d34f36 4273 #define DMA_DCHPRI9_DPA_MASK 0x40u
ethaderu 3:78f223d34f36 4274 #define DMA_DCHPRI9_DPA_SHIFT 6
ethaderu 3:78f223d34f36 4275 #define DMA_DCHPRI9_ECP_MASK 0x80u
ethaderu 3:78f223d34f36 4276 #define DMA_DCHPRI9_ECP_SHIFT 7
ethaderu 3:78f223d34f36 4277 /* DCHPRI8 Bit Fields */
ethaderu 3:78f223d34f36 4278 #define DMA_DCHPRI8_CHPRI_MASK 0xFu
ethaderu 3:78f223d34f36 4279 #define DMA_DCHPRI8_CHPRI_SHIFT 0
ethaderu 3:78f223d34f36 4280 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
ethaderu 3:78f223d34f36 4281 #define DMA_DCHPRI8_DPA_MASK 0x40u
ethaderu 3:78f223d34f36 4282 #define DMA_DCHPRI8_DPA_SHIFT 6
ethaderu 3:78f223d34f36 4283 #define DMA_DCHPRI8_ECP_MASK 0x80u
ethaderu 3:78f223d34f36 4284 #define DMA_DCHPRI8_ECP_SHIFT 7
ethaderu 3:78f223d34f36 4285 /* DCHPRI15 Bit Fields */
ethaderu 3:78f223d34f36 4286 #define DMA_DCHPRI15_CHPRI_MASK 0xFu
ethaderu 3:78f223d34f36 4287 #define DMA_DCHPRI15_CHPRI_SHIFT 0
ethaderu 3:78f223d34f36 4288 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
ethaderu 3:78f223d34f36 4289 #define DMA_DCHPRI15_DPA_MASK 0x40u
ethaderu 3:78f223d34f36 4290 #define DMA_DCHPRI15_DPA_SHIFT 6
ethaderu 3:78f223d34f36 4291 #define DMA_DCHPRI15_ECP_MASK 0x80u
ethaderu 3:78f223d34f36 4292 #define DMA_DCHPRI15_ECP_SHIFT 7
ethaderu 3:78f223d34f36 4293 /* DCHPRI14 Bit Fields */
ethaderu 3:78f223d34f36 4294 #define DMA_DCHPRI14_CHPRI_MASK 0xFu
ethaderu 3:78f223d34f36 4295 #define DMA_DCHPRI14_CHPRI_SHIFT 0
ethaderu 3:78f223d34f36 4296 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
ethaderu 3:78f223d34f36 4297 #define DMA_DCHPRI14_DPA_MASK 0x40u
ethaderu 3:78f223d34f36 4298 #define DMA_DCHPRI14_DPA_SHIFT 6
ethaderu 3:78f223d34f36 4299 #define DMA_DCHPRI14_ECP_MASK 0x80u
ethaderu 3:78f223d34f36 4300 #define DMA_DCHPRI14_ECP_SHIFT 7
ethaderu 3:78f223d34f36 4301 /* DCHPRI13 Bit Fields */
ethaderu 3:78f223d34f36 4302 #define DMA_DCHPRI13_CHPRI_MASK 0xFu
ethaderu 3:78f223d34f36 4303 #define DMA_DCHPRI13_CHPRI_SHIFT 0
ethaderu 3:78f223d34f36 4304 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
ethaderu 3:78f223d34f36 4305 #define DMA_DCHPRI13_DPA_MASK 0x40u
ethaderu 3:78f223d34f36 4306 #define DMA_DCHPRI13_DPA_SHIFT 6
ethaderu 3:78f223d34f36 4307 #define DMA_DCHPRI13_ECP_MASK 0x80u
ethaderu 3:78f223d34f36 4308 #define DMA_DCHPRI13_ECP_SHIFT 7
ethaderu 3:78f223d34f36 4309 /* DCHPRI12 Bit Fields */
ethaderu 3:78f223d34f36 4310 #define DMA_DCHPRI12_CHPRI_MASK 0xFu
ethaderu 3:78f223d34f36 4311 #define DMA_DCHPRI12_CHPRI_SHIFT 0
ethaderu 3:78f223d34f36 4312 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
ethaderu 3:78f223d34f36 4313 #define DMA_DCHPRI12_DPA_MASK 0x40u
ethaderu 3:78f223d34f36 4314 #define DMA_DCHPRI12_DPA_SHIFT 6
ethaderu 3:78f223d34f36 4315 #define DMA_DCHPRI12_ECP_MASK 0x80u
ethaderu 3:78f223d34f36 4316 #define DMA_DCHPRI12_ECP_SHIFT 7
ethaderu 3:78f223d34f36 4317 /* SADDR Bit Fields */
ethaderu 3:78f223d34f36 4318 #define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 4319 #define DMA_SADDR_SADDR_SHIFT 0
ethaderu 3:78f223d34f36 4320 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
ethaderu 3:78f223d34f36 4321 /* SOFF Bit Fields */
ethaderu 3:78f223d34f36 4322 #define DMA_SOFF_SOFF_MASK 0xFFFFu
ethaderu 3:78f223d34f36 4323 #define DMA_SOFF_SOFF_SHIFT 0
ethaderu 3:78f223d34f36 4324 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
ethaderu 3:78f223d34f36 4325 /* ATTR Bit Fields */
ethaderu 3:78f223d34f36 4326 #define DMA_ATTR_DSIZE_MASK 0x7u
ethaderu 3:78f223d34f36 4327 #define DMA_ATTR_DSIZE_SHIFT 0
ethaderu 3:78f223d34f36 4328 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
ethaderu 3:78f223d34f36 4329 #define DMA_ATTR_DMOD_MASK 0xF8u
ethaderu 3:78f223d34f36 4330 #define DMA_ATTR_DMOD_SHIFT 3
ethaderu 3:78f223d34f36 4331 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
ethaderu 3:78f223d34f36 4332 #define DMA_ATTR_SSIZE_MASK 0x700u
ethaderu 3:78f223d34f36 4333 #define DMA_ATTR_SSIZE_SHIFT 8
ethaderu 3:78f223d34f36 4334 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
ethaderu 3:78f223d34f36 4335 #define DMA_ATTR_SMOD_MASK 0xF800u
ethaderu 3:78f223d34f36 4336 #define DMA_ATTR_SMOD_SHIFT 11
ethaderu 3:78f223d34f36 4337 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
ethaderu 3:78f223d34f36 4338 /* NBYTES_MLNO Bit Fields */
ethaderu 3:78f223d34f36 4339 #define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 4340 #define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
ethaderu 3:78f223d34f36 4341 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
ethaderu 3:78f223d34f36 4342 /* NBYTES_MLOFFNO Bit Fields */
ethaderu 3:78f223d34f36 4343 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
ethaderu 3:78f223d34f36 4344 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
ethaderu 3:78f223d34f36 4345 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
ethaderu 3:78f223d34f36 4346 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
ethaderu 3:78f223d34f36 4347 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
ethaderu 3:78f223d34f36 4348 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
ethaderu 3:78f223d34f36 4349 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
ethaderu 3:78f223d34f36 4350 /* NBYTES_MLOFFYES Bit Fields */
ethaderu 3:78f223d34f36 4351 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
ethaderu 3:78f223d34f36 4352 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
ethaderu 3:78f223d34f36 4353 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
ethaderu 3:78f223d34f36 4354 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
ethaderu 3:78f223d34f36 4355 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
ethaderu 3:78f223d34f36 4356 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
ethaderu 3:78f223d34f36 4357 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
ethaderu 3:78f223d34f36 4358 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
ethaderu 3:78f223d34f36 4359 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
ethaderu 3:78f223d34f36 4360 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
ethaderu 3:78f223d34f36 4361 /* SLAST Bit Fields */
ethaderu 3:78f223d34f36 4362 #define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 4363 #define DMA_SLAST_SLAST_SHIFT 0
ethaderu 3:78f223d34f36 4364 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
ethaderu 3:78f223d34f36 4365 /* DADDR Bit Fields */
ethaderu 3:78f223d34f36 4366 #define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 4367 #define DMA_DADDR_DADDR_SHIFT 0
ethaderu 3:78f223d34f36 4368 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
ethaderu 3:78f223d34f36 4369 /* DOFF Bit Fields */
ethaderu 3:78f223d34f36 4370 #define DMA_DOFF_DOFF_MASK 0xFFFFu
ethaderu 3:78f223d34f36 4371 #define DMA_DOFF_DOFF_SHIFT 0
ethaderu 3:78f223d34f36 4372 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
ethaderu 3:78f223d34f36 4373 /* CITER_ELINKNO Bit Fields */
ethaderu 3:78f223d34f36 4374 #define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
ethaderu 3:78f223d34f36 4375 #define DMA_CITER_ELINKNO_CITER_SHIFT 0
ethaderu 3:78f223d34f36 4376 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
ethaderu 3:78f223d34f36 4377 #define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
ethaderu 3:78f223d34f36 4378 #define DMA_CITER_ELINKNO_ELINK_SHIFT 15
ethaderu 3:78f223d34f36 4379 /* CITER_ELINKYES Bit Fields */
ethaderu 3:78f223d34f36 4380 #define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
ethaderu 3:78f223d34f36 4381 #define DMA_CITER_ELINKYES_CITER_SHIFT 0
ethaderu 3:78f223d34f36 4382 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
ethaderu 3:78f223d34f36 4383 #define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
ethaderu 3:78f223d34f36 4384 #define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
ethaderu 3:78f223d34f36 4385 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
ethaderu 3:78f223d34f36 4386 #define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
ethaderu 3:78f223d34f36 4387 #define DMA_CITER_ELINKYES_ELINK_SHIFT 15
ethaderu 3:78f223d34f36 4388 /* DLAST_SGA Bit Fields */
ethaderu 3:78f223d34f36 4389 #define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 4390 #define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
ethaderu 3:78f223d34f36 4391 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
ethaderu 3:78f223d34f36 4392 /* CSR Bit Fields */
ethaderu 3:78f223d34f36 4393 #define DMA_CSR_START_MASK 0x1u
ethaderu 3:78f223d34f36 4394 #define DMA_CSR_START_SHIFT 0
ethaderu 3:78f223d34f36 4395 #define DMA_CSR_INTMAJOR_MASK 0x2u
ethaderu 3:78f223d34f36 4396 #define DMA_CSR_INTMAJOR_SHIFT 1
ethaderu 3:78f223d34f36 4397 #define DMA_CSR_INTHALF_MASK 0x4u
ethaderu 3:78f223d34f36 4398 #define DMA_CSR_INTHALF_SHIFT 2
ethaderu 3:78f223d34f36 4399 #define DMA_CSR_DREQ_MASK 0x8u
ethaderu 3:78f223d34f36 4400 #define DMA_CSR_DREQ_SHIFT 3
ethaderu 3:78f223d34f36 4401 #define DMA_CSR_ESG_MASK 0x10u
ethaderu 3:78f223d34f36 4402 #define DMA_CSR_ESG_SHIFT 4
ethaderu 3:78f223d34f36 4403 #define DMA_CSR_MAJORELINK_MASK 0x20u
ethaderu 3:78f223d34f36 4404 #define DMA_CSR_MAJORELINK_SHIFT 5
ethaderu 3:78f223d34f36 4405 #define DMA_CSR_ACTIVE_MASK 0x40u
ethaderu 3:78f223d34f36 4406 #define DMA_CSR_ACTIVE_SHIFT 6
ethaderu 3:78f223d34f36 4407 #define DMA_CSR_DONE_MASK 0x80u
ethaderu 3:78f223d34f36 4408 #define DMA_CSR_DONE_SHIFT 7
ethaderu 3:78f223d34f36 4409 #define DMA_CSR_MAJORLINKCH_MASK 0xF00u
ethaderu 3:78f223d34f36 4410 #define DMA_CSR_MAJORLINKCH_SHIFT 8
ethaderu 3:78f223d34f36 4411 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
ethaderu 3:78f223d34f36 4412 #define DMA_CSR_BWC_MASK 0xC000u
ethaderu 3:78f223d34f36 4413 #define DMA_CSR_BWC_SHIFT 14
ethaderu 3:78f223d34f36 4414 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
ethaderu 3:78f223d34f36 4415 /* BITER_ELINKNO Bit Fields */
ethaderu 3:78f223d34f36 4416 #define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
ethaderu 3:78f223d34f36 4417 #define DMA_BITER_ELINKNO_BITER_SHIFT 0
ethaderu 3:78f223d34f36 4418 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
ethaderu 3:78f223d34f36 4419 #define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
ethaderu 3:78f223d34f36 4420 #define DMA_BITER_ELINKNO_ELINK_SHIFT 15
ethaderu 3:78f223d34f36 4421 /* BITER_ELINKYES Bit Fields */
ethaderu 3:78f223d34f36 4422 #define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
ethaderu 3:78f223d34f36 4423 #define DMA_BITER_ELINKYES_BITER_SHIFT 0
ethaderu 3:78f223d34f36 4424 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
ethaderu 3:78f223d34f36 4425 #define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
ethaderu 3:78f223d34f36 4426 #define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
ethaderu 3:78f223d34f36 4427 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
ethaderu 3:78f223d34f36 4428 #define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
ethaderu 3:78f223d34f36 4429 #define DMA_BITER_ELINKYES_ELINK_SHIFT 15
ethaderu 3:78f223d34f36 4430
ethaderu 3:78f223d34f36 4431 /*!
ethaderu 3:78f223d34f36 4432 * @}
ethaderu 3:78f223d34f36 4433 */ /* end of group DMA_Register_Masks */
ethaderu 3:78f223d34f36 4434
ethaderu 3:78f223d34f36 4435
ethaderu 3:78f223d34f36 4436 /* DMA - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 4437 /** Peripheral DMA base address */
ethaderu 3:78f223d34f36 4438 #define DMA_BASE (0x40008000u)
ethaderu 3:78f223d34f36 4439 /** Peripheral DMA base pointer */
ethaderu 3:78f223d34f36 4440 #define DMA0 ((DMA_Type *)DMA_BASE)
ethaderu 3:78f223d34f36 4441 #define DMA_BASE_PTR (DMA0)
ethaderu 3:78f223d34f36 4442 /** Array initializer of DMA peripheral base addresses */
ethaderu 3:78f223d34f36 4443 #define DMA_BASE_ADDRS { DMA_BASE }
ethaderu 3:78f223d34f36 4444 /** Array initializer of DMA peripheral base pointers */
ethaderu 3:78f223d34f36 4445 #define DMA_BASE_PTRS { DMA0 }
ethaderu 3:78f223d34f36 4446 /** Interrupt vectors for the DMA peripheral type */
ethaderu 3:78f223d34f36 4447 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
ethaderu 3:78f223d34f36 4448 #define DMA_ERROR_IRQS { DMA_Error_IRQn }
ethaderu 3:78f223d34f36 4449
ethaderu 3:78f223d34f36 4450 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 4451 -- DMA - Register accessor macros
ethaderu 3:78f223d34f36 4452 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 4453
ethaderu 3:78f223d34f36 4454 /*!
ethaderu 3:78f223d34f36 4455 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
ethaderu 3:78f223d34f36 4456 * @{
ethaderu 3:78f223d34f36 4457 */
ethaderu 3:78f223d34f36 4458
ethaderu 3:78f223d34f36 4459
ethaderu 3:78f223d34f36 4460 /* DMA - Register instance definitions */
ethaderu 3:78f223d34f36 4461 /* DMA */
ethaderu 3:78f223d34f36 4462 #define DMA_CR DMA_CR_REG(DMA0)
ethaderu 3:78f223d34f36 4463 #define DMA_ES DMA_ES_REG(DMA0)
ethaderu 3:78f223d34f36 4464 #define DMA_ERQ DMA_ERQ_REG(DMA0)
ethaderu 3:78f223d34f36 4465 #define DMA_EEI DMA_EEI_REG(DMA0)
ethaderu 3:78f223d34f36 4466 #define DMA_CEEI DMA_CEEI_REG(DMA0)
ethaderu 3:78f223d34f36 4467 #define DMA_SEEI DMA_SEEI_REG(DMA0)
ethaderu 3:78f223d34f36 4468 #define DMA_CERQ DMA_CERQ_REG(DMA0)
ethaderu 3:78f223d34f36 4469 #define DMA_SERQ DMA_SERQ_REG(DMA0)
ethaderu 3:78f223d34f36 4470 #define DMA_CDNE DMA_CDNE_REG(DMA0)
ethaderu 3:78f223d34f36 4471 #define DMA_SSRT DMA_SSRT_REG(DMA0)
ethaderu 3:78f223d34f36 4472 #define DMA_CERR DMA_CERR_REG(DMA0)
ethaderu 3:78f223d34f36 4473 #define DMA_CINT DMA_CINT_REG(DMA0)
ethaderu 3:78f223d34f36 4474 #define DMA_INT DMA_INT_REG(DMA0)
ethaderu 3:78f223d34f36 4475 #define DMA_ERR DMA_ERR_REG(DMA0)
ethaderu 3:78f223d34f36 4476 #define DMA_HRS DMA_HRS_REG(DMA0)
ethaderu 3:78f223d34f36 4477 #define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA0)
ethaderu 3:78f223d34f36 4478 #define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA0)
ethaderu 3:78f223d34f36 4479 #define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA0)
ethaderu 3:78f223d34f36 4480 #define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA0)
ethaderu 3:78f223d34f36 4481 #define DMA_DCHPRI7 DMA_DCHPRI7_REG(DMA0)
ethaderu 3:78f223d34f36 4482 #define DMA_DCHPRI6 DMA_DCHPRI6_REG(DMA0)
ethaderu 3:78f223d34f36 4483 #define DMA_DCHPRI5 DMA_DCHPRI5_REG(DMA0)
ethaderu 3:78f223d34f36 4484 #define DMA_DCHPRI4 DMA_DCHPRI4_REG(DMA0)
ethaderu 3:78f223d34f36 4485 #define DMA_DCHPRI11 DMA_DCHPRI11_REG(DMA0)
ethaderu 3:78f223d34f36 4486 #define DMA_DCHPRI10 DMA_DCHPRI10_REG(DMA0)
ethaderu 3:78f223d34f36 4487 #define DMA_DCHPRI9 DMA_DCHPRI9_REG(DMA0)
ethaderu 3:78f223d34f36 4488 #define DMA_DCHPRI8 DMA_DCHPRI8_REG(DMA0)
ethaderu 3:78f223d34f36 4489 #define DMA_DCHPRI15 DMA_DCHPRI15_REG(DMA0)
ethaderu 3:78f223d34f36 4490 #define DMA_DCHPRI14 DMA_DCHPRI14_REG(DMA0)
ethaderu 3:78f223d34f36 4491 #define DMA_DCHPRI13 DMA_DCHPRI13_REG(DMA0)
ethaderu 3:78f223d34f36 4492 #define DMA_DCHPRI12 DMA_DCHPRI12_REG(DMA0)
ethaderu 3:78f223d34f36 4493 #define DMA_TCD0_SADDR DMA_SADDR_REG(DMA0,0)
ethaderu 3:78f223d34f36 4494 #define DMA_TCD0_SOFF DMA_SOFF_REG(DMA0,0)
ethaderu 3:78f223d34f36 4495 #define DMA_TCD0_ATTR DMA_ATTR_REG(DMA0,0)
ethaderu 3:78f223d34f36 4496 #define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,0)
ethaderu 3:78f223d34f36 4497 #define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,0)
ethaderu 3:78f223d34f36 4498 #define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,0)
ethaderu 3:78f223d34f36 4499 #define DMA_TCD0_SLAST DMA_SLAST_REG(DMA0,0)
ethaderu 3:78f223d34f36 4500 #define DMA_TCD0_DADDR DMA_DADDR_REG(DMA0,0)
ethaderu 3:78f223d34f36 4501 #define DMA_TCD0_DOFF DMA_DOFF_REG(DMA0,0)
ethaderu 3:78f223d34f36 4502 #define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,0)
ethaderu 3:78f223d34f36 4503 #define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,0)
ethaderu 3:78f223d34f36 4504 #define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA0,0)
ethaderu 3:78f223d34f36 4505 #define DMA_TCD0_CSR DMA_CSR_REG(DMA0,0)
ethaderu 3:78f223d34f36 4506 #define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,0)
ethaderu 3:78f223d34f36 4507 #define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,0)
ethaderu 3:78f223d34f36 4508 #define DMA_TCD1_SADDR DMA_SADDR_REG(DMA0,1)
ethaderu 3:78f223d34f36 4509 #define DMA_TCD1_SOFF DMA_SOFF_REG(DMA0,1)
ethaderu 3:78f223d34f36 4510 #define DMA_TCD1_ATTR DMA_ATTR_REG(DMA0,1)
ethaderu 3:78f223d34f36 4511 #define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,1)
ethaderu 3:78f223d34f36 4512 #define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,1)
ethaderu 3:78f223d34f36 4513 #define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,1)
ethaderu 3:78f223d34f36 4514 #define DMA_TCD1_SLAST DMA_SLAST_REG(DMA0,1)
ethaderu 3:78f223d34f36 4515 #define DMA_TCD1_DADDR DMA_DADDR_REG(DMA0,1)
ethaderu 3:78f223d34f36 4516 #define DMA_TCD1_DOFF DMA_DOFF_REG(DMA0,1)
ethaderu 3:78f223d34f36 4517 #define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,1)
ethaderu 3:78f223d34f36 4518 #define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,1)
ethaderu 3:78f223d34f36 4519 #define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA0,1)
ethaderu 3:78f223d34f36 4520 #define DMA_TCD1_CSR DMA_CSR_REG(DMA0,1)
ethaderu 3:78f223d34f36 4521 #define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,1)
ethaderu 3:78f223d34f36 4522 #define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,1)
ethaderu 3:78f223d34f36 4523 #define DMA_TCD2_SADDR DMA_SADDR_REG(DMA0,2)
ethaderu 3:78f223d34f36 4524 #define DMA_TCD2_SOFF DMA_SOFF_REG(DMA0,2)
ethaderu 3:78f223d34f36 4525 #define DMA_TCD2_ATTR DMA_ATTR_REG(DMA0,2)
ethaderu 3:78f223d34f36 4526 #define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,2)
ethaderu 3:78f223d34f36 4527 #define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,2)
ethaderu 3:78f223d34f36 4528 #define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,2)
ethaderu 3:78f223d34f36 4529 #define DMA_TCD2_SLAST DMA_SLAST_REG(DMA0,2)
ethaderu 3:78f223d34f36 4530 #define DMA_TCD2_DADDR DMA_DADDR_REG(DMA0,2)
ethaderu 3:78f223d34f36 4531 #define DMA_TCD2_DOFF DMA_DOFF_REG(DMA0,2)
ethaderu 3:78f223d34f36 4532 #define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,2)
ethaderu 3:78f223d34f36 4533 #define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,2)
ethaderu 3:78f223d34f36 4534 #define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA0,2)
ethaderu 3:78f223d34f36 4535 #define DMA_TCD2_CSR DMA_CSR_REG(DMA0,2)
ethaderu 3:78f223d34f36 4536 #define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,2)
ethaderu 3:78f223d34f36 4537 #define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,2)
ethaderu 3:78f223d34f36 4538 #define DMA_TCD3_SADDR DMA_SADDR_REG(DMA0,3)
ethaderu 3:78f223d34f36 4539 #define DMA_TCD3_SOFF DMA_SOFF_REG(DMA0,3)
ethaderu 3:78f223d34f36 4540 #define DMA_TCD3_ATTR DMA_ATTR_REG(DMA0,3)
ethaderu 3:78f223d34f36 4541 #define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,3)
ethaderu 3:78f223d34f36 4542 #define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,3)
ethaderu 3:78f223d34f36 4543 #define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,3)
ethaderu 3:78f223d34f36 4544 #define DMA_TCD3_SLAST DMA_SLAST_REG(DMA0,3)
ethaderu 3:78f223d34f36 4545 #define DMA_TCD3_DADDR DMA_DADDR_REG(DMA0,3)
ethaderu 3:78f223d34f36 4546 #define DMA_TCD3_DOFF DMA_DOFF_REG(DMA0,3)
ethaderu 3:78f223d34f36 4547 #define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,3)
ethaderu 3:78f223d34f36 4548 #define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,3)
ethaderu 3:78f223d34f36 4549 #define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA0,3)
ethaderu 3:78f223d34f36 4550 #define DMA_TCD3_CSR DMA_CSR_REG(DMA0,3)
ethaderu 3:78f223d34f36 4551 #define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,3)
ethaderu 3:78f223d34f36 4552 #define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,3)
ethaderu 3:78f223d34f36 4553 #define DMA_TCD4_SADDR DMA_SADDR_REG(DMA0,4)
ethaderu 3:78f223d34f36 4554 #define DMA_TCD4_SOFF DMA_SOFF_REG(DMA0,4)
ethaderu 3:78f223d34f36 4555 #define DMA_TCD4_ATTR DMA_ATTR_REG(DMA0,4)
ethaderu 3:78f223d34f36 4556 #define DMA_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,4)
ethaderu 3:78f223d34f36 4557 #define DMA_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,4)
ethaderu 3:78f223d34f36 4558 #define DMA_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,4)
ethaderu 3:78f223d34f36 4559 #define DMA_TCD4_SLAST DMA_SLAST_REG(DMA0,4)
ethaderu 3:78f223d34f36 4560 #define DMA_TCD4_DADDR DMA_DADDR_REG(DMA0,4)
ethaderu 3:78f223d34f36 4561 #define DMA_TCD4_DOFF DMA_DOFF_REG(DMA0,4)
ethaderu 3:78f223d34f36 4562 #define DMA_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,4)
ethaderu 3:78f223d34f36 4563 #define DMA_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,4)
ethaderu 3:78f223d34f36 4564 #define DMA_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA0,4)
ethaderu 3:78f223d34f36 4565 #define DMA_TCD4_CSR DMA_CSR_REG(DMA0,4)
ethaderu 3:78f223d34f36 4566 #define DMA_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,4)
ethaderu 3:78f223d34f36 4567 #define DMA_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,4)
ethaderu 3:78f223d34f36 4568 #define DMA_TCD5_SADDR DMA_SADDR_REG(DMA0,5)
ethaderu 3:78f223d34f36 4569 #define DMA_TCD5_SOFF DMA_SOFF_REG(DMA0,5)
ethaderu 3:78f223d34f36 4570 #define DMA_TCD5_ATTR DMA_ATTR_REG(DMA0,5)
ethaderu 3:78f223d34f36 4571 #define DMA_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,5)
ethaderu 3:78f223d34f36 4572 #define DMA_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,5)
ethaderu 3:78f223d34f36 4573 #define DMA_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,5)
ethaderu 3:78f223d34f36 4574 #define DMA_TCD5_SLAST DMA_SLAST_REG(DMA0,5)
ethaderu 3:78f223d34f36 4575 #define DMA_TCD5_DADDR DMA_DADDR_REG(DMA0,5)
ethaderu 3:78f223d34f36 4576 #define DMA_TCD5_DOFF DMA_DOFF_REG(DMA0,5)
ethaderu 3:78f223d34f36 4577 #define DMA_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,5)
ethaderu 3:78f223d34f36 4578 #define DMA_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,5)
ethaderu 3:78f223d34f36 4579 #define DMA_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA0,5)
ethaderu 3:78f223d34f36 4580 #define DMA_TCD5_CSR DMA_CSR_REG(DMA0,5)
ethaderu 3:78f223d34f36 4581 #define DMA_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,5)
ethaderu 3:78f223d34f36 4582 #define DMA_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,5)
ethaderu 3:78f223d34f36 4583 #define DMA_TCD6_SADDR DMA_SADDR_REG(DMA0,6)
ethaderu 3:78f223d34f36 4584 #define DMA_TCD6_SOFF DMA_SOFF_REG(DMA0,6)
ethaderu 3:78f223d34f36 4585 #define DMA_TCD6_ATTR DMA_ATTR_REG(DMA0,6)
ethaderu 3:78f223d34f36 4586 #define DMA_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,6)
ethaderu 3:78f223d34f36 4587 #define DMA_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,6)
ethaderu 3:78f223d34f36 4588 #define DMA_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,6)
ethaderu 3:78f223d34f36 4589 #define DMA_TCD6_SLAST DMA_SLAST_REG(DMA0,6)
ethaderu 3:78f223d34f36 4590 #define DMA_TCD6_DADDR DMA_DADDR_REG(DMA0,6)
ethaderu 3:78f223d34f36 4591 #define DMA_TCD6_DOFF DMA_DOFF_REG(DMA0,6)
ethaderu 3:78f223d34f36 4592 #define DMA_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,6)
ethaderu 3:78f223d34f36 4593 #define DMA_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,6)
ethaderu 3:78f223d34f36 4594 #define DMA_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA0,6)
ethaderu 3:78f223d34f36 4595 #define DMA_TCD6_CSR DMA_CSR_REG(DMA0,6)
ethaderu 3:78f223d34f36 4596 #define DMA_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,6)
ethaderu 3:78f223d34f36 4597 #define DMA_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,6)
ethaderu 3:78f223d34f36 4598 #define DMA_TCD7_SADDR DMA_SADDR_REG(DMA0,7)
ethaderu 3:78f223d34f36 4599 #define DMA_TCD7_SOFF DMA_SOFF_REG(DMA0,7)
ethaderu 3:78f223d34f36 4600 #define DMA_TCD7_ATTR DMA_ATTR_REG(DMA0,7)
ethaderu 3:78f223d34f36 4601 #define DMA_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,7)
ethaderu 3:78f223d34f36 4602 #define DMA_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,7)
ethaderu 3:78f223d34f36 4603 #define DMA_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,7)
ethaderu 3:78f223d34f36 4604 #define DMA_TCD7_SLAST DMA_SLAST_REG(DMA0,7)
ethaderu 3:78f223d34f36 4605 #define DMA_TCD7_DADDR DMA_DADDR_REG(DMA0,7)
ethaderu 3:78f223d34f36 4606 #define DMA_TCD7_DOFF DMA_DOFF_REG(DMA0,7)
ethaderu 3:78f223d34f36 4607 #define DMA_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,7)
ethaderu 3:78f223d34f36 4608 #define DMA_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,7)
ethaderu 3:78f223d34f36 4609 #define DMA_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA0,7)
ethaderu 3:78f223d34f36 4610 #define DMA_TCD7_CSR DMA_CSR_REG(DMA0,7)
ethaderu 3:78f223d34f36 4611 #define DMA_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,7)
ethaderu 3:78f223d34f36 4612 #define DMA_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,7)
ethaderu 3:78f223d34f36 4613 #define DMA_TCD8_SADDR DMA_SADDR_REG(DMA0,8)
ethaderu 3:78f223d34f36 4614 #define DMA_TCD8_SOFF DMA_SOFF_REG(DMA0,8)
ethaderu 3:78f223d34f36 4615 #define DMA_TCD8_ATTR DMA_ATTR_REG(DMA0,8)
ethaderu 3:78f223d34f36 4616 #define DMA_TCD8_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,8)
ethaderu 3:78f223d34f36 4617 #define DMA_TCD8_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,8)
ethaderu 3:78f223d34f36 4618 #define DMA_TCD8_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,8)
ethaderu 3:78f223d34f36 4619 #define DMA_TCD8_SLAST DMA_SLAST_REG(DMA0,8)
ethaderu 3:78f223d34f36 4620 #define DMA_TCD8_DADDR DMA_DADDR_REG(DMA0,8)
ethaderu 3:78f223d34f36 4621 #define DMA_TCD8_DOFF DMA_DOFF_REG(DMA0,8)
ethaderu 3:78f223d34f36 4622 #define DMA_TCD8_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,8)
ethaderu 3:78f223d34f36 4623 #define DMA_TCD8_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,8)
ethaderu 3:78f223d34f36 4624 #define DMA_TCD8_DLASTSGA DMA_DLAST_SGA_REG(DMA0,8)
ethaderu 3:78f223d34f36 4625 #define DMA_TCD8_CSR DMA_CSR_REG(DMA0,8)
ethaderu 3:78f223d34f36 4626 #define DMA_TCD8_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,8)
ethaderu 3:78f223d34f36 4627 #define DMA_TCD8_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,8)
ethaderu 3:78f223d34f36 4628 #define DMA_TCD9_SADDR DMA_SADDR_REG(DMA0,9)
ethaderu 3:78f223d34f36 4629 #define DMA_TCD9_SOFF DMA_SOFF_REG(DMA0,9)
ethaderu 3:78f223d34f36 4630 #define DMA_TCD9_ATTR DMA_ATTR_REG(DMA0,9)
ethaderu 3:78f223d34f36 4631 #define DMA_TCD9_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,9)
ethaderu 3:78f223d34f36 4632 #define DMA_TCD9_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,9)
ethaderu 3:78f223d34f36 4633 #define DMA_TCD9_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,9)
ethaderu 3:78f223d34f36 4634 #define DMA_TCD9_SLAST DMA_SLAST_REG(DMA0,9)
ethaderu 3:78f223d34f36 4635 #define DMA_TCD9_DADDR DMA_DADDR_REG(DMA0,9)
ethaderu 3:78f223d34f36 4636 #define DMA_TCD9_DOFF DMA_DOFF_REG(DMA0,9)
ethaderu 3:78f223d34f36 4637 #define DMA_TCD9_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,9)
ethaderu 3:78f223d34f36 4638 #define DMA_TCD9_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,9)
ethaderu 3:78f223d34f36 4639 #define DMA_TCD9_DLASTSGA DMA_DLAST_SGA_REG(DMA0,9)
ethaderu 3:78f223d34f36 4640 #define DMA_TCD9_CSR DMA_CSR_REG(DMA0,9)
ethaderu 3:78f223d34f36 4641 #define DMA_TCD9_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,9)
ethaderu 3:78f223d34f36 4642 #define DMA_TCD9_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,9)
ethaderu 3:78f223d34f36 4643 #define DMA_TCD10_SADDR DMA_SADDR_REG(DMA0,10)
ethaderu 3:78f223d34f36 4644 #define DMA_TCD10_SOFF DMA_SOFF_REG(DMA0,10)
ethaderu 3:78f223d34f36 4645 #define DMA_TCD10_ATTR DMA_ATTR_REG(DMA0,10)
ethaderu 3:78f223d34f36 4646 #define DMA_TCD10_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,10)
ethaderu 3:78f223d34f36 4647 #define DMA_TCD10_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,10)
ethaderu 3:78f223d34f36 4648 #define DMA_TCD10_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,10)
ethaderu 3:78f223d34f36 4649 #define DMA_TCD10_SLAST DMA_SLAST_REG(DMA0,10)
ethaderu 3:78f223d34f36 4650 #define DMA_TCD10_DADDR DMA_DADDR_REG(DMA0,10)
ethaderu 3:78f223d34f36 4651 #define DMA_TCD10_DOFF DMA_DOFF_REG(DMA0,10)
ethaderu 3:78f223d34f36 4652 #define DMA_TCD10_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,10)
ethaderu 3:78f223d34f36 4653 #define DMA_TCD10_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,10)
ethaderu 3:78f223d34f36 4654 #define DMA_TCD10_DLASTSGA DMA_DLAST_SGA_REG(DMA0,10)
ethaderu 3:78f223d34f36 4655 #define DMA_TCD10_CSR DMA_CSR_REG(DMA0,10)
ethaderu 3:78f223d34f36 4656 #define DMA_TCD10_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,10)
ethaderu 3:78f223d34f36 4657 #define DMA_TCD10_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,10)
ethaderu 3:78f223d34f36 4658 #define DMA_TCD11_SADDR DMA_SADDR_REG(DMA0,11)
ethaderu 3:78f223d34f36 4659 #define DMA_TCD11_SOFF DMA_SOFF_REG(DMA0,11)
ethaderu 3:78f223d34f36 4660 #define DMA_TCD11_ATTR DMA_ATTR_REG(DMA0,11)
ethaderu 3:78f223d34f36 4661 #define DMA_TCD11_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,11)
ethaderu 3:78f223d34f36 4662 #define DMA_TCD11_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,11)
ethaderu 3:78f223d34f36 4663 #define DMA_TCD11_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,11)
ethaderu 3:78f223d34f36 4664 #define DMA_TCD11_SLAST DMA_SLAST_REG(DMA0,11)
ethaderu 3:78f223d34f36 4665 #define DMA_TCD11_DADDR DMA_DADDR_REG(DMA0,11)
ethaderu 3:78f223d34f36 4666 #define DMA_TCD11_DOFF DMA_DOFF_REG(DMA0,11)
ethaderu 3:78f223d34f36 4667 #define DMA_TCD11_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,11)
ethaderu 3:78f223d34f36 4668 #define DMA_TCD11_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,11)
ethaderu 3:78f223d34f36 4669 #define DMA_TCD11_DLASTSGA DMA_DLAST_SGA_REG(DMA0,11)
ethaderu 3:78f223d34f36 4670 #define DMA_TCD11_CSR DMA_CSR_REG(DMA0,11)
ethaderu 3:78f223d34f36 4671 #define DMA_TCD11_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,11)
ethaderu 3:78f223d34f36 4672 #define DMA_TCD11_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,11)
ethaderu 3:78f223d34f36 4673 #define DMA_TCD12_SADDR DMA_SADDR_REG(DMA0,12)
ethaderu 3:78f223d34f36 4674 #define DMA_TCD12_SOFF DMA_SOFF_REG(DMA0,12)
ethaderu 3:78f223d34f36 4675 #define DMA_TCD12_ATTR DMA_ATTR_REG(DMA0,12)
ethaderu 3:78f223d34f36 4676 #define DMA_TCD12_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,12)
ethaderu 3:78f223d34f36 4677 #define DMA_TCD12_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,12)
ethaderu 3:78f223d34f36 4678 #define DMA_TCD12_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,12)
ethaderu 3:78f223d34f36 4679 #define DMA_TCD12_SLAST DMA_SLAST_REG(DMA0,12)
ethaderu 3:78f223d34f36 4680 #define DMA_TCD12_DADDR DMA_DADDR_REG(DMA0,12)
ethaderu 3:78f223d34f36 4681 #define DMA_TCD12_DOFF DMA_DOFF_REG(DMA0,12)
ethaderu 3:78f223d34f36 4682 #define DMA_TCD12_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,12)
ethaderu 3:78f223d34f36 4683 #define DMA_TCD12_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,12)
ethaderu 3:78f223d34f36 4684 #define DMA_TCD12_DLASTSGA DMA_DLAST_SGA_REG(DMA0,12)
ethaderu 3:78f223d34f36 4685 #define DMA_TCD12_CSR DMA_CSR_REG(DMA0,12)
ethaderu 3:78f223d34f36 4686 #define DMA_TCD12_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,12)
ethaderu 3:78f223d34f36 4687 #define DMA_TCD12_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,12)
ethaderu 3:78f223d34f36 4688 #define DMA_TCD13_SADDR DMA_SADDR_REG(DMA0,13)
ethaderu 3:78f223d34f36 4689 #define DMA_TCD13_SOFF DMA_SOFF_REG(DMA0,13)
ethaderu 3:78f223d34f36 4690 #define DMA_TCD13_ATTR DMA_ATTR_REG(DMA0,13)
ethaderu 3:78f223d34f36 4691 #define DMA_TCD13_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,13)
ethaderu 3:78f223d34f36 4692 #define DMA_TCD13_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,13)
ethaderu 3:78f223d34f36 4693 #define DMA_TCD13_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,13)
ethaderu 3:78f223d34f36 4694 #define DMA_TCD13_SLAST DMA_SLAST_REG(DMA0,13)
ethaderu 3:78f223d34f36 4695 #define DMA_TCD13_DADDR DMA_DADDR_REG(DMA0,13)
ethaderu 3:78f223d34f36 4696 #define DMA_TCD13_DOFF DMA_DOFF_REG(DMA0,13)
ethaderu 3:78f223d34f36 4697 #define DMA_TCD13_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,13)
ethaderu 3:78f223d34f36 4698 #define DMA_TCD13_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,13)
ethaderu 3:78f223d34f36 4699 #define DMA_TCD13_DLASTSGA DMA_DLAST_SGA_REG(DMA0,13)
ethaderu 3:78f223d34f36 4700 #define DMA_TCD13_CSR DMA_CSR_REG(DMA0,13)
ethaderu 3:78f223d34f36 4701 #define DMA_TCD13_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,13)
ethaderu 3:78f223d34f36 4702 #define DMA_TCD13_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,13)
ethaderu 3:78f223d34f36 4703 #define DMA_TCD14_SADDR DMA_SADDR_REG(DMA0,14)
ethaderu 3:78f223d34f36 4704 #define DMA_TCD14_SOFF DMA_SOFF_REG(DMA0,14)
ethaderu 3:78f223d34f36 4705 #define DMA_TCD14_ATTR DMA_ATTR_REG(DMA0,14)
ethaderu 3:78f223d34f36 4706 #define DMA_TCD14_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,14)
ethaderu 3:78f223d34f36 4707 #define DMA_TCD14_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,14)
ethaderu 3:78f223d34f36 4708 #define DMA_TCD14_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,14)
ethaderu 3:78f223d34f36 4709 #define DMA_TCD14_SLAST DMA_SLAST_REG(DMA0,14)
ethaderu 3:78f223d34f36 4710 #define DMA_TCD14_DADDR DMA_DADDR_REG(DMA0,14)
ethaderu 3:78f223d34f36 4711 #define DMA_TCD14_DOFF DMA_DOFF_REG(DMA0,14)
ethaderu 3:78f223d34f36 4712 #define DMA_TCD14_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,14)
ethaderu 3:78f223d34f36 4713 #define DMA_TCD14_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,14)
ethaderu 3:78f223d34f36 4714 #define DMA_TCD14_DLASTSGA DMA_DLAST_SGA_REG(DMA0,14)
ethaderu 3:78f223d34f36 4715 #define DMA_TCD14_CSR DMA_CSR_REG(DMA0,14)
ethaderu 3:78f223d34f36 4716 #define DMA_TCD14_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,14)
ethaderu 3:78f223d34f36 4717 #define DMA_TCD14_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,14)
ethaderu 3:78f223d34f36 4718 #define DMA_TCD15_SADDR DMA_SADDR_REG(DMA0,15)
ethaderu 3:78f223d34f36 4719 #define DMA_TCD15_SOFF DMA_SOFF_REG(DMA0,15)
ethaderu 3:78f223d34f36 4720 #define DMA_TCD15_ATTR DMA_ATTR_REG(DMA0,15)
ethaderu 3:78f223d34f36 4721 #define DMA_TCD15_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,15)
ethaderu 3:78f223d34f36 4722 #define DMA_TCD15_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,15)
ethaderu 3:78f223d34f36 4723 #define DMA_TCD15_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,15)
ethaderu 3:78f223d34f36 4724 #define DMA_TCD15_SLAST DMA_SLAST_REG(DMA0,15)
ethaderu 3:78f223d34f36 4725 #define DMA_TCD15_DADDR DMA_DADDR_REG(DMA0,15)
ethaderu 3:78f223d34f36 4726 #define DMA_TCD15_DOFF DMA_DOFF_REG(DMA0,15)
ethaderu 3:78f223d34f36 4727 #define DMA_TCD15_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,15)
ethaderu 3:78f223d34f36 4728 #define DMA_TCD15_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,15)
ethaderu 3:78f223d34f36 4729 #define DMA_TCD15_DLASTSGA DMA_DLAST_SGA_REG(DMA0,15)
ethaderu 3:78f223d34f36 4730 #define DMA_TCD15_CSR DMA_CSR_REG(DMA0,15)
ethaderu 3:78f223d34f36 4731 #define DMA_TCD15_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,15)
ethaderu 3:78f223d34f36 4732 #define DMA_TCD15_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,15)
ethaderu 3:78f223d34f36 4733
ethaderu 3:78f223d34f36 4734 /* DMA - Register array accessors */
ethaderu 3:78f223d34f36 4735 #define DMA_SADDR(index) DMA_SADDR_REG(DMA0,index)
ethaderu 3:78f223d34f36 4736 #define DMA_SOFF(index) DMA_SOFF_REG(DMA0,index)
ethaderu 3:78f223d34f36 4737 #define DMA_ATTR(index) DMA_ATTR_REG(DMA0,index)
ethaderu 3:78f223d34f36 4738 #define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA0,index)
ethaderu 3:78f223d34f36 4739 #define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA0,index)
ethaderu 3:78f223d34f36 4740 #define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA0,index)
ethaderu 3:78f223d34f36 4741 #define DMA_SLAST(index) DMA_SLAST_REG(DMA0,index)
ethaderu 3:78f223d34f36 4742 #define DMA_DADDR(index) DMA_DADDR_REG(DMA0,index)
ethaderu 3:78f223d34f36 4743 #define DMA_DOFF(index) DMA_DOFF_REG(DMA0,index)
ethaderu 3:78f223d34f36 4744 #define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA0,index)
ethaderu 3:78f223d34f36 4745 #define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA0,index)
ethaderu 3:78f223d34f36 4746 #define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA0,index)
ethaderu 3:78f223d34f36 4747 #define DMA_CSR(index) DMA_CSR_REG(DMA0,index)
ethaderu 3:78f223d34f36 4748 #define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA0,index)
ethaderu 3:78f223d34f36 4749 #define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA0,index)
ethaderu 3:78f223d34f36 4750
ethaderu 3:78f223d34f36 4751 /*!
ethaderu 3:78f223d34f36 4752 * @}
ethaderu 3:78f223d34f36 4753 */ /* end of group DMA_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 4754
ethaderu 3:78f223d34f36 4755
ethaderu 3:78f223d34f36 4756 /*!
ethaderu 3:78f223d34f36 4757 * @}
ethaderu 3:78f223d34f36 4758 */ /* end of group DMA_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 4759
ethaderu 3:78f223d34f36 4760
ethaderu 3:78f223d34f36 4761 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 4762 -- DMAMUX Peripheral Access Layer
ethaderu 3:78f223d34f36 4763 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 4764
ethaderu 3:78f223d34f36 4765 /*!
ethaderu 3:78f223d34f36 4766 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
ethaderu 3:78f223d34f36 4767 * @{
ethaderu 3:78f223d34f36 4768 */
ethaderu 3:78f223d34f36 4769
ethaderu 3:78f223d34f36 4770 /** DMAMUX - Register Layout Typedef */
ethaderu 3:78f223d34f36 4771 typedef struct {
ethaderu 3:78f223d34f36 4772 __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
ethaderu 3:78f223d34f36 4773 } DMAMUX_Type, *DMAMUX_MemMapPtr;
ethaderu 3:78f223d34f36 4774
ethaderu 3:78f223d34f36 4775 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 4776 -- DMAMUX - Register accessor macros
ethaderu 3:78f223d34f36 4777 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 4778
ethaderu 3:78f223d34f36 4779 /*!
ethaderu 3:78f223d34f36 4780 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
ethaderu 3:78f223d34f36 4781 * @{
ethaderu 3:78f223d34f36 4782 */
ethaderu 3:78f223d34f36 4783
ethaderu 3:78f223d34f36 4784
ethaderu 3:78f223d34f36 4785 /* DMAMUX - Register accessors */
ethaderu 3:78f223d34f36 4786 #define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
ethaderu 3:78f223d34f36 4787
ethaderu 3:78f223d34f36 4788 /*!
ethaderu 3:78f223d34f36 4789 * @}
ethaderu 3:78f223d34f36 4790 */ /* end of group DMAMUX_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 4791
ethaderu 3:78f223d34f36 4792
ethaderu 3:78f223d34f36 4793 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 4794 -- DMAMUX Register Masks
ethaderu 3:78f223d34f36 4795 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 4796
ethaderu 3:78f223d34f36 4797 /*!
ethaderu 3:78f223d34f36 4798 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
ethaderu 3:78f223d34f36 4799 * @{
ethaderu 3:78f223d34f36 4800 */
ethaderu 3:78f223d34f36 4801
ethaderu 3:78f223d34f36 4802 /* CHCFG Bit Fields */
ethaderu 3:78f223d34f36 4803 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
ethaderu 3:78f223d34f36 4804 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
ethaderu 3:78f223d34f36 4805 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
ethaderu 3:78f223d34f36 4806 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
ethaderu 3:78f223d34f36 4807 #define DMAMUX_CHCFG_TRIG_SHIFT 6
ethaderu 3:78f223d34f36 4808 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
ethaderu 3:78f223d34f36 4809 #define DMAMUX_CHCFG_ENBL_SHIFT 7
ethaderu 3:78f223d34f36 4810
ethaderu 3:78f223d34f36 4811 /*!
ethaderu 3:78f223d34f36 4812 * @}
ethaderu 3:78f223d34f36 4813 */ /* end of group DMAMUX_Register_Masks */
ethaderu 3:78f223d34f36 4814
ethaderu 3:78f223d34f36 4815
ethaderu 3:78f223d34f36 4816 /* DMAMUX - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 4817 /** Peripheral DMAMUX base address */
ethaderu 3:78f223d34f36 4818 #define DMAMUX_BASE (0x40021000u)
ethaderu 3:78f223d34f36 4819 /** Peripheral DMAMUX base pointer */
ethaderu 3:78f223d34f36 4820 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
ethaderu 3:78f223d34f36 4821 #define DMAMUX_BASE_PTR (DMAMUX)
ethaderu 3:78f223d34f36 4822 /** Array initializer of DMAMUX peripheral base addresses */
ethaderu 3:78f223d34f36 4823 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
ethaderu 3:78f223d34f36 4824 /** Array initializer of DMAMUX peripheral base pointers */
ethaderu 3:78f223d34f36 4825 #define DMAMUX_BASE_PTRS { DMAMUX }
ethaderu 3:78f223d34f36 4826
ethaderu 3:78f223d34f36 4827 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 4828 -- DMAMUX - Register accessor macros
ethaderu 3:78f223d34f36 4829 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 4830
ethaderu 3:78f223d34f36 4831 /*!
ethaderu 3:78f223d34f36 4832 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
ethaderu 3:78f223d34f36 4833 * @{
ethaderu 3:78f223d34f36 4834 */
ethaderu 3:78f223d34f36 4835
ethaderu 3:78f223d34f36 4836
ethaderu 3:78f223d34f36 4837 /* DMAMUX - Register instance definitions */
ethaderu 3:78f223d34f36 4838 /* DMAMUX */
ethaderu 3:78f223d34f36 4839 #define DMAMUX_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX,0)
ethaderu 3:78f223d34f36 4840 #define DMAMUX_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX,1)
ethaderu 3:78f223d34f36 4841 #define DMAMUX_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX,2)
ethaderu 3:78f223d34f36 4842 #define DMAMUX_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX,3)
ethaderu 3:78f223d34f36 4843 #define DMAMUX_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX,4)
ethaderu 3:78f223d34f36 4844 #define DMAMUX_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX,5)
ethaderu 3:78f223d34f36 4845 #define DMAMUX_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX,6)
ethaderu 3:78f223d34f36 4846 #define DMAMUX_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX,7)
ethaderu 3:78f223d34f36 4847 #define DMAMUX_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX,8)
ethaderu 3:78f223d34f36 4848 #define DMAMUX_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX,9)
ethaderu 3:78f223d34f36 4849 #define DMAMUX_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX,10)
ethaderu 3:78f223d34f36 4850 #define DMAMUX_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX,11)
ethaderu 3:78f223d34f36 4851 #define DMAMUX_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX,12)
ethaderu 3:78f223d34f36 4852 #define DMAMUX_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX,13)
ethaderu 3:78f223d34f36 4853 #define DMAMUX_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX,14)
ethaderu 3:78f223d34f36 4854 #define DMAMUX_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX,15)
ethaderu 3:78f223d34f36 4855
ethaderu 3:78f223d34f36 4856 /* DMAMUX - Register array accessors */
ethaderu 3:78f223d34f36 4857 #define DMAMUX_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX,index)
ethaderu 3:78f223d34f36 4858
ethaderu 3:78f223d34f36 4859 /*!
ethaderu 3:78f223d34f36 4860 * @}
ethaderu 3:78f223d34f36 4861 */ /* end of group DMAMUX_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 4862
ethaderu 3:78f223d34f36 4863
ethaderu 3:78f223d34f36 4864 /*!
ethaderu 3:78f223d34f36 4865 * @}
ethaderu 3:78f223d34f36 4866 */ /* end of group DMAMUX_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 4867
ethaderu 3:78f223d34f36 4868
ethaderu 3:78f223d34f36 4869 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 4870 -- ENET Peripheral Access Layer
ethaderu 3:78f223d34f36 4871 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 4872
ethaderu 3:78f223d34f36 4873 /*!
ethaderu 3:78f223d34f36 4874 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
ethaderu 3:78f223d34f36 4875 * @{
ethaderu 3:78f223d34f36 4876 */
ethaderu 3:78f223d34f36 4877
ethaderu 3:78f223d34f36 4878 /** ENET - Register Layout Typedef */
ethaderu 3:78f223d34f36 4879 typedef struct {
ethaderu 3:78f223d34f36 4880 uint8_t RESERVED_0[4];
ethaderu 3:78f223d34f36 4881 __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
ethaderu 3:78f223d34f36 4882 __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
ethaderu 3:78f223d34f36 4883 uint8_t RESERVED_1[4];
ethaderu 3:78f223d34f36 4884 __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */
ethaderu 3:78f223d34f36 4885 __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */
ethaderu 3:78f223d34f36 4886 uint8_t RESERVED_2[12];
ethaderu 3:78f223d34f36 4887 __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
ethaderu 3:78f223d34f36 4888 uint8_t RESERVED_3[24];
ethaderu 3:78f223d34f36 4889 __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
ethaderu 3:78f223d34f36 4890 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
ethaderu 3:78f223d34f36 4891 uint8_t RESERVED_4[28];
ethaderu 3:78f223d34f36 4892 __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
ethaderu 3:78f223d34f36 4893 uint8_t RESERVED_5[28];
ethaderu 3:78f223d34f36 4894 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
ethaderu 3:78f223d34f36 4895 uint8_t RESERVED_6[60];
ethaderu 3:78f223d34f36 4896 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
ethaderu 3:78f223d34f36 4897 uint8_t RESERVED_7[28];
ethaderu 3:78f223d34f36 4898 __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
ethaderu 3:78f223d34f36 4899 __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
ethaderu 3:78f223d34f36 4900 __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
ethaderu 3:78f223d34f36 4901 uint8_t RESERVED_8[40];
ethaderu 3:78f223d34f36 4902 __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
ethaderu 3:78f223d34f36 4903 __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
ethaderu 3:78f223d34f36 4904 __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
ethaderu 3:78f223d34f36 4905 __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
ethaderu 3:78f223d34f36 4906 uint8_t RESERVED_9[28];
ethaderu 3:78f223d34f36 4907 __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
ethaderu 3:78f223d34f36 4908 uint8_t RESERVED_10[56];
ethaderu 3:78f223d34f36 4909 __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */
ethaderu 3:78f223d34f36 4910 __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
ethaderu 3:78f223d34f36 4911 __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */
ethaderu 3:78f223d34f36 4912 uint8_t RESERVED_11[4];
ethaderu 3:78f223d34f36 4913 __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
ethaderu 3:78f223d34f36 4914 __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
ethaderu 3:78f223d34f36 4915 __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
ethaderu 3:78f223d34f36 4916 __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
ethaderu 3:78f223d34f36 4917 __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
ethaderu 3:78f223d34f36 4918 __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
ethaderu 3:78f223d34f36 4919 __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
ethaderu 3:78f223d34f36 4920 __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
ethaderu 3:78f223d34f36 4921 __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
ethaderu 3:78f223d34f36 4922 uint8_t RESERVED_12[12];
ethaderu 3:78f223d34f36 4923 __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
ethaderu 3:78f223d34f36 4924 __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
ethaderu 3:78f223d34f36 4925 uint8_t RESERVED_13[60];
ethaderu 3:78f223d34f36 4926 __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
ethaderu 3:78f223d34f36 4927 __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
ethaderu 3:78f223d34f36 4928 __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
ethaderu 3:78f223d34f36 4929 __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
ethaderu 3:78f223d34f36 4930 __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
ethaderu 3:78f223d34f36 4931 __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
ethaderu 3:78f223d34f36 4932 __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
ethaderu 3:78f223d34f36 4933 __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
ethaderu 3:78f223d34f36 4934 __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
ethaderu 3:78f223d34f36 4935 __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
ethaderu 3:78f223d34f36 4936 __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
ethaderu 3:78f223d34f36 4937 __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
ethaderu 3:78f223d34f36 4938 __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
ethaderu 3:78f223d34f36 4939 __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
ethaderu 3:78f223d34f36 4940 __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
ethaderu 3:78f223d34f36 4941 __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
ethaderu 3:78f223d34f36 4942 __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
ethaderu 3:78f223d34f36 4943 uint8_t RESERVED_14[4];
ethaderu 3:78f223d34f36 4944 __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
ethaderu 3:78f223d34f36 4945 __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
ethaderu 3:78f223d34f36 4946 __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
ethaderu 3:78f223d34f36 4947 __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
ethaderu 3:78f223d34f36 4948 __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
ethaderu 3:78f223d34f36 4949 __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
ethaderu 3:78f223d34f36 4950 __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
ethaderu 3:78f223d34f36 4951 __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
ethaderu 3:78f223d34f36 4952 uint8_t RESERVED_15[4];
ethaderu 3:78f223d34f36 4953 __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
ethaderu 3:78f223d34f36 4954 __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
ethaderu 3:78f223d34f36 4955 uint8_t RESERVED_16[12];
ethaderu 3:78f223d34f36 4956 __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
ethaderu 3:78f223d34f36 4957 __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
ethaderu 3:78f223d34f36 4958 __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
ethaderu 3:78f223d34f36 4959 __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
ethaderu 3:78f223d34f36 4960 __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
ethaderu 3:78f223d34f36 4961 __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
ethaderu 3:78f223d34f36 4962 __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
ethaderu 3:78f223d34f36 4963 __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
ethaderu 3:78f223d34f36 4964 uint8_t RESERVED_17[4];
ethaderu 3:78f223d34f36 4965 __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
ethaderu 3:78f223d34f36 4966 __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
ethaderu 3:78f223d34f36 4967 __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
ethaderu 3:78f223d34f36 4968 __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
ethaderu 3:78f223d34f36 4969 __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
ethaderu 3:78f223d34f36 4970 __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
ethaderu 3:78f223d34f36 4971 __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
ethaderu 3:78f223d34f36 4972 __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
ethaderu 3:78f223d34f36 4973 __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
ethaderu 3:78f223d34f36 4974 __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
ethaderu 3:78f223d34f36 4975 __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
ethaderu 3:78f223d34f36 4976 __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
ethaderu 3:78f223d34f36 4977 __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
ethaderu 3:78f223d34f36 4978 __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
ethaderu 3:78f223d34f36 4979 __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
ethaderu 3:78f223d34f36 4980 uint8_t RESERVED_18[284];
ethaderu 3:78f223d34f36 4981 __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
ethaderu 3:78f223d34f36 4982 __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
ethaderu 3:78f223d34f36 4983 __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
ethaderu 3:78f223d34f36 4984 __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
ethaderu 3:78f223d34f36 4985 __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
ethaderu 3:78f223d34f36 4986 __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
ethaderu 3:78f223d34f36 4987 __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
ethaderu 3:78f223d34f36 4988 uint8_t RESERVED_19[488];
ethaderu 3:78f223d34f36 4989 __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
ethaderu 3:78f223d34f36 4990 struct { /* offset: 0x608, array step: 0x8 */
ethaderu 3:78f223d34f36 4991 __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
ethaderu 3:78f223d34f36 4992 __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
ethaderu 3:78f223d34f36 4993 } CHANNEL[4];
ethaderu 3:78f223d34f36 4994 } ENET_Type, *ENET_MemMapPtr;
ethaderu 3:78f223d34f36 4995
ethaderu 3:78f223d34f36 4996 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 4997 -- ENET - Register accessor macros
ethaderu 3:78f223d34f36 4998 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 4999
ethaderu 3:78f223d34f36 5000 /*!
ethaderu 3:78f223d34f36 5001 * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
ethaderu 3:78f223d34f36 5002 * @{
ethaderu 3:78f223d34f36 5003 */
ethaderu 3:78f223d34f36 5004
ethaderu 3:78f223d34f36 5005
ethaderu 3:78f223d34f36 5006 /* ENET - Register accessors */
ethaderu 3:78f223d34f36 5007 #define ENET_EIR_REG(base) ((base)->EIR)
ethaderu 3:78f223d34f36 5008 #define ENET_EIMR_REG(base) ((base)->EIMR)
ethaderu 3:78f223d34f36 5009 #define ENET_RDAR_REG(base) ((base)->RDAR)
ethaderu 3:78f223d34f36 5010 #define ENET_TDAR_REG(base) ((base)->TDAR)
ethaderu 3:78f223d34f36 5011 #define ENET_ECR_REG(base) ((base)->ECR)
ethaderu 3:78f223d34f36 5012 #define ENET_MMFR_REG(base) ((base)->MMFR)
ethaderu 3:78f223d34f36 5013 #define ENET_MSCR_REG(base) ((base)->MSCR)
ethaderu 3:78f223d34f36 5014 #define ENET_MIBC_REG(base) ((base)->MIBC)
ethaderu 3:78f223d34f36 5015 #define ENET_RCR_REG(base) ((base)->RCR)
ethaderu 3:78f223d34f36 5016 #define ENET_TCR_REG(base) ((base)->TCR)
ethaderu 3:78f223d34f36 5017 #define ENET_PALR_REG(base) ((base)->PALR)
ethaderu 3:78f223d34f36 5018 #define ENET_PAUR_REG(base) ((base)->PAUR)
ethaderu 3:78f223d34f36 5019 #define ENET_OPD_REG(base) ((base)->OPD)
ethaderu 3:78f223d34f36 5020 #define ENET_IAUR_REG(base) ((base)->IAUR)
ethaderu 3:78f223d34f36 5021 #define ENET_IALR_REG(base) ((base)->IALR)
ethaderu 3:78f223d34f36 5022 #define ENET_GAUR_REG(base) ((base)->GAUR)
ethaderu 3:78f223d34f36 5023 #define ENET_GALR_REG(base) ((base)->GALR)
ethaderu 3:78f223d34f36 5024 #define ENET_TFWR_REG(base) ((base)->TFWR)
ethaderu 3:78f223d34f36 5025 #define ENET_RDSR_REG(base) ((base)->RDSR)
ethaderu 3:78f223d34f36 5026 #define ENET_TDSR_REG(base) ((base)->TDSR)
ethaderu 3:78f223d34f36 5027 #define ENET_MRBR_REG(base) ((base)->MRBR)
ethaderu 3:78f223d34f36 5028 #define ENET_RSFL_REG(base) ((base)->RSFL)
ethaderu 3:78f223d34f36 5029 #define ENET_RSEM_REG(base) ((base)->RSEM)
ethaderu 3:78f223d34f36 5030 #define ENET_RAEM_REG(base) ((base)->RAEM)
ethaderu 3:78f223d34f36 5031 #define ENET_RAFL_REG(base) ((base)->RAFL)
ethaderu 3:78f223d34f36 5032 #define ENET_TSEM_REG(base) ((base)->TSEM)
ethaderu 3:78f223d34f36 5033 #define ENET_TAEM_REG(base) ((base)->TAEM)
ethaderu 3:78f223d34f36 5034 #define ENET_TAFL_REG(base) ((base)->TAFL)
ethaderu 3:78f223d34f36 5035 #define ENET_TIPG_REG(base) ((base)->TIPG)
ethaderu 3:78f223d34f36 5036 #define ENET_FTRL_REG(base) ((base)->FTRL)
ethaderu 3:78f223d34f36 5037 #define ENET_TACC_REG(base) ((base)->TACC)
ethaderu 3:78f223d34f36 5038 #define ENET_RACC_REG(base) ((base)->RACC)
ethaderu 3:78f223d34f36 5039 #define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS)
ethaderu 3:78f223d34f36 5040 #define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT)
ethaderu 3:78f223d34f36 5041 #define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT)
ethaderu 3:78f223d34f36 5042 #define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN)
ethaderu 3:78f223d34f36 5043 #define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE)
ethaderu 3:78f223d34f36 5044 #define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE)
ethaderu 3:78f223d34f36 5045 #define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG)
ethaderu 3:78f223d34f36 5046 #define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB)
ethaderu 3:78f223d34f36 5047 #define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL)
ethaderu 3:78f223d34f36 5048 #define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64)
ethaderu 3:78f223d34f36 5049 #define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127)
ethaderu 3:78f223d34f36 5050 #define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255)
ethaderu 3:78f223d34f36 5051 #define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511)
ethaderu 3:78f223d34f36 5052 #define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023)
ethaderu 3:78f223d34f36 5053 #define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047)
ethaderu 3:78f223d34f36 5054 #define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048)
ethaderu 3:78f223d34f36 5055 #define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS)
ethaderu 3:78f223d34f36 5056 #define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK)
ethaderu 3:78f223d34f36 5057 #define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL)
ethaderu 3:78f223d34f36 5058 #define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL)
ethaderu 3:78f223d34f36 5059 #define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF)
ethaderu 3:78f223d34f36 5060 #define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL)
ethaderu 3:78f223d34f36 5061 #define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL)
ethaderu 3:78f223d34f36 5062 #define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR)
ethaderu 3:78f223d34f36 5063 #define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR)
ethaderu 3:78f223d34f36 5064 #define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC)
ethaderu 3:78f223d34f36 5065 #define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK)
ethaderu 3:78f223d34f36 5066 #define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS)
ethaderu 3:78f223d34f36 5067 #define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT)
ethaderu 3:78f223d34f36 5068 #define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT)
ethaderu 3:78f223d34f36 5069 #define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN)
ethaderu 3:78f223d34f36 5070 #define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE)
ethaderu 3:78f223d34f36 5071 #define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE)
ethaderu 3:78f223d34f36 5072 #define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG)
ethaderu 3:78f223d34f36 5073 #define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB)
ethaderu 3:78f223d34f36 5074 #define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64)
ethaderu 3:78f223d34f36 5075 #define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127)
ethaderu 3:78f223d34f36 5076 #define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255)
ethaderu 3:78f223d34f36 5077 #define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511)
ethaderu 3:78f223d34f36 5078 #define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023)
ethaderu 3:78f223d34f36 5079 #define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047)
ethaderu 3:78f223d34f36 5080 #define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048)
ethaderu 3:78f223d34f36 5081 #define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS)
ethaderu 3:78f223d34f36 5082 #define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP)
ethaderu 3:78f223d34f36 5083 #define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK)
ethaderu 3:78f223d34f36 5084 #define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC)
ethaderu 3:78f223d34f36 5085 #define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN)
ethaderu 3:78f223d34f36 5086 #define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR)
ethaderu 3:78f223d34f36 5087 #define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC)
ethaderu 3:78f223d34f36 5088 #define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK)
ethaderu 3:78f223d34f36 5089 #define ENET_ATCR_REG(base) ((base)->ATCR)
ethaderu 3:78f223d34f36 5090 #define ENET_ATVR_REG(base) ((base)->ATVR)
ethaderu 3:78f223d34f36 5091 #define ENET_ATOFF_REG(base) ((base)->ATOFF)
ethaderu 3:78f223d34f36 5092 #define ENET_ATPER_REG(base) ((base)->ATPER)
ethaderu 3:78f223d34f36 5093 #define ENET_ATCOR_REG(base) ((base)->ATCOR)
ethaderu 3:78f223d34f36 5094 #define ENET_ATINC_REG(base) ((base)->ATINC)
ethaderu 3:78f223d34f36 5095 #define ENET_ATSTMP_REG(base) ((base)->ATSTMP)
ethaderu 3:78f223d34f36 5096 #define ENET_TGSR_REG(base) ((base)->TGSR)
ethaderu 3:78f223d34f36 5097 #define ENET_TCSR_REG(base,index) ((base)->CHANNEL[index].TCSR)
ethaderu 3:78f223d34f36 5098 #define ENET_TCCR_REG(base,index) ((base)->CHANNEL[index].TCCR)
ethaderu 3:78f223d34f36 5099
ethaderu 3:78f223d34f36 5100 /*!
ethaderu 3:78f223d34f36 5101 * @}
ethaderu 3:78f223d34f36 5102 */ /* end of group ENET_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 5103
ethaderu 3:78f223d34f36 5104
ethaderu 3:78f223d34f36 5105 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 5106 -- ENET Register Masks
ethaderu 3:78f223d34f36 5107 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 5108
ethaderu 3:78f223d34f36 5109 /*!
ethaderu 3:78f223d34f36 5110 * @addtogroup ENET_Register_Masks ENET Register Masks
ethaderu 3:78f223d34f36 5111 * @{
ethaderu 3:78f223d34f36 5112 */
ethaderu 3:78f223d34f36 5113
ethaderu 3:78f223d34f36 5114 /* EIR Bit Fields */
ethaderu 3:78f223d34f36 5115 #define ENET_EIR_TS_TIMER_MASK 0x8000u
ethaderu 3:78f223d34f36 5116 #define ENET_EIR_TS_TIMER_SHIFT 15
ethaderu 3:78f223d34f36 5117 #define ENET_EIR_TS_AVAIL_MASK 0x10000u
ethaderu 3:78f223d34f36 5118 #define ENET_EIR_TS_AVAIL_SHIFT 16
ethaderu 3:78f223d34f36 5119 #define ENET_EIR_WAKEUP_MASK 0x20000u
ethaderu 3:78f223d34f36 5120 #define ENET_EIR_WAKEUP_SHIFT 17
ethaderu 3:78f223d34f36 5121 #define ENET_EIR_PLR_MASK 0x40000u
ethaderu 3:78f223d34f36 5122 #define ENET_EIR_PLR_SHIFT 18
ethaderu 3:78f223d34f36 5123 #define ENET_EIR_UN_MASK 0x80000u
ethaderu 3:78f223d34f36 5124 #define ENET_EIR_UN_SHIFT 19
ethaderu 3:78f223d34f36 5125 #define ENET_EIR_RL_MASK 0x100000u
ethaderu 3:78f223d34f36 5126 #define ENET_EIR_RL_SHIFT 20
ethaderu 3:78f223d34f36 5127 #define ENET_EIR_LC_MASK 0x200000u
ethaderu 3:78f223d34f36 5128 #define ENET_EIR_LC_SHIFT 21
ethaderu 3:78f223d34f36 5129 #define ENET_EIR_EBERR_MASK 0x400000u
ethaderu 3:78f223d34f36 5130 #define ENET_EIR_EBERR_SHIFT 22
ethaderu 3:78f223d34f36 5131 #define ENET_EIR_MII_MASK 0x800000u
ethaderu 3:78f223d34f36 5132 #define ENET_EIR_MII_SHIFT 23
ethaderu 3:78f223d34f36 5133 #define ENET_EIR_RXB_MASK 0x1000000u
ethaderu 3:78f223d34f36 5134 #define ENET_EIR_RXB_SHIFT 24
ethaderu 3:78f223d34f36 5135 #define ENET_EIR_RXF_MASK 0x2000000u
ethaderu 3:78f223d34f36 5136 #define ENET_EIR_RXF_SHIFT 25
ethaderu 3:78f223d34f36 5137 #define ENET_EIR_TXB_MASK 0x4000000u
ethaderu 3:78f223d34f36 5138 #define ENET_EIR_TXB_SHIFT 26
ethaderu 3:78f223d34f36 5139 #define ENET_EIR_TXF_MASK 0x8000000u
ethaderu 3:78f223d34f36 5140 #define ENET_EIR_TXF_SHIFT 27
ethaderu 3:78f223d34f36 5141 #define ENET_EIR_GRA_MASK 0x10000000u
ethaderu 3:78f223d34f36 5142 #define ENET_EIR_GRA_SHIFT 28
ethaderu 3:78f223d34f36 5143 #define ENET_EIR_BABT_MASK 0x20000000u
ethaderu 3:78f223d34f36 5144 #define ENET_EIR_BABT_SHIFT 29
ethaderu 3:78f223d34f36 5145 #define ENET_EIR_BABR_MASK 0x40000000u
ethaderu 3:78f223d34f36 5146 #define ENET_EIR_BABR_SHIFT 30
ethaderu 3:78f223d34f36 5147 /* EIMR Bit Fields */
ethaderu 3:78f223d34f36 5148 #define ENET_EIMR_TS_TIMER_MASK 0x8000u
ethaderu 3:78f223d34f36 5149 #define ENET_EIMR_TS_TIMER_SHIFT 15
ethaderu 3:78f223d34f36 5150 #define ENET_EIMR_TS_AVAIL_MASK 0x10000u
ethaderu 3:78f223d34f36 5151 #define ENET_EIMR_TS_AVAIL_SHIFT 16
ethaderu 3:78f223d34f36 5152 #define ENET_EIMR_WAKEUP_MASK 0x20000u
ethaderu 3:78f223d34f36 5153 #define ENET_EIMR_WAKEUP_SHIFT 17
ethaderu 3:78f223d34f36 5154 #define ENET_EIMR_PLR_MASK 0x40000u
ethaderu 3:78f223d34f36 5155 #define ENET_EIMR_PLR_SHIFT 18
ethaderu 3:78f223d34f36 5156 #define ENET_EIMR_UN_MASK 0x80000u
ethaderu 3:78f223d34f36 5157 #define ENET_EIMR_UN_SHIFT 19
ethaderu 3:78f223d34f36 5158 #define ENET_EIMR_RL_MASK 0x100000u
ethaderu 3:78f223d34f36 5159 #define ENET_EIMR_RL_SHIFT 20
ethaderu 3:78f223d34f36 5160 #define ENET_EIMR_LC_MASK 0x200000u
ethaderu 3:78f223d34f36 5161 #define ENET_EIMR_LC_SHIFT 21
ethaderu 3:78f223d34f36 5162 #define ENET_EIMR_EBERR_MASK 0x400000u
ethaderu 3:78f223d34f36 5163 #define ENET_EIMR_EBERR_SHIFT 22
ethaderu 3:78f223d34f36 5164 #define ENET_EIMR_MII_MASK 0x800000u
ethaderu 3:78f223d34f36 5165 #define ENET_EIMR_MII_SHIFT 23
ethaderu 3:78f223d34f36 5166 #define ENET_EIMR_RXB_MASK 0x1000000u
ethaderu 3:78f223d34f36 5167 #define ENET_EIMR_RXB_SHIFT 24
ethaderu 3:78f223d34f36 5168 #define ENET_EIMR_RXF_MASK 0x2000000u
ethaderu 3:78f223d34f36 5169 #define ENET_EIMR_RXF_SHIFT 25
ethaderu 3:78f223d34f36 5170 #define ENET_EIMR_TXB_MASK 0x4000000u
ethaderu 3:78f223d34f36 5171 #define ENET_EIMR_TXB_SHIFT 26
ethaderu 3:78f223d34f36 5172 #define ENET_EIMR_TXF_MASK 0x8000000u
ethaderu 3:78f223d34f36 5173 #define ENET_EIMR_TXF_SHIFT 27
ethaderu 3:78f223d34f36 5174 #define ENET_EIMR_GRA_MASK 0x10000000u
ethaderu 3:78f223d34f36 5175 #define ENET_EIMR_GRA_SHIFT 28
ethaderu 3:78f223d34f36 5176 #define ENET_EIMR_BABT_MASK 0x20000000u
ethaderu 3:78f223d34f36 5177 #define ENET_EIMR_BABT_SHIFT 29
ethaderu 3:78f223d34f36 5178 #define ENET_EIMR_BABR_MASK 0x40000000u
ethaderu 3:78f223d34f36 5179 #define ENET_EIMR_BABR_SHIFT 30
ethaderu 3:78f223d34f36 5180 /* RDAR Bit Fields */
ethaderu 3:78f223d34f36 5181 #define ENET_RDAR_RDAR_MASK 0x1000000u
ethaderu 3:78f223d34f36 5182 #define ENET_RDAR_RDAR_SHIFT 24
ethaderu 3:78f223d34f36 5183 /* TDAR Bit Fields */
ethaderu 3:78f223d34f36 5184 #define ENET_TDAR_TDAR_MASK 0x1000000u
ethaderu 3:78f223d34f36 5185 #define ENET_TDAR_TDAR_SHIFT 24
ethaderu 3:78f223d34f36 5186 /* ECR Bit Fields */
ethaderu 3:78f223d34f36 5187 #define ENET_ECR_RESET_MASK 0x1u
ethaderu 3:78f223d34f36 5188 #define ENET_ECR_RESET_SHIFT 0
ethaderu 3:78f223d34f36 5189 #define ENET_ECR_ETHEREN_MASK 0x2u
ethaderu 3:78f223d34f36 5190 #define ENET_ECR_ETHEREN_SHIFT 1
ethaderu 3:78f223d34f36 5191 #define ENET_ECR_MAGICEN_MASK 0x4u
ethaderu 3:78f223d34f36 5192 #define ENET_ECR_MAGICEN_SHIFT 2
ethaderu 3:78f223d34f36 5193 #define ENET_ECR_SLEEP_MASK 0x8u
ethaderu 3:78f223d34f36 5194 #define ENET_ECR_SLEEP_SHIFT 3
ethaderu 3:78f223d34f36 5195 #define ENET_ECR_EN1588_MASK 0x10u
ethaderu 3:78f223d34f36 5196 #define ENET_ECR_EN1588_SHIFT 4
ethaderu 3:78f223d34f36 5197 #define ENET_ECR_DBGEN_MASK 0x40u
ethaderu 3:78f223d34f36 5198 #define ENET_ECR_DBGEN_SHIFT 6
ethaderu 3:78f223d34f36 5199 #define ENET_ECR_STOPEN_MASK 0x80u
ethaderu 3:78f223d34f36 5200 #define ENET_ECR_STOPEN_SHIFT 7
ethaderu 3:78f223d34f36 5201 #define ENET_ECR_DBSWP_MASK 0x100u
ethaderu 3:78f223d34f36 5202 #define ENET_ECR_DBSWP_SHIFT 8
ethaderu 3:78f223d34f36 5203 /* MMFR Bit Fields */
ethaderu 3:78f223d34f36 5204 #define ENET_MMFR_DATA_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5205 #define ENET_MMFR_DATA_SHIFT 0
ethaderu 3:78f223d34f36 5206 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
ethaderu 3:78f223d34f36 5207 #define ENET_MMFR_TA_MASK 0x30000u
ethaderu 3:78f223d34f36 5208 #define ENET_MMFR_TA_SHIFT 16
ethaderu 3:78f223d34f36 5209 #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
ethaderu 3:78f223d34f36 5210 #define ENET_MMFR_RA_MASK 0x7C0000u
ethaderu 3:78f223d34f36 5211 #define ENET_MMFR_RA_SHIFT 18
ethaderu 3:78f223d34f36 5212 #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
ethaderu 3:78f223d34f36 5213 #define ENET_MMFR_PA_MASK 0xF800000u
ethaderu 3:78f223d34f36 5214 #define ENET_MMFR_PA_SHIFT 23
ethaderu 3:78f223d34f36 5215 #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
ethaderu 3:78f223d34f36 5216 #define ENET_MMFR_OP_MASK 0x30000000u
ethaderu 3:78f223d34f36 5217 #define ENET_MMFR_OP_SHIFT 28
ethaderu 3:78f223d34f36 5218 #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
ethaderu 3:78f223d34f36 5219 #define ENET_MMFR_ST_MASK 0xC0000000u
ethaderu 3:78f223d34f36 5220 #define ENET_MMFR_ST_SHIFT 30
ethaderu 3:78f223d34f36 5221 #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
ethaderu 3:78f223d34f36 5222 /* MSCR Bit Fields */
ethaderu 3:78f223d34f36 5223 #define ENET_MSCR_MII_SPEED_MASK 0x7Eu
ethaderu 3:78f223d34f36 5224 #define ENET_MSCR_MII_SPEED_SHIFT 1
ethaderu 3:78f223d34f36 5225 #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
ethaderu 3:78f223d34f36 5226 #define ENET_MSCR_DIS_PRE_MASK 0x80u
ethaderu 3:78f223d34f36 5227 #define ENET_MSCR_DIS_PRE_SHIFT 7
ethaderu 3:78f223d34f36 5228 #define ENET_MSCR_HOLDTIME_MASK 0x700u
ethaderu 3:78f223d34f36 5229 #define ENET_MSCR_HOLDTIME_SHIFT 8
ethaderu 3:78f223d34f36 5230 #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
ethaderu 3:78f223d34f36 5231 /* MIBC Bit Fields */
ethaderu 3:78f223d34f36 5232 #define ENET_MIBC_MIB_CLEAR_MASK 0x20000000u
ethaderu 3:78f223d34f36 5233 #define ENET_MIBC_MIB_CLEAR_SHIFT 29
ethaderu 3:78f223d34f36 5234 #define ENET_MIBC_MIB_IDLE_MASK 0x40000000u
ethaderu 3:78f223d34f36 5235 #define ENET_MIBC_MIB_IDLE_SHIFT 30
ethaderu 3:78f223d34f36 5236 #define ENET_MIBC_MIB_DIS_MASK 0x80000000u
ethaderu 3:78f223d34f36 5237 #define ENET_MIBC_MIB_DIS_SHIFT 31
ethaderu 3:78f223d34f36 5238 /* RCR Bit Fields */
ethaderu 3:78f223d34f36 5239 #define ENET_RCR_LOOP_MASK 0x1u
ethaderu 3:78f223d34f36 5240 #define ENET_RCR_LOOP_SHIFT 0
ethaderu 3:78f223d34f36 5241 #define ENET_RCR_DRT_MASK 0x2u
ethaderu 3:78f223d34f36 5242 #define ENET_RCR_DRT_SHIFT 1
ethaderu 3:78f223d34f36 5243 #define ENET_RCR_MII_MODE_MASK 0x4u
ethaderu 3:78f223d34f36 5244 #define ENET_RCR_MII_MODE_SHIFT 2
ethaderu 3:78f223d34f36 5245 #define ENET_RCR_PROM_MASK 0x8u
ethaderu 3:78f223d34f36 5246 #define ENET_RCR_PROM_SHIFT 3
ethaderu 3:78f223d34f36 5247 #define ENET_RCR_BC_REJ_MASK 0x10u
ethaderu 3:78f223d34f36 5248 #define ENET_RCR_BC_REJ_SHIFT 4
ethaderu 3:78f223d34f36 5249 #define ENET_RCR_FCE_MASK 0x20u
ethaderu 3:78f223d34f36 5250 #define ENET_RCR_FCE_SHIFT 5
ethaderu 3:78f223d34f36 5251 #define ENET_RCR_RMII_MODE_MASK 0x100u
ethaderu 3:78f223d34f36 5252 #define ENET_RCR_RMII_MODE_SHIFT 8
ethaderu 3:78f223d34f36 5253 #define ENET_RCR_RMII_10T_MASK 0x200u
ethaderu 3:78f223d34f36 5254 #define ENET_RCR_RMII_10T_SHIFT 9
ethaderu 3:78f223d34f36 5255 #define ENET_RCR_PADEN_MASK 0x1000u
ethaderu 3:78f223d34f36 5256 #define ENET_RCR_PADEN_SHIFT 12
ethaderu 3:78f223d34f36 5257 #define ENET_RCR_PAUFWD_MASK 0x2000u
ethaderu 3:78f223d34f36 5258 #define ENET_RCR_PAUFWD_SHIFT 13
ethaderu 3:78f223d34f36 5259 #define ENET_RCR_CRCFWD_MASK 0x4000u
ethaderu 3:78f223d34f36 5260 #define ENET_RCR_CRCFWD_SHIFT 14
ethaderu 3:78f223d34f36 5261 #define ENET_RCR_CFEN_MASK 0x8000u
ethaderu 3:78f223d34f36 5262 #define ENET_RCR_CFEN_SHIFT 15
ethaderu 3:78f223d34f36 5263 #define ENET_RCR_MAX_FL_MASK 0x3FFF0000u
ethaderu 3:78f223d34f36 5264 #define ENET_RCR_MAX_FL_SHIFT 16
ethaderu 3:78f223d34f36 5265 #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
ethaderu 3:78f223d34f36 5266 #define ENET_RCR_NLC_MASK 0x40000000u
ethaderu 3:78f223d34f36 5267 #define ENET_RCR_NLC_SHIFT 30
ethaderu 3:78f223d34f36 5268 #define ENET_RCR_GRS_MASK 0x80000000u
ethaderu 3:78f223d34f36 5269 #define ENET_RCR_GRS_SHIFT 31
ethaderu 3:78f223d34f36 5270 /* TCR Bit Fields */
ethaderu 3:78f223d34f36 5271 #define ENET_TCR_GTS_MASK 0x1u
ethaderu 3:78f223d34f36 5272 #define ENET_TCR_GTS_SHIFT 0
ethaderu 3:78f223d34f36 5273 #define ENET_TCR_FDEN_MASK 0x4u
ethaderu 3:78f223d34f36 5274 #define ENET_TCR_FDEN_SHIFT 2
ethaderu 3:78f223d34f36 5275 #define ENET_TCR_TFC_PAUSE_MASK 0x8u
ethaderu 3:78f223d34f36 5276 #define ENET_TCR_TFC_PAUSE_SHIFT 3
ethaderu 3:78f223d34f36 5277 #define ENET_TCR_RFC_PAUSE_MASK 0x10u
ethaderu 3:78f223d34f36 5278 #define ENET_TCR_RFC_PAUSE_SHIFT 4
ethaderu 3:78f223d34f36 5279 #define ENET_TCR_ADDSEL_MASK 0xE0u
ethaderu 3:78f223d34f36 5280 #define ENET_TCR_ADDSEL_SHIFT 5
ethaderu 3:78f223d34f36 5281 #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
ethaderu 3:78f223d34f36 5282 #define ENET_TCR_ADDINS_MASK 0x100u
ethaderu 3:78f223d34f36 5283 #define ENET_TCR_ADDINS_SHIFT 8
ethaderu 3:78f223d34f36 5284 #define ENET_TCR_CRCFWD_MASK 0x200u
ethaderu 3:78f223d34f36 5285 #define ENET_TCR_CRCFWD_SHIFT 9
ethaderu 3:78f223d34f36 5286 /* PALR Bit Fields */
ethaderu 3:78f223d34f36 5287 #define ENET_PALR_PADDR1_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 5288 #define ENET_PALR_PADDR1_SHIFT 0
ethaderu 3:78f223d34f36 5289 #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
ethaderu 3:78f223d34f36 5290 /* PAUR Bit Fields */
ethaderu 3:78f223d34f36 5291 #define ENET_PAUR_TYPE_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5292 #define ENET_PAUR_TYPE_SHIFT 0
ethaderu 3:78f223d34f36 5293 #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
ethaderu 3:78f223d34f36 5294 #define ENET_PAUR_PADDR2_MASK 0xFFFF0000u
ethaderu 3:78f223d34f36 5295 #define ENET_PAUR_PADDR2_SHIFT 16
ethaderu 3:78f223d34f36 5296 #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
ethaderu 3:78f223d34f36 5297 /* OPD Bit Fields */
ethaderu 3:78f223d34f36 5298 #define ENET_OPD_PAUSE_DUR_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5299 #define ENET_OPD_PAUSE_DUR_SHIFT 0
ethaderu 3:78f223d34f36 5300 #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
ethaderu 3:78f223d34f36 5301 #define ENET_OPD_OPCODE_MASK 0xFFFF0000u
ethaderu 3:78f223d34f36 5302 #define ENET_OPD_OPCODE_SHIFT 16
ethaderu 3:78f223d34f36 5303 #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
ethaderu 3:78f223d34f36 5304 /* IAUR Bit Fields */
ethaderu 3:78f223d34f36 5305 #define ENET_IAUR_IADDR1_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 5306 #define ENET_IAUR_IADDR1_SHIFT 0
ethaderu 3:78f223d34f36 5307 #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
ethaderu 3:78f223d34f36 5308 /* IALR Bit Fields */
ethaderu 3:78f223d34f36 5309 #define ENET_IALR_IADDR2_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 5310 #define ENET_IALR_IADDR2_SHIFT 0
ethaderu 3:78f223d34f36 5311 #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
ethaderu 3:78f223d34f36 5312 /* GAUR Bit Fields */
ethaderu 3:78f223d34f36 5313 #define ENET_GAUR_GADDR1_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 5314 #define ENET_GAUR_GADDR1_SHIFT 0
ethaderu 3:78f223d34f36 5315 #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
ethaderu 3:78f223d34f36 5316 /* GALR Bit Fields */
ethaderu 3:78f223d34f36 5317 #define ENET_GALR_GADDR2_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 5318 #define ENET_GALR_GADDR2_SHIFT 0
ethaderu 3:78f223d34f36 5319 #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
ethaderu 3:78f223d34f36 5320 /* TFWR Bit Fields */
ethaderu 3:78f223d34f36 5321 #define ENET_TFWR_TFWR_MASK 0x3Fu
ethaderu 3:78f223d34f36 5322 #define ENET_TFWR_TFWR_SHIFT 0
ethaderu 3:78f223d34f36 5323 #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
ethaderu 3:78f223d34f36 5324 #define ENET_TFWR_STRFWD_MASK 0x100u
ethaderu 3:78f223d34f36 5325 #define ENET_TFWR_STRFWD_SHIFT 8
ethaderu 3:78f223d34f36 5326 /* RDSR Bit Fields */
ethaderu 3:78f223d34f36 5327 #define ENET_RDSR_R_DES_START_MASK 0xFFFFFFF8u
ethaderu 3:78f223d34f36 5328 #define ENET_RDSR_R_DES_START_SHIFT 3
ethaderu 3:78f223d34f36 5329 #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
ethaderu 3:78f223d34f36 5330 /* TDSR Bit Fields */
ethaderu 3:78f223d34f36 5331 #define ENET_TDSR_X_DES_START_MASK 0xFFFFFFF8u
ethaderu 3:78f223d34f36 5332 #define ENET_TDSR_X_DES_START_SHIFT 3
ethaderu 3:78f223d34f36 5333 #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
ethaderu 3:78f223d34f36 5334 /* MRBR Bit Fields */
ethaderu 3:78f223d34f36 5335 #define ENET_MRBR_R_BUF_SIZE_MASK 0x3FF0u
ethaderu 3:78f223d34f36 5336 #define ENET_MRBR_R_BUF_SIZE_SHIFT 4
ethaderu 3:78f223d34f36 5337 #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
ethaderu 3:78f223d34f36 5338 /* RSFL Bit Fields */
ethaderu 3:78f223d34f36 5339 #define ENET_RSFL_RX_SECTION_FULL_MASK 0xFFu
ethaderu 3:78f223d34f36 5340 #define ENET_RSFL_RX_SECTION_FULL_SHIFT 0
ethaderu 3:78f223d34f36 5341 #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
ethaderu 3:78f223d34f36 5342 /* RSEM Bit Fields */
ethaderu 3:78f223d34f36 5343 #define ENET_RSEM_RX_SECTION_EMPTY_MASK 0xFFu
ethaderu 3:78f223d34f36 5344 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT 0
ethaderu 3:78f223d34f36 5345 #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
ethaderu 3:78f223d34f36 5346 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK 0x1F0000u
ethaderu 3:78f223d34f36 5347 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT 16
ethaderu 3:78f223d34f36 5348 #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
ethaderu 3:78f223d34f36 5349 /* RAEM Bit Fields */
ethaderu 3:78f223d34f36 5350 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK 0xFFu
ethaderu 3:78f223d34f36 5351 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT 0
ethaderu 3:78f223d34f36 5352 #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
ethaderu 3:78f223d34f36 5353 /* RAFL Bit Fields */
ethaderu 3:78f223d34f36 5354 #define ENET_RAFL_RX_ALMOST_FULL_MASK 0xFFu
ethaderu 3:78f223d34f36 5355 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT 0
ethaderu 3:78f223d34f36 5356 #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
ethaderu 3:78f223d34f36 5357 /* TSEM Bit Fields */
ethaderu 3:78f223d34f36 5358 #define ENET_TSEM_TX_SECTION_EMPTY_MASK 0xFFu
ethaderu 3:78f223d34f36 5359 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT 0
ethaderu 3:78f223d34f36 5360 #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
ethaderu 3:78f223d34f36 5361 /* TAEM Bit Fields */
ethaderu 3:78f223d34f36 5362 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK 0xFFu
ethaderu 3:78f223d34f36 5363 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT 0
ethaderu 3:78f223d34f36 5364 #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
ethaderu 3:78f223d34f36 5365 /* TAFL Bit Fields */
ethaderu 3:78f223d34f36 5366 #define ENET_TAFL_TX_ALMOST_FULL_MASK 0xFFu
ethaderu 3:78f223d34f36 5367 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT 0
ethaderu 3:78f223d34f36 5368 #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
ethaderu 3:78f223d34f36 5369 /* TIPG Bit Fields */
ethaderu 3:78f223d34f36 5370 #define ENET_TIPG_IPG_MASK 0x1Fu
ethaderu 3:78f223d34f36 5371 #define ENET_TIPG_IPG_SHIFT 0
ethaderu 3:78f223d34f36 5372 #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
ethaderu 3:78f223d34f36 5373 /* FTRL Bit Fields */
ethaderu 3:78f223d34f36 5374 #define ENET_FTRL_TRUNC_FL_MASK 0x3FFFu
ethaderu 3:78f223d34f36 5375 #define ENET_FTRL_TRUNC_FL_SHIFT 0
ethaderu 3:78f223d34f36 5376 #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
ethaderu 3:78f223d34f36 5377 /* TACC Bit Fields */
ethaderu 3:78f223d34f36 5378 #define ENET_TACC_SHIFT16_MASK 0x1u
ethaderu 3:78f223d34f36 5379 #define ENET_TACC_SHIFT16_SHIFT 0
ethaderu 3:78f223d34f36 5380 #define ENET_TACC_IPCHK_MASK 0x8u
ethaderu 3:78f223d34f36 5381 #define ENET_TACC_IPCHK_SHIFT 3
ethaderu 3:78f223d34f36 5382 #define ENET_TACC_PROCHK_MASK 0x10u
ethaderu 3:78f223d34f36 5383 #define ENET_TACC_PROCHK_SHIFT 4
ethaderu 3:78f223d34f36 5384 /* RACC Bit Fields */
ethaderu 3:78f223d34f36 5385 #define ENET_RACC_PADREM_MASK 0x1u
ethaderu 3:78f223d34f36 5386 #define ENET_RACC_PADREM_SHIFT 0
ethaderu 3:78f223d34f36 5387 #define ENET_RACC_IPDIS_MASK 0x2u
ethaderu 3:78f223d34f36 5388 #define ENET_RACC_IPDIS_SHIFT 1
ethaderu 3:78f223d34f36 5389 #define ENET_RACC_PRODIS_MASK 0x4u
ethaderu 3:78f223d34f36 5390 #define ENET_RACC_PRODIS_SHIFT 2
ethaderu 3:78f223d34f36 5391 #define ENET_RACC_LINEDIS_MASK 0x40u
ethaderu 3:78f223d34f36 5392 #define ENET_RACC_LINEDIS_SHIFT 6
ethaderu 3:78f223d34f36 5393 #define ENET_RACC_SHIFT16_MASK 0x80u
ethaderu 3:78f223d34f36 5394 #define ENET_RACC_SHIFT16_SHIFT 7
ethaderu 3:78f223d34f36 5395 /* RMON_T_PACKETS Bit Fields */
ethaderu 3:78f223d34f36 5396 #define ENET_RMON_T_PACKETS_TXPKTS_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5397 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT 0
ethaderu 3:78f223d34f36 5398 #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)
ethaderu 3:78f223d34f36 5399 /* RMON_T_BC_PKT Bit Fields */
ethaderu 3:78f223d34f36 5400 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5401 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT 0
ethaderu 3:78f223d34f36 5402 #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)
ethaderu 3:78f223d34f36 5403 /* RMON_T_MC_PKT Bit Fields */
ethaderu 3:78f223d34f36 5404 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5405 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT 0
ethaderu 3:78f223d34f36 5406 #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)
ethaderu 3:78f223d34f36 5407 /* RMON_T_CRC_ALIGN Bit Fields */
ethaderu 3:78f223d34f36 5408 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5409 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT 0
ethaderu 3:78f223d34f36 5410 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
ethaderu 3:78f223d34f36 5411 /* RMON_T_UNDERSIZE Bit Fields */
ethaderu 3:78f223d34f36 5412 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5413 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT 0
ethaderu 3:78f223d34f36 5414 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
ethaderu 3:78f223d34f36 5415 /* RMON_T_OVERSIZE Bit Fields */
ethaderu 3:78f223d34f36 5416 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5417 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT 0
ethaderu 3:78f223d34f36 5418 #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
ethaderu 3:78f223d34f36 5419 /* RMON_T_FRAG Bit Fields */
ethaderu 3:78f223d34f36 5420 #define ENET_RMON_T_FRAG_TXPKTS_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5421 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT 0
ethaderu 3:78f223d34f36 5422 #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)
ethaderu 3:78f223d34f36 5423 /* RMON_T_JAB Bit Fields */
ethaderu 3:78f223d34f36 5424 #define ENET_RMON_T_JAB_TXPKTS_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5425 #define ENET_RMON_T_JAB_TXPKTS_SHIFT 0
ethaderu 3:78f223d34f36 5426 #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)
ethaderu 3:78f223d34f36 5427 /* RMON_T_COL Bit Fields */
ethaderu 3:78f223d34f36 5428 #define ENET_RMON_T_COL_TXPKTS_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5429 #define ENET_RMON_T_COL_TXPKTS_SHIFT 0
ethaderu 3:78f223d34f36 5430 #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)
ethaderu 3:78f223d34f36 5431 /* RMON_T_P64 Bit Fields */
ethaderu 3:78f223d34f36 5432 #define ENET_RMON_T_P64_TXPKTS_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5433 #define ENET_RMON_T_P64_TXPKTS_SHIFT 0
ethaderu 3:78f223d34f36 5434 #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)
ethaderu 3:78f223d34f36 5435 /* RMON_T_P65TO127 Bit Fields */
ethaderu 3:78f223d34f36 5436 #define ENET_RMON_T_P65TO127_TXPKTS_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5437 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT 0
ethaderu 3:78f223d34f36 5438 #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)
ethaderu 3:78f223d34f36 5439 /* RMON_T_P128TO255 Bit Fields */
ethaderu 3:78f223d34f36 5440 #define ENET_RMON_T_P128TO255_TXPKTS_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5441 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT 0
ethaderu 3:78f223d34f36 5442 #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)
ethaderu 3:78f223d34f36 5443 /* RMON_T_P256TO511 Bit Fields */
ethaderu 3:78f223d34f36 5444 #define ENET_RMON_T_P256TO511_TXPKTS_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5445 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT 0
ethaderu 3:78f223d34f36 5446 #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)
ethaderu 3:78f223d34f36 5447 /* RMON_T_P512TO1023 Bit Fields */
ethaderu 3:78f223d34f36 5448 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5449 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT 0
ethaderu 3:78f223d34f36 5450 #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)
ethaderu 3:78f223d34f36 5451 /* RMON_T_P1024TO2047 Bit Fields */
ethaderu 3:78f223d34f36 5452 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5453 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT 0
ethaderu 3:78f223d34f36 5454 #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
ethaderu 3:78f223d34f36 5455 /* RMON_T_P_GTE2048 Bit Fields */
ethaderu 3:78f223d34f36 5456 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5457 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT 0
ethaderu 3:78f223d34f36 5458 #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
ethaderu 3:78f223d34f36 5459 /* RMON_T_OCTETS Bit Fields */
ethaderu 3:78f223d34f36 5460 #define ENET_RMON_T_OCTETS_TXOCTS_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 5461 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT 0
ethaderu 3:78f223d34f36 5462 #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)
ethaderu 3:78f223d34f36 5463 /* IEEE_T_FRAME_OK Bit Fields */
ethaderu 3:78f223d34f36 5464 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5465 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5466 #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)
ethaderu 3:78f223d34f36 5467 /* IEEE_T_1COL Bit Fields */
ethaderu 3:78f223d34f36 5468 #define ENET_IEEE_T_1COL_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5469 #define ENET_IEEE_T_1COL_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5470 #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)
ethaderu 3:78f223d34f36 5471 /* IEEE_T_MCOL Bit Fields */
ethaderu 3:78f223d34f36 5472 #define ENET_IEEE_T_MCOL_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5473 #define ENET_IEEE_T_MCOL_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5474 #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)
ethaderu 3:78f223d34f36 5475 /* IEEE_T_DEF Bit Fields */
ethaderu 3:78f223d34f36 5476 #define ENET_IEEE_T_DEF_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5477 #define ENET_IEEE_T_DEF_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5478 #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)
ethaderu 3:78f223d34f36 5479 /* IEEE_T_LCOL Bit Fields */
ethaderu 3:78f223d34f36 5480 #define ENET_IEEE_T_LCOL_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5481 #define ENET_IEEE_T_LCOL_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5482 #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)
ethaderu 3:78f223d34f36 5483 /* IEEE_T_EXCOL Bit Fields */
ethaderu 3:78f223d34f36 5484 #define ENET_IEEE_T_EXCOL_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5485 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5486 #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)
ethaderu 3:78f223d34f36 5487 /* IEEE_T_MACERR Bit Fields */
ethaderu 3:78f223d34f36 5488 #define ENET_IEEE_T_MACERR_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5489 #define ENET_IEEE_T_MACERR_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5490 #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)
ethaderu 3:78f223d34f36 5491 /* IEEE_T_CSERR Bit Fields */
ethaderu 3:78f223d34f36 5492 #define ENET_IEEE_T_CSERR_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5493 #define ENET_IEEE_T_CSERR_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5494 #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)
ethaderu 3:78f223d34f36 5495 /* IEEE_T_FDXFC Bit Fields */
ethaderu 3:78f223d34f36 5496 #define ENET_IEEE_T_FDXFC_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5497 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5498 #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)
ethaderu 3:78f223d34f36 5499 /* IEEE_T_OCTETS_OK Bit Fields */
ethaderu 3:78f223d34f36 5500 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 5501 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5502 #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
ethaderu 3:78f223d34f36 5503 /* RMON_R_PACKETS Bit Fields */
ethaderu 3:78f223d34f36 5504 #define ENET_RMON_R_PACKETS_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5505 #define ENET_RMON_R_PACKETS_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5506 #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)
ethaderu 3:78f223d34f36 5507 /* RMON_R_BC_PKT Bit Fields */
ethaderu 3:78f223d34f36 5508 #define ENET_RMON_R_BC_PKT_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5509 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5510 #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)
ethaderu 3:78f223d34f36 5511 /* RMON_R_MC_PKT Bit Fields */
ethaderu 3:78f223d34f36 5512 #define ENET_RMON_R_MC_PKT_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5513 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5514 #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)
ethaderu 3:78f223d34f36 5515 /* RMON_R_CRC_ALIGN Bit Fields */
ethaderu 3:78f223d34f36 5516 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5517 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5518 #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
ethaderu 3:78f223d34f36 5519 /* RMON_R_UNDERSIZE Bit Fields */
ethaderu 3:78f223d34f36 5520 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5521 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5522 #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)
ethaderu 3:78f223d34f36 5523 /* RMON_R_OVERSIZE Bit Fields */
ethaderu 3:78f223d34f36 5524 #define ENET_RMON_R_OVERSIZE_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5525 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5526 #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)
ethaderu 3:78f223d34f36 5527 /* RMON_R_FRAG Bit Fields */
ethaderu 3:78f223d34f36 5528 #define ENET_RMON_R_FRAG_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5529 #define ENET_RMON_R_FRAG_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5530 #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)
ethaderu 3:78f223d34f36 5531 /* RMON_R_JAB Bit Fields */
ethaderu 3:78f223d34f36 5532 #define ENET_RMON_R_JAB_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5533 #define ENET_RMON_R_JAB_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5534 #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)
ethaderu 3:78f223d34f36 5535 /* RMON_R_P64 Bit Fields */
ethaderu 3:78f223d34f36 5536 #define ENET_RMON_R_P64_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5537 #define ENET_RMON_R_P64_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5538 #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)
ethaderu 3:78f223d34f36 5539 /* RMON_R_P65TO127 Bit Fields */
ethaderu 3:78f223d34f36 5540 #define ENET_RMON_R_P65TO127_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5541 #define ENET_RMON_R_P65TO127_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5542 #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)
ethaderu 3:78f223d34f36 5543 /* RMON_R_P128TO255 Bit Fields */
ethaderu 3:78f223d34f36 5544 #define ENET_RMON_R_P128TO255_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5545 #define ENET_RMON_R_P128TO255_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5546 #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)
ethaderu 3:78f223d34f36 5547 /* RMON_R_P256TO511 Bit Fields */
ethaderu 3:78f223d34f36 5548 #define ENET_RMON_R_P256TO511_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5549 #define ENET_RMON_R_P256TO511_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5550 #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)
ethaderu 3:78f223d34f36 5551 /* RMON_R_P512TO1023 Bit Fields */
ethaderu 3:78f223d34f36 5552 #define ENET_RMON_R_P512TO1023_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5553 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5554 #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)
ethaderu 3:78f223d34f36 5555 /* RMON_R_P1024TO2047 Bit Fields */
ethaderu 3:78f223d34f36 5556 #define ENET_RMON_R_P1024TO2047_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5557 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5558 #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)
ethaderu 3:78f223d34f36 5559 /* RMON_R_P_GTE2048 Bit Fields */
ethaderu 3:78f223d34f36 5560 #define ENET_RMON_R_P_GTE2048_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5561 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5562 #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK)
ethaderu 3:78f223d34f36 5563 /* RMON_R_OCTETS Bit Fields */
ethaderu 3:78f223d34f36 5564 #define ENET_RMON_R_OCTETS_COUNT_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 5565 #define ENET_RMON_R_OCTETS_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5566 #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)
ethaderu 3:78f223d34f36 5567 /* IEEE_R_DROP Bit Fields */
ethaderu 3:78f223d34f36 5568 #define ENET_IEEE_R_DROP_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5569 #define ENET_IEEE_R_DROP_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5570 #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)
ethaderu 3:78f223d34f36 5571 /* IEEE_R_FRAME_OK Bit Fields */
ethaderu 3:78f223d34f36 5572 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5573 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5574 #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)
ethaderu 3:78f223d34f36 5575 /* IEEE_R_CRC Bit Fields */
ethaderu 3:78f223d34f36 5576 #define ENET_IEEE_R_CRC_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5577 #define ENET_IEEE_R_CRC_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5578 #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)
ethaderu 3:78f223d34f36 5579 /* IEEE_R_ALIGN Bit Fields */
ethaderu 3:78f223d34f36 5580 #define ENET_IEEE_R_ALIGN_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5581 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5582 #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)
ethaderu 3:78f223d34f36 5583 /* IEEE_R_MACERR Bit Fields */
ethaderu 3:78f223d34f36 5584 #define ENET_IEEE_R_MACERR_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5585 #define ENET_IEEE_R_MACERR_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5586 #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)
ethaderu 3:78f223d34f36 5587 /* IEEE_R_FDXFC Bit Fields */
ethaderu 3:78f223d34f36 5588 #define ENET_IEEE_R_FDXFC_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 5589 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5590 #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)
ethaderu 3:78f223d34f36 5591 /* IEEE_R_OCTETS_OK Bit Fields */
ethaderu 3:78f223d34f36 5592 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 5593 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 5594 #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
ethaderu 3:78f223d34f36 5595 /* ATCR Bit Fields */
ethaderu 3:78f223d34f36 5596 #define ENET_ATCR_EN_MASK 0x1u
ethaderu 3:78f223d34f36 5597 #define ENET_ATCR_EN_SHIFT 0
ethaderu 3:78f223d34f36 5598 #define ENET_ATCR_OFFEN_MASK 0x4u
ethaderu 3:78f223d34f36 5599 #define ENET_ATCR_OFFEN_SHIFT 2
ethaderu 3:78f223d34f36 5600 #define ENET_ATCR_OFFRST_MASK 0x8u
ethaderu 3:78f223d34f36 5601 #define ENET_ATCR_OFFRST_SHIFT 3
ethaderu 3:78f223d34f36 5602 #define ENET_ATCR_PEREN_MASK 0x10u
ethaderu 3:78f223d34f36 5603 #define ENET_ATCR_PEREN_SHIFT 4
ethaderu 3:78f223d34f36 5604 #define ENET_ATCR_PINPER_MASK 0x80u
ethaderu 3:78f223d34f36 5605 #define ENET_ATCR_PINPER_SHIFT 7
ethaderu 3:78f223d34f36 5606 #define ENET_ATCR_RESTART_MASK 0x200u
ethaderu 3:78f223d34f36 5607 #define ENET_ATCR_RESTART_SHIFT 9
ethaderu 3:78f223d34f36 5608 #define ENET_ATCR_CAPTURE_MASK 0x800u
ethaderu 3:78f223d34f36 5609 #define ENET_ATCR_CAPTURE_SHIFT 11
ethaderu 3:78f223d34f36 5610 #define ENET_ATCR_SLAVE_MASK 0x2000u
ethaderu 3:78f223d34f36 5611 #define ENET_ATCR_SLAVE_SHIFT 13
ethaderu 3:78f223d34f36 5612 /* ATVR Bit Fields */
ethaderu 3:78f223d34f36 5613 #define ENET_ATVR_ATIME_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 5614 #define ENET_ATVR_ATIME_SHIFT 0
ethaderu 3:78f223d34f36 5615 #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
ethaderu 3:78f223d34f36 5616 /* ATOFF Bit Fields */
ethaderu 3:78f223d34f36 5617 #define ENET_ATOFF_OFFSET_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 5618 #define ENET_ATOFF_OFFSET_SHIFT 0
ethaderu 3:78f223d34f36 5619 #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
ethaderu 3:78f223d34f36 5620 /* ATPER Bit Fields */
ethaderu 3:78f223d34f36 5621 #define ENET_ATPER_PERIOD_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 5622 #define ENET_ATPER_PERIOD_SHIFT 0
ethaderu 3:78f223d34f36 5623 #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
ethaderu 3:78f223d34f36 5624 /* ATCOR Bit Fields */
ethaderu 3:78f223d34f36 5625 #define ENET_ATCOR_COR_MASK 0x7FFFFFFFu
ethaderu 3:78f223d34f36 5626 #define ENET_ATCOR_COR_SHIFT 0
ethaderu 3:78f223d34f36 5627 #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
ethaderu 3:78f223d34f36 5628 /* ATINC Bit Fields */
ethaderu 3:78f223d34f36 5629 #define ENET_ATINC_INC_MASK 0x7Fu
ethaderu 3:78f223d34f36 5630 #define ENET_ATINC_INC_SHIFT 0
ethaderu 3:78f223d34f36 5631 #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
ethaderu 3:78f223d34f36 5632 #define ENET_ATINC_INC_CORR_MASK 0x7F00u
ethaderu 3:78f223d34f36 5633 #define ENET_ATINC_INC_CORR_SHIFT 8
ethaderu 3:78f223d34f36 5634 #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
ethaderu 3:78f223d34f36 5635 /* ATSTMP Bit Fields */
ethaderu 3:78f223d34f36 5636 #define ENET_ATSTMP_TIMESTAMP_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 5637 #define ENET_ATSTMP_TIMESTAMP_SHIFT 0
ethaderu 3:78f223d34f36 5638 #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
ethaderu 3:78f223d34f36 5639 /* TGSR Bit Fields */
ethaderu 3:78f223d34f36 5640 #define ENET_TGSR_TF0_MASK 0x1u
ethaderu 3:78f223d34f36 5641 #define ENET_TGSR_TF0_SHIFT 0
ethaderu 3:78f223d34f36 5642 #define ENET_TGSR_TF1_MASK 0x2u
ethaderu 3:78f223d34f36 5643 #define ENET_TGSR_TF1_SHIFT 1
ethaderu 3:78f223d34f36 5644 #define ENET_TGSR_TF2_MASK 0x4u
ethaderu 3:78f223d34f36 5645 #define ENET_TGSR_TF2_SHIFT 2
ethaderu 3:78f223d34f36 5646 #define ENET_TGSR_TF3_MASK 0x8u
ethaderu 3:78f223d34f36 5647 #define ENET_TGSR_TF3_SHIFT 3
ethaderu 3:78f223d34f36 5648 /* TCSR Bit Fields */
ethaderu 3:78f223d34f36 5649 #define ENET_TCSR_TDRE_MASK 0x1u
ethaderu 3:78f223d34f36 5650 #define ENET_TCSR_TDRE_SHIFT 0
ethaderu 3:78f223d34f36 5651 #define ENET_TCSR_TMODE_MASK 0x3Cu
ethaderu 3:78f223d34f36 5652 #define ENET_TCSR_TMODE_SHIFT 2
ethaderu 3:78f223d34f36 5653 #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
ethaderu 3:78f223d34f36 5654 #define ENET_TCSR_TIE_MASK 0x40u
ethaderu 3:78f223d34f36 5655 #define ENET_TCSR_TIE_SHIFT 6
ethaderu 3:78f223d34f36 5656 #define ENET_TCSR_TF_MASK 0x80u
ethaderu 3:78f223d34f36 5657 #define ENET_TCSR_TF_SHIFT 7
ethaderu 3:78f223d34f36 5658 /* TCCR Bit Fields */
ethaderu 3:78f223d34f36 5659 #define ENET_TCCR_TCC_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 5660 #define ENET_TCCR_TCC_SHIFT 0
ethaderu 3:78f223d34f36 5661 #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
ethaderu 3:78f223d34f36 5662
ethaderu 3:78f223d34f36 5663 /*!
ethaderu 3:78f223d34f36 5664 * @}
ethaderu 3:78f223d34f36 5665 */ /* end of group ENET_Register_Masks */
ethaderu 3:78f223d34f36 5666
ethaderu 3:78f223d34f36 5667
ethaderu 3:78f223d34f36 5668 /* ENET - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 5669 /** Peripheral ENET base address */
ethaderu 3:78f223d34f36 5670 #define ENET_BASE (0x400C0000u)
ethaderu 3:78f223d34f36 5671 /** Peripheral ENET base pointer */
ethaderu 3:78f223d34f36 5672 #define ENET ((ENET_Type *)ENET_BASE)
ethaderu 3:78f223d34f36 5673 #define ENET_BASE_PTR (ENET)
ethaderu 3:78f223d34f36 5674 /** Array initializer of ENET peripheral base addresses */
ethaderu 3:78f223d34f36 5675 #define ENET_BASE_ADDRS { ENET_BASE }
ethaderu 3:78f223d34f36 5676 /** Array initializer of ENET peripheral base pointers */
ethaderu 3:78f223d34f36 5677 #define ENET_BASE_PTRS { ENET }
ethaderu 3:78f223d34f36 5678 /** Interrupt vectors for the ENET peripheral type */
ethaderu 3:78f223d34f36 5679 #define ENET_Transmit_IRQS { ENET_Transmit_IRQn }
ethaderu 3:78f223d34f36 5680 #define ENET_Receive_IRQS { ENET_Receive_IRQn }
ethaderu 3:78f223d34f36 5681 #define ENET_Error_IRQS { ENET_Error_IRQn }
ethaderu 3:78f223d34f36 5682 #define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }
ethaderu 3:78f223d34f36 5683
ethaderu 3:78f223d34f36 5684 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 5685 -- ENET - Register accessor macros
ethaderu 3:78f223d34f36 5686 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 5687
ethaderu 3:78f223d34f36 5688 /*!
ethaderu 3:78f223d34f36 5689 * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
ethaderu 3:78f223d34f36 5690 * @{
ethaderu 3:78f223d34f36 5691 */
ethaderu 3:78f223d34f36 5692
ethaderu 3:78f223d34f36 5693
ethaderu 3:78f223d34f36 5694 /* ENET - Register instance definitions */
ethaderu 3:78f223d34f36 5695 /* ENET */
ethaderu 3:78f223d34f36 5696 #define ENET_EIR ENET_EIR_REG(ENET)
ethaderu 3:78f223d34f36 5697 #define ENET_EIMR ENET_EIMR_REG(ENET)
ethaderu 3:78f223d34f36 5698 #define ENET_RDAR ENET_RDAR_REG(ENET)
ethaderu 3:78f223d34f36 5699 #define ENET_TDAR ENET_TDAR_REG(ENET)
ethaderu 3:78f223d34f36 5700 #define ENET_ECR ENET_ECR_REG(ENET)
ethaderu 3:78f223d34f36 5701 #define ENET_MMFR ENET_MMFR_REG(ENET)
ethaderu 3:78f223d34f36 5702 #define ENET_MSCR ENET_MSCR_REG(ENET)
ethaderu 3:78f223d34f36 5703 #define ENET_MIBC ENET_MIBC_REG(ENET)
ethaderu 3:78f223d34f36 5704 #define ENET_RCR ENET_RCR_REG(ENET)
ethaderu 3:78f223d34f36 5705 #define ENET_TCR ENET_TCR_REG(ENET)
ethaderu 3:78f223d34f36 5706 #define ENET_PALR ENET_PALR_REG(ENET)
ethaderu 3:78f223d34f36 5707 #define ENET_PAUR ENET_PAUR_REG(ENET)
ethaderu 3:78f223d34f36 5708 #define ENET_OPD ENET_OPD_REG(ENET)
ethaderu 3:78f223d34f36 5709 #define ENET_IAUR ENET_IAUR_REG(ENET)
ethaderu 3:78f223d34f36 5710 #define ENET_IALR ENET_IALR_REG(ENET)
ethaderu 3:78f223d34f36 5711 #define ENET_GAUR ENET_GAUR_REG(ENET)
ethaderu 3:78f223d34f36 5712 #define ENET_GALR ENET_GALR_REG(ENET)
ethaderu 3:78f223d34f36 5713 #define ENET_TFWR ENET_TFWR_REG(ENET)
ethaderu 3:78f223d34f36 5714 #define ENET_RDSR ENET_RDSR_REG(ENET)
ethaderu 3:78f223d34f36 5715 #define ENET_TDSR ENET_TDSR_REG(ENET)
ethaderu 3:78f223d34f36 5716 #define ENET_MRBR ENET_MRBR_REG(ENET)
ethaderu 3:78f223d34f36 5717 #define ENET_RSFL ENET_RSFL_REG(ENET)
ethaderu 3:78f223d34f36 5718 #define ENET_RSEM ENET_RSEM_REG(ENET)
ethaderu 3:78f223d34f36 5719 #define ENET_RAEM ENET_RAEM_REG(ENET)
ethaderu 3:78f223d34f36 5720 #define ENET_RAFL ENET_RAFL_REG(ENET)
ethaderu 3:78f223d34f36 5721 #define ENET_TSEM ENET_TSEM_REG(ENET)
ethaderu 3:78f223d34f36 5722 #define ENET_TAEM ENET_TAEM_REG(ENET)
ethaderu 3:78f223d34f36 5723 #define ENET_TAFL ENET_TAFL_REG(ENET)
ethaderu 3:78f223d34f36 5724 #define ENET_TIPG ENET_TIPG_REG(ENET)
ethaderu 3:78f223d34f36 5725 #define ENET_FTRL ENET_FTRL_REG(ENET)
ethaderu 3:78f223d34f36 5726 #define ENET_TACC ENET_TACC_REG(ENET)
ethaderu 3:78f223d34f36 5727 #define ENET_RACC ENET_RACC_REG(ENET)
ethaderu 3:78f223d34f36 5728 #define ENET_RMON_T_PACKETS ENET_RMON_T_PACKETS_REG(ENET)
ethaderu 3:78f223d34f36 5729 #define ENET_RMON_T_BC_PKT ENET_RMON_T_BC_PKT_REG(ENET)
ethaderu 3:78f223d34f36 5730 #define ENET_RMON_T_MC_PKT ENET_RMON_T_MC_PKT_REG(ENET)
ethaderu 3:78f223d34f36 5731 #define ENET_RMON_T_CRC_ALIGN ENET_RMON_T_CRC_ALIGN_REG(ENET)
ethaderu 3:78f223d34f36 5732 #define ENET_RMON_T_UNDERSIZE ENET_RMON_T_UNDERSIZE_REG(ENET)
ethaderu 3:78f223d34f36 5733 #define ENET_RMON_T_OVERSIZE ENET_RMON_T_OVERSIZE_REG(ENET)
ethaderu 3:78f223d34f36 5734 #define ENET_RMON_T_FRAG ENET_RMON_T_FRAG_REG(ENET)
ethaderu 3:78f223d34f36 5735 #define ENET_RMON_T_JAB ENET_RMON_T_JAB_REG(ENET)
ethaderu 3:78f223d34f36 5736 #define ENET_RMON_T_COL ENET_RMON_T_COL_REG(ENET)
ethaderu 3:78f223d34f36 5737 #define ENET_RMON_T_P64 ENET_RMON_T_P64_REG(ENET)
ethaderu 3:78f223d34f36 5738 #define ENET_RMON_T_P65TO127 ENET_RMON_T_P65TO127_REG(ENET)
ethaderu 3:78f223d34f36 5739 #define ENET_RMON_T_P128TO255 ENET_RMON_T_P128TO255_REG(ENET)
ethaderu 3:78f223d34f36 5740 #define ENET_RMON_T_P256TO511 ENET_RMON_T_P256TO511_REG(ENET)
ethaderu 3:78f223d34f36 5741 #define ENET_RMON_T_P512TO1023 ENET_RMON_T_P512TO1023_REG(ENET)
ethaderu 3:78f223d34f36 5742 #define ENET_RMON_T_P1024TO2047 ENET_RMON_T_P1024TO2047_REG(ENET)
ethaderu 3:78f223d34f36 5743 #define ENET_RMON_T_P_GTE2048 ENET_RMON_T_P_GTE2048_REG(ENET)
ethaderu 3:78f223d34f36 5744 #define ENET_RMON_T_OCTETS ENET_RMON_T_OCTETS_REG(ENET)
ethaderu 3:78f223d34f36 5745 #define ENET_IEEE_T_FRAME_OK ENET_IEEE_T_FRAME_OK_REG(ENET)
ethaderu 3:78f223d34f36 5746 #define ENET_IEEE_T_1COL ENET_IEEE_T_1COL_REG(ENET)
ethaderu 3:78f223d34f36 5747 #define ENET_IEEE_T_MCOL ENET_IEEE_T_MCOL_REG(ENET)
ethaderu 3:78f223d34f36 5748 #define ENET_IEEE_T_DEF ENET_IEEE_T_DEF_REG(ENET)
ethaderu 3:78f223d34f36 5749 #define ENET_IEEE_T_LCOL ENET_IEEE_T_LCOL_REG(ENET)
ethaderu 3:78f223d34f36 5750 #define ENET_IEEE_T_EXCOL ENET_IEEE_T_EXCOL_REG(ENET)
ethaderu 3:78f223d34f36 5751 #define ENET_IEEE_T_MACERR ENET_IEEE_T_MACERR_REG(ENET)
ethaderu 3:78f223d34f36 5752 #define ENET_IEEE_T_CSERR ENET_IEEE_T_CSERR_REG(ENET)
ethaderu 3:78f223d34f36 5753 #define ENET_IEEE_T_FDXFC ENET_IEEE_T_FDXFC_REG(ENET)
ethaderu 3:78f223d34f36 5754 #define ENET_IEEE_T_OCTETS_OK ENET_IEEE_T_OCTETS_OK_REG(ENET)
ethaderu 3:78f223d34f36 5755 #define ENET_RMON_R_PACKETS ENET_RMON_R_PACKETS_REG(ENET)
ethaderu 3:78f223d34f36 5756 #define ENET_RMON_R_BC_PKT ENET_RMON_R_BC_PKT_REG(ENET)
ethaderu 3:78f223d34f36 5757 #define ENET_RMON_R_MC_PKT ENET_RMON_R_MC_PKT_REG(ENET)
ethaderu 3:78f223d34f36 5758 #define ENET_RMON_R_CRC_ALIGN ENET_RMON_R_CRC_ALIGN_REG(ENET)
ethaderu 3:78f223d34f36 5759 #define ENET_RMON_R_UNDERSIZE ENET_RMON_R_UNDERSIZE_REG(ENET)
ethaderu 3:78f223d34f36 5760 #define ENET_RMON_R_OVERSIZE ENET_RMON_R_OVERSIZE_REG(ENET)
ethaderu 3:78f223d34f36 5761 #define ENET_RMON_R_FRAG ENET_RMON_R_FRAG_REG(ENET)
ethaderu 3:78f223d34f36 5762 #define ENET_RMON_R_JAB ENET_RMON_R_JAB_REG(ENET)
ethaderu 3:78f223d34f36 5763 #define ENET_RMON_R_P64 ENET_RMON_R_P64_REG(ENET)
ethaderu 3:78f223d34f36 5764 #define ENET_RMON_R_P65TO127 ENET_RMON_R_P65TO127_REG(ENET)
ethaderu 3:78f223d34f36 5765 #define ENET_RMON_R_P128TO255 ENET_RMON_R_P128TO255_REG(ENET)
ethaderu 3:78f223d34f36 5766 #define ENET_RMON_R_P256TO511 ENET_RMON_R_P256TO511_REG(ENET)
ethaderu 3:78f223d34f36 5767 #define ENET_RMON_R_P512TO1023 ENET_RMON_R_P512TO1023_REG(ENET)
ethaderu 3:78f223d34f36 5768 #define ENET_RMON_R_P1024TO2047 ENET_RMON_R_P1024TO2047_REG(ENET)
ethaderu 3:78f223d34f36 5769 #define ENET_RMON_R_P_GTE2048 ENET_RMON_R_P_GTE2048_REG(ENET)
ethaderu 3:78f223d34f36 5770 #define ENET_RMON_R_OCTETS ENET_RMON_R_OCTETS_REG(ENET)
ethaderu 3:78f223d34f36 5771 #define ENET_IEEE_R_DROP ENET_IEEE_R_DROP_REG(ENET)
ethaderu 3:78f223d34f36 5772 #define ENET_IEEE_R_FRAME_OK ENET_IEEE_R_FRAME_OK_REG(ENET)
ethaderu 3:78f223d34f36 5773 #define ENET_IEEE_R_CRC ENET_IEEE_R_CRC_REG(ENET)
ethaderu 3:78f223d34f36 5774 #define ENET_IEEE_R_ALIGN ENET_IEEE_R_ALIGN_REG(ENET)
ethaderu 3:78f223d34f36 5775 #define ENET_IEEE_R_MACERR ENET_IEEE_R_MACERR_REG(ENET)
ethaderu 3:78f223d34f36 5776 #define ENET_IEEE_R_FDXFC ENET_IEEE_R_FDXFC_REG(ENET)
ethaderu 3:78f223d34f36 5777 #define ENET_IEEE_R_OCTETS_OK ENET_IEEE_R_OCTETS_OK_REG(ENET)
ethaderu 3:78f223d34f36 5778 #define ENET_ATCR ENET_ATCR_REG(ENET)
ethaderu 3:78f223d34f36 5779 #define ENET_ATVR ENET_ATVR_REG(ENET)
ethaderu 3:78f223d34f36 5780 #define ENET_ATOFF ENET_ATOFF_REG(ENET)
ethaderu 3:78f223d34f36 5781 #define ENET_ATPER ENET_ATPER_REG(ENET)
ethaderu 3:78f223d34f36 5782 #define ENET_ATCOR ENET_ATCOR_REG(ENET)
ethaderu 3:78f223d34f36 5783 #define ENET_ATINC ENET_ATINC_REG(ENET)
ethaderu 3:78f223d34f36 5784 #define ENET_ATSTMP ENET_ATSTMP_REG(ENET)
ethaderu 3:78f223d34f36 5785 #define ENET_TGSR ENET_TGSR_REG(ENET)
ethaderu 3:78f223d34f36 5786 #define ENET_TCSR0 ENET_TCSR_REG(ENET,0)
ethaderu 3:78f223d34f36 5787 #define ENET_TCCR0 ENET_TCCR_REG(ENET,0)
ethaderu 3:78f223d34f36 5788 #define ENET_TCSR1 ENET_TCSR_REG(ENET,1)
ethaderu 3:78f223d34f36 5789 #define ENET_TCCR1 ENET_TCCR_REG(ENET,1)
ethaderu 3:78f223d34f36 5790 #define ENET_TCSR2 ENET_TCSR_REG(ENET,2)
ethaderu 3:78f223d34f36 5791 #define ENET_TCCR2 ENET_TCCR_REG(ENET,2)
ethaderu 3:78f223d34f36 5792 #define ENET_TCSR3 ENET_TCSR_REG(ENET,3)
ethaderu 3:78f223d34f36 5793 #define ENET_TCCR3 ENET_TCCR_REG(ENET,3)
ethaderu 3:78f223d34f36 5794
ethaderu 3:78f223d34f36 5795 /* ENET - Register array accessors */
ethaderu 3:78f223d34f36 5796 #define ENET_TCSR(index) ENET_TCSR_REG(ENET,index)
ethaderu 3:78f223d34f36 5797 #define ENET_TCCR(index) ENET_TCCR_REG(ENET,index)
ethaderu 3:78f223d34f36 5798
ethaderu 3:78f223d34f36 5799 /*!
ethaderu 3:78f223d34f36 5800 * @}
ethaderu 3:78f223d34f36 5801 */ /* end of group ENET_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 5802
ethaderu 3:78f223d34f36 5803
ethaderu 3:78f223d34f36 5804 /*!
ethaderu 3:78f223d34f36 5805 * @}
ethaderu 3:78f223d34f36 5806 */ /* end of group ENET_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 5807
ethaderu 3:78f223d34f36 5808
ethaderu 3:78f223d34f36 5809 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 5810 -- EWM Peripheral Access Layer
ethaderu 3:78f223d34f36 5811 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 5812
ethaderu 3:78f223d34f36 5813 /*!
ethaderu 3:78f223d34f36 5814 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
ethaderu 3:78f223d34f36 5815 * @{
ethaderu 3:78f223d34f36 5816 */
ethaderu 3:78f223d34f36 5817
ethaderu 3:78f223d34f36 5818 /** EWM - Register Layout Typedef */
ethaderu 3:78f223d34f36 5819 typedef struct {
ethaderu 3:78f223d34f36 5820 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
ethaderu 3:78f223d34f36 5821 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
ethaderu 3:78f223d34f36 5822 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
ethaderu 3:78f223d34f36 5823 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
ethaderu 3:78f223d34f36 5824 } EWM_Type, *EWM_MemMapPtr;
ethaderu 3:78f223d34f36 5825
ethaderu 3:78f223d34f36 5826 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 5827 -- EWM - Register accessor macros
ethaderu 3:78f223d34f36 5828 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 5829
ethaderu 3:78f223d34f36 5830 /*!
ethaderu 3:78f223d34f36 5831 * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
ethaderu 3:78f223d34f36 5832 * @{
ethaderu 3:78f223d34f36 5833 */
ethaderu 3:78f223d34f36 5834
ethaderu 3:78f223d34f36 5835
ethaderu 3:78f223d34f36 5836 /* EWM - Register accessors */
ethaderu 3:78f223d34f36 5837 #define EWM_CTRL_REG(base) ((base)->CTRL)
ethaderu 3:78f223d34f36 5838 #define EWM_SERV_REG(base) ((base)->SERV)
ethaderu 3:78f223d34f36 5839 #define EWM_CMPL_REG(base) ((base)->CMPL)
ethaderu 3:78f223d34f36 5840 #define EWM_CMPH_REG(base) ((base)->CMPH)
ethaderu 3:78f223d34f36 5841
ethaderu 3:78f223d34f36 5842 /*!
ethaderu 3:78f223d34f36 5843 * @}
ethaderu 3:78f223d34f36 5844 */ /* end of group EWM_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 5845
ethaderu 3:78f223d34f36 5846
ethaderu 3:78f223d34f36 5847 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 5848 -- EWM Register Masks
ethaderu 3:78f223d34f36 5849 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 5850
ethaderu 3:78f223d34f36 5851 /*!
ethaderu 3:78f223d34f36 5852 * @addtogroup EWM_Register_Masks EWM Register Masks
ethaderu 3:78f223d34f36 5853 * @{
ethaderu 3:78f223d34f36 5854 */
ethaderu 3:78f223d34f36 5855
ethaderu 3:78f223d34f36 5856 /* CTRL Bit Fields */
ethaderu 3:78f223d34f36 5857 #define EWM_CTRL_EWMEN_MASK 0x1u
ethaderu 3:78f223d34f36 5858 #define EWM_CTRL_EWMEN_SHIFT 0
ethaderu 3:78f223d34f36 5859 #define EWM_CTRL_ASSIN_MASK 0x2u
ethaderu 3:78f223d34f36 5860 #define EWM_CTRL_ASSIN_SHIFT 1
ethaderu 3:78f223d34f36 5861 #define EWM_CTRL_INEN_MASK 0x4u
ethaderu 3:78f223d34f36 5862 #define EWM_CTRL_INEN_SHIFT 2
ethaderu 3:78f223d34f36 5863 #define EWM_CTRL_INTEN_MASK 0x8u
ethaderu 3:78f223d34f36 5864 #define EWM_CTRL_INTEN_SHIFT 3
ethaderu 3:78f223d34f36 5865 /* SERV Bit Fields */
ethaderu 3:78f223d34f36 5866 #define EWM_SERV_SERVICE_MASK 0xFFu
ethaderu 3:78f223d34f36 5867 #define EWM_SERV_SERVICE_SHIFT 0
ethaderu 3:78f223d34f36 5868 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
ethaderu 3:78f223d34f36 5869 /* CMPL Bit Fields */
ethaderu 3:78f223d34f36 5870 #define EWM_CMPL_COMPAREL_MASK 0xFFu
ethaderu 3:78f223d34f36 5871 #define EWM_CMPL_COMPAREL_SHIFT 0
ethaderu 3:78f223d34f36 5872 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
ethaderu 3:78f223d34f36 5873 /* CMPH Bit Fields */
ethaderu 3:78f223d34f36 5874 #define EWM_CMPH_COMPAREH_MASK 0xFFu
ethaderu 3:78f223d34f36 5875 #define EWM_CMPH_COMPAREH_SHIFT 0
ethaderu 3:78f223d34f36 5876 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
ethaderu 3:78f223d34f36 5877
ethaderu 3:78f223d34f36 5878 /*!
ethaderu 3:78f223d34f36 5879 * @}
ethaderu 3:78f223d34f36 5880 */ /* end of group EWM_Register_Masks */
ethaderu 3:78f223d34f36 5881
ethaderu 3:78f223d34f36 5882
ethaderu 3:78f223d34f36 5883 /* EWM - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 5884 /** Peripheral EWM base address */
ethaderu 3:78f223d34f36 5885 #define EWM_BASE (0x40061000u)
ethaderu 3:78f223d34f36 5886 /** Peripheral EWM base pointer */
ethaderu 3:78f223d34f36 5887 #define EWM ((EWM_Type *)EWM_BASE)
ethaderu 3:78f223d34f36 5888 #define EWM_BASE_PTR (EWM)
ethaderu 3:78f223d34f36 5889 /** Array initializer of EWM peripheral base addresses */
ethaderu 3:78f223d34f36 5890 #define EWM_BASE_ADDRS { EWM_BASE }
ethaderu 3:78f223d34f36 5891 /** Array initializer of EWM peripheral base pointers */
ethaderu 3:78f223d34f36 5892 #define EWM_BASE_PTRS { EWM }
ethaderu 3:78f223d34f36 5893 /** Interrupt vectors for the EWM peripheral type */
ethaderu 3:78f223d34f36 5894 #define EWM_IRQS { Watchdog_IRQn }
ethaderu 3:78f223d34f36 5895
ethaderu 3:78f223d34f36 5896 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 5897 -- EWM - Register accessor macros
ethaderu 3:78f223d34f36 5898 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 5899
ethaderu 3:78f223d34f36 5900 /*!
ethaderu 3:78f223d34f36 5901 * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
ethaderu 3:78f223d34f36 5902 * @{
ethaderu 3:78f223d34f36 5903 */
ethaderu 3:78f223d34f36 5904
ethaderu 3:78f223d34f36 5905
ethaderu 3:78f223d34f36 5906 /* EWM - Register instance definitions */
ethaderu 3:78f223d34f36 5907 /* EWM */
ethaderu 3:78f223d34f36 5908 #define EWM_CTRL EWM_CTRL_REG(EWM)
ethaderu 3:78f223d34f36 5909 #define EWM_SERV EWM_SERV_REG(EWM)
ethaderu 3:78f223d34f36 5910 #define EWM_CMPL EWM_CMPL_REG(EWM)
ethaderu 3:78f223d34f36 5911 #define EWM_CMPH EWM_CMPH_REG(EWM)
ethaderu 3:78f223d34f36 5912
ethaderu 3:78f223d34f36 5913 /*!
ethaderu 3:78f223d34f36 5914 * @}
ethaderu 3:78f223d34f36 5915 */ /* end of group EWM_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 5916
ethaderu 3:78f223d34f36 5917
ethaderu 3:78f223d34f36 5918 /*!
ethaderu 3:78f223d34f36 5919 * @}
ethaderu 3:78f223d34f36 5920 */ /* end of group EWM_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 5921
ethaderu 3:78f223d34f36 5922
ethaderu 3:78f223d34f36 5923 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 5924 -- FB Peripheral Access Layer
ethaderu 3:78f223d34f36 5925 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 5926
ethaderu 3:78f223d34f36 5927 /*!
ethaderu 3:78f223d34f36 5928 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
ethaderu 3:78f223d34f36 5929 * @{
ethaderu 3:78f223d34f36 5930 */
ethaderu 3:78f223d34f36 5931
ethaderu 3:78f223d34f36 5932 /** FB - Register Layout Typedef */
ethaderu 3:78f223d34f36 5933 typedef struct {
ethaderu 3:78f223d34f36 5934 struct { /* offset: 0x0, array step: 0xC */
ethaderu 3:78f223d34f36 5935 __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
ethaderu 3:78f223d34f36 5936 __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
ethaderu 3:78f223d34f36 5937 __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
ethaderu 3:78f223d34f36 5938 } CS[6];
ethaderu 3:78f223d34f36 5939 uint8_t RESERVED_0[24];
ethaderu 3:78f223d34f36 5940 __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
ethaderu 3:78f223d34f36 5941 } FB_Type, *FB_MemMapPtr;
ethaderu 3:78f223d34f36 5942
ethaderu 3:78f223d34f36 5943 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 5944 -- FB - Register accessor macros
ethaderu 3:78f223d34f36 5945 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 5946
ethaderu 3:78f223d34f36 5947 /*!
ethaderu 3:78f223d34f36 5948 * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
ethaderu 3:78f223d34f36 5949 * @{
ethaderu 3:78f223d34f36 5950 */
ethaderu 3:78f223d34f36 5951
ethaderu 3:78f223d34f36 5952
ethaderu 3:78f223d34f36 5953 /* FB - Register accessors */
ethaderu 3:78f223d34f36 5954 #define FB_CSAR_REG(base,index) ((base)->CS[index].CSAR)
ethaderu 3:78f223d34f36 5955 #define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR)
ethaderu 3:78f223d34f36 5956 #define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR)
ethaderu 3:78f223d34f36 5957 #define FB_CSPMCR_REG(base) ((base)->CSPMCR)
ethaderu 3:78f223d34f36 5958
ethaderu 3:78f223d34f36 5959 /*!
ethaderu 3:78f223d34f36 5960 * @}
ethaderu 3:78f223d34f36 5961 */ /* end of group FB_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 5962
ethaderu 3:78f223d34f36 5963
ethaderu 3:78f223d34f36 5964 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 5965 -- FB Register Masks
ethaderu 3:78f223d34f36 5966 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 5967
ethaderu 3:78f223d34f36 5968 /*!
ethaderu 3:78f223d34f36 5969 * @addtogroup FB_Register_Masks FB Register Masks
ethaderu 3:78f223d34f36 5970 * @{
ethaderu 3:78f223d34f36 5971 */
ethaderu 3:78f223d34f36 5972
ethaderu 3:78f223d34f36 5973 /* CSAR Bit Fields */
ethaderu 3:78f223d34f36 5974 #define FB_CSAR_BA_MASK 0xFFFF0000u
ethaderu 3:78f223d34f36 5975 #define FB_CSAR_BA_SHIFT 16
ethaderu 3:78f223d34f36 5976 #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
ethaderu 3:78f223d34f36 5977 /* CSMR Bit Fields */
ethaderu 3:78f223d34f36 5978 #define FB_CSMR_V_MASK 0x1u
ethaderu 3:78f223d34f36 5979 #define FB_CSMR_V_SHIFT 0
ethaderu 3:78f223d34f36 5980 #define FB_CSMR_WP_MASK 0x100u
ethaderu 3:78f223d34f36 5981 #define FB_CSMR_WP_SHIFT 8
ethaderu 3:78f223d34f36 5982 #define FB_CSMR_BAM_MASK 0xFFFF0000u
ethaderu 3:78f223d34f36 5983 #define FB_CSMR_BAM_SHIFT 16
ethaderu 3:78f223d34f36 5984 #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
ethaderu 3:78f223d34f36 5985 /* CSCR Bit Fields */
ethaderu 3:78f223d34f36 5986 #define FB_CSCR_BSTW_MASK 0x8u
ethaderu 3:78f223d34f36 5987 #define FB_CSCR_BSTW_SHIFT 3
ethaderu 3:78f223d34f36 5988 #define FB_CSCR_BSTR_MASK 0x10u
ethaderu 3:78f223d34f36 5989 #define FB_CSCR_BSTR_SHIFT 4
ethaderu 3:78f223d34f36 5990 #define FB_CSCR_BEM_MASK 0x20u
ethaderu 3:78f223d34f36 5991 #define FB_CSCR_BEM_SHIFT 5
ethaderu 3:78f223d34f36 5992 #define FB_CSCR_PS_MASK 0xC0u
ethaderu 3:78f223d34f36 5993 #define FB_CSCR_PS_SHIFT 6
ethaderu 3:78f223d34f36 5994 #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
ethaderu 3:78f223d34f36 5995 #define FB_CSCR_AA_MASK 0x100u
ethaderu 3:78f223d34f36 5996 #define FB_CSCR_AA_SHIFT 8
ethaderu 3:78f223d34f36 5997 #define FB_CSCR_BLS_MASK 0x200u
ethaderu 3:78f223d34f36 5998 #define FB_CSCR_BLS_SHIFT 9
ethaderu 3:78f223d34f36 5999 #define FB_CSCR_WS_MASK 0xFC00u
ethaderu 3:78f223d34f36 6000 #define FB_CSCR_WS_SHIFT 10
ethaderu 3:78f223d34f36 6001 #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
ethaderu 3:78f223d34f36 6002 #define FB_CSCR_WRAH_MASK 0x30000u
ethaderu 3:78f223d34f36 6003 #define FB_CSCR_WRAH_SHIFT 16
ethaderu 3:78f223d34f36 6004 #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
ethaderu 3:78f223d34f36 6005 #define FB_CSCR_RDAH_MASK 0xC0000u
ethaderu 3:78f223d34f36 6006 #define FB_CSCR_RDAH_SHIFT 18
ethaderu 3:78f223d34f36 6007 #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
ethaderu 3:78f223d34f36 6008 #define FB_CSCR_ASET_MASK 0x300000u
ethaderu 3:78f223d34f36 6009 #define FB_CSCR_ASET_SHIFT 20
ethaderu 3:78f223d34f36 6010 #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
ethaderu 3:78f223d34f36 6011 #define FB_CSCR_EXTS_MASK 0x400000u
ethaderu 3:78f223d34f36 6012 #define FB_CSCR_EXTS_SHIFT 22
ethaderu 3:78f223d34f36 6013 #define FB_CSCR_SWSEN_MASK 0x800000u
ethaderu 3:78f223d34f36 6014 #define FB_CSCR_SWSEN_SHIFT 23
ethaderu 3:78f223d34f36 6015 #define FB_CSCR_SWS_MASK 0xFC000000u
ethaderu 3:78f223d34f36 6016 #define FB_CSCR_SWS_SHIFT 26
ethaderu 3:78f223d34f36 6017 #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
ethaderu 3:78f223d34f36 6018 /* CSPMCR Bit Fields */
ethaderu 3:78f223d34f36 6019 #define FB_CSPMCR_GROUP5_MASK 0xF000u
ethaderu 3:78f223d34f36 6020 #define FB_CSPMCR_GROUP5_SHIFT 12
ethaderu 3:78f223d34f36 6021 #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
ethaderu 3:78f223d34f36 6022 #define FB_CSPMCR_GROUP4_MASK 0xF0000u
ethaderu 3:78f223d34f36 6023 #define FB_CSPMCR_GROUP4_SHIFT 16
ethaderu 3:78f223d34f36 6024 #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
ethaderu 3:78f223d34f36 6025 #define FB_CSPMCR_GROUP3_MASK 0xF00000u
ethaderu 3:78f223d34f36 6026 #define FB_CSPMCR_GROUP3_SHIFT 20
ethaderu 3:78f223d34f36 6027 #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
ethaderu 3:78f223d34f36 6028 #define FB_CSPMCR_GROUP2_MASK 0xF000000u
ethaderu 3:78f223d34f36 6029 #define FB_CSPMCR_GROUP2_SHIFT 24
ethaderu 3:78f223d34f36 6030 #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
ethaderu 3:78f223d34f36 6031 #define FB_CSPMCR_GROUP1_MASK 0xF0000000u
ethaderu 3:78f223d34f36 6032 #define FB_CSPMCR_GROUP1_SHIFT 28
ethaderu 3:78f223d34f36 6033 #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
ethaderu 3:78f223d34f36 6034
ethaderu 3:78f223d34f36 6035 /*!
ethaderu 3:78f223d34f36 6036 * @}
ethaderu 3:78f223d34f36 6037 */ /* end of group FB_Register_Masks */
ethaderu 3:78f223d34f36 6038
ethaderu 3:78f223d34f36 6039
ethaderu 3:78f223d34f36 6040 /* FB - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 6041 /** Peripheral FB base address */
ethaderu 3:78f223d34f36 6042 #define FB_BASE (0x4000C000u)
ethaderu 3:78f223d34f36 6043 /** Peripheral FB base pointer */
ethaderu 3:78f223d34f36 6044 #define FB ((FB_Type *)FB_BASE)
ethaderu 3:78f223d34f36 6045 #define FB_BASE_PTR (FB)
ethaderu 3:78f223d34f36 6046 /** Array initializer of FB peripheral base addresses */
ethaderu 3:78f223d34f36 6047 #define FB_BASE_ADDRS { FB_BASE }
ethaderu 3:78f223d34f36 6048 /** Array initializer of FB peripheral base pointers */
ethaderu 3:78f223d34f36 6049 #define FB_BASE_PTRS { FB }
ethaderu 3:78f223d34f36 6050
ethaderu 3:78f223d34f36 6051 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 6052 -- FB - Register accessor macros
ethaderu 3:78f223d34f36 6053 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 6054
ethaderu 3:78f223d34f36 6055 /*!
ethaderu 3:78f223d34f36 6056 * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
ethaderu 3:78f223d34f36 6057 * @{
ethaderu 3:78f223d34f36 6058 */
ethaderu 3:78f223d34f36 6059
ethaderu 3:78f223d34f36 6060
ethaderu 3:78f223d34f36 6061 /* FB - Register instance definitions */
ethaderu 3:78f223d34f36 6062 /* FB */
ethaderu 3:78f223d34f36 6063 #define FB_CSAR0 FB_CSAR_REG(FB,0)
ethaderu 3:78f223d34f36 6064 #define FB_CSMR0 FB_CSMR_REG(FB,0)
ethaderu 3:78f223d34f36 6065 #define FB_CSCR0 FB_CSCR_REG(FB,0)
ethaderu 3:78f223d34f36 6066 #define FB_CSAR1 FB_CSAR_REG(FB,1)
ethaderu 3:78f223d34f36 6067 #define FB_CSMR1 FB_CSMR_REG(FB,1)
ethaderu 3:78f223d34f36 6068 #define FB_CSCR1 FB_CSCR_REG(FB,1)
ethaderu 3:78f223d34f36 6069 #define FB_CSAR2 FB_CSAR_REG(FB,2)
ethaderu 3:78f223d34f36 6070 #define FB_CSMR2 FB_CSMR_REG(FB,2)
ethaderu 3:78f223d34f36 6071 #define FB_CSCR2 FB_CSCR_REG(FB,2)
ethaderu 3:78f223d34f36 6072 #define FB_CSAR3 FB_CSAR_REG(FB,3)
ethaderu 3:78f223d34f36 6073 #define FB_CSMR3 FB_CSMR_REG(FB,3)
ethaderu 3:78f223d34f36 6074 #define FB_CSCR3 FB_CSCR_REG(FB,3)
ethaderu 3:78f223d34f36 6075 #define FB_CSAR4 FB_CSAR_REG(FB,4)
ethaderu 3:78f223d34f36 6076 #define FB_CSMR4 FB_CSMR_REG(FB,4)
ethaderu 3:78f223d34f36 6077 #define FB_CSCR4 FB_CSCR_REG(FB,4)
ethaderu 3:78f223d34f36 6078 #define FB_CSAR5 FB_CSAR_REG(FB,5)
ethaderu 3:78f223d34f36 6079 #define FB_CSMR5 FB_CSMR_REG(FB,5)
ethaderu 3:78f223d34f36 6080 #define FB_CSCR5 FB_CSCR_REG(FB,5)
ethaderu 3:78f223d34f36 6081 #define FB_CSPMCR FB_CSPMCR_REG(FB)
ethaderu 3:78f223d34f36 6082
ethaderu 3:78f223d34f36 6083 /* FB - Register array accessors */
ethaderu 3:78f223d34f36 6084 #define FB_CSAR(index) FB_CSAR_REG(FB,index)
ethaderu 3:78f223d34f36 6085 #define FB_CSMR(index) FB_CSMR_REG(FB,index)
ethaderu 3:78f223d34f36 6086 #define FB_CSCR(index) FB_CSCR_REG(FB,index)
ethaderu 3:78f223d34f36 6087
ethaderu 3:78f223d34f36 6088 /*!
ethaderu 3:78f223d34f36 6089 * @}
ethaderu 3:78f223d34f36 6090 */ /* end of group FB_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 6091
ethaderu 3:78f223d34f36 6092
ethaderu 3:78f223d34f36 6093 /*!
ethaderu 3:78f223d34f36 6094 * @}
ethaderu 3:78f223d34f36 6095 */ /* end of group FB_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 6096
ethaderu 3:78f223d34f36 6097
ethaderu 3:78f223d34f36 6098 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 6099 -- FMC Peripheral Access Layer
ethaderu 3:78f223d34f36 6100 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 6101
ethaderu 3:78f223d34f36 6102 /*!
ethaderu 3:78f223d34f36 6103 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
ethaderu 3:78f223d34f36 6104 * @{
ethaderu 3:78f223d34f36 6105 */
ethaderu 3:78f223d34f36 6106
ethaderu 3:78f223d34f36 6107 /** FMC - Register Layout Typedef */
ethaderu 3:78f223d34f36 6108 typedef struct {
ethaderu 3:78f223d34f36 6109 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
ethaderu 3:78f223d34f36 6110 __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
ethaderu 3:78f223d34f36 6111 __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
ethaderu 3:78f223d34f36 6112 uint8_t RESERVED_0[244];
ethaderu 3:78f223d34f36 6113 __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
ethaderu 3:78f223d34f36 6114 __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
ethaderu 3:78f223d34f36 6115 __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
ethaderu 3:78f223d34f36 6116 __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
ethaderu 3:78f223d34f36 6117 uint8_t RESERVED_1[192];
ethaderu 3:78f223d34f36 6118 struct { /* offset: 0x200, array step: index*0x20, index2*0x8 */
ethaderu 3:78f223d34f36 6119 __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
ethaderu 3:78f223d34f36 6120 __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
ethaderu 3:78f223d34f36 6121 } SET[4][4];
ethaderu 3:78f223d34f36 6122 } FMC_Type, *FMC_MemMapPtr;
ethaderu 3:78f223d34f36 6123
ethaderu 3:78f223d34f36 6124 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 6125 -- FMC - Register accessor macros
ethaderu 3:78f223d34f36 6126 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 6127
ethaderu 3:78f223d34f36 6128 /*!
ethaderu 3:78f223d34f36 6129 * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
ethaderu 3:78f223d34f36 6130 * @{
ethaderu 3:78f223d34f36 6131 */
ethaderu 3:78f223d34f36 6132
ethaderu 3:78f223d34f36 6133
ethaderu 3:78f223d34f36 6134 /* FMC - Register accessors */
ethaderu 3:78f223d34f36 6135 #define FMC_PFAPR_REG(base) ((base)->PFAPR)
ethaderu 3:78f223d34f36 6136 #define FMC_PFB0CR_REG(base) ((base)->PFB0CR)
ethaderu 3:78f223d34f36 6137 #define FMC_PFB1CR_REG(base) ((base)->PFB1CR)
ethaderu 3:78f223d34f36 6138 #define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index])
ethaderu 3:78f223d34f36 6139 #define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index])
ethaderu 3:78f223d34f36 6140 #define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index])
ethaderu 3:78f223d34f36 6141 #define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index])
ethaderu 3:78f223d34f36 6142 #define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U)
ethaderu 3:78f223d34f36 6143 #define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L)
ethaderu 3:78f223d34f36 6144
ethaderu 3:78f223d34f36 6145 /*!
ethaderu 3:78f223d34f36 6146 * @}
ethaderu 3:78f223d34f36 6147 */ /* end of group FMC_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 6148
ethaderu 3:78f223d34f36 6149
ethaderu 3:78f223d34f36 6150 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 6151 -- FMC Register Masks
ethaderu 3:78f223d34f36 6152 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 6153
ethaderu 3:78f223d34f36 6154 /*!
ethaderu 3:78f223d34f36 6155 * @addtogroup FMC_Register_Masks FMC Register Masks
ethaderu 3:78f223d34f36 6156 * @{
ethaderu 3:78f223d34f36 6157 */
ethaderu 3:78f223d34f36 6158
ethaderu 3:78f223d34f36 6159 /* PFAPR Bit Fields */
ethaderu 3:78f223d34f36 6160 #define FMC_PFAPR_M0AP_MASK 0x3u
ethaderu 3:78f223d34f36 6161 #define FMC_PFAPR_M0AP_SHIFT 0
ethaderu 3:78f223d34f36 6162 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
ethaderu 3:78f223d34f36 6163 #define FMC_PFAPR_M1AP_MASK 0xCu
ethaderu 3:78f223d34f36 6164 #define FMC_PFAPR_M1AP_SHIFT 2
ethaderu 3:78f223d34f36 6165 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
ethaderu 3:78f223d34f36 6166 #define FMC_PFAPR_M2AP_MASK 0x30u
ethaderu 3:78f223d34f36 6167 #define FMC_PFAPR_M2AP_SHIFT 4
ethaderu 3:78f223d34f36 6168 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
ethaderu 3:78f223d34f36 6169 #define FMC_PFAPR_M3AP_MASK 0xC0u
ethaderu 3:78f223d34f36 6170 #define FMC_PFAPR_M3AP_SHIFT 6
ethaderu 3:78f223d34f36 6171 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
ethaderu 3:78f223d34f36 6172 #define FMC_PFAPR_M4AP_MASK 0x300u
ethaderu 3:78f223d34f36 6173 #define FMC_PFAPR_M4AP_SHIFT 8
ethaderu 3:78f223d34f36 6174 #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
ethaderu 3:78f223d34f36 6175 #define FMC_PFAPR_M5AP_MASK 0xC00u
ethaderu 3:78f223d34f36 6176 #define FMC_PFAPR_M5AP_SHIFT 10
ethaderu 3:78f223d34f36 6177 #define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
ethaderu 3:78f223d34f36 6178 #define FMC_PFAPR_M6AP_MASK 0x3000u
ethaderu 3:78f223d34f36 6179 #define FMC_PFAPR_M6AP_SHIFT 12
ethaderu 3:78f223d34f36 6180 #define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
ethaderu 3:78f223d34f36 6181 #define FMC_PFAPR_M7AP_MASK 0xC000u
ethaderu 3:78f223d34f36 6182 #define FMC_PFAPR_M7AP_SHIFT 14
ethaderu 3:78f223d34f36 6183 #define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
ethaderu 3:78f223d34f36 6184 #define FMC_PFAPR_M0PFD_MASK 0x10000u
ethaderu 3:78f223d34f36 6185 #define FMC_PFAPR_M0PFD_SHIFT 16
ethaderu 3:78f223d34f36 6186 #define FMC_PFAPR_M1PFD_MASK 0x20000u
ethaderu 3:78f223d34f36 6187 #define FMC_PFAPR_M1PFD_SHIFT 17
ethaderu 3:78f223d34f36 6188 #define FMC_PFAPR_M2PFD_MASK 0x40000u
ethaderu 3:78f223d34f36 6189 #define FMC_PFAPR_M2PFD_SHIFT 18
ethaderu 3:78f223d34f36 6190 #define FMC_PFAPR_M3PFD_MASK 0x80000u
ethaderu 3:78f223d34f36 6191 #define FMC_PFAPR_M3PFD_SHIFT 19
ethaderu 3:78f223d34f36 6192 #define FMC_PFAPR_M4PFD_MASK 0x100000u
ethaderu 3:78f223d34f36 6193 #define FMC_PFAPR_M4PFD_SHIFT 20
ethaderu 3:78f223d34f36 6194 #define FMC_PFAPR_M5PFD_MASK 0x200000u
ethaderu 3:78f223d34f36 6195 #define FMC_PFAPR_M5PFD_SHIFT 21
ethaderu 3:78f223d34f36 6196 #define FMC_PFAPR_M6PFD_MASK 0x400000u
ethaderu 3:78f223d34f36 6197 #define FMC_PFAPR_M6PFD_SHIFT 22
ethaderu 3:78f223d34f36 6198 #define FMC_PFAPR_M7PFD_MASK 0x800000u
ethaderu 3:78f223d34f36 6199 #define FMC_PFAPR_M7PFD_SHIFT 23
ethaderu 3:78f223d34f36 6200 /* PFB0CR Bit Fields */
ethaderu 3:78f223d34f36 6201 #define FMC_PFB0CR_B0SEBE_MASK 0x1u
ethaderu 3:78f223d34f36 6202 #define FMC_PFB0CR_B0SEBE_SHIFT 0
ethaderu 3:78f223d34f36 6203 #define FMC_PFB0CR_B0IPE_MASK 0x2u
ethaderu 3:78f223d34f36 6204 #define FMC_PFB0CR_B0IPE_SHIFT 1
ethaderu 3:78f223d34f36 6205 #define FMC_PFB0CR_B0DPE_MASK 0x4u
ethaderu 3:78f223d34f36 6206 #define FMC_PFB0CR_B0DPE_SHIFT 2
ethaderu 3:78f223d34f36 6207 #define FMC_PFB0CR_B0ICE_MASK 0x8u
ethaderu 3:78f223d34f36 6208 #define FMC_PFB0CR_B0ICE_SHIFT 3
ethaderu 3:78f223d34f36 6209 #define FMC_PFB0CR_B0DCE_MASK 0x10u
ethaderu 3:78f223d34f36 6210 #define FMC_PFB0CR_B0DCE_SHIFT 4
ethaderu 3:78f223d34f36 6211 #define FMC_PFB0CR_CRC_MASK 0xE0u
ethaderu 3:78f223d34f36 6212 #define FMC_PFB0CR_CRC_SHIFT 5
ethaderu 3:78f223d34f36 6213 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
ethaderu 3:78f223d34f36 6214 #define FMC_PFB0CR_B0MW_MASK 0x60000u
ethaderu 3:78f223d34f36 6215 #define FMC_PFB0CR_B0MW_SHIFT 17
ethaderu 3:78f223d34f36 6216 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
ethaderu 3:78f223d34f36 6217 #define FMC_PFB0CR_S_B_INV_MASK 0x80000u
ethaderu 3:78f223d34f36 6218 #define FMC_PFB0CR_S_B_INV_SHIFT 19
ethaderu 3:78f223d34f36 6219 #define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
ethaderu 3:78f223d34f36 6220 #define FMC_PFB0CR_CINV_WAY_SHIFT 20
ethaderu 3:78f223d34f36 6221 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
ethaderu 3:78f223d34f36 6222 #define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
ethaderu 3:78f223d34f36 6223 #define FMC_PFB0CR_CLCK_WAY_SHIFT 24
ethaderu 3:78f223d34f36 6224 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
ethaderu 3:78f223d34f36 6225 #define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
ethaderu 3:78f223d34f36 6226 #define FMC_PFB0CR_B0RWSC_SHIFT 28
ethaderu 3:78f223d34f36 6227 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
ethaderu 3:78f223d34f36 6228 /* PFB1CR Bit Fields */
ethaderu 3:78f223d34f36 6229 #define FMC_PFB1CR_B1SEBE_MASK 0x1u
ethaderu 3:78f223d34f36 6230 #define FMC_PFB1CR_B1SEBE_SHIFT 0
ethaderu 3:78f223d34f36 6231 #define FMC_PFB1CR_B1IPE_MASK 0x2u
ethaderu 3:78f223d34f36 6232 #define FMC_PFB1CR_B1IPE_SHIFT 1
ethaderu 3:78f223d34f36 6233 #define FMC_PFB1CR_B1DPE_MASK 0x4u
ethaderu 3:78f223d34f36 6234 #define FMC_PFB1CR_B1DPE_SHIFT 2
ethaderu 3:78f223d34f36 6235 #define FMC_PFB1CR_B1ICE_MASK 0x8u
ethaderu 3:78f223d34f36 6236 #define FMC_PFB1CR_B1ICE_SHIFT 3
ethaderu 3:78f223d34f36 6237 #define FMC_PFB1CR_B1DCE_MASK 0x10u
ethaderu 3:78f223d34f36 6238 #define FMC_PFB1CR_B1DCE_SHIFT 4
ethaderu 3:78f223d34f36 6239 #define FMC_PFB1CR_B1MW_MASK 0x60000u
ethaderu 3:78f223d34f36 6240 #define FMC_PFB1CR_B1MW_SHIFT 17
ethaderu 3:78f223d34f36 6241 #define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
ethaderu 3:78f223d34f36 6242 #define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
ethaderu 3:78f223d34f36 6243 #define FMC_PFB1CR_B1RWSC_SHIFT 28
ethaderu 3:78f223d34f36 6244 #define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
ethaderu 3:78f223d34f36 6245 /* TAGVDW0S Bit Fields */
ethaderu 3:78f223d34f36 6246 #define FMC_TAGVDW0S_valid_MASK 0x1u
ethaderu 3:78f223d34f36 6247 #define FMC_TAGVDW0S_valid_SHIFT 0
ethaderu 3:78f223d34f36 6248 #define FMC_TAGVDW0S_tag_MASK 0x7FFE0u
ethaderu 3:78f223d34f36 6249 #define FMC_TAGVDW0S_tag_SHIFT 5
ethaderu 3:78f223d34f36 6250 #define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
ethaderu 3:78f223d34f36 6251 /* TAGVDW1S Bit Fields */
ethaderu 3:78f223d34f36 6252 #define FMC_TAGVDW1S_valid_MASK 0x1u
ethaderu 3:78f223d34f36 6253 #define FMC_TAGVDW1S_valid_SHIFT 0
ethaderu 3:78f223d34f36 6254 #define FMC_TAGVDW1S_tag_MASK 0x7FFE0u
ethaderu 3:78f223d34f36 6255 #define FMC_TAGVDW1S_tag_SHIFT 5
ethaderu 3:78f223d34f36 6256 #define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
ethaderu 3:78f223d34f36 6257 /* TAGVDW2S Bit Fields */
ethaderu 3:78f223d34f36 6258 #define FMC_TAGVDW2S_valid_MASK 0x1u
ethaderu 3:78f223d34f36 6259 #define FMC_TAGVDW2S_valid_SHIFT 0
ethaderu 3:78f223d34f36 6260 #define FMC_TAGVDW2S_tag_MASK 0x7FFE0u
ethaderu 3:78f223d34f36 6261 #define FMC_TAGVDW2S_tag_SHIFT 5
ethaderu 3:78f223d34f36 6262 #define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
ethaderu 3:78f223d34f36 6263 /* TAGVDW3S Bit Fields */
ethaderu 3:78f223d34f36 6264 #define FMC_TAGVDW3S_valid_MASK 0x1u
ethaderu 3:78f223d34f36 6265 #define FMC_TAGVDW3S_valid_SHIFT 0
ethaderu 3:78f223d34f36 6266 #define FMC_TAGVDW3S_tag_MASK 0x7FFE0u
ethaderu 3:78f223d34f36 6267 #define FMC_TAGVDW3S_tag_SHIFT 5
ethaderu 3:78f223d34f36 6268 #define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
ethaderu 3:78f223d34f36 6269 /* DATA_U Bit Fields */
ethaderu 3:78f223d34f36 6270 #define FMC_DATA_U_data_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 6271 #define FMC_DATA_U_data_SHIFT 0
ethaderu 3:78f223d34f36 6272 #define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
ethaderu 3:78f223d34f36 6273 /* DATA_L Bit Fields */
ethaderu 3:78f223d34f36 6274 #define FMC_DATA_L_data_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 6275 #define FMC_DATA_L_data_SHIFT 0
ethaderu 3:78f223d34f36 6276 #define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
ethaderu 3:78f223d34f36 6277
ethaderu 3:78f223d34f36 6278 /*!
ethaderu 3:78f223d34f36 6279 * @}
ethaderu 3:78f223d34f36 6280 */ /* end of group FMC_Register_Masks */
ethaderu 3:78f223d34f36 6281
ethaderu 3:78f223d34f36 6282
ethaderu 3:78f223d34f36 6283 /* FMC - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 6284 /** Peripheral FMC base address */
ethaderu 3:78f223d34f36 6285 #define FMC_BASE (0x4001F000u)
ethaderu 3:78f223d34f36 6286 /** Peripheral FMC base pointer */
ethaderu 3:78f223d34f36 6287 #define FMC ((FMC_Type *)FMC_BASE)
ethaderu 3:78f223d34f36 6288 #define FMC_BASE_PTR (FMC)
ethaderu 3:78f223d34f36 6289 /** Array initializer of FMC peripheral base addresses */
ethaderu 3:78f223d34f36 6290 #define FMC_BASE_ADDRS { FMC_BASE }
ethaderu 3:78f223d34f36 6291 /** Array initializer of FMC peripheral base pointers */
ethaderu 3:78f223d34f36 6292 #define FMC_BASE_PTRS { FMC }
ethaderu 3:78f223d34f36 6293
ethaderu 3:78f223d34f36 6294 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 6295 -- FMC - Register accessor macros
ethaderu 3:78f223d34f36 6296 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 6297
ethaderu 3:78f223d34f36 6298 /*!
ethaderu 3:78f223d34f36 6299 * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
ethaderu 3:78f223d34f36 6300 * @{
ethaderu 3:78f223d34f36 6301 */
ethaderu 3:78f223d34f36 6302
ethaderu 3:78f223d34f36 6303
ethaderu 3:78f223d34f36 6304 /* FMC - Register instance definitions */
ethaderu 3:78f223d34f36 6305 /* FMC */
ethaderu 3:78f223d34f36 6306 #define FMC_PFAPR FMC_PFAPR_REG(FMC)
ethaderu 3:78f223d34f36 6307 #define FMC_PFB0CR FMC_PFB0CR_REG(FMC)
ethaderu 3:78f223d34f36 6308 #define FMC_PFB1CR FMC_PFB1CR_REG(FMC)
ethaderu 3:78f223d34f36 6309 #define FMC_TAGVDW0S0 FMC_TAGVDW0S_REG(FMC,0)
ethaderu 3:78f223d34f36 6310 #define FMC_TAGVDW0S1 FMC_TAGVDW0S_REG(FMC,1)
ethaderu 3:78f223d34f36 6311 #define FMC_TAGVDW0S2 FMC_TAGVDW0S_REG(FMC,2)
ethaderu 3:78f223d34f36 6312 #define FMC_TAGVDW0S3 FMC_TAGVDW0S_REG(FMC,3)
ethaderu 3:78f223d34f36 6313 #define FMC_TAGVDW1S0 FMC_TAGVDW1S_REG(FMC,0)
ethaderu 3:78f223d34f36 6314 #define FMC_TAGVDW1S1 FMC_TAGVDW1S_REG(FMC,1)
ethaderu 3:78f223d34f36 6315 #define FMC_TAGVDW1S2 FMC_TAGVDW1S_REG(FMC,2)
ethaderu 3:78f223d34f36 6316 #define FMC_TAGVDW1S3 FMC_TAGVDW1S_REG(FMC,3)
ethaderu 3:78f223d34f36 6317 #define FMC_TAGVDW2S0 FMC_TAGVDW2S_REG(FMC,0)
ethaderu 3:78f223d34f36 6318 #define FMC_TAGVDW2S1 FMC_TAGVDW2S_REG(FMC,1)
ethaderu 3:78f223d34f36 6319 #define FMC_TAGVDW2S2 FMC_TAGVDW2S_REG(FMC,2)
ethaderu 3:78f223d34f36 6320 #define FMC_TAGVDW2S3 FMC_TAGVDW2S_REG(FMC,3)
ethaderu 3:78f223d34f36 6321 #define FMC_TAGVDW3S0 FMC_TAGVDW3S_REG(FMC,0)
ethaderu 3:78f223d34f36 6322 #define FMC_TAGVDW3S1 FMC_TAGVDW3S_REG(FMC,1)
ethaderu 3:78f223d34f36 6323 #define FMC_TAGVDW3S2 FMC_TAGVDW3S_REG(FMC,2)
ethaderu 3:78f223d34f36 6324 #define FMC_TAGVDW3S3 FMC_TAGVDW3S_REG(FMC,3)
ethaderu 3:78f223d34f36 6325 #define FMC_DATAW0S0U FMC_DATA_U_REG(FMC,0,0)
ethaderu 3:78f223d34f36 6326 #define FMC_DATAW0S0L FMC_DATA_L_REG(FMC,0,0)
ethaderu 3:78f223d34f36 6327 #define FMC_DATAW0S1U FMC_DATA_U_REG(FMC,0,1)
ethaderu 3:78f223d34f36 6328 #define FMC_DATAW0S1L FMC_DATA_L_REG(FMC,0,1)
ethaderu 3:78f223d34f36 6329 #define FMC_DATAW0S2U FMC_DATA_U_REG(FMC,0,2)
ethaderu 3:78f223d34f36 6330 #define FMC_DATAW0S2L FMC_DATA_L_REG(FMC,0,2)
ethaderu 3:78f223d34f36 6331 #define FMC_DATAW0S3U FMC_DATA_U_REG(FMC,0,3)
ethaderu 3:78f223d34f36 6332 #define FMC_DATAW0S3L FMC_DATA_L_REG(FMC,0,3)
ethaderu 3:78f223d34f36 6333 #define FMC_DATAW1S0U FMC_DATA_U_REG(FMC,1,0)
ethaderu 3:78f223d34f36 6334 #define FMC_DATAW1S0L FMC_DATA_L_REG(FMC,1,0)
ethaderu 3:78f223d34f36 6335 #define FMC_DATAW1S1U FMC_DATA_U_REG(FMC,1,1)
ethaderu 3:78f223d34f36 6336 #define FMC_DATAW1S1L FMC_DATA_L_REG(FMC,1,1)
ethaderu 3:78f223d34f36 6337 #define FMC_DATAW1S2U FMC_DATA_U_REG(FMC,1,2)
ethaderu 3:78f223d34f36 6338 #define FMC_DATAW1S2L FMC_DATA_L_REG(FMC,1,2)
ethaderu 3:78f223d34f36 6339 #define FMC_DATAW1S3U FMC_DATA_U_REG(FMC,1,3)
ethaderu 3:78f223d34f36 6340 #define FMC_DATAW1S3L FMC_DATA_L_REG(FMC,1,3)
ethaderu 3:78f223d34f36 6341 #define FMC_DATAW2S0U FMC_DATA_U_REG(FMC,2,0)
ethaderu 3:78f223d34f36 6342 #define FMC_DATAW2S0L FMC_DATA_L_REG(FMC,2,0)
ethaderu 3:78f223d34f36 6343 #define FMC_DATAW2S1U FMC_DATA_U_REG(FMC,2,1)
ethaderu 3:78f223d34f36 6344 #define FMC_DATAW2S1L FMC_DATA_L_REG(FMC,2,1)
ethaderu 3:78f223d34f36 6345 #define FMC_DATAW2S2U FMC_DATA_U_REG(FMC,2,2)
ethaderu 3:78f223d34f36 6346 #define FMC_DATAW2S2L FMC_DATA_L_REG(FMC,2,2)
ethaderu 3:78f223d34f36 6347 #define FMC_DATAW2S3U FMC_DATA_U_REG(FMC,2,3)
ethaderu 3:78f223d34f36 6348 #define FMC_DATAW2S3L FMC_DATA_L_REG(FMC,2,3)
ethaderu 3:78f223d34f36 6349 #define FMC_DATAW3S0U FMC_DATA_U_REG(FMC,3,0)
ethaderu 3:78f223d34f36 6350 #define FMC_DATAW3S0L FMC_DATA_L_REG(FMC,3,0)
ethaderu 3:78f223d34f36 6351 #define FMC_DATAW3S1U FMC_DATA_U_REG(FMC,3,1)
ethaderu 3:78f223d34f36 6352 #define FMC_DATAW3S1L FMC_DATA_L_REG(FMC,3,1)
ethaderu 3:78f223d34f36 6353 #define FMC_DATAW3S2U FMC_DATA_U_REG(FMC,3,2)
ethaderu 3:78f223d34f36 6354 #define FMC_DATAW3S2L FMC_DATA_L_REG(FMC,3,2)
ethaderu 3:78f223d34f36 6355 #define FMC_DATAW3S3U FMC_DATA_U_REG(FMC,3,3)
ethaderu 3:78f223d34f36 6356 #define FMC_DATAW3S3L FMC_DATA_L_REG(FMC,3,3)
ethaderu 3:78f223d34f36 6357
ethaderu 3:78f223d34f36 6358 /* FMC - Register array accessors */
ethaderu 3:78f223d34f36 6359 #define FMC_TAGVDW0S(index) FMC_TAGVDW0S_REG(FMC,index)
ethaderu 3:78f223d34f36 6360 #define FMC_TAGVDW1S(index) FMC_TAGVDW1S_REG(FMC,index)
ethaderu 3:78f223d34f36 6361 #define FMC_TAGVDW2S(index) FMC_TAGVDW2S_REG(FMC,index)
ethaderu 3:78f223d34f36 6362 #define FMC_TAGVDW3S(index) FMC_TAGVDW3S_REG(FMC,index)
ethaderu 3:78f223d34f36 6363 #define FMC_DATA_U(index,index2) FMC_DATA_U_REG(FMC,index,index2)
ethaderu 3:78f223d34f36 6364 #define FMC_DATA_L(index,index2) FMC_DATA_L_REG(FMC,index,index2)
ethaderu 3:78f223d34f36 6365
ethaderu 3:78f223d34f36 6366 /*!
ethaderu 3:78f223d34f36 6367 * @}
ethaderu 3:78f223d34f36 6368 */ /* end of group FMC_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 6369
ethaderu 3:78f223d34f36 6370
ethaderu 3:78f223d34f36 6371 /*!
ethaderu 3:78f223d34f36 6372 * @}
ethaderu 3:78f223d34f36 6373 */ /* end of group FMC_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 6374
ethaderu 3:78f223d34f36 6375
ethaderu 3:78f223d34f36 6376 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 6377 -- FTFE Peripheral Access Layer
ethaderu 3:78f223d34f36 6378 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 6379
ethaderu 3:78f223d34f36 6380 /*!
ethaderu 3:78f223d34f36 6381 * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
ethaderu 3:78f223d34f36 6382 * @{
ethaderu 3:78f223d34f36 6383 */
ethaderu 3:78f223d34f36 6384
ethaderu 3:78f223d34f36 6385 /** FTFE - Register Layout Typedef */
ethaderu 3:78f223d34f36 6386 typedef struct {
ethaderu 3:78f223d34f36 6387 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
ethaderu 3:78f223d34f36 6388 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
ethaderu 3:78f223d34f36 6389 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
ethaderu 3:78f223d34f36 6390 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
ethaderu 3:78f223d34f36 6391 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
ethaderu 3:78f223d34f36 6392 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
ethaderu 3:78f223d34f36 6393 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
ethaderu 3:78f223d34f36 6394 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
ethaderu 3:78f223d34f36 6395 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
ethaderu 3:78f223d34f36 6396 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
ethaderu 3:78f223d34f36 6397 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
ethaderu 3:78f223d34f36 6398 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
ethaderu 3:78f223d34f36 6399 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
ethaderu 3:78f223d34f36 6400 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
ethaderu 3:78f223d34f36 6401 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
ethaderu 3:78f223d34f36 6402 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
ethaderu 3:78f223d34f36 6403 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
ethaderu 3:78f223d34f36 6404 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
ethaderu 3:78f223d34f36 6405 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
ethaderu 3:78f223d34f36 6406 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
ethaderu 3:78f223d34f36 6407 uint8_t RESERVED_0[2];
ethaderu 3:78f223d34f36 6408 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
ethaderu 3:78f223d34f36 6409 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
ethaderu 3:78f223d34f36 6410 } FTFE_Type, *FTFE_MemMapPtr;
ethaderu 3:78f223d34f36 6411
ethaderu 3:78f223d34f36 6412 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 6413 -- FTFE - Register accessor macros
ethaderu 3:78f223d34f36 6414 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 6415
ethaderu 3:78f223d34f36 6416 /*!
ethaderu 3:78f223d34f36 6417 * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
ethaderu 3:78f223d34f36 6418 * @{
ethaderu 3:78f223d34f36 6419 */
ethaderu 3:78f223d34f36 6420
ethaderu 3:78f223d34f36 6421
ethaderu 3:78f223d34f36 6422 /* FTFE - Register accessors */
ethaderu 3:78f223d34f36 6423 #define FTFE_FSTAT_REG(base) ((base)->FSTAT)
ethaderu 3:78f223d34f36 6424 #define FTFE_FCNFG_REG(base) ((base)->FCNFG)
ethaderu 3:78f223d34f36 6425 #define FTFE_FSEC_REG(base) ((base)->FSEC)
ethaderu 3:78f223d34f36 6426 #define FTFE_FOPT_REG(base) ((base)->FOPT)
ethaderu 3:78f223d34f36 6427 #define FTFE_FCCOB3_REG(base) ((base)->FCCOB3)
ethaderu 3:78f223d34f36 6428 #define FTFE_FCCOB2_REG(base) ((base)->FCCOB2)
ethaderu 3:78f223d34f36 6429 #define FTFE_FCCOB1_REG(base) ((base)->FCCOB1)
ethaderu 3:78f223d34f36 6430 #define FTFE_FCCOB0_REG(base) ((base)->FCCOB0)
ethaderu 3:78f223d34f36 6431 #define FTFE_FCCOB7_REG(base) ((base)->FCCOB7)
ethaderu 3:78f223d34f36 6432 #define FTFE_FCCOB6_REG(base) ((base)->FCCOB6)
ethaderu 3:78f223d34f36 6433 #define FTFE_FCCOB5_REG(base) ((base)->FCCOB5)
ethaderu 3:78f223d34f36 6434 #define FTFE_FCCOB4_REG(base) ((base)->FCCOB4)
ethaderu 3:78f223d34f36 6435 #define FTFE_FCCOBB_REG(base) ((base)->FCCOBB)
ethaderu 3:78f223d34f36 6436 #define FTFE_FCCOBA_REG(base) ((base)->FCCOBA)
ethaderu 3:78f223d34f36 6437 #define FTFE_FCCOB9_REG(base) ((base)->FCCOB9)
ethaderu 3:78f223d34f36 6438 #define FTFE_FCCOB8_REG(base) ((base)->FCCOB8)
ethaderu 3:78f223d34f36 6439 #define FTFE_FPROT3_REG(base) ((base)->FPROT3)
ethaderu 3:78f223d34f36 6440 #define FTFE_FPROT2_REG(base) ((base)->FPROT2)
ethaderu 3:78f223d34f36 6441 #define FTFE_FPROT1_REG(base) ((base)->FPROT1)
ethaderu 3:78f223d34f36 6442 #define FTFE_FPROT0_REG(base) ((base)->FPROT0)
ethaderu 3:78f223d34f36 6443 #define FTFE_FEPROT_REG(base) ((base)->FEPROT)
ethaderu 3:78f223d34f36 6444 #define FTFE_FDPROT_REG(base) ((base)->FDPROT)
ethaderu 3:78f223d34f36 6445
ethaderu 3:78f223d34f36 6446 /*!
ethaderu 3:78f223d34f36 6447 * @}
ethaderu 3:78f223d34f36 6448 */ /* end of group FTFE_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 6449
ethaderu 3:78f223d34f36 6450
ethaderu 3:78f223d34f36 6451 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 6452 -- FTFE Register Masks
ethaderu 3:78f223d34f36 6453 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 6454
ethaderu 3:78f223d34f36 6455 /*!
ethaderu 3:78f223d34f36 6456 * @addtogroup FTFE_Register_Masks FTFE Register Masks
ethaderu 3:78f223d34f36 6457 * @{
ethaderu 3:78f223d34f36 6458 */
ethaderu 3:78f223d34f36 6459
ethaderu 3:78f223d34f36 6460 /* FSTAT Bit Fields */
ethaderu 3:78f223d34f36 6461 #define FTFE_FSTAT_MGSTAT0_MASK 0x1u
ethaderu 3:78f223d34f36 6462 #define FTFE_FSTAT_MGSTAT0_SHIFT 0
ethaderu 3:78f223d34f36 6463 #define FTFE_FSTAT_FPVIOL_MASK 0x10u
ethaderu 3:78f223d34f36 6464 #define FTFE_FSTAT_FPVIOL_SHIFT 4
ethaderu 3:78f223d34f36 6465 #define FTFE_FSTAT_ACCERR_MASK 0x20u
ethaderu 3:78f223d34f36 6466 #define FTFE_FSTAT_ACCERR_SHIFT 5
ethaderu 3:78f223d34f36 6467 #define FTFE_FSTAT_RDCOLERR_MASK 0x40u
ethaderu 3:78f223d34f36 6468 #define FTFE_FSTAT_RDCOLERR_SHIFT 6
ethaderu 3:78f223d34f36 6469 #define FTFE_FSTAT_CCIF_MASK 0x80u
ethaderu 3:78f223d34f36 6470 #define FTFE_FSTAT_CCIF_SHIFT 7
ethaderu 3:78f223d34f36 6471 /* FCNFG Bit Fields */
ethaderu 3:78f223d34f36 6472 #define FTFE_FCNFG_EEERDY_MASK 0x1u
ethaderu 3:78f223d34f36 6473 #define FTFE_FCNFG_EEERDY_SHIFT 0
ethaderu 3:78f223d34f36 6474 #define FTFE_FCNFG_RAMRDY_MASK 0x2u
ethaderu 3:78f223d34f36 6475 #define FTFE_FCNFG_RAMRDY_SHIFT 1
ethaderu 3:78f223d34f36 6476 #define FTFE_FCNFG_PFLSH_MASK 0x4u
ethaderu 3:78f223d34f36 6477 #define FTFE_FCNFG_PFLSH_SHIFT 2
ethaderu 3:78f223d34f36 6478 #define FTFE_FCNFG_SWAP_MASK 0x8u
ethaderu 3:78f223d34f36 6479 #define FTFE_FCNFG_SWAP_SHIFT 3
ethaderu 3:78f223d34f36 6480 #define FTFE_FCNFG_ERSSUSP_MASK 0x10u
ethaderu 3:78f223d34f36 6481 #define FTFE_FCNFG_ERSSUSP_SHIFT 4
ethaderu 3:78f223d34f36 6482 #define FTFE_FCNFG_ERSAREQ_MASK 0x20u
ethaderu 3:78f223d34f36 6483 #define FTFE_FCNFG_ERSAREQ_SHIFT 5
ethaderu 3:78f223d34f36 6484 #define FTFE_FCNFG_RDCOLLIE_MASK 0x40u
ethaderu 3:78f223d34f36 6485 #define FTFE_FCNFG_RDCOLLIE_SHIFT 6
ethaderu 3:78f223d34f36 6486 #define FTFE_FCNFG_CCIE_MASK 0x80u
ethaderu 3:78f223d34f36 6487 #define FTFE_FCNFG_CCIE_SHIFT 7
ethaderu 3:78f223d34f36 6488 /* FSEC Bit Fields */
ethaderu 3:78f223d34f36 6489 #define FTFE_FSEC_SEC_MASK 0x3u
ethaderu 3:78f223d34f36 6490 #define FTFE_FSEC_SEC_SHIFT 0
ethaderu 3:78f223d34f36 6491 #define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_SEC_SHIFT))&FTFE_FSEC_SEC_MASK)
ethaderu 3:78f223d34f36 6492 #define FTFE_FSEC_FSLACC_MASK 0xCu
ethaderu 3:78f223d34f36 6493 #define FTFE_FSEC_FSLACC_SHIFT 2
ethaderu 3:78f223d34f36 6494 #define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_FSLACC_SHIFT))&FTFE_FSEC_FSLACC_MASK)
ethaderu 3:78f223d34f36 6495 #define FTFE_FSEC_MEEN_MASK 0x30u
ethaderu 3:78f223d34f36 6496 #define FTFE_FSEC_MEEN_SHIFT 4
ethaderu 3:78f223d34f36 6497 #define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_MEEN_SHIFT))&FTFE_FSEC_MEEN_MASK)
ethaderu 3:78f223d34f36 6498 #define FTFE_FSEC_KEYEN_MASK 0xC0u
ethaderu 3:78f223d34f36 6499 #define FTFE_FSEC_KEYEN_SHIFT 6
ethaderu 3:78f223d34f36 6500 #define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_KEYEN_SHIFT))&FTFE_FSEC_KEYEN_MASK)
ethaderu 3:78f223d34f36 6501 /* FOPT Bit Fields */
ethaderu 3:78f223d34f36 6502 #define FTFE_FOPT_OPT_MASK 0xFFu
ethaderu 3:78f223d34f36 6503 #define FTFE_FOPT_OPT_SHIFT 0
ethaderu 3:78f223d34f36 6504 #define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FOPT_OPT_SHIFT))&FTFE_FOPT_OPT_MASK)
ethaderu 3:78f223d34f36 6505 /* FCCOB3 Bit Fields */
ethaderu 3:78f223d34f36 6506 #define FTFE_FCCOB3_CCOBn_MASK 0xFFu
ethaderu 3:78f223d34f36 6507 #define FTFE_FCCOB3_CCOBn_SHIFT 0
ethaderu 3:78f223d34f36 6508 #define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB3_CCOBn_SHIFT))&FTFE_FCCOB3_CCOBn_MASK)
ethaderu 3:78f223d34f36 6509 /* FCCOB2 Bit Fields */
ethaderu 3:78f223d34f36 6510 #define FTFE_FCCOB2_CCOBn_MASK 0xFFu
ethaderu 3:78f223d34f36 6511 #define FTFE_FCCOB2_CCOBn_SHIFT 0
ethaderu 3:78f223d34f36 6512 #define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB2_CCOBn_SHIFT))&FTFE_FCCOB2_CCOBn_MASK)
ethaderu 3:78f223d34f36 6513 /* FCCOB1 Bit Fields */
ethaderu 3:78f223d34f36 6514 #define FTFE_FCCOB1_CCOBn_MASK 0xFFu
ethaderu 3:78f223d34f36 6515 #define FTFE_FCCOB1_CCOBn_SHIFT 0
ethaderu 3:78f223d34f36 6516 #define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB1_CCOBn_SHIFT))&FTFE_FCCOB1_CCOBn_MASK)
ethaderu 3:78f223d34f36 6517 /* FCCOB0 Bit Fields */
ethaderu 3:78f223d34f36 6518 #define FTFE_FCCOB0_CCOBn_MASK 0xFFu
ethaderu 3:78f223d34f36 6519 #define FTFE_FCCOB0_CCOBn_SHIFT 0
ethaderu 3:78f223d34f36 6520 #define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB0_CCOBn_SHIFT))&FTFE_FCCOB0_CCOBn_MASK)
ethaderu 3:78f223d34f36 6521 /* FCCOB7 Bit Fields */
ethaderu 3:78f223d34f36 6522 #define FTFE_FCCOB7_CCOBn_MASK 0xFFu
ethaderu 3:78f223d34f36 6523 #define FTFE_FCCOB7_CCOBn_SHIFT 0
ethaderu 3:78f223d34f36 6524 #define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB7_CCOBn_SHIFT))&FTFE_FCCOB7_CCOBn_MASK)
ethaderu 3:78f223d34f36 6525 /* FCCOB6 Bit Fields */
ethaderu 3:78f223d34f36 6526 #define FTFE_FCCOB6_CCOBn_MASK 0xFFu
ethaderu 3:78f223d34f36 6527 #define FTFE_FCCOB6_CCOBn_SHIFT 0
ethaderu 3:78f223d34f36 6528 #define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB6_CCOBn_SHIFT))&FTFE_FCCOB6_CCOBn_MASK)
ethaderu 3:78f223d34f36 6529 /* FCCOB5 Bit Fields */
ethaderu 3:78f223d34f36 6530 #define FTFE_FCCOB5_CCOBn_MASK 0xFFu
ethaderu 3:78f223d34f36 6531 #define FTFE_FCCOB5_CCOBn_SHIFT 0
ethaderu 3:78f223d34f36 6532 #define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB5_CCOBn_SHIFT))&FTFE_FCCOB5_CCOBn_MASK)
ethaderu 3:78f223d34f36 6533 /* FCCOB4 Bit Fields */
ethaderu 3:78f223d34f36 6534 #define FTFE_FCCOB4_CCOBn_MASK 0xFFu
ethaderu 3:78f223d34f36 6535 #define FTFE_FCCOB4_CCOBn_SHIFT 0
ethaderu 3:78f223d34f36 6536 #define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB4_CCOBn_SHIFT))&FTFE_FCCOB4_CCOBn_MASK)
ethaderu 3:78f223d34f36 6537 /* FCCOBB Bit Fields */
ethaderu 3:78f223d34f36 6538 #define FTFE_FCCOBB_CCOBn_MASK 0xFFu
ethaderu 3:78f223d34f36 6539 #define FTFE_FCCOBB_CCOBn_SHIFT 0
ethaderu 3:78f223d34f36 6540 #define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBB_CCOBn_SHIFT))&FTFE_FCCOBB_CCOBn_MASK)
ethaderu 3:78f223d34f36 6541 /* FCCOBA Bit Fields */
ethaderu 3:78f223d34f36 6542 #define FTFE_FCCOBA_CCOBn_MASK 0xFFu
ethaderu 3:78f223d34f36 6543 #define FTFE_FCCOBA_CCOBn_SHIFT 0
ethaderu 3:78f223d34f36 6544 #define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBA_CCOBn_SHIFT))&FTFE_FCCOBA_CCOBn_MASK)
ethaderu 3:78f223d34f36 6545 /* FCCOB9 Bit Fields */
ethaderu 3:78f223d34f36 6546 #define FTFE_FCCOB9_CCOBn_MASK 0xFFu
ethaderu 3:78f223d34f36 6547 #define FTFE_FCCOB9_CCOBn_SHIFT 0
ethaderu 3:78f223d34f36 6548 #define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB9_CCOBn_SHIFT))&FTFE_FCCOB9_CCOBn_MASK)
ethaderu 3:78f223d34f36 6549 /* FCCOB8 Bit Fields */
ethaderu 3:78f223d34f36 6550 #define FTFE_FCCOB8_CCOBn_MASK 0xFFu
ethaderu 3:78f223d34f36 6551 #define FTFE_FCCOB8_CCOBn_SHIFT 0
ethaderu 3:78f223d34f36 6552 #define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB8_CCOBn_SHIFT))&FTFE_FCCOB8_CCOBn_MASK)
ethaderu 3:78f223d34f36 6553 /* FPROT3 Bit Fields */
ethaderu 3:78f223d34f36 6554 #define FTFE_FPROT3_PROT_MASK 0xFFu
ethaderu 3:78f223d34f36 6555 #define FTFE_FPROT3_PROT_SHIFT 0
ethaderu 3:78f223d34f36 6556 #define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT3_PROT_SHIFT))&FTFE_FPROT3_PROT_MASK)
ethaderu 3:78f223d34f36 6557 /* FPROT2 Bit Fields */
ethaderu 3:78f223d34f36 6558 #define FTFE_FPROT2_PROT_MASK 0xFFu
ethaderu 3:78f223d34f36 6559 #define FTFE_FPROT2_PROT_SHIFT 0
ethaderu 3:78f223d34f36 6560 #define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT2_PROT_SHIFT))&FTFE_FPROT2_PROT_MASK)
ethaderu 3:78f223d34f36 6561 /* FPROT1 Bit Fields */
ethaderu 3:78f223d34f36 6562 #define FTFE_FPROT1_PROT_MASK 0xFFu
ethaderu 3:78f223d34f36 6563 #define FTFE_FPROT1_PROT_SHIFT 0
ethaderu 3:78f223d34f36 6564 #define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT1_PROT_SHIFT))&FTFE_FPROT1_PROT_MASK)
ethaderu 3:78f223d34f36 6565 /* FPROT0 Bit Fields */
ethaderu 3:78f223d34f36 6566 #define FTFE_FPROT0_PROT_MASK 0xFFu
ethaderu 3:78f223d34f36 6567 #define FTFE_FPROT0_PROT_SHIFT 0
ethaderu 3:78f223d34f36 6568 #define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT0_PROT_SHIFT))&FTFE_FPROT0_PROT_MASK)
ethaderu 3:78f223d34f36 6569 /* FEPROT Bit Fields */
ethaderu 3:78f223d34f36 6570 #define FTFE_FEPROT_EPROT_MASK 0xFFu
ethaderu 3:78f223d34f36 6571 #define FTFE_FEPROT_EPROT_SHIFT 0
ethaderu 3:78f223d34f36 6572 #define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FEPROT_EPROT_SHIFT))&FTFE_FEPROT_EPROT_MASK)
ethaderu 3:78f223d34f36 6573 /* FDPROT Bit Fields */
ethaderu 3:78f223d34f36 6574 #define FTFE_FDPROT_DPROT_MASK 0xFFu
ethaderu 3:78f223d34f36 6575 #define FTFE_FDPROT_DPROT_SHIFT 0
ethaderu 3:78f223d34f36 6576 #define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FDPROT_DPROT_SHIFT))&FTFE_FDPROT_DPROT_MASK)
ethaderu 3:78f223d34f36 6577
ethaderu 3:78f223d34f36 6578 /*!
ethaderu 3:78f223d34f36 6579 * @}
ethaderu 3:78f223d34f36 6580 */ /* end of group FTFE_Register_Masks */
ethaderu 3:78f223d34f36 6581
ethaderu 3:78f223d34f36 6582
ethaderu 3:78f223d34f36 6583 /* FTFE - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 6584 /** Peripheral FTFE base address */
ethaderu 3:78f223d34f36 6585 #define FTFE_BASE (0x40020000u)
ethaderu 3:78f223d34f36 6586 /** Peripheral FTFE base pointer */
ethaderu 3:78f223d34f36 6587 #define FTFE ((FTFE_Type *)FTFE_BASE)
ethaderu 3:78f223d34f36 6588 #define FTFE_BASE_PTR (FTFE)
ethaderu 3:78f223d34f36 6589 /** Array initializer of FTFE peripheral base addresses */
ethaderu 3:78f223d34f36 6590 #define FTFE_BASE_ADDRS { FTFE_BASE }
ethaderu 3:78f223d34f36 6591 /** Array initializer of FTFE peripheral base pointers */
ethaderu 3:78f223d34f36 6592 #define FTFE_BASE_PTRS { FTFE }
ethaderu 3:78f223d34f36 6593 /** Interrupt vectors for the FTFE peripheral type */
ethaderu 3:78f223d34f36 6594 #define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn }
ethaderu 3:78f223d34f36 6595 #define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn }
ethaderu 3:78f223d34f36 6596
ethaderu 3:78f223d34f36 6597 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 6598 -- FTFE - Register accessor macros
ethaderu 3:78f223d34f36 6599 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 6600
ethaderu 3:78f223d34f36 6601 /*!
ethaderu 3:78f223d34f36 6602 * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
ethaderu 3:78f223d34f36 6603 * @{
ethaderu 3:78f223d34f36 6604 */
ethaderu 3:78f223d34f36 6605
ethaderu 3:78f223d34f36 6606
ethaderu 3:78f223d34f36 6607 /* FTFE - Register instance definitions */
ethaderu 3:78f223d34f36 6608 /* FTFE */
ethaderu 3:78f223d34f36 6609 #define FTFE_FSTAT FTFE_FSTAT_REG(FTFE)
ethaderu 3:78f223d34f36 6610 #define FTFE_FCNFG FTFE_FCNFG_REG(FTFE)
ethaderu 3:78f223d34f36 6611 #define FTFE_FSEC FTFE_FSEC_REG(FTFE)
ethaderu 3:78f223d34f36 6612 #define FTFE_FOPT FTFE_FOPT_REG(FTFE)
ethaderu 3:78f223d34f36 6613 #define FTFE_FCCOB3 FTFE_FCCOB3_REG(FTFE)
ethaderu 3:78f223d34f36 6614 #define FTFE_FCCOB2 FTFE_FCCOB2_REG(FTFE)
ethaderu 3:78f223d34f36 6615 #define FTFE_FCCOB1 FTFE_FCCOB1_REG(FTFE)
ethaderu 3:78f223d34f36 6616 #define FTFE_FCCOB0 FTFE_FCCOB0_REG(FTFE)
ethaderu 3:78f223d34f36 6617 #define FTFE_FCCOB7 FTFE_FCCOB7_REG(FTFE)
ethaderu 3:78f223d34f36 6618 #define FTFE_FCCOB6 FTFE_FCCOB6_REG(FTFE)
ethaderu 3:78f223d34f36 6619 #define FTFE_FCCOB5 FTFE_FCCOB5_REG(FTFE)
ethaderu 3:78f223d34f36 6620 #define FTFE_FCCOB4 FTFE_FCCOB4_REG(FTFE)
ethaderu 3:78f223d34f36 6621 #define FTFE_FCCOBB FTFE_FCCOBB_REG(FTFE)
ethaderu 3:78f223d34f36 6622 #define FTFE_FCCOBA FTFE_FCCOBA_REG(FTFE)
ethaderu 3:78f223d34f36 6623 #define FTFE_FCCOB9 FTFE_FCCOB9_REG(FTFE)
ethaderu 3:78f223d34f36 6624 #define FTFE_FCCOB8 FTFE_FCCOB8_REG(FTFE)
ethaderu 3:78f223d34f36 6625 #define FTFE_FPROT3 FTFE_FPROT3_REG(FTFE)
ethaderu 3:78f223d34f36 6626 #define FTFE_FPROT2 FTFE_FPROT2_REG(FTFE)
ethaderu 3:78f223d34f36 6627 #define FTFE_FPROT1 FTFE_FPROT1_REG(FTFE)
ethaderu 3:78f223d34f36 6628 #define FTFE_FPROT0 FTFE_FPROT0_REG(FTFE)
ethaderu 3:78f223d34f36 6629 #define FTFE_FEPROT FTFE_FEPROT_REG(FTFE)
ethaderu 3:78f223d34f36 6630 #define FTFE_FDPROT FTFE_FDPROT_REG(FTFE)
ethaderu 3:78f223d34f36 6631
ethaderu 3:78f223d34f36 6632 /*!
ethaderu 3:78f223d34f36 6633 * @}
ethaderu 3:78f223d34f36 6634 */ /* end of group FTFE_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 6635
ethaderu 3:78f223d34f36 6636
ethaderu 3:78f223d34f36 6637 /*!
ethaderu 3:78f223d34f36 6638 * @}
ethaderu 3:78f223d34f36 6639 */ /* end of group FTFE_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 6640
ethaderu 3:78f223d34f36 6641
ethaderu 3:78f223d34f36 6642 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 6643 -- FTM Peripheral Access Layer
ethaderu 3:78f223d34f36 6644 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 6645
ethaderu 3:78f223d34f36 6646 /*!
ethaderu 3:78f223d34f36 6647 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
ethaderu 3:78f223d34f36 6648 * @{
ethaderu 3:78f223d34f36 6649 */
ethaderu 3:78f223d34f36 6650
ethaderu 3:78f223d34f36 6651 /** FTM - Register Layout Typedef */
ethaderu 3:78f223d34f36 6652 typedef struct {
ethaderu 3:78f223d34f36 6653 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
ethaderu 3:78f223d34f36 6654 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
ethaderu 3:78f223d34f36 6655 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
ethaderu 3:78f223d34f36 6656 struct { /* offset: 0xC, array step: 0x8 */
ethaderu 3:78f223d34f36 6657 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
ethaderu 3:78f223d34f36 6658 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
ethaderu 3:78f223d34f36 6659 } CONTROLS[8];
ethaderu 3:78f223d34f36 6660 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
ethaderu 3:78f223d34f36 6661 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
ethaderu 3:78f223d34f36 6662 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
ethaderu 3:78f223d34f36 6663 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
ethaderu 3:78f223d34f36 6664 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
ethaderu 3:78f223d34f36 6665 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
ethaderu 3:78f223d34f36 6666 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
ethaderu 3:78f223d34f36 6667 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
ethaderu 3:78f223d34f36 6668 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
ethaderu 3:78f223d34f36 6669 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
ethaderu 3:78f223d34f36 6670 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
ethaderu 3:78f223d34f36 6671 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
ethaderu 3:78f223d34f36 6672 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
ethaderu 3:78f223d34f36 6673 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
ethaderu 3:78f223d34f36 6674 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
ethaderu 3:78f223d34f36 6675 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
ethaderu 3:78f223d34f36 6676 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
ethaderu 3:78f223d34f36 6677 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
ethaderu 3:78f223d34f36 6678 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
ethaderu 3:78f223d34f36 6679 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
ethaderu 3:78f223d34f36 6680 } FTM_Type, *FTM_MemMapPtr;
ethaderu 3:78f223d34f36 6681
ethaderu 3:78f223d34f36 6682 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 6683 -- FTM - Register accessor macros
ethaderu 3:78f223d34f36 6684 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 6685
ethaderu 3:78f223d34f36 6686 /*!
ethaderu 3:78f223d34f36 6687 * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
ethaderu 3:78f223d34f36 6688 * @{
ethaderu 3:78f223d34f36 6689 */
ethaderu 3:78f223d34f36 6690
ethaderu 3:78f223d34f36 6691
ethaderu 3:78f223d34f36 6692 /* FTM - Register accessors */
ethaderu 3:78f223d34f36 6693 #define FTM_SC_REG(base) ((base)->SC)
ethaderu 3:78f223d34f36 6694 #define FTM_CNT_REG(base) ((base)->CNT)
ethaderu 3:78f223d34f36 6695 #define FTM_MOD_REG(base) ((base)->MOD)
ethaderu 3:78f223d34f36 6696 #define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
ethaderu 3:78f223d34f36 6697 #define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
ethaderu 3:78f223d34f36 6698 #define FTM_CNTIN_REG(base) ((base)->CNTIN)
ethaderu 3:78f223d34f36 6699 #define FTM_STATUS_REG(base) ((base)->STATUS)
ethaderu 3:78f223d34f36 6700 #define FTM_MODE_REG(base) ((base)->MODE)
ethaderu 3:78f223d34f36 6701 #define FTM_SYNC_REG(base) ((base)->SYNC)
ethaderu 3:78f223d34f36 6702 #define FTM_OUTINIT_REG(base) ((base)->OUTINIT)
ethaderu 3:78f223d34f36 6703 #define FTM_OUTMASK_REG(base) ((base)->OUTMASK)
ethaderu 3:78f223d34f36 6704 #define FTM_COMBINE_REG(base) ((base)->COMBINE)
ethaderu 3:78f223d34f36 6705 #define FTM_DEADTIME_REG(base) ((base)->DEADTIME)
ethaderu 3:78f223d34f36 6706 #define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)
ethaderu 3:78f223d34f36 6707 #define FTM_POL_REG(base) ((base)->POL)
ethaderu 3:78f223d34f36 6708 #define FTM_FMS_REG(base) ((base)->FMS)
ethaderu 3:78f223d34f36 6709 #define FTM_FILTER_REG(base) ((base)->FILTER)
ethaderu 3:78f223d34f36 6710 #define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)
ethaderu 3:78f223d34f36 6711 #define FTM_QDCTRL_REG(base) ((base)->QDCTRL)
ethaderu 3:78f223d34f36 6712 #define FTM_CONF_REG(base) ((base)->CONF)
ethaderu 3:78f223d34f36 6713 #define FTM_FLTPOL_REG(base) ((base)->FLTPOL)
ethaderu 3:78f223d34f36 6714 #define FTM_SYNCONF_REG(base) ((base)->SYNCONF)
ethaderu 3:78f223d34f36 6715 #define FTM_INVCTRL_REG(base) ((base)->INVCTRL)
ethaderu 3:78f223d34f36 6716 #define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)
ethaderu 3:78f223d34f36 6717 #define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)
ethaderu 3:78f223d34f36 6718
ethaderu 3:78f223d34f36 6719 /*!
ethaderu 3:78f223d34f36 6720 * @}
ethaderu 3:78f223d34f36 6721 */ /* end of group FTM_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 6722
ethaderu 3:78f223d34f36 6723
ethaderu 3:78f223d34f36 6724 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 6725 -- FTM Register Masks
ethaderu 3:78f223d34f36 6726 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 6727
ethaderu 3:78f223d34f36 6728 /*!
ethaderu 3:78f223d34f36 6729 * @addtogroup FTM_Register_Masks FTM Register Masks
ethaderu 3:78f223d34f36 6730 * @{
ethaderu 3:78f223d34f36 6731 */
ethaderu 3:78f223d34f36 6732
ethaderu 3:78f223d34f36 6733 /* SC Bit Fields */
ethaderu 3:78f223d34f36 6734 #define FTM_SC_PS_MASK 0x7u
ethaderu 3:78f223d34f36 6735 #define FTM_SC_PS_SHIFT 0
ethaderu 3:78f223d34f36 6736 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
ethaderu 3:78f223d34f36 6737 #define FTM_SC_CLKS_MASK 0x18u
ethaderu 3:78f223d34f36 6738 #define FTM_SC_CLKS_SHIFT 3
ethaderu 3:78f223d34f36 6739 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
ethaderu 3:78f223d34f36 6740 #define FTM_SC_CPWMS_MASK 0x20u
ethaderu 3:78f223d34f36 6741 #define FTM_SC_CPWMS_SHIFT 5
ethaderu 3:78f223d34f36 6742 #define FTM_SC_TOIE_MASK 0x40u
ethaderu 3:78f223d34f36 6743 #define FTM_SC_TOIE_SHIFT 6
ethaderu 3:78f223d34f36 6744 #define FTM_SC_TOF_MASK 0x80u
ethaderu 3:78f223d34f36 6745 #define FTM_SC_TOF_SHIFT 7
ethaderu 3:78f223d34f36 6746 /* CNT Bit Fields */
ethaderu 3:78f223d34f36 6747 #define FTM_CNT_COUNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 6748 #define FTM_CNT_COUNT_SHIFT 0
ethaderu 3:78f223d34f36 6749 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
ethaderu 3:78f223d34f36 6750 /* MOD Bit Fields */
ethaderu 3:78f223d34f36 6751 #define FTM_MOD_MOD_MASK 0xFFFFu
ethaderu 3:78f223d34f36 6752 #define FTM_MOD_MOD_SHIFT 0
ethaderu 3:78f223d34f36 6753 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
ethaderu 3:78f223d34f36 6754 /* CnSC Bit Fields */
ethaderu 3:78f223d34f36 6755 #define FTM_CnSC_DMA_MASK 0x1u
ethaderu 3:78f223d34f36 6756 #define FTM_CnSC_DMA_SHIFT 0
ethaderu 3:78f223d34f36 6757 #define FTM_CnSC_ELSA_MASK 0x4u
ethaderu 3:78f223d34f36 6758 #define FTM_CnSC_ELSA_SHIFT 2
ethaderu 3:78f223d34f36 6759 #define FTM_CnSC_ELSB_MASK 0x8u
ethaderu 3:78f223d34f36 6760 #define FTM_CnSC_ELSB_SHIFT 3
ethaderu 3:78f223d34f36 6761 #define FTM_CnSC_MSA_MASK 0x10u
ethaderu 3:78f223d34f36 6762 #define FTM_CnSC_MSA_SHIFT 4
ethaderu 3:78f223d34f36 6763 #define FTM_CnSC_MSB_MASK 0x20u
ethaderu 3:78f223d34f36 6764 #define FTM_CnSC_MSB_SHIFT 5
ethaderu 3:78f223d34f36 6765 #define FTM_CnSC_CHIE_MASK 0x40u
ethaderu 3:78f223d34f36 6766 #define FTM_CnSC_CHIE_SHIFT 6
ethaderu 3:78f223d34f36 6767 #define FTM_CnSC_CHF_MASK 0x80u
ethaderu 3:78f223d34f36 6768 #define FTM_CnSC_CHF_SHIFT 7
ethaderu 3:78f223d34f36 6769 /* CnV Bit Fields */
ethaderu 3:78f223d34f36 6770 #define FTM_CnV_VAL_MASK 0xFFFFu
ethaderu 3:78f223d34f36 6771 #define FTM_CnV_VAL_SHIFT 0
ethaderu 3:78f223d34f36 6772 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
ethaderu 3:78f223d34f36 6773 /* CNTIN Bit Fields */
ethaderu 3:78f223d34f36 6774 #define FTM_CNTIN_INIT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 6775 #define FTM_CNTIN_INIT_SHIFT 0
ethaderu 3:78f223d34f36 6776 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
ethaderu 3:78f223d34f36 6777 /* STATUS Bit Fields */
ethaderu 3:78f223d34f36 6778 #define FTM_STATUS_CH0F_MASK 0x1u
ethaderu 3:78f223d34f36 6779 #define FTM_STATUS_CH0F_SHIFT 0
ethaderu 3:78f223d34f36 6780 #define FTM_STATUS_CH1F_MASK 0x2u
ethaderu 3:78f223d34f36 6781 #define FTM_STATUS_CH1F_SHIFT 1
ethaderu 3:78f223d34f36 6782 #define FTM_STATUS_CH2F_MASK 0x4u
ethaderu 3:78f223d34f36 6783 #define FTM_STATUS_CH2F_SHIFT 2
ethaderu 3:78f223d34f36 6784 #define FTM_STATUS_CH3F_MASK 0x8u
ethaderu 3:78f223d34f36 6785 #define FTM_STATUS_CH3F_SHIFT 3
ethaderu 3:78f223d34f36 6786 #define FTM_STATUS_CH4F_MASK 0x10u
ethaderu 3:78f223d34f36 6787 #define FTM_STATUS_CH4F_SHIFT 4
ethaderu 3:78f223d34f36 6788 #define FTM_STATUS_CH5F_MASK 0x20u
ethaderu 3:78f223d34f36 6789 #define FTM_STATUS_CH5F_SHIFT 5
ethaderu 3:78f223d34f36 6790 #define FTM_STATUS_CH6F_MASK 0x40u
ethaderu 3:78f223d34f36 6791 #define FTM_STATUS_CH6F_SHIFT 6
ethaderu 3:78f223d34f36 6792 #define FTM_STATUS_CH7F_MASK 0x80u
ethaderu 3:78f223d34f36 6793 #define FTM_STATUS_CH7F_SHIFT 7
ethaderu 3:78f223d34f36 6794 /* MODE Bit Fields */
ethaderu 3:78f223d34f36 6795 #define FTM_MODE_FTMEN_MASK 0x1u
ethaderu 3:78f223d34f36 6796 #define FTM_MODE_FTMEN_SHIFT 0
ethaderu 3:78f223d34f36 6797 #define FTM_MODE_INIT_MASK 0x2u
ethaderu 3:78f223d34f36 6798 #define FTM_MODE_INIT_SHIFT 1
ethaderu 3:78f223d34f36 6799 #define FTM_MODE_WPDIS_MASK 0x4u
ethaderu 3:78f223d34f36 6800 #define FTM_MODE_WPDIS_SHIFT 2
ethaderu 3:78f223d34f36 6801 #define FTM_MODE_PWMSYNC_MASK 0x8u
ethaderu 3:78f223d34f36 6802 #define FTM_MODE_PWMSYNC_SHIFT 3
ethaderu 3:78f223d34f36 6803 #define FTM_MODE_CAPTEST_MASK 0x10u
ethaderu 3:78f223d34f36 6804 #define FTM_MODE_CAPTEST_SHIFT 4
ethaderu 3:78f223d34f36 6805 #define FTM_MODE_FAULTM_MASK 0x60u
ethaderu 3:78f223d34f36 6806 #define FTM_MODE_FAULTM_SHIFT 5
ethaderu 3:78f223d34f36 6807 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
ethaderu 3:78f223d34f36 6808 #define FTM_MODE_FAULTIE_MASK 0x80u
ethaderu 3:78f223d34f36 6809 #define FTM_MODE_FAULTIE_SHIFT 7
ethaderu 3:78f223d34f36 6810 /* SYNC Bit Fields */
ethaderu 3:78f223d34f36 6811 #define FTM_SYNC_CNTMIN_MASK 0x1u
ethaderu 3:78f223d34f36 6812 #define FTM_SYNC_CNTMIN_SHIFT 0
ethaderu 3:78f223d34f36 6813 #define FTM_SYNC_CNTMAX_MASK 0x2u
ethaderu 3:78f223d34f36 6814 #define FTM_SYNC_CNTMAX_SHIFT 1
ethaderu 3:78f223d34f36 6815 #define FTM_SYNC_REINIT_MASK 0x4u
ethaderu 3:78f223d34f36 6816 #define FTM_SYNC_REINIT_SHIFT 2
ethaderu 3:78f223d34f36 6817 #define FTM_SYNC_SYNCHOM_MASK 0x8u
ethaderu 3:78f223d34f36 6818 #define FTM_SYNC_SYNCHOM_SHIFT 3
ethaderu 3:78f223d34f36 6819 #define FTM_SYNC_TRIG0_MASK 0x10u
ethaderu 3:78f223d34f36 6820 #define FTM_SYNC_TRIG0_SHIFT 4
ethaderu 3:78f223d34f36 6821 #define FTM_SYNC_TRIG1_MASK 0x20u
ethaderu 3:78f223d34f36 6822 #define FTM_SYNC_TRIG1_SHIFT 5
ethaderu 3:78f223d34f36 6823 #define FTM_SYNC_TRIG2_MASK 0x40u
ethaderu 3:78f223d34f36 6824 #define FTM_SYNC_TRIG2_SHIFT 6
ethaderu 3:78f223d34f36 6825 #define FTM_SYNC_SWSYNC_MASK 0x80u
ethaderu 3:78f223d34f36 6826 #define FTM_SYNC_SWSYNC_SHIFT 7
ethaderu 3:78f223d34f36 6827 /* OUTINIT Bit Fields */
ethaderu 3:78f223d34f36 6828 #define FTM_OUTINIT_CH0OI_MASK 0x1u
ethaderu 3:78f223d34f36 6829 #define FTM_OUTINIT_CH0OI_SHIFT 0
ethaderu 3:78f223d34f36 6830 #define FTM_OUTINIT_CH1OI_MASK 0x2u
ethaderu 3:78f223d34f36 6831 #define FTM_OUTINIT_CH1OI_SHIFT 1
ethaderu 3:78f223d34f36 6832 #define FTM_OUTINIT_CH2OI_MASK 0x4u
ethaderu 3:78f223d34f36 6833 #define FTM_OUTINIT_CH2OI_SHIFT 2
ethaderu 3:78f223d34f36 6834 #define FTM_OUTINIT_CH3OI_MASK 0x8u
ethaderu 3:78f223d34f36 6835 #define FTM_OUTINIT_CH3OI_SHIFT 3
ethaderu 3:78f223d34f36 6836 #define FTM_OUTINIT_CH4OI_MASK 0x10u
ethaderu 3:78f223d34f36 6837 #define FTM_OUTINIT_CH4OI_SHIFT 4
ethaderu 3:78f223d34f36 6838 #define FTM_OUTINIT_CH5OI_MASK 0x20u
ethaderu 3:78f223d34f36 6839 #define FTM_OUTINIT_CH5OI_SHIFT 5
ethaderu 3:78f223d34f36 6840 #define FTM_OUTINIT_CH6OI_MASK 0x40u
ethaderu 3:78f223d34f36 6841 #define FTM_OUTINIT_CH6OI_SHIFT 6
ethaderu 3:78f223d34f36 6842 #define FTM_OUTINIT_CH7OI_MASK 0x80u
ethaderu 3:78f223d34f36 6843 #define FTM_OUTINIT_CH7OI_SHIFT 7
ethaderu 3:78f223d34f36 6844 /* OUTMASK Bit Fields */
ethaderu 3:78f223d34f36 6845 #define FTM_OUTMASK_CH0OM_MASK 0x1u
ethaderu 3:78f223d34f36 6846 #define FTM_OUTMASK_CH0OM_SHIFT 0
ethaderu 3:78f223d34f36 6847 #define FTM_OUTMASK_CH1OM_MASK 0x2u
ethaderu 3:78f223d34f36 6848 #define FTM_OUTMASK_CH1OM_SHIFT 1
ethaderu 3:78f223d34f36 6849 #define FTM_OUTMASK_CH2OM_MASK 0x4u
ethaderu 3:78f223d34f36 6850 #define FTM_OUTMASK_CH2OM_SHIFT 2
ethaderu 3:78f223d34f36 6851 #define FTM_OUTMASK_CH3OM_MASK 0x8u
ethaderu 3:78f223d34f36 6852 #define FTM_OUTMASK_CH3OM_SHIFT 3
ethaderu 3:78f223d34f36 6853 #define FTM_OUTMASK_CH4OM_MASK 0x10u
ethaderu 3:78f223d34f36 6854 #define FTM_OUTMASK_CH4OM_SHIFT 4
ethaderu 3:78f223d34f36 6855 #define FTM_OUTMASK_CH5OM_MASK 0x20u
ethaderu 3:78f223d34f36 6856 #define FTM_OUTMASK_CH5OM_SHIFT 5
ethaderu 3:78f223d34f36 6857 #define FTM_OUTMASK_CH6OM_MASK 0x40u
ethaderu 3:78f223d34f36 6858 #define FTM_OUTMASK_CH6OM_SHIFT 6
ethaderu 3:78f223d34f36 6859 #define FTM_OUTMASK_CH7OM_MASK 0x80u
ethaderu 3:78f223d34f36 6860 #define FTM_OUTMASK_CH7OM_SHIFT 7
ethaderu 3:78f223d34f36 6861 /* COMBINE Bit Fields */
ethaderu 3:78f223d34f36 6862 #define FTM_COMBINE_COMBINE0_MASK 0x1u
ethaderu 3:78f223d34f36 6863 #define FTM_COMBINE_COMBINE0_SHIFT 0
ethaderu 3:78f223d34f36 6864 #define FTM_COMBINE_COMP0_MASK 0x2u
ethaderu 3:78f223d34f36 6865 #define FTM_COMBINE_COMP0_SHIFT 1
ethaderu 3:78f223d34f36 6866 #define FTM_COMBINE_DECAPEN0_MASK 0x4u
ethaderu 3:78f223d34f36 6867 #define FTM_COMBINE_DECAPEN0_SHIFT 2
ethaderu 3:78f223d34f36 6868 #define FTM_COMBINE_DECAP0_MASK 0x8u
ethaderu 3:78f223d34f36 6869 #define FTM_COMBINE_DECAP0_SHIFT 3
ethaderu 3:78f223d34f36 6870 #define FTM_COMBINE_DTEN0_MASK 0x10u
ethaderu 3:78f223d34f36 6871 #define FTM_COMBINE_DTEN0_SHIFT 4
ethaderu 3:78f223d34f36 6872 #define FTM_COMBINE_SYNCEN0_MASK 0x20u
ethaderu 3:78f223d34f36 6873 #define FTM_COMBINE_SYNCEN0_SHIFT 5
ethaderu 3:78f223d34f36 6874 #define FTM_COMBINE_FAULTEN0_MASK 0x40u
ethaderu 3:78f223d34f36 6875 #define FTM_COMBINE_FAULTEN0_SHIFT 6
ethaderu 3:78f223d34f36 6876 #define FTM_COMBINE_COMBINE1_MASK 0x100u
ethaderu 3:78f223d34f36 6877 #define FTM_COMBINE_COMBINE1_SHIFT 8
ethaderu 3:78f223d34f36 6878 #define FTM_COMBINE_COMP1_MASK 0x200u
ethaderu 3:78f223d34f36 6879 #define FTM_COMBINE_COMP1_SHIFT 9
ethaderu 3:78f223d34f36 6880 #define FTM_COMBINE_DECAPEN1_MASK 0x400u
ethaderu 3:78f223d34f36 6881 #define FTM_COMBINE_DECAPEN1_SHIFT 10
ethaderu 3:78f223d34f36 6882 #define FTM_COMBINE_DECAP1_MASK 0x800u
ethaderu 3:78f223d34f36 6883 #define FTM_COMBINE_DECAP1_SHIFT 11
ethaderu 3:78f223d34f36 6884 #define FTM_COMBINE_DTEN1_MASK 0x1000u
ethaderu 3:78f223d34f36 6885 #define FTM_COMBINE_DTEN1_SHIFT 12
ethaderu 3:78f223d34f36 6886 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u
ethaderu 3:78f223d34f36 6887 #define FTM_COMBINE_SYNCEN1_SHIFT 13
ethaderu 3:78f223d34f36 6888 #define FTM_COMBINE_FAULTEN1_MASK 0x4000u
ethaderu 3:78f223d34f36 6889 #define FTM_COMBINE_FAULTEN1_SHIFT 14
ethaderu 3:78f223d34f36 6890 #define FTM_COMBINE_COMBINE2_MASK 0x10000u
ethaderu 3:78f223d34f36 6891 #define FTM_COMBINE_COMBINE2_SHIFT 16
ethaderu 3:78f223d34f36 6892 #define FTM_COMBINE_COMP2_MASK 0x20000u
ethaderu 3:78f223d34f36 6893 #define FTM_COMBINE_COMP2_SHIFT 17
ethaderu 3:78f223d34f36 6894 #define FTM_COMBINE_DECAPEN2_MASK 0x40000u
ethaderu 3:78f223d34f36 6895 #define FTM_COMBINE_DECAPEN2_SHIFT 18
ethaderu 3:78f223d34f36 6896 #define FTM_COMBINE_DECAP2_MASK 0x80000u
ethaderu 3:78f223d34f36 6897 #define FTM_COMBINE_DECAP2_SHIFT 19
ethaderu 3:78f223d34f36 6898 #define FTM_COMBINE_DTEN2_MASK 0x100000u
ethaderu 3:78f223d34f36 6899 #define FTM_COMBINE_DTEN2_SHIFT 20
ethaderu 3:78f223d34f36 6900 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u
ethaderu 3:78f223d34f36 6901 #define FTM_COMBINE_SYNCEN2_SHIFT 21
ethaderu 3:78f223d34f36 6902 #define FTM_COMBINE_FAULTEN2_MASK 0x400000u
ethaderu 3:78f223d34f36 6903 #define FTM_COMBINE_FAULTEN2_SHIFT 22
ethaderu 3:78f223d34f36 6904 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u
ethaderu 3:78f223d34f36 6905 #define FTM_COMBINE_COMBINE3_SHIFT 24
ethaderu 3:78f223d34f36 6906 #define FTM_COMBINE_COMP3_MASK 0x2000000u
ethaderu 3:78f223d34f36 6907 #define FTM_COMBINE_COMP3_SHIFT 25
ethaderu 3:78f223d34f36 6908 #define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
ethaderu 3:78f223d34f36 6909 #define FTM_COMBINE_DECAPEN3_SHIFT 26
ethaderu 3:78f223d34f36 6910 #define FTM_COMBINE_DECAP3_MASK 0x8000000u
ethaderu 3:78f223d34f36 6911 #define FTM_COMBINE_DECAP3_SHIFT 27
ethaderu 3:78f223d34f36 6912 #define FTM_COMBINE_DTEN3_MASK 0x10000000u
ethaderu 3:78f223d34f36 6913 #define FTM_COMBINE_DTEN3_SHIFT 28
ethaderu 3:78f223d34f36 6914 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
ethaderu 3:78f223d34f36 6915 #define FTM_COMBINE_SYNCEN3_SHIFT 29
ethaderu 3:78f223d34f36 6916 #define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
ethaderu 3:78f223d34f36 6917 #define FTM_COMBINE_FAULTEN3_SHIFT 30
ethaderu 3:78f223d34f36 6918 /* DEADTIME Bit Fields */
ethaderu 3:78f223d34f36 6919 #define FTM_DEADTIME_DTVAL_MASK 0x3Fu
ethaderu 3:78f223d34f36 6920 #define FTM_DEADTIME_DTVAL_SHIFT 0
ethaderu 3:78f223d34f36 6921 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
ethaderu 3:78f223d34f36 6922 #define FTM_DEADTIME_DTPS_MASK 0xC0u
ethaderu 3:78f223d34f36 6923 #define FTM_DEADTIME_DTPS_SHIFT 6
ethaderu 3:78f223d34f36 6924 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
ethaderu 3:78f223d34f36 6925 /* EXTTRIG Bit Fields */
ethaderu 3:78f223d34f36 6926 #define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
ethaderu 3:78f223d34f36 6927 #define FTM_EXTTRIG_CH2TRIG_SHIFT 0
ethaderu 3:78f223d34f36 6928 #define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
ethaderu 3:78f223d34f36 6929 #define FTM_EXTTRIG_CH3TRIG_SHIFT 1
ethaderu 3:78f223d34f36 6930 #define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
ethaderu 3:78f223d34f36 6931 #define FTM_EXTTRIG_CH4TRIG_SHIFT 2
ethaderu 3:78f223d34f36 6932 #define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
ethaderu 3:78f223d34f36 6933 #define FTM_EXTTRIG_CH5TRIG_SHIFT 3
ethaderu 3:78f223d34f36 6934 #define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
ethaderu 3:78f223d34f36 6935 #define FTM_EXTTRIG_CH0TRIG_SHIFT 4
ethaderu 3:78f223d34f36 6936 #define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
ethaderu 3:78f223d34f36 6937 #define FTM_EXTTRIG_CH1TRIG_SHIFT 5
ethaderu 3:78f223d34f36 6938 #define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
ethaderu 3:78f223d34f36 6939 #define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
ethaderu 3:78f223d34f36 6940 #define FTM_EXTTRIG_TRIGF_MASK 0x80u
ethaderu 3:78f223d34f36 6941 #define FTM_EXTTRIG_TRIGF_SHIFT 7
ethaderu 3:78f223d34f36 6942 /* POL Bit Fields */
ethaderu 3:78f223d34f36 6943 #define FTM_POL_POL0_MASK 0x1u
ethaderu 3:78f223d34f36 6944 #define FTM_POL_POL0_SHIFT 0
ethaderu 3:78f223d34f36 6945 #define FTM_POL_POL1_MASK 0x2u
ethaderu 3:78f223d34f36 6946 #define FTM_POL_POL1_SHIFT 1
ethaderu 3:78f223d34f36 6947 #define FTM_POL_POL2_MASK 0x4u
ethaderu 3:78f223d34f36 6948 #define FTM_POL_POL2_SHIFT 2
ethaderu 3:78f223d34f36 6949 #define FTM_POL_POL3_MASK 0x8u
ethaderu 3:78f223d34f36 6950 #define FTM_POL_POL3_SHIFT 3
ethaderu 3:78f223d34f36 6951 #define FTM_POL_POL4_MASK 0x10u
ethaderu 3:78f223d34f36 6952 #define FTM_POL_POL4_SHIFT 4
ethaderu 3:78f223d34f36 6953 #define FTM_POL_POL5_MASK 0x20u
ethaderu 3:78f223d34f36 6954 #define FTM_POL_POL5_SHIFT 5
ethaderu 3:78f223d34f36 6955 #define FTM_POL_POL6_MASK 0x40u
ethaderu 3:78f223d34f36 6956 #define FTM_POL_POL6_SHIFT 6
ethaderu 3:78f223d34f36 6957 #define FTM_POL_POL7_MASK 0x80u
ethaderu 3:78f223d34f36 6958 #define FTM_POL_POL7_SHIFT 7
ethaderu 3:78f223d34f36 6959 /* FMS Bit Fields */
ethaderu 3:78f223d34f36 6960 #define FTM_FMS_FAULTF0_MASK 0x1u
ethaderu 3:78f223d34f36 6961 #define FTM_FMS_FAULTF0_SHIFT 0
ethaderu 3:78f223d34f36 6962 #define FTM_FMS_FAULTF1_MASK 0x2u
ethaderu 3:78f223d34f36 6963 #define FTM_FMS_FAULTF1_SHIFT 1
ethaderu 3:78f223d34f36 6964 #define FTM_FMS_FAULTF2_MASK 0x4u
ethaderu 3:78f223d34f36 6965 #define FTM_FMS_FAULTF2_SHIFT 2
ethaderu 3:78f223d34f36 6966 #define FTM_FMS_FAULTF3_MASK 0x8u
ethaderu 3:78f223d34f36 6967 #define FTM_FMS_FAULTF3_SHIFT 3
ethaderu 3:78f223d34f36 6968 #define FTM_FMS_FAULTIN_MASK 0x20u
ethaderu 3:78f223d34f36 6969 #define FTM_FMS_FAULTIN_SHIFT 5
ethaderu 3:78f223d34f36 6970 #define FTM_FMS_WPEN_MASK 0x40u
ethaderu 3:78f223d34f36 6971 #define FTM_FMS_WPEN_SHIFT 6
ethaderu 3:78f223d34f36 6972 #define FTM_FMS_FAULTF_MASK 0x80u
ethaderu 3:78f223d34f36 6973 #define FTM_FMS_FAULTF_SHIFT 7
ethaderu 3:78f223d34f36 6974 /* FILTER Bit Fields */
ethaderu 3:78f223d34f36 6975 #define FTM_FILTER_CH0FVAL_MASK 0xFu
ethaderu 3:78f223d34f36 6976 #define FTM_FILTER_CH0FVAL_SHIFT 0
ethaderu 3:78f223d34f36 6977 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
ethaderu 3:78f223d34f36 6978 #define FTM_FILTER_CH1FVAL_MASK 0xF0u
ethaderu 3:78f223d34f36 6979 #define FTM_FILTER_CH1FVAL_SHIFT 4
ethaderu 3:78f223d34f36 6980 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
ethaderu 3:78f223d34f36 6981 #define FTM_FILTER_CH2FVAL_MASK 0xF00u
ethaderu 3:78f223d34f36 6982 #define FTM_FILTER_CH2FVAL_SHIFT 8
ethaderu 3:78f223d34f36 6983 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
ethaderu 3:78f223d34f36 6984 #define FTM_FILTER_CH3FVAL_MASK 0xF000u
ethaderu 3:78f223d34f36 6985 #define FTM_FILTER_CH3FVAL_SHIFT 12
ethaderu 3:78f223d34f36 6986 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
ethaderu 3:78f223d34f36 6987 /* FLTCTRL Bit Fields */
ethaderu 3:78f223d34f36 6988 #define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
ethaderu 3:78f223d34f36 6989 #define FTM_FLTCTRL_FAULT0EN_SHIFT 0
ethaderu 3:78f223d34f36 6990 #define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
ethaderu 3:78f223d34f36 6991 #define FTM_FLTCTRL_FAULT1EN_SHIFT 1
ethaderu 3:78f223d34f36 6992 #define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
ethaderu 3:78f223d34f36 6993 #define FTM_FLTCTRL_FAULT2EN_SHIFT 2
ethaderu 3:78f223d34f36 6994 #define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
ethaderu 3:78f223d34f36 6995 #define FTM_FLTCTRL_FAULT3EN_SHIFT 3
ethaderu 3:78f223d34f36 6996 #define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
ethaderu 3:78f223d34f36 6997 #define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
ethaderu 3:78f223d34f36 6998 #define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
ethaderu 3:78f223d34f36 6999 #define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
ethaderu 3:78f223d34f36 7000 #define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
ethaderu 3:78f223d34f36 7001 #define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
ethaderu 3:78f223d34f36 7002 #define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
ethaderu 3:78f223d34f36 7003 #define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
ethaderu 3:78f223d34f36 7004 #define FTM_FLTCTRL_FFVAL_MASK 0xF00u
ethaderu 3:78f223d34f36 7005 #define FTM_FLTCTRL_FFVAL_SHIFT 8
ethaderu 3:78f223d34f36 7006 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
ethaderu 3:78f223d34f36 7007 /* QDCTRL Bit Fields */
ethaderu 3:78f223d34f36 7008 #define FTM_QDCTRL_QUADEN_MASK 0x1u
ethaderu 3:78f223d34f36 7009 #define FTM_QDCTRL_QUADEN_SHIFT 0
ethaderu 3:78f223d34f36 7010 #define FTM_QDCTRL_TOFDIR_MASK 0x2u
ethaderu 3:78f223d34f36 7011 #define FTM_QDCTRL_TOFDIR_SHIFT 1
ethaderu 3:78f223d34f36 7012 #define FTM_QDCTRL_QUADIR_MASK 0x4u
ethaderu 3:78f223d34f36 7013 #define FTM_QDCTRL_QUADIR_SHIFT 2
ethaderu 3:78f223d34f36 7014 #define FTM_QDCTRL_QUADMODE_MASK 0x8u
ethaderu 3:78f223d34f36 7015 #define FTM_QDCTRL_QUADMODE_SHIFT 3
ethaderu 3:78f223d34f36 7016 #define FTM_QDCTRL_PHBPOL_MASK 0x10u
ethaderu 3:78f223d34f36 7017 #define FTM_QDCTRL_PHBPOL_SHIFT 4
ethaderu 3:78f223d34f36 7018 #define FTM_QDCTRL_PHAPOL_MASK 0x20u
ethaderu 3:78f223d34f36 7019 #define FTM_QDCTRL_PHAPOL_SHIFT 5
ethaderu 3:78f223d34f36 7020 #define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
ethaderu 3:78f223d34f36 7021 #define FTM_QDCTRL_PHBFLTREN_SHIFT 6
ethaderu 3:78f223d34f36 7022 #define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
ethaderu 3:78f223d34f36 7023 #define FTM_QDCTRL_PHAFLTREN_SHIFT 7
ethaderu 3:78f223d34f36 7024 /* CONF Bit Fields */
ethaderu 3:78f223d34f36 7025 #define FTM_CONF_NUMTOF_MASK 0x1Fu
ethaderu 3:78f223d34f36 7026 #define FTM_CONF_NUMTOF_SHIFT 0
ethaderu 3:78f223d34f36 7027 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
ethaderu 3:78f223d34f36 7028 #define FTM_CONF_BDMMODE_MASK 0xC0u
ethaderu 3:78f223d34f36 7029 #define FTM_CONF_BDMMODE_SHIFT 6
ethaderu 3:78f223d34f36 7030 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
ethaderu 3:78f223d34f36 7031 #define FTM_CONF_GTBEEN_MASK 0x200u
ethaderu 3:78f223d34f36 7032 #define FTM_CONF_GTBEEN_SHIFT 9
ethaderu 3:78f223d34f36 7033 #define FTM_CONF_GTBEOUT_MASK 0x400u
ethaderu 3:78f223d34f36 7034 #define FTM_CONF_GTBEOUT_SHIFT 10
ethaderu 3:78f223d34f36 7035 /* FLTPOL Bit Fields */
ethaderu 3:78f223d34f36 7036 #define FTM_FLTPOL_FLT0POL_MASK 0x1u
ethaderu 3:78f223d34f36 7037 #define FTM_FLTPOL_FLT0POL_SHIFT 0
ethaderu 3:78f223d34f36 7038 #define FTM_FLTPOL_FLT1POL_MASK 0x2u
ethaderu 3:78f223d34f36 7039 #define FTM_FLTPOL_FLT1POL_SHIFT 1
ethaderu 3:78f223d34f36 7040 #define FTM_FLTPOL_FLT2POL_MASK 0x4u
ethaderu 3:78f223d34f36 7041 #define FTM_FLTPOL_FLT2POL_SHIFT 2
ethaderu 3:78f223d34f36 7042 #define FTM_FLTPOL_FLT3POL_MASK 0x8u
ethaderu 3:78f223d34f36 7043 #define FTM_FLTPOL_FLT3POL_SHIFT 3
ethaderu 3:78f223d34f36 7044 /* SYNCONF Bit Fields */
ethaderu 3:78f223d34f36 7045 #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
ethaderu 3:78f223d34f36 7046 #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
ethaderu 3:78f223d34f36 7047 #define FTM_SYNCONF_CNTINC_MASK 0x4u
ethaderu 3:78f223d34f36 7048 #define FTM_SYNCONF_CNTINC_SHIFT 2
ethaderu 3:78f223d34f36 7049 #define FTM_SYNCONF_INVC_MASK 0x10u
ethaderu 3:78f223d34f36 7050 #define FTM_SYNCONF_INVC_SHIFT 4
ethaderu 3:78f223d34f36 7051 #define FTM_SYNCONF_SWOC_MASK 0x20u
ethaderu 3:78f223d34f36 7052 #define FTM_SYNCONF_SWOC_SHIFT 5
ethaderu 3:78f223d34f36 7053 #define FTM_SYNCONF_SYNCMODE_MASK 0x80u
ethaderu 3:78f223d34f36 7054 #define FTM_SYNCONF_SYNCMODE_SHIFT 7
ethaderu 3:78f223d34f36 7055 #define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
ethaderu 3:78f223d34f36 7056 #define FTM_SYNCONF_SWRSTCNT_SHIFT 8
ethaderu 3:78f223d34f36 7057 #define FTM_SYNCONF_SWWRBUF_MASK 0x200u
ethaderu 3:78f223d34f36 7058 #define FTM_SYNCONF_SWWRBUF_SHIFT 9
ethaderu 3:78f223d34f36 7059 #define FTM_SYNCONF_SWOM_MASK 0x400u
ethaderu 3:78f223d34f36 7060 #define FTM_SYNCONF_SWOM_SHIFT 10
ethaderu 3:78f223d34f36 7061 #define FTM_SYNCONF_SWINVC_MASK 0x800u
ethaderu 3:78f223d34f36 7062 #define FTM_SYNCONF_SWINVC_SHIFT 11
ethaderu 3:78f223d34f36 7063 #define FTM_SYNCONF_SWSOC_MASK 0x1000u
ethaderu 3:78f223d34f36 7064 #define FTM_SYNCONF_SWSOC_SHIFT 12
ethaderu 3:78f223d34f36 7065 #define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
ethaderu 3:78f223d34f36 7066 #define FTM_SYNCONF_HWRSTCNT_SHIFT 16
ethaderu 3:78f223d34f36 7067 #define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
ethaderu 3:78f223d34f36 7068 #define FTM_SYNCONF_HWWRBUF_SHIFT 17
ethaderu 3:78f223d34f36 7069 #define FTM_SYNCONF_HWOM_MASK 0x40000u
ethaderu 3:78f223d34f36 7070 #define FTM_SYNCONF_HWOM_SHIFT 18
ethaderu 3:78f223d34f36 7071 #define FTM_SYNCONF_HWINVC_MASK 0x80000u
ethaderu 3:78f223d34f36 7072 #define FTM_SYNCONF_HWINVC_SHIFT 19
ethaderu 3:78f223d34f36 7073 #define FTM_SYNCONF_HWSOC_MASK 0x100000u
ethaderu 3:78f223d34f36 7074 #define FTM_SYNCONF_HWSOC_SHIFT 20
ethaderu 3:78f223d34f36 7075 /* INVCTRL Bit Fields */
ethaderu 3:78f223d34f36 7076 #define FTM_INVCTRL_INV0EN_MASK 0x1u
ethaderu 3:78f223d34f36 7077 #define FTM_INVCTRL_INV0EN_SHIFT 0
ethaderu 3:78f223d34f36 7078 #define FTM_INVCTRL_INV1EN_MASK 0x2u
ethaderu 3:78f223d34f36 7079 #define FTM_INVCTRL_INV1EN_SHIFT 1
ethaderu 3:78f223d34f36 7080 #define FTM_INVCTRL_INV2EN_MASK 0x4u
ethaderu 3:78f223d34f36 7081 #define FTM_INVCTRL_INV2EN_SHIFT 2
ethaderu 3:78f223d34f36 7082 #define FTM_INVCTRL_INV3EN_MASK 0x8u
ethaderu 3:78f223d34f36 7083 #define FTM_INVCTRL_INV3EN_SHIFT 3
ethaderu 3:78f223d34f36 7084 /* SWOCTRL Bit Fields */
ethaderu 3:78f223d34f36 7085 #define FTM_SWOCTRL_CH0OC_MASK 0x1u
ethaderu 3:78f223d34f36 7086 #define FTM_SWOCTRL_CH0OC_SHIFT 0
ethaderu 3:78f223d34f36 7087 #define FTM_SWOCTRL_CH1OC_MASK 0x2u
ethaderu 3:78f223d34f36 7088 #define FTM_SWOCTRL_CH1OC_SHIFT 1
ethaderu 3:78f223d34f36 7089 #define FTM_SWOCTRL_CH2OC_MASK 0x4u
ethaderu 3:78f223d34f36 7090 #define FTM_SWOCTRL_CH2OC_SHIFT 2
ethaderu 3:78f223d34f36 7091 #define FTM_SWOCTRL_CH3OC_MASK 0x8u
ethaderu 3:78f223d34f36 7092 #define FTM_SWOCTRL_CH3OC_SHIFT 3
ethaderu 3:78f223d34f36 7093 #define FTM_SWOCTRL_CH4OC_MASK 0x10u
ethaderu 3:78f223d34f36 7094 #define FTM_SWOCTRL_CH4OC_SHIFT 4
ethaderu 3:78f223d34f36 7095 #define FTM_SWOCTRL_CH5OC_MASK 0x20u
ethaderu 3:78f223d34f36 7096 #define FTM_SWOCTRL_CH5OC_SHIFT 5
ethaderu 3:78f223d34f36 7097 #define FTM_SWOCTRL_CH6OC_MASK 0x40u
ethaderu 3:78f223d34f36 7098 #define FTM_SWOCTRL_CH6OC_SHIFT 6
ethaderu 3:78f223d34f36 7099 #define FTM_SWOCTRL_CH7OC_MASK 0x80u
ethaderu 3:78f223d34f36 7100 #define FTM_SWOCTRL_CH7OC_SHIFT 7
ethaderu 3:78f223d34f36 7101 #define FTM_SWOCTRL_CH0OCV_MASK 0x100u
ethaderu 3:78f223d34f36 7102 #define FTM_SWOCTRL_CH0OCV_SHIFT 8
ethaderu 3:78f223d34f36 7103 #define FTM_SWOCTRL_CH1OCV_MASK 0x200u
ethaderu 3:78f223d34f36 7104 #define FTM_SWOCTRL_CH1OCV_SHIFT 9
ethaderu 3:78f223d34f36 7105 #define FTM_SWOCTRL_CH2OCV_MASK 0x400u
ethaderu 3:78f223d34f36 7106 #define FTM_SWOCTRL_CH2OCV_SHIFT 10
ethaderu 3:78f223d34f36 7107 #define FTM_SWOCTRL_CH3OCV_MASK 0x800u
ethaderu 3:78f223d34f36 7108 #define FTM_SWOCTRL_CH3OCV_SHIFT 11
ethaderu 3:78f223d34f36 7109 #define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
ethaderu 3:78f223d34f36 7110 #define FTM_SWOCTRL_CH4OCV_SHIFT 12
ethaderu 3:78f223d34f36 7111 #define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
ethaderu 3:78f223d34f36 7112 #define FTM_SWOCTRL_CH5OCV_SHIFT 13
ethaderu 3:78f223d34f36 7113 #define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
ethaderu 3:78f223d34f36 7114 #define FTM_SWOCTRL_CH6OCV_SHIFT 14
ethaderu 3:78f223d34f36 7115 #define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
ethaderu 3:78f223d34f36 7116 #define FTM_SWOCTRL_CH7OCV_SHIFT 15
ethaderu 3:78f223d34f36 7117 /* PWMLOAD Bit Fields */
ethaderu 3:78f223d34f36 7118 #define FTM_PWMLOAD_CH0SEL_MASK 0x1u
ethaderu 3:78f223d34f36 7119 #define FTM_PWMLOAD_CH0SEL_SHIFT 0
ethaderu 3:78f223d34f36 7120 #define FTM_PWMLOAD_CH1SEL_MASK 0x2u
ethaderu 3:78f223d34f36 7121 #define FTM_PWMLOAD_CH1SEL_SHIFT 1
ethaderu 3:78f223d34f36 7122 #define FTM_PWMLOAD_CH2SEL_MASK 0x4u
ethaderu 3:78f223d34f36 7123 #define FTM_PWMLOAD_CH2SEL_SHIFT 2
ethaderu 3:78f223d34f36 7124 #define FTM_PWMLOAD_CH3SEL_MASK 0x8u
ethaderu 3:78f223d34f36 7125 #define FTM_PWMLOAD_CH3SEL_SHIFT 3
ethaderu 3:78f223d34f36 7126 #define FTM_PWMLOAD_CH4SEL_MASK 0x10u
ethaderu 3:78f223d34f36 7127 #define FTM_PWMLOAD_CH4SEL_SHIFT 4
ethaderu 3:78f223d34f36 7128 #define FTM_PWMLOAD_CH5SEL_MASK 0x20u
ethaderu 3:78f223d34f36 7129 #define FTM_PWMLOAD_CH5SEL_SHIFT 5
ethaderu 3:78f223d34f36 7130 #define FTM_PWMLOAD_CH6SEL_MASK 0x40u
ethaderu 3:78f223d34f36 7131 #define FTM_PWMLOAD_CH6SEL_SHIFT 6
ethaderu 3:78f223d34f36 7132 #define FTM_PWMLOAD_CH7SEL_MASK 0x80u
ethaderu 3:78f223d34f36 7133 #define FTM_PWMLOAD_CH7SEL_SHIFT 7
ethaderu 3:78f223d34f36 7134 #define FTM_PWMLOAD_LDOK_MASK 0x200u
ethaderu 3:78f223d34f36 7135 #define FTM_PWMLOAD_LDOK_SHIFT 9
ethaderu 3:78f223d34f36 7136
ethaderu 3:78f223d34f36 7137 /*!
ethaderu 3:78f223d34f36 7138 * @}
ethaderu 3:78f223d34f36 7139 */ /* end of group FTM_Register_Masks */
ethaderu 3:78f223d34f36 7140
ethaderu 3:78f223d34f36 7141
ethaderu 3:78f223d34f36 7142 /* FTM - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 7143 /** Peripheral FTM0 base address */
ethaderu 3:78f223d34f36 7144 #define FTM0_BASE (0x40038000u)
ethaderu 3:78f223d34f36 7145 /** Peripheral FTM0 base pointer */
ethaderu 3:78f223d34f36 7146 #define FTM0 ((FTM_Type *)FTM0_BASE)
ethaderu 3:78f223d34f36 7147 #define FTM0_BASE_PTR (FTM0)
ethaderu 3:78f223d34f36 7148 /** Peripheral FTM1 base address */
ethaderu 3:78f223d34f36 7149 #define FTM1_BASE (0x40039000u)
ethaderu 3:78f223d34f36 7150 /** Peripheral FTM1 base pointer */
ethaderu 3:78f223d34f36 7151 #define FTM1 ((FTM_Type *)FTM1_BASE)
ethaderu 3:78f223d34f36 7152 #define FTM1_BASE_PTR (FTM1)
ethaderu 3:78f223d34f36 7153 /** Peripheral FTM2 base address */
ethaderu 3:78f223d34f36 7154 #define FTM2_BASE (0x4003A000u)
ethaderu 3:78f223d34f36 7155 /** Peripheral FTM2 base pointer */
ethaderu 3:78f223d34f36 7156 #define FTM2 ((FTM_Type *)FTM2_BASE)
ethaderu 3:78f223d34f36 7157 #define FTM2_BASE_PTR (FTM2)
ethaderu 3:78f223d34f36 7158 /** Peripheral FTM3 base address */
ethaderu 3:78f223d34f36 7159 #define FTM3_BASE (0x400B9000u)
ethaderu 3:78f223d34f36 7160 /** Peripheral FTM3 base pointer */
ethaderu 3:78f223d34f36 7161 #define FTM3 ((FTM_Type *)FTM3_BASE)
ethaderu 3:78f223d34f36 7162 #define FTM3_BASE_PTR (FTM3)
ethaderu 3:78f223d34f36 7163 /** Array initializer of FTM peripheral base addresses */
ethaderu 3:78f223d34f36 7164 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
ethaderu 3:78f223d34f36 7165 /** Array initializer of FTM peripheral base pointers */
ethaderu 3:78f223d34f36 7166 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
ethaderu 3:78f223d34f36 7167 /** Interrupt vectors for the FTM peripheral type */
ethaderu 3:78f223d34f36 7168 #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
ethaderu 3:78f223d34f36 7169
ethaderu 3:78f223d34f36 7170 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 7171 -- FTM - Register accessor macros
ethaderu 3:78f223d34f36 7172 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 7173
ethaderu 3:78f223d34f36 7174 /*!
ethaderu 3:78f223d34f36 7175 * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
ethaderu 3:78f223d34f36 7176 * @{
ethaderu 3:78f223d34f36 7177 */
ethaderu 3:78f223d34f36 7178
ethaderu 3:78f223d34f36 7179
ethaderu 3:78f223d34f36 7180 /* FTM - Register instance definitions */
ethaderu 3:78f223d34f36 7181 /* FTM0 */
ethaderu 3:78f223d34f36 7182 #define FTM0_SC FTM_SC_REG(FTM0)
ethaderu 3:78f223d34f36 7183 #define FTM0_CNT FTM_CNT_REG(FTM0)
ethaderu 3:78f223d34f36 7184 #define FTM0_MOD FTM_MOD_REG(FTM0)
ethaderu 3:78f223d34f36 7185 #define FTM0_C0SC FTM_CnSC_REG(FTM0,0)
ethaderu 3:78f223d34f36 7186 #define FTM0_C0V FTM_CnV_REG(FTM0,0)
ethaderu 3:78f223d34f36 7187 #define FTM0_C1SC FTM_CnSC_REG(FTM0,1)
ethaderu 3:78f223d34f36 7188 #define FTM0_C1V FTM_CnV_REG(FTM0,1)
ethaderu 3:78f223d34f36 7189 #define FTM0_C2SC FTM_CnSC_REG(FTM0,2)
ethaderu 3:78f223d34f36 7190 #define FTM0_C2V FTM_CnV_REG(FTM0,2)
ethaderu 3:78f223d34f36 7191 #define FTM0_C3SC FTM_CnSC_REG(FTM0,3)
ethaderu 3:78f223d34f36 7192 #define FTM0_C3V FTM_CnV_REG(FTM0,3)
ethaderu 3:78f223d34f36 7193 #define FTM0_C4SC FTM_CnSC_REG(FTM0,4)
ethaderu 3:78f223d34f36 7194 #define FTM0_C4V FTM_CnV_REG(FTM0,4)
ethaderu 3:78f223d34f36 7195 #define FTM0_C5SC FTM_CnSC_REG(FTM0,5)
ethaderu 3:78f223d34f36 7196 #define FTM0_C5V FTM_CnV_REG(FTM0,5)
ethaderu 3:78f223d34f36 7197 #define FTM0_C6SC FTM_CnSC_REG(FTM0,6)
ethaderu 3:78f223d34f36 7198 #define FTM0_C6V FTM_CnV_REG(FTM0,6)
ethaderu 3:78f223d34f36 7199 #define FTM0_C7SC FTM_CnSC_REG(FTM0,7)
ethaderu 3:78f223d34f36 7200 #define FTM0_C7V FTM_CnV_REG(FTM0,7)
ethaderu 3:78f223d34f36 7201 #define FTM0_CNTIN FTM_CNTIN_REG(FTM0)
ethaderu 3:78f223d34f36 7202 #define FTM0_STATUS FTM_STATUS_REG(FTM0)
ethaderu 3:78f223d34f36 7203 #define FTM0_MODE FTM_MODE_REG(FTM0)
ethaderu 3:78f223d34f36 7204 #define FTM0_SYNC FTM_SYNC_REG(FTM0)
ethaderu 3:78f223d34f36 7205 #define FTM0_OUTINIT FTM_OUTINIT_REG(FTM0)
ethaderu 3:78f223d34f36 7206 #define FTM0_OUTMASK FTM_OUTMASK_REG(FTM0)
ethaderu 3:78f223d34f36 7207 #define FTM0_COMBINE FTM_COMBINE_REG(FTM0)
ethaderu 3:78f223d34f36 7208 #define FTM0_DEADTIME FTM_DEADTIME_REG(FTM0)
ethaderu 3:78f223d34f36 7209 #define FTM0_EXTTRIG FTM_EXTTRIG_REG(FTM0)
ethaderu 3:78f223d34f36 7210 #define FTM0_POL FTM_POL_REG(FTM0)
ethaderu 3:78f223d34f36 7211 #define FTM0_FMS FTM_FMS_REG(FTM0)
ethaderu 3:78f223d34f36 7212 #define FTM0_FILTER FTM_FILTER_REG(FTM0)
ethaderu 3:78f223d34f36 7213 #define FTM0_FLTCTRL FTM_FLTCTRL_REG(FTM0)
ethaderu 3:78f223d34f36 7214 #define FTM0_QDCTRL FTM_QDCTRL_REG(FTM0)
ethaderu 3:78f223d34f36 7215 #define FTM0_CONF FTM_CONF_REG(FTM0)
ethaderu 3:78f223d34f36 7216 #define FTM0_FLTPOL FTM_FLTPOL_REG(FTM0)
ethaderu 3:78f223d34f36 7217 #define FTM0_SYNCONF FTM_SYNCONF_REG(FTM0)
ethaderu 3:78f223d34f36 7218 #define FTM0_INVCTRL FTM_INVCTRL_REG(FTM0)
ethaderu 3:78f223d34f36 7219 #define FTM0_SWOCTRL FTM_SWOCTRL_REG(FTM0)
ethaderu 3:78f223d34f36 7220 #define FTM0_PWMLOAD FTM_PWMLOAD_REG(FTM0)
ethaderu 3:78f223d34f36 7221 /* FTM1 */
ethaderu 3:78f223d34f36 7222 #define FTM1_SC FTM_SC_REG(FTM1)
ethaderu 3:78f223d34f36 7223 #define FTM1_CNT FTM_CNT_REG(FTM1)
ethaderu 3:78f223d34f36 7224 #define FTM1_MOD FTM_MOD_REG(FTM1)
ethaderu 3:78f223d34f36 7225 #define FTM1_C0SC FTM_CnSC_REG(FTM1,0)
ethaderu 3:78f223d34f36 7226 #define FTM1_C0V FTM_CnV_REG(FTM1,0)
ethaderu 3:78f223d34f36 7227 #define FTM1_C1SC FTM_CnSC_REG(FTM1,1)
ethaderu 3:78f223d34f36 7228 #define FTM1_C1V FTM_CnV_REG(FTM1,1)
ethaderu 3:78f223d34f36 7229 #define FTM1_CNTIN FTM_CNTIN_REG(FTM1)
ethaderu 3:78f223d34f36 7230 #define FTM1_STATUS FTM_STATUS_REG(FTM1)
ethaderu 3:78f223d34f36 7231 #define FTM1_MODE FTM_MODE_REG(FTM1)
ethaderu 3:78f223d34f36 7232 #define FTM1_SYNC FTM_SYNC_REG(FTM1)
ethaderu 3:78f223d34f36 7233 #define FTM1_OUTINIT FTM_OUTINIT_REG(FTM1)
ethaderu 3:78f223d34f36 7234 #define FTM1_OUTMASK FTM_OUTMASK_REG(FTM1)
ethaderu 3:78f223d34f36 7235 #define FTM1_COMBINE FTM_COMBINE_REG(FTM1)
ethaderu 3:78f223d34f36 7236 #define FTM1_DEADTIME FTM_DEADTIME_REG(FTM1)
ethaderu 3:78f223d34f36 7237 #define FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1)
ethaderu 3:78f223d34f36 7238 #define FTM1_POL FTM_POL_REG(FTM1)
ethaderu 3:78f223d34f36 7239 #define FTM1_FMS FTM_FMS_REG(FTM1)
ethaderu 3:78f223d34f36 7240 #define FTM1_FILTER FTM_FILTER_REG(FTM1)
ethaderu 3:78f223d34f36 7241 #define FTM1_FLTCTRL FTM_FLTCTRL_REG(FTM1)
ethaderu 3:78f223d34f36 7242 #define FTM1_QDCTRL FTM_QDCTRL_REG(FTM1)
ethaderu 3:78f223d34f36 7243 #define FTM1_CONF FTM_CONF_REG(FTM1)
ethaderu 3:78f223d34f36 7244 #define FTM1_FLTPOL FTM_FLTPOL_REG(FTM1)
ethaderu 3:78f223d34f36 7245 #define FTM1_SYNCONF FTM_SYNCONF_REG(FTM1)
ethaderu 3:78f223d34f36 7246 #define FTM1_INVCTRL FTM_INVCTRL_REG(FTM1)
ethaderu 3:78f223d34f36 7247 #define FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1)
ethaderu 3:78f223d34f36 7248 #define FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1)
ethaderu 3:78f223d34f36 7249 /* FTM2 */
ethaderu 3:78f223d34f36 7250 #define FTM2_SC FTM_SC_REG(FTM2)
ethaderu 3:78f223d34f36 7251 #define FTM2_CNT FTM_CNT_REG(FTM2)
ethaderu 3:78f223d34f36 7252 #define FTM2_MOD FTM_MOD_REG(FTM2)
ethaderu 3:78f223d34f36 7253 #define FTM2_C0SC FTM_CnSC_REG(FTM2,0)
ethaderu 3:78f223d34f36 7254 #define FTM2_C0V FTM_CnV_REG(FTM2,0)
ethaderu 3:78f223d34f36 7255 #define FTM2_C1SC FTM_CnSC_REG(FTM2,1)
ethaderu 3:78f223d34f36 7256 #define FTM2_C1V FTM_CnV_REG(FTM2,1)
ethaderu 3:78f223d34f36 7257 #define FTM2_CNTIN FTM_CNTIN_REG(FTM2)
ethaderu 3:78f223d34f36 7258 #define FTM2_STATUS FTM_STATUS_REG(FTM2)
ethaderu 3:78f223d34f36 7259 #define FTM2_MODE FTM_MODE_REG(FTM2)
ethaderu 3:78f223d34f36 7260 #define FTM2_SYNC FTM_SYNC_REG(FTM2)
ethaderu 3:78f223d34f36 7261 #define FTM2_OUTINIT FTM_OUTINIT_REG(FTM2)
ethaderu 3:78f223d34f36 7262 #define FTM2_OUTMASK FTM_OUTMASK_REG(FTM2)
ethaderu 3:78f223d34f36 7263 #define FTM2_COMBINE FTM_COMBINE_REG(FTM2)
ethaderu 3:78f223d34f36 7264 #define FTM2_DEADTIME FTM_DEADTIME_REG(FTM2)
ethaderu 3:78f223d34f36 7265 #define FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2)
ethaderu 3:78f223d34f36 7266 #define FTM2_POL FTM_POL_REG(FTM2)
ethaderu 3:78f223d34f36 7267 #define FTM2_FMS FTM_FMS_REG(FTM2)
ethaderu 3:78f223d34f36 7268 #define FTM2_FILTER FTM_FILTER_REG(FTM2)
ethaderu 3:78f223d34f36 7269 #define FTM2_FLTCTRL FTM_FLTCTRL_REG(FTM2)
ethaderu 3:78f223d34f36 7270 #define FTM2_QDCTRL FTM_QDCTRL_REG(FTM2)
ethaderu 3:78f223d34f36 7271 #define FTM2_CONF FTM_CONF_REG(FTM2)
ethaderu 3:78f223d34f36 7272 #define FTM2_FLTPOL FTM_FLTPOL_REG(FTM2)
ethaderu 3:78f223d34f36 7273 #define FTM2_SYNCONF FTM_SYNCONF_REG(FTM2)
ethaderu 3:78f223d34f36 7274 #define FTM2_INVCTRL FTM_INVCTRL_REG(FTM2)
ethaderu 3:78f223d34f36 7275 #define FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2)
ethaderu 3:78f223d34f36 7276 #define FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2)
ethaderu 3:78f223d34f36 7277 /* FTM3 */
ethaderu 3:78f223d34f36 7278 #define FTM3_SC FTM_SC_REG(FTM3)
ethaderu 3:78f223d34f36 7279 #define FTM3_CNT FTM_CNT_REG(FTM3)
ethaderu 3:78f223d34f36 7280 #define FTM3_MOD FTM_MOD_REG(FTM3)
ethaderu 3:78f223d34f36 7281 #define FTM3_C0SC FTM_CnSC_REG(FTM3,0)
ethaderu 3:78f223d34f36 7282 #define FTM3_C0V FTM_CnV_REG(FTM3,0)
ethaderu 3:78f223d34f36 7283 #define FTM3_C1SC FTM_CnSC_REG(FTM3,1)
ethaderu 3:78f223d34f36 7284 #define FTM3_C1V FTM_CnV_REG(FTM3,1)
ethaderu 3:78f223d34f36 7285 #define FTM3_C2SC FTM_CnSC_REG(FTM3,2)
ethaderu 3:78f223d34f36 7286 #define FTM3_C2V FTM_CnV_REG(FTM3,2)
ethaderu 3:78f223d34f36 7287 #define FTM3_C3SC FTM_CnSC_REG(FTM3,3)
ethaderu 3:78f223d34f36 7288 #define FTM3_C3V FTM_CnV_REG(FTM3,3)
ethaderu 3:78f223d34f36 7289 #define FTM3_C4SC FTM_CnSC_REG(FTM3,4)
ethaderu 3:78f223d34f36 7290 #define FTM3_C4V FTM_CnV_REG(FTM3,4)
ethaderu 3:78f223d34f36 7291 #define FTM3_C5SC FTM_CnSC_REG(FTM3,5)
ethaderu 3:78f223d34f36 7292 #define FTM3_C5V FTM_CnV_REG(FTM3,5)
ethaderu 3:78f223d34f36 7293 #define FTM3_C6SC FTM_CnSC_REG(FTM3,6)
ethaderu 3:78f223d34f36 7294 #define FTM3_C6V FTM_CnV_REG(FTM3,6)
ethaderu 3:78f223d34f36 7295 #define FTM3_C7SC FTM_CnSC_REG(FTM3,7)
ethaderu 3:78f223d34f36 7296 #define FTM3_C7V FTM_CnV_REG(FTM3,7)
ethaderu 3:78f223d34f36 7297 #define FTM3_CNTIN FTM_CNTIN_REG(FTM3)
ethaderu 3:78f223d34f36 7298 #define FTM3_STATUS FTM_STATUS_REG(FTM3)
ethaderu 3:78f223d34f36 7299 #define FTM3_MODE FTM_MODE_REG(FTM3)
ethaderu 3:78f223d34f36 7300 #define FTM3_SYNC FTM_SYNC_REG(FTM3)
ethaderu 3:78f223d34f36 7301 #define FTM3_OUTINIT FTM_OUTINIT_REG(FTM3)
ethaderu 3:78f223d34f36 7302 #define FTM3_OUTMASK FTM_OUTMASK_REG(FTM3)
ethaderu 3:78f223d34f36 7303 #define FTM3_COMBINE FTM_COMBINE_REG(FTM3)
ethaderu 3:78f223d34f36 7304 #define FTM3_DEADTIME FTM_DEADTIME_REG(FTM3)
ethaderu 3:78f223d34f36 7305 #define FTM3_EXTTRIG FTM_EXTTRIG_REG(FTM3)
ethaderu 3:78f223d34f36 7306 #define FTM3_POL FTM_POL_REG(FTM3)
ethaderu 3:78f223d34f36 7307 #define FTM3_FMS FTM_FMS_REG(FTM3)
ethaderu 3:78f223d34f36 7308 #define FTM3_FILTER FTM_FILTER_REG(FTM3)
ethaderu 3:78f223d34f36 7309 #define FTM3_FLTCTRL FTM_FLTCTRL_REG(FTM3)
ethaderu 3:78f223d34f36 7310 #define FTM3_QDCTRL FTM_QDCTRL_REG(FTM3)
ethaderu 3:78f223d34f36 7311 #define FTM3_CONF FTM_CONF_REG(FTM3)
ethaderu 3:78f223d34f36 7312 #define FTM3_FLTPOL FTM_FLTPOL_REG(FTM3)
ethaderu 3:78f223d34f36 7313 #define FTM3_SYNCONF FTM_SYNCONF_REG(FTM3)
ethaderu 3:78f223d34f36 7314 #define FTM3_INVCTRL FTM_INVCTRL_REG(FTM3)
ethaderu 3:78f223d34f36 7315 #define FTM3_SWOCTRL FTM_SWOCTRL_REG(FTM3)
ethaderu 3:78f223d34f36 7316 #define FTM3_PWMLOAD FTM_PWMLOAD_REG(FTM3)
ethaderu 3:78f223d34f36 7317
ethaderu 3:78f223d34f36 7318 /* FTM - Register array accessors */
ethaderu 3:78f223d34f36 7319 #define FTM0_CnSC(index) FTM_CnSC_REG(FTM0,index)
ethaderu 3:78f223d34f36 7320 #define FTM1_CnSC(index) FTM_CnSC_REG(FTM1,index)
ethaderu 3:78f223d34f36 7321 #define FTM2_CnSC(index) FTM_CnSC_REG(FTM2,index)
ethaderu 3:78f223d34f36 7322 #define FTM3_CnSC(index) FTM_CnSC_REG(FTM3,index)
ethaderu 3:78f223d34f36 7323 #define FTM0_CnV(index) FTM_CnV_REG(FTM0,index)
ethaderu 3:78f223d34f36 7324 #define FTM1_CnV(index) FTM_CnV_REG(FTM1,index)
ethaderu 3:78f223d34f36 7325 #define FTM2_CnV(index) FTM_CnV_REG(FTM2,index)
ethaderu 3:78f223d34f36 7326 #define FTM3_CnV(index) FTM_CnV_REG(FTM3,index)
ethaderu 3:78f223d34f36 7327
ethaderu 3:78f223d34f36 7328 /*!
ethaderu 3:78f223d34f36 7329 * @}
ethaderu 3:78f223d34f36 7330 */ /* end of group FTM_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 7331
ethaderu 3:78f223d34f36 7332
ethaderu 3:78f223d34f36 7333 /*!
ethaderu 3:78f223d34f36 7334 * @}
ethaderu 3:78f223d34f36 7335 */ /* end of group FTM_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 7336
ethaderu 3:78f223d34f36 7337
ethaderu 3:78f223d34f36 7338 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 7339 -- GPIO Peripheral Access Layer
ethaderu 3:78f223d34f36 7340 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 7341
ethaderu 3:78f223d34f36 7342 /*!
ethaderu 3:78f223d34f36 7343 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
ethaderu 3:78f223d34f36 7344 * @{
ethaderu 3:78f223d34f36 7345 */
ethaderu 3:78f223d34f36 7346
ethaderu 3:78f223d34f36 7347 /** GPIO - Register Layout Typedef */
ethaderu 3:78f223d34f36 7348 typedef struct {
ethaderu 3:78f223d34f36 7349 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
ethaderu 3:78f223d34f36 7350 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
ethaderu 3:78f223d34f36 7351 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
ethaderu 3:78f223d34f36 7352 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
ethaderu 3:78f223d34f36 7353 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
ethaderu 3:78f223d34f36 7354 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
ethaderu 3:78f223d34f36 7355 } GPIO_Type, *GPIO_MemMapPtr;
ethaderu 3:78f223d34f36 7356
ethaderu 3:78f223d34f36 7357 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 7358 -- GPIO - Register accessor macros
ethaderu 3:78f223d34f36 7359 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 7360
ethaderu 3:78f223d34f36 7361 /*!
ethaderu 3:78f223d34f36 7362 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
ethaderu 3:78f223d34f36 7363 * @{
ethaderu 3:78f223d34f36 7364 */
ethaderu 3:78f223d34f36 7365
ethaderu 3:78f223d34f36 7366
ethaderu 3:78f223d34f36 7367 /* GPIO - Register accessors */
ethaderu 3:78f223d34f36 7368 #define GPIO_PDOR_REG(base) ((base)->PDOR)
ethaderu 3:78f223d34f36 7369 #define GPIO_PSOR_REG(base) ((base)->PSOR)
ethaderu 3:78f223d34f36 7370 #define GPIO_PCOR_REG(base) ((base)->PCOR)
ethaderu 3:78f223d34f36 7371 #define GPIO_PTOR_REG(base) ((base)->PTOR)
ethaderu 3:78f223d34f36 7372 #define GPIO_PDIR_REG(base) ((base)->PDIR)
ethaderu 3:78f223d34f36 7373 #define GPIO_PDDR_REG(base) ((base)->PDDR)
ethaderu 3:78f223d34f36 7374
ethaderu 3:78f223d34f36 7375 /*!
ethaderu 3:78f223d34f36 7376 * @}
ethaderu 3:78f223d34f36 7377 */ /* end of group GPIO_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 7378
ethaderu 3:78f223d34f36 7379
ethaderu 3:78f223d34f36 7380 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 7381 -- GPIO Register Masks
ethaderu 3:78f223d34f36 7382 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 7383
ethaderu 3:78f223d34f36 7384 /*!
ethaderu 3:78f223d34f36 7385 * @addtogroup GPIO_Register_Masks GPIO Register Masks
ethaderu 3:78f223d34f36 7386 * @{
ethaderu 3:78f223d34f36 7387 */
ethaderu 3:78f223d34f36 7388
ethaderu 3:78f223d34f36 7389 /* PDOR Bit Fields */
ethaderu 3:78f223d34f36 7390 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 7391 #define GPIO_PDOR_PDO_SHIFT 0
ethaderu 3:78f223d34f36 7392 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
ethaderu 3:78f223d34f36 7393 /* PSOR Bit Fields */
ethaderu 3:78f223d34f36 7394 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 7395 #define GPIO_PSOR_PTSO_SHIFT 0
ethaderu 3:78f223d34f36 7396 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
ethaderu 3:78f223d34f36 7397 /* PCOR Bit Fields */
ethaderu 3:78f223d34f36 7398 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 7399 #define GPIO_PCOR_PTCO_SHIFT 0
ethaderu 3:78f223d34f36 7400 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
ethaderu 3:78f223d34f36 7401 /* PTOR Bit Fields */
ethaderu 3:78f223d34f36 7402 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 7403 #define GPIO_PTOR_PTTO_SHIFT 0
ethaderu 3:78f223d34f36 7404 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
ethaderu 3:78f223d34f36 7405 /* PDIR Bit Fields */
ethaderu 3:78f223d34f36 7406 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 7407 #define GPIO_PDIR_PDI_SHIFT 0
ethaderu 3:78f223d34f36 7408 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
ethaderu 3:78f223d34f36 7409 /* PDDR Bit Fields */
ethaderu 3:78f223d34f36 7410 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 7411 #define GPIO_PDDR_PDD_SHIFT 0
ethaderu 3:78f223d34f36 7412 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
ethaderu 3:78f223d34f36 7413
ethaderu 3:78f223d34f36 7414 /*!
ethaderu 3:78f223d34f36 7415 * @}
ethaderu 3:78f223d34f36 7416 */ /* end of group GPIO_Register_Masks */
ethaderu 3:78f223d34f36 7417
ethaderu 3:78f223d34f36 7418
ethaderu 3:78f223d34f36 7419 /* GPIO - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 7420 /** Peripheral PTA base address */
ethaderu 3:78f223d34f36 7421 #define PTA_BASE (0x400FF000u)
ethaderu 3:78f223d34f36 7422 /** Peripheral PTA base pointer */
ethaderu 3:78f223d34f36 7423 #define PTA ((GPIO_Type *)PTA_BASE)
ethaderu 3:78f223d34f36 7424 #define PTA_BASE_PTR (PTA)
ethaderu 3:78f223d34f36 7425 /** Peripheral PTB base address */
ethaderu 3:78f223d34f36 7426 #define PTB_BASE (0x400FF040u)
ethaderu 3:78f223d34f36 7427 /** Peripheral PTB base pointer */
ethaderu 3:78f223d34f36 7428 #define PTB ((GPIO_Type *)PTB_BASE)
ethaderu 3:78f223d34f36 7429 #define PTB_BASE_PTR (PTB)
ethaderu 3:78f223d34f36 7430 /** Peripheral PTC base address */
ethaderu 3:78f223d34f36 7431 #define PTC_BASE (0x400FF080u)
ethaderu 3:78f223d34f36 7432 /** Peripheral PTC base pointer */
ethaderu 3:78f223d34f36 7433 #define PTC ((GPIO_Type *)PTC_BASE)
ethaderu 3:78f223d34f36 7434 #define PTC_BASE_PTR (PTC)
ethaderu 3:78f223d34f36 7435 /** Peripheral PTD base address */
ethaderu 3:78f223d34f36 7436 #define PTD_BASE (0x400FF0C0u)
ethaderu 3:78f223d34f36 7437 /** Peripheral PTD base pointer */
ethaderu 3:78f223d34f36 7438 #define PTD ((GPIO_Type *)PTD_BASE)
ethaderu 3:78f223d34f36 7439 #define PTD_BASE_PTR (PTD)
ethaderu 3:78f223d34f36 7440 /** Peripheral PTE base address */
ethaderu 3:78f223d34f36 7441 #define PTE_BASE (0x400FF100u)
ethaderu 3:78f223d34f36 7442 /** Peripheral PTE base pointer */
ethaderu 3:78f223d34f36 7443 #define PTE ((GPIO_Type *)PTE_BASE)
ethaderu 3:78f223d34f36 7444 #define PTE_BASE_PTR (PTE)
ethaderu 3:78f223d34f36 7445 /** Array initializer of GPIO peripheral base addresses */
ethaderu 3:78f223d34f36 7446 #define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
ethaderu 3:78f223d34f36 7447 /** Array initializer of GPIO peripheral base pointers */
ethaderu 3:78f223d34f36 7448 #define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
ethaderu 3:78f223d34f36 7449
ethaderu 3:78f223d34f36 7450 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 7451 -- GPIO - Register accessor macros
ethaderu 3:78f223d34f36 7452 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 7453
ethaderu 3:78f223d34f36 7454 /*!
ethaderu 3:78f223d34f36 7455 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
ethaderu 3:78f223d34f36 7456 * @{
ethaderu 3:78f223d34f36 7457 */
ethaderu 3:78f223d34f36 7458
ethaderu 3:78f223d34f36 7459
ethaderu 3:78f223d34f36 7460 /* GPIO - Register instance definitions */
ethaderu 3:78f223d34f36 7461 /* PTA */
ethaderu 3:78f223d34f36 7462 #define GPIOA_PDOR GPIO_PDOR_REG(PTA)
ethaderu 3:78f223d34f36 7463 #define GPIOA_PSOR GPIO_PSOR_REG(PTA)
ethaderu 3:78f223d34f36 7464 #define GPIOA_PCOR GPIO_PCOR_REG(PTA)
ethaderu 3:78f223d34f36 7465 #define GPIOA_PTOR GPIO_PTOR_REG(PTA)
ethaderu 3:78f223d34f36 7466 #define GPIOA_PDIR GPIO_PDIR_REG(PTA)
ethaderu 3:78f223d34f36 7467 #define GPIOA_PDDR GPIO_PDDR_REG(PTA)
ethaderu 3:78f223d34f36 7468 /* PTB */
ethaderu 3:78f223d34f36 7469 #define GPIOB_PDOR GPIO_PDOR_REG(PTB)
ethaderu 3:78f223d34f36 7470 #define GPIOB_PSOR GPIO_PSOR_REG(PTB)
ethaderu 3:78f223d34f36 7471 #define GPIOB_PCOR GPIO_PCOR_REG(PTB)
ethaderu 3:78f223d34f36 7472 #define GPIOB_PTOR GPIO_PTOR_REG(PTB)
ethaderu 3:78f223d34f36 7473 #define GPIOB_PDIR GPIO_PDIR_REG(PTB)
ethaderu 3:78f223d34f36 7474 #define GPIOB_PDDR GPIO_PDDR_REG(PTB)
ethaderu 3:78f223d34f36 7475 /* PTC */
ethaderu 3:78f223d34f36 7476 #define GPIOC_PDOR GPIO_PDOR_REG(PTC)
ethaderu 3:78f223d34f36 7477 #define GPIOC_PSOR GPIO_PSOR_REG(PTC)
ethaderu 3:78f223d34f36 7478 #define GPIOC_PCOR GPIO_PCOR_REG(PTC)
ethaderu 3:78f223d34f36 7479 #define GPIOC_PTOR GPIO_PTOR_REG(PTC)
ethaderu 3:78f223d34f36 7480 #define GPIOC_PDIR GPIO_PDIR_REG(PTC)
ethaderu 3:78f223d34f36 7481 #define GPIOC_PDDR GPIO_PDDR_REG(PTC)
ethaderu 3:78f223d34f36 7482 /* PTD */
ethaderu 3:78f223d34f36 7483 #define GPIOD_PDOR GPIO_PDOR_REG(PTD)
ethaderu 3:78f223d34f36 7484 #define GPIOD_PSOR GPIO_PSOR_REG(PTD)
ethaderu 3:78f223d34f36 7485 #define GPIOD_PCOR GPIO_PCOR_REG(PTD)
ethaderu 3:78f223d34f36 7486 #define GPIOD_PTOR GPIO_PTOR_REG(PTD)
ethaderu 3:78f223d34f36 7487 #define GPIOD_PDIR GPIO_PDIR_REG(PTD)
ethaderu 3:78f223d34f36 7488 #define GPIOD_PDDR GPIO_PDDR_REG(PTD)
ethaderu 3:78f223d34f36 7489 /* PTE */
ethaderu 3:78f223d34f36 7490 #define GPIOE_PDOR GPIO_PDOR_REG(PTE)
ethaderu 3:78f223d34f36 7491 #define GPIOE_PSOR GPIO_PSOR_REG(PTE)
ethaderu 3:78f223d34f36 7492 #define GPIOE_PCOR GPIO_PCOR_REG(PTE)
ethaderu 3:78f223d34f36 7493 #define GPIOE_PTOR GPIO_PTOR_REG(PTE)
ethaderu 3:78f223d34f36 7494 #define GPIOE_PDIR GPIO_PDIR_REG(PTE)
ethaderu 3:78f223d34f36 7495 #define GPIOE_PDDR GPIO_PDDR_REG(PTE)
ethaderu 3:78f223d34f36 7496
ethaderu 3:78f223d34f36 7497 /*!
ethaderu 3:78f223d34f36 7498 * @}
ethaderu 3:78f223d34f36 7499 */ /* end of group GPIO_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 7500
ethaderu 3:78f223d34f36 7501
ethaderu 3:78f223d34f36 7502 /*!
ethaderu 3:78f223d34f36 7503 * @}
ethaderu 3:78f223d34f36 7504 */ /* end of group GPIO_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 7505
ethaderu 3:78f223d34f36 7506
ethaderu 3:78f223d34f36 7507 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 7508 -- I2C Peripheral Access Layer
ethaderu 3:78f223d34f36 7509 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 7510
ethaderu 3:78f223d34f36 7511 /*!
ethaderu 3:78f223d34f36 7512 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
ethaderu 3:78f223d34f36 7513 * @{
ethaderu 3:78f223d34f36 7514 */
ethaderu 3:78f223d34f36 7515
ethaderu 3:78f223d34f36 7516 /** I2C - Register Layout Typedef */
ethaderu 3:78f223d34f36 7517 typedef struct {
ethaderu 3:78f223d34f36 7518 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
ethaderu 3:78f223d34f36 7519 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
ethaderu 3:78f223d34f36 7520 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
ethaderu 3:78f223d34f36 7521 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
ethaderu 3:78f223d34f36 7522 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
ethaderu 3:78f223d34f36 7523 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
ethaderu 3:78f223d34f36 7524 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
ethaderu 3:78f223d34f36 7525 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
ethaderu 3:78f223d34f36 7526 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
ethaderu 3:78f223d34f36 7527 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
ethaderu 3:78f223d34f36 7528 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
ethaderu 3:78f223d34f36 7529 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
ethaderu 3:78f223d34f36 7530 } I2C_Type, *I2C_MemMapPtr;
ethaderu 3:78f223d34f36 7531
ethaderu 3:78f223d34f36 7532 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 7533 -- I2C - Register accessor macros
ethaderu 3:78f223d34f36 7534 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 7535
ethaderu 3:78f223d34f36 7536 /*!
ethaderu 3:78f223d34f36 7537 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
ethaderu 3:78f223d34f36 7538 * @{
ethaderu 3:78f223d34f36 7539 */
ethaderu 3:78f223d34f36 7540
ethaderu 3:78f223d34f36 7541
ethaderu 3:78f223d34f36 7542 /* I2C - Register accessors */
ethaderu 3:78f223d34f36 7543 #define I2C_A1_REG(base) ((base)->A1)
ethaderu 3:78f223d34f36 7544 #define I2C_F_REG(base) ((base)->F)
ethaderu 3:78f223d34f36 7545 #define I2C_C1_REG(base) ((base)->C1)
ethaderu 3:78f223d34f36 7546 #define I2C_S_REG(base) ((base)->S)
ethaderu 3:78f223d34f36 7547 #define I2C_D_REG(base) ((base)->D)
ethaderu 3:78f223d34f36 7548 #define I2C_C2_REG(base) ((base)->C2)
ethaderu 3:78f223d34f36 7549 #define I2C_FLT_REG(base) ((base)->FLT)
ethaderu 3:78f223d34f36 7550 #define I2C_RA_REG(base) ((base)->RA)
ethaderu 3:78f223d34f36 7551 #define I2C_SMB_REG(base) ((base)->SMB)
ethaderu 3:78f223d34f36 7552 #define I2C_A2_REG(base) ((base)->A2)
ethaderu 3:78f223d34f36 7553 #define I2C_SLTH_REG(base) ((base)->SLTH)
ethaderu 3:78f223d34f36 7554 #define I2C_SLTL_REG(base) ((base)->SLTL)
ethaderu 3:78f223d34f36 7555
ethaderu 3:78f223d34f36 7556 /*!
ethaderu 3:78f223d34f36 7557 * @}
ethaderu 3:78f223d34f36 7558 */ /* end of group I2C_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 7559
ethaderu 3:78f223d34f36 7560
ethaderu 3:78f223d34f36 7561 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 7562 -- I2C Register Masks
ethaderu 3:78f223d34f36 7563 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 7564
ethaderu 3:78f223d34f36 7565 /*!
ethaderu 3:78f223d34f36 7566 * @addtogroup I2C_Register_Masks I2C Register Masks
ethaderu 3:78f223d34f36 7567 * @{
ethaderu 3:78f223d34f36 7568 */
ethaderu 3:78f223d34f36 7569
ethaderu 3:78f223d34f36 7570 /* A1 Bit Fields */
ethaderu 3:78f223d34f36 7571 #define I2C_A1_AD_MASK 0xFEu
ethaderu 3:78f223d34f36 7572 #define I2C_A1_AD_SHIFT 1
ethaderu 3:78f223d34f36 7573 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
ethaderu 3:78f223d34f36 7574 /* F Bit Fields */
ethaderu 3:78f223d34f36 7575 #define I2C_F_ICR_MASK 0x3Fu
ethaderu 3:78f223d34f36 7576 #define I2C_F_ICR_SHIFT 0
ethaderu 3:78f223d34f36 7577 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
ethaderu 3:78f223d34f36 7578 #define I2C_F_MULT_MASK 0xC0u
ethaderu 3:78f223d34f36 7579 #define I2C_F_MULT_SHIFT 6
ethaderu 3:78f223d34f36 7580 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
ethaderu 3:78f223d34f36 7581 /* C1 Bit Fields */
ethaderu 3:78f223d34f36 7582 #define I2C_C1_DMAEN_MASK 0x1u
ethaderu 3:78f223d34f36 7583 #define I2C_C1_DMAEN_SHIFT 0
ethaderu 3:78f223d34f36 7584 #define I2C_C1_WUEN_MASK 0x2u
ethaderu 3:78f223d34f36 7585 #define I2C_C1_WUEN_SHIFT 1
ethaderu 3:78f223d34f36 7586 #define I2C_C1_RSTA_MASK 0x4u
ethaderu 3:78f223d34f36 7587 #define I2C_C1_RSTA_SHIFT 2
ethaderu 3:78f223d34f36 7588 #define I2C_C1_TXAK_MASK 0x8u
ethaderu 3:78f223d34f36 7589 #define I2C_C1_TXAK_SHIFT 3
ethaderu 3:78f223d34f36 7590 #define I2C_C1_TX_MASK 0x10u
ethaderu 3:78f223d34f36 7591 #define I2C_C1_TX_SHIFT 4
ethaderu 3:78f223d34f36 7592 #define I2C_C1_MST_MASK 0x20u
ethaderu 3:78f223d34f36 7593 #define I2C_C1_MST_SHIFT 5
ethaderu 3:78f223d34f36 7594 #define I2C_C1_IICIE_MASK 0x40u
ethaderu 3:78f223d34f36 7595 #define I2C_C1_IICIE_SHIFT 6
ethaderu 3:78f223d34f36 7596 #define I2C_C1_IICEN_MASK 0x80u
ethaderu 3:78f223d34f36 7597 #define I2C_C1_IICEN_SHIFT 7
ethaderu 3:78f223d34f36 7598 /* S Bit Fields */
ethaderu 3:78f223d34f36 7599 #define I2C_S_RXAK_MASK 0x1u
ethaderu 3:78f223d34f36 7600 #define I2C_S_RXAK_SHIFT 0
ethaderu 3:78f223d34f36 7601 #define I2C_S_IICIF_MASK 0x2u
ethaderu 3:78f223d34f36 7602 #define I2C_S_IICIF_SHIFT 1
ethaderu 3:78f223d34f36 7603 #define I2C_S_SRW_MASK 0x4u
ethaderu 3:78f223d34f36 7604 #define I2C_S_SRW_SHIFT 2
ethaderu 3:78f223d34f36 7605 #define I2C_S_RAM_MASK 0x8u
ethaderu 3:78f223d34f36 7606 #define I2C_S_RAM_SHIFT 3
ethaderu 3:78f223d34f36 7607 #define I2C_S_ARBL_MASK 0x10u
ethaderu 3:78f223d34f36 7608 #define I2C_S_ARBL_SHIFT 4
ethaderu 3:78f223d34f36 7609 #define I2C_S_BUSY_MASK 0x20u
ethaderu 3:78f223d34f36 7610 #define I2C_S_BUSY_SHIFT 5
ethaderu 3:78f223d34f36 7611 #define I2C_S_IAAS_MASK 0x40u
ethaderu 3:78f223d34f36 7612 #define I2C_S_IAAS_SHIFT 6
ethaderu 3:78f223d34f36 7613 #define I2C_S_TCF_MASK 0x80u
ethaderu 3:78f223d34f36 7614 #define I2C_S_TCF_SHIFT 7
ethaderu 3:78f223d34f36 7615 /* D Bit Fields */
ethaderu 3:78f223d34f36 7616 #define I2C_D_DATA_MASK 0xFFu
ethaderu 3:78f223d34f36 7617 #define I2C_D_DATA_SHIFT 0
ethaderu 3:78f223d34f36 7618 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
ethaderu 3:78f223d34f36 7619 /* C2 Bit Fields */
ethaderu 3:78f223d34f36 7620 #define I2C_C2_AD_MASK 0x7u
ethaderu 3:78f223d34f36 7621 #define I2C_C2_AD_SHIFT 0
ethaderu 3:78f223d34f36 7622 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
ethaderu 3:78f223d34f36 7623 #define I2C_C2_RMEN_MASK 0x8u
ethaderu 3:78f223d34f36 7624 #define I2C_C2_RMEN_SHIFT 3
ethaderu 3:78f223d34f36 7625 #define I2C_C2_SBRC_MASK 0x10u
ethaderu 3:78f223d34f36 7626 #define I2C_C2_SBRC_SHIFT 4
ethaderu 3:78f223d34f36 7627 #define I2C_C2_HDRS_MASK 0x20u
ethaderu 3:78f223d34f36 7628 #define I2C_C2_HDRS_SHIFT 5
ethaderu 3:78f223d34f36 7629 #define I2C_C2_ADEXT_MASK 0x40u
ethaderu 3:78f223d34f36 7630 #define I2C_C2_ADEXT_SHIFT 6
ethaderu 3:78f223d34f36 7631 #define I2C_C2_GCAEN_MASK 0x80u
ethaderu 3:78f223d34f36 7632 #define I2C_C2_GCAEN_SHIFT 7
ethaderu 3:78f223d34f36 7633 /* FLT Bit Fields */
ethaderu 3:78f223d34f36 7634 #define I2C_FLT_FLT_MASK 0xFu
ethaderu 3:78f223d34f36 7635 #define I2C_FLT_FLT_SHIFT 0
ethaderu 3:78f223d34f36 7636 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
ethaderu 3:78f223d34f36 7637 #define I2C_FLT_STARTF_MASK 0x10u
ethaderu 3:78f223d34f36 7638 #define I2C_FLT_STARTF_SHIFT 4
ethaderu 3:78f223d34f36 7639 #define I2C_FLT_SSIE_MASK 0x20u
ethaderu 3:78f223d34f36 7640 #define I2C_FLT_SSIE_SHIFT 5
ethaderu 3:78f223d34f36 7641 #define I2C_FLT_STOPF_MASK 0x40u
ethaderu 3:78f223d34f36 7642 #define I2C_FLT_STOPF_SHIFT 6
ethaderu 3:78f223d34f36 7643 #define I2C_FLT_SHEN_MASK 0x80u
ethaderu 3:78f223d34f36 7644 #define I2C_FLT_SHEN_SHIFT 7
ethaderu 3:78f223d34f36 7645 /* RA Bit Fields */
ethaderu 3:78f223d34f36 7646 #define I2C_RA_RAD_MASK 0xFEu
ethaderu 3:78f223d34f36 7647 #define I2C_RA_RAD_SHIFT 1
ethaderu 3:78f223d34f36 7648 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
ethaderu 3:78f223d34f36 7649 /* SMB Bit Fields */
ethaderu 3:78f223d34f36 7650 #define I2C_SMB_SHTF2IE_MASK 0x1u
ethaderu 3:78f223d34f36 7651 #define I2C_SMB_SHTF2IE_SHIFT 0
ethaderu 3:78f223d34f36 7652 #define I2C_SMB_SHTF2_MASK 0x2u
ethaderu 3:78f223d34f36 7653 #define I2C_SMB_SHTF2_SHIFT 1
ethaderu 3:78f223d34f36 7654 #define I2C_SMB_SHTF1_MASK 0x4u
ethaderu 3:78f223d34f36 7655 #define I2C_SMB_SHTF1_SHIFT 2
ethaderu 3:78f223d34f36 7656 #define I2C_SMB_SLTF_MASK 0x8u
ethaderu 3:78f223d34f36 7657 #define I2C_SMB_SLTF_SHIFT 3
ethaderu 3:78f223d34f36 7658 #define I2C_SMB_TCKSEL_MASK 0x10u
ethaderu 3:78f223d34f36 7659 #define I2C_SMB_TCKSEL_SHIFT 4
ethaderu 3:78f223d34f36 7660 #define I2C_SMB_SIICAEN_MASK 0x20u
ethaderu 3:78f223d34f36 7661 #define I2C_SMB_SIICAEN_SHIFT 5
ethaderu 3:78f223d34f36 7662 #define I2C_SMB_ALERTEN_MASK 0x40u
ethaderu 3:78f223d34f36 7663 #define I2C_SMB_ALERTEN_SHIFT 6
ethaderu 3:78f223d34f36 7664 #define I2C_SMB_FACK_MASK 0x80u
ethaderu 3:78f223d34f36 7665 #define I2C_SMB_FACK_SHIFT 7
ethaderu 3:78f223d34f36 7666 /* A2 Bit Fields */
ethaderu 3:78f223d34f36 7667 #define I2C_A2_SAD_MASK 0xFEu
ethaderu 3:78f223d34f36 7668 #define I2C_A2_SAD_SHIFT 1
ethaderu 3:78f223d34f36 7669 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
ethaderu 3:78f223d34f36 7670 /* SLTH Bit Fields */
ethaderu 3:78f223d34f36 7671 #define I2C_SLTH_SSLT_MASK 0xFFu
ethaderu 3:78f223d34f36 7672 #define I2C_SLTH_SSLT_SHIFT 0
ethaderu 3:78f223d34f36 7673 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
ethaderu 3:78f223d34f36 7674 /* SLTL Bit Fields */
ethaderu 3:78f223d34f36 7675 #define I2C_SLTL_SSLT_MASK 0xFFu
ethaderu 3:78f223d34f36 7676 #define I2C_SLTL_SSLT_SHIFT 0
ethaderu 3:78f223d34f36 7677 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
ethaderu 3:78f223d34f36 7678
ethaderu 3:78f223d34f36 7679 /*!
ethaderu 3:78f223d34f36 7680 * @}
ethaderu 3:78f223d34f36 7681 */ /* end of group I2C_Register_Masks */
ethaderu 3:78f223d34f36 7682
ethaderu 3:78f223d34f36 7683
ethaderu 3:78f223d34f36 7684 /* I2C - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 7685 /** Peripheral I2C0 base address */
ethaderu 3:78f223d34f36 7686 #define I2C0_BASE (0x40066000u)
ethaderu 3:78f223d34f36 7687 /** Peripheral I2C0 base pointer */
ethaderu 3:78f223d34f36 7688 #define I2C0 ((I2C_Type *)I2C0_BASE)
ethaderu 3:78f223d34f36 7689 #define I2C0_BASE_PTR (I2C0)
ethaderu 3:78f223d34f36 7690 /** Peripheral I2C1 base address */
ethaderu 3:78f223d34f36 7691 #define I2C1_BASE (0x40067000u)
ethaderu 3:78f223d34f36 7692 /** Peripheral I2C1 base pointer */
ethaderu 3:78f223d34f36 7693 #define I2C1 ((I2C_Type *)I2C1_BASE)
ethaderu 3:78f223d34f36 7694 #define I2C1_BASE_PTR (I2C1)
ethaderu 3:78f223d34f36 7695 /** Peripheral I2C2 base address */
ethaderu 3:78f223d34f36 7696 #define I2C2_BASE (0x400E6000u)
ethaderu 3:78f223d34f36 7697 /** Peripheral I2C2 base pointer */
ethaderu 3:78f223d34f36 7698 #define I2C2 ((I2C_Type *)I2C2_BASE)
ethaderu 3:78f223d34f36 7699 #define I2C2_BASE_PTR (I2C2)
ethaderu 3:78f223d34f36 7700 /** Array initializer of I2C peripheral base addresses */
ethaderu 3:78f223d34f36 7701 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE }
ethaderu 3:78f223d34f36 7702 /** Array initializer of I2C peripheral base pointers */
ethaderu 3:78f223d34f36 7703 #define I2C_BASE_PTRS { I2C0, I2C1, I2C2 }
ethaderu 3:78f223d34f36 7704 /** Interrupt vectors for the I2C peripheral type */
ethaderu 3:78f223d34f36 7705 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn }
ethaderu 3:78f223d34f36 7706
ethaderu 3:78f223d34f36 7707 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 7708 -- I2C - Register accessor macros
ethaderu 3:78f223d34f36 7709 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 7710
ethaderu 3:78f223d34f36 7711 /*!
ethaderu 3:78f223d34f36 7712 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
ethaderu 3:78f223d34f36 7713 * @{
ethaderu 3:78f223d34f36 7714 */
ethaderu 3:78f223d34f36 7715
ethaderu 3:78f223d34f36 7716
ethaderu 3:78f223d34f36 7717 /* I2C - Register instance definitions */
ethaderu 3:78f223d34f36 7718 /* I2C0 */
ethaderu 3:78f223d34f36 7719 #define I2C0_A1 I2C_A1_REG(I2C0)
ethaderu 3:78f223d34f36 7720 #define I2C0_F I2C_F_REG(I2C0)
ethaderu 3:78f223d34f36 7721 #define I2C0_C1 I2C_C1_REG(I2C0)
ethaderu 3:78f223d34f36 7722 #define I2C0_S I2C_S_REG(I2C0)
ethaderu 3:78f223d34f36 7723 #define I2C0_D I2C_D_REG(I2C0)
ethaderu 3:78f223d34f36 7724 #define I2C0_C2 I2C_C2_REG(I2C0)
ethaderu 3:78f223d34f36 7725 #define I2C0_FLT I2C_FLT_REG(I2C0)
ethaderu 3:78f223d34f36 7726 #define I2C0_RA I2C_RA_REG(I2C0)
ethaderu 3:78f223d34f36 7727 #define I2C0_SMB I2C_SMB_REG(I2C0)
ethaderu 3:78f223d34f36 7728 #define I2C0_A2 I2C_A2_REG(I2C0)
ethaderu 3:78f223d34f36 7729 #define I2C0_SLTH I2C_SLTH_REG(I2C0)
ethaderu 3:78f223d34f36 7730 #define I2C0_SLTL I2C_SLTL_REG(I2C0)
ethaderu 3:78f223d34f36 7731 /* I2C1 */
ethaderu 3:78f223d34f36 7732 #define I2C1_A1 I2C_A1_REG(I2C1)
ethaderu 3:78f223d34f36 7733 #define I2C1_F I2C_F_REG(I2C1)
ethaderu 3:78f223d34f36 7734 #define I2C1_C1 I2C_C1_REG(I2C1)
ethaderu 3:78f223d34f36 7735 #define I2C1_S I2C_S_REG(I2C1)
ethaderu 3:78f223d34f36 7736 #define I2C1_D I2C_D_REG(I2C1)
ethaderu 3:78f223d34f36 7737 #define I2C1_C2 I2C_C2_REG(I2C1)
ethaderu 3:78f223d34f36 7738 #define I2C1_FLT I2C_FLT_REG(I2C1)
ethaderu 3:78f223d34f36 7739 #define I2C1_RA I2C_RA_REG(I2C1)
ethaderu 3:78f223d34f36 7740 #define I2C1_SMB I2C_SMB_REG(I2C1)
ethaderu 3:78f223d34f36 7741 #define I2C1_A2 I2C_A2_REG(I2C1)
ethaderu 3:78f223d34f36 7742 #define I2C1_SLTH I2C_SLTH_REG(I2C1)
ethaderu 3:78f223d34f36 7743 #define I2C1_SLTL I2C_SLTL_REG(I2C1)
ethaderu 3:78f223d34f36 7744 /* I2C2 */
ethaderu 3:78f223d34f36 7745 #define I2C2_A1 I2C_A1_REG(I2C2)
ethaderu 3:78f223d34f36 7746 #define I2C2_F I2C_F_REG(I2C2)
ethaderu 3:78f223d34f36 7747 #define I2C2_C1 I2C_C1_REG(I2C2)
ethaderu 3:78f223d34f36 7748 #define I2C2_S I2C_S_REG(I2C2)
ethaderu 3:78f223d34f36 7749 #define I2C2_D I2C_D_REG(I2C2)
ethaderu 3:78f223d34f36 7750 #define I2C2_C2 I2C_C2_REG(I2C2)
ethaderu 3:78f223d34f36 7751 #define I2C2_FLT I2C_FLT_REG(I2C2)
ethaderu 3:78f223d34f36 7752 #define I2C2_RA I2C_RA_REG(I2C2)
ethaderu 3:78f223d34f36 7753 #define I2C2_SMB I2C_SMB_REG(I2C2)
ethaderu 3:78f223d34f36 7754 #define I2C2_A2 I2C_A2_REG(I2C2)
ethaderu 3:78f223d34f36 7755 #define I2C2_SLTH I2C_SLTH_REG(I2C2)
ethaderu 3:78f223d34f36 7756 #define I2C2_SLTL I2C_SLTL_REG(I2C2)
ethaderu 3:78f223d34f36 7757
ethaderu 3:78f223d34f36 7758 /*!
ethaderu 3:78f223d34f36 7759 * @}
ethaderu 3:78f223d34f36 7760 */ /* end of group I2C_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 7761
ethaderu 3:78f223d34f36 7762
ethaderu 3:78f223d34f36 7763 /*!
ethaderu 3:78f223d34f36 7764 * @}
ethaderu 3:78f223d34f36 7765 */ /* end of group I2C_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 7766
ethaderu 3:78f223d34f36 7767
ethaderu 3:78f223d34f36 7768 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 7769 -- I2S Peripheral Access Layer
ethaderu 3:78f223d34f36 7770 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 7771
ethaderu 3:78f223d34f36 7772 /*!
ethaderu 3:78f223d34f36 7773 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
ethaderu 3:78f223d34f36 7774 * @{
ethaderu 3:78f223d34f36 7775 */
ethaderu 3:78f223d34f36 7776
ethaderu 3:78f223d34f36 7777 /** I2S - Register Layout Typedef */
ethaderu 3:78f223d34f36 7778 typedef struct {
ethaderu 3:78f223d34f36 7779 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
ethaderu 3:78f223d34f36 7780 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
ethaderu 3:78f223d34f36 7781 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
ethaderu 3:78f223d34f36 7782 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
ethaderu 3:78f223d34f36 7783 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
ethaderu 3:78f223d34f36 7784 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
ethaderu 3:78f223d34f36 7785 uint8_t RESERVED_0[8];
ethaderu 3:78f223d34f36 7786 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
ethaderu 3:78f223d34f36 7787 uint8_t RESERVED_1[24];
ethaderu 3:78f223d34f36 7788 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
ethaderu 3:78f223d34f36 7789 uint8_t RESERVED_2[24];
ethaderu 3:78f223d34f36 7790 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
ethaderu 3:78f223d34f36 7791 uint8_t RESERVED_3[28];
ethaderu 3:78f223d34f36 7792 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
ethaderu 3:78f223d34f36 7793 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
ethaderu 3:78f223d34f36 7794 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
ethaderu 3:78f223d34f36 7795 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
ethaderu 3:78f223d34f36 7796 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
ethaderu 3:78f223d34f36 7797 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
ethaderu 3:78f223d34f36 7798 uint8_t RESERVED_4[8];
ethaderu 3:78f223d34f36 7799 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
ethaderu 3:78f223d34f36 7800 uint8_t RESERVED_5[24];
ethaderu 3:78f223d34f36 7801 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
ethaderu 3:78f223d34f36 7802 uint8_t RESERVED_6[24];
ethaderu 3:78f223d34f36 7803 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
ethaderu 3:78f223d34f36 7804 uint8_t RESERVED_7[28];
ethaderu 3:78f223d34f36 7805 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
ethaderu 3:78f223d34f36 7806 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
ethaderu 3:78f223d34f36 7807 } I2S_Type, *I2S_MemMapPtr;
ethaderu 3:78f223d34f36 7808
ethaderu 3:78f223d34f36 7809 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 7810 -- I2S - Register accessor macros
ethaderu 3:78f223d34f36 7811 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 7812
ethaderu 3:78f223d34f36 7813 /*!
ethaderu 3:78f223d34f36 7814 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
ethaderu 3:78f223d34f36 7815 * @{
ethaderu 3:78f223d34f36 7816 */
ethaderu 3:78f223d34f36 7817
ethaderu 3:78f223d34f36 7818
ethaderu 3:78f223d34f36 7819 /* I2S - Register accessors */
ethaderu 3:78f223d34f36 7820 #define I2S_TCSR_REG(base) ((base)->TCSR)
ethaderu 3:78f223d34f36 7821 #define I2S_TCR1_REG(base) ((base)->TCR1)
ethaderu 3:78f223d34f36 7822 #define I2S_TCR2_REG(base) ((base)->TCR2)
ethaderu 3:78f223d34f36 7823 #define I2S_TCR3_REG(base) ((base)->TCR3)
ethaderu 3:78f223d34f36 7824 #define I2S_TCR4_REG(base) ((base)->TCR4)
ethaderu 3:78f223d34f36 7825 #define I2S_TCR5_REG(base) ((base)->TCR5)
ethaderu 3:78f223d34f36 7826 #define I2S_TDR_REG(base,index) ((base)->TDR[index])
ethaderu 3:78f223d34f36 7827 #define I2S_TFR_REG(base,index) ((base)->TFR[index])
ethaderu 3:78f223d34f36 7828 #define I2S_TMR_REG(base) ((base)->TMR)
ethaderu 3:78f223d34f36 7829 #define I2S_RCSR_REG(base) ((base)->RCSR)
ethaderu 3:78f223d34f36 7830 #define I2S_RCR1_REG(base) ((base)->RCR1)
ethaderu 3:78f223d34f36 7831 #define I2S_RCR2_REG(base) ((base)->RCR2)
ethaderu 3:78f223d34f36 7832 #define I2S_RCR3_REG(base) ((base)->RCR3)
ethaderu 3:78f223d34f36 7833 #define I2S_RCR4_REG(base) ((base)->RCR4)
ethaderu 3:78f223d34f36 7834 #define I2S_RCR5_REG(base) ((base)->RCR5)
ethaderu 3:78f223d34f36 7835 #define I2S_RDR_REG(base,index) ((base)->RDR[index])
ethaderu 3:78f223d34f36 7836 #define I2S_RFR_REG(base,index) ((base)->RFR[index])
ethaderu 3:78f223d34f36 7837 #define I2S_RMR_REG(base) ((base)->RMR)
ethaderu 3:78f223d34f36 7838 #define I2S_MCR_REG(base) ((base)->MCR)
ethaderu 3:78f223d34f36 7839 #define I2S_MDR_REG(base) ((base)->MDR)
ethaderu 3:78f223d34f36 7840
ethaderu 3:78f223d34f36 7841 /*!
ethaderu 3:78f223d34f36 7842 * @}
ethaderu 3:78f223d34f36 7843 */ /* end of group I2S_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 7844
ethaderu 3:78f223d34f36 7845
ethaderu 3:78f223d34f36 7846 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 7847 -- I2S Register Masks
ethaderu 3:78f223d34f36 7848 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 7849
ethaderu 3:78f223d34f36 7850 /*!
ethaderu 3:78f223d34f36 7851 * @addtogroup I2S_Register_Masks I2S Register Masks
ethaderu 3:78f223d34f36 7852 * @{
ethaderu 3:78f223d34f36 7853 */
ethaderu 3:78f223d34f36 7854
ethaderu 3:78f223d34f36 7855 /* TCSR Bit Fields */
ethaderu 3:78f223d34f36 7856 #define I2S_TCSR_FRDE_MASK 0x1u
ethaderu 3:78f223d34f36 7857 #define I2S_TCSR_FRDE_SHIFT 0
ethaderu 3:78f223d34f36 7858 #define I2S_TCSR_FWDE_MASK 0x2u
ethaderu 3:78f223d34f36 7859 #define I2S_TCSR_FWDE_SHIFT 1
ethaderu 3:78f223d34f36 7860 #define I2S_TCSR_FRIE_MASK 0x100u
ethaderu 3:78f223d34f36 7861 #define I2S_TCSR_FRIE_SHIFT 8
ethaderu 3:78f223d34f36 7862 #define I2S_TCSR_FWIE_MASK 0x200u
ethaderu 3:78f223d34f36 7863 #define I2S_TCSR_FWIE_SHIFT 9
ethaderu 3:78f223d34f36 7864 #define I2S_TCSR_FEIE_MASK 0x400u
ethaderu 3:78f223d34f36 7865 #define I2S_TCSR_FEIE_SHIFT 10
ethaderu 3:78f223d34f36 7866 #define I2S_TCSR_SEIE_MASK 0x800u
ethaderu 3:78f223d34f36 7867 #define I2S_TCSR_SEIE_SHIFT 11
ethaderu 3:78f223d34f36 7868 #define I2S_TCSR_WSIE_MASK 0x1000u
ethaderu 3:78f223d34f36 7869 #define I2S_TCSR_WSIE_SHIFT 12
ethaderu 3:78f223d34f36 7870 #define I2S_TCSR_FRF_MASK 0x10000u
ethaderu 3:78f223d34f36 7871 #define I2S_TCSR_FRF_SHIFT 16
ethaderu 3:78f223d34f36 7872 #define I2S_TCSR_FWF_MASK 0x20000u
ethaderu 3:78f223d34f36 7873 #define I2S_TCSR_FWF_SHIFT 17
ethaderu 3:78f223d34f36 7874 #define I2S_TCSR_FEF_MASK 0x40000u
ethaderu 3:78f223d34f36 7875 #define I2S_TCSR_FEF_SHIFT 18
ethaderu 3:78f223d34f36 7876 #define I2S_TCSR_SEF_MASK 0x80000u
ethaderu 3:78f223d34f36 7877 #define I2S_TCSR_SEF_SHIFT 19
ethaderu 3:78f223d34f36 7878 #define I2S_TCSR_WSF_MASK 0x100000u
ethaderu 3:78f223d34f36 7879 #define I2S_TCSR_WSF_SHIFT 20
ethaderu 3:78f223d34f36 7880 #define I2S_TCSR_SR_MASK 0x1000000u
ethaderu 3:78f223d34f36 7881 #define I2S_TCSR_SR_SHIFT 24
ethaderu 3:78f223d34f36 7882 #define I2S_TCSR_FR_MASK 0x2000000u
ethaderu 3:78f223d34f36 7883 #define I2S_TCSR_FR_SHIFT 25
ethaderu 3:78f223d34f36 7884 #define I2S_TCSR_BCE_MASK 0x10000000u
ethaderu 3:78f223d34f36 7885 #define I2S_TCSR_BCE_SHIFT 28
ethaderu 3:78f223d34f36 7886 #define I2S_TCSR_DBGE_MASK 0x20000000u
ethaderu 3:78f223d34f36 7887 #define I2S_TCSR_DBGE_SHIFT 29
ethaderu 3:78f223d34f36 7888 #define I2S_TCSR_STOPE_MASK 0x40000000u
ethaderu 3:78f223d34f36 7889 #define I2S_TCSR_STOPE_SHIFT 30
ethaderu 3:78f223d34f36 7890 #define I2S_TCSR_TE_MASK 0x80000000u
ethaderu 3:78f223d34f36 7891 #define I2S_TCSR_TE_SHIFT 31
ethaderu 3:78f223d34f36 7892 /* TCR1 Bit Fields */
ethaderu 3:78f223d34f36 7893 #define I2S_TCR1_TFW_MASK 0x7u
ethaderu 3:78f223d34f36 7894 #define I2S_TCR1_TFW_SHIFT 0
ethaderu 3:78f223d34f36 7895 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
ethaderu 3:78f223d34f36 7896 /* TCR2 Bit Fields */
ethaderu 3:78f223d34f36 7897 #define I2S_TCR2_DIV_MASK 0xFFu
ethaderu 3:78f223d34f36 7898 #define I2S_TCR2_DIV_SHIFT 0
ethaderu 3:78f223d34f36 7899 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
ethaderu 3:78f223d34f36 7900 #define I2S_TCR2_BCD_MASK 0x1000000u
ethaderu 3:78f223d34f36 7901 #define I2S_TCR2_BCD_SHIFT 24
ethaderu 3:78f223d34f36 7902 #define I2S_TCR2_BCP_MASK 0x2000000u
ethaderu 3:78f223d34f36 7903 #define I2S_TCR2_BCP_SHIFT 25
ethaderu 3:78f223d34f36 7904 #define I2S_TCR2_MSEL_MASK 0xC000000u
ethaderu 3:78f223d34f36 7905 #define I2S_TCR2_MSEL_SHIFT 26
ethaderu 3:78f223d34f36 7906 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
ethaderu 3:78f223d34f36 7907 #define I2S_TCR2_BCI_MASK 0x10000000u
ethaderu 3:78f223d34f36 7908 #define I2S_TCR2_BCI_SHIFT 28
ethaderu 3:78f223d34f36 7909 #define I2S_TCR2_BCS_MASK 0x20000000u
ethaderu 3:78f223d34f36 7910 #define I2S_TCR2_BCS_SHIFT 29
ethaderu 3:78f223d34f36 7911 #define I2S_TCR2_SYNC_MASK 0xC0000000u
ethaderu 3:78f223d34f36 7912 #define I2S_TCR2_SYNC_SHIFT 30
ethaderu 3:78f223d34f36 7913 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
ethaderu 3:78f223d34f36 7914 /* TCR3 Bit Fields */
ethaderu 3:78f223d34f36 7915 #define I2S_TCR3_WDFL_MASK 0x1Fu
ethaderu 3:78f223d34f36 7916 #define I2S_TCR3_WDFL_SHIFT 0
ethaderu 3:78f223d34f36 7917 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
ethaderu 3:78f223d34f36 7918 #define I2S_TCR3_TCE_MASK 0x30000u
ethaderu 3:78f223d34f36 7919 #define I2S_TCR3_TCE_SHIFT 16
ethaderu 3:78f223d34f36 7920 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
ethaderu 3:78f223d34f36 7921 /* TCR4 Bit Fields */
ethaderu 3:78f223d34f36 7922 #define I2S_TCR4_FSD_MASK 0x1u
ethaderu 3:78f223d34f36 7923 #define I2S_TCR4_FSD_SHIFT 0
ethaderu 3:78f223d34f36 7924 #define I2S_TCR4_FSP_MASK 0x2u
ethaderu 3:78f223d34f36 7925 #define I2S_TCR4_FSP_SHIFT 1
ethaderu 3:78f223d34f36 7926 #define I2S_TCR4_FSE_MASK 0x8u
ethaderu 3:78f223d34f36 7927 #define I2S_TCR4_FSE_SHIFT 3
ethaderu 3:78f223d34f36 7928 #define I2S_TCR4_MF_MASK 0x10u
ethaderu 3:78f223d34f36 7929 #define I2S_TCR4_MF_SHIFT 4
ethaderu 3:78f223d34f36 7930 #define I2S_TCR4_SYWD_MASK 0x1F00u
ethaderu 3:78f223d34f36 7931 #define I2S_TCR4_SYWD_SHIFT 8
ethaderu 3:78f223d34f36 7932 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
ethaderu 3:78f223d34f36 7933 #define I2S_TCR4_FRSZ_MASK 0x1F0000u
ethaderu 3:78f223d34f36 7934 #define I2S_TCR4_FRSZ_SHIFT 16
ethaderu 3:78f223d34f36 7935 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
ethaderu 3:78f223d34f36 7936 /* TCR5 Bit Fields */
ethaderu 3:78f223d34f36 7937 #define I2S_TCR5_FBT_MASK 0x1F00u
ethaderu 3:78f223d34f36 7938 #define I2S_TCR5_FBT_SHIFT 8
ethaderu 3:78f223d34f36 7939 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
ethaderu 3:78f223d34f36 7940 #define I2S_TCR5_W0W_MASK 0x1F0000u
ethaderu 3:78f223d34f36 7941 #define I2S_TCR5_W0W_SHIFT 16
ethaderu 3:78f223d34f36 7942 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
ethaderu 3:78f223d34f36 7943 #define I2S_TCR5_WNW_MASK 0x1F000000u
ethaderu 3:78f223d34f36 7944 #define I2S_TCR5_WNW_SHIFT 24
ethaderu 3:78f223d34f36 7945 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
ethaderu 3:78f223d34f36 7946 /* TDR Bit Fields */
ethaderu 3:78f223d34f36 7947 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 7948 #define I2S_TDR_TDR_SHIFT 0
ethaderu 3:78f223d34f36 7949 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
ethaderu 3:78f223d34f36 7950 /* TFR Bit Fields */
ethaderu 3:78f223d34f36 7951 #define I2S_TFR_RFP_MASK 0xFu
ethaderu 3:78f223d34f36 7952 #define I2S_TFR_RFP_SHIFT 0
ethaderu 3:78f223d34f36 7953 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
ethaderu 3:78f223d34f36 7954 #define I2S_TFR_WFP_MASK 0xF0000u
ethaderu 3:78f223d34f36 7955 #define I2S_TFR_WFP_SHIFT 16
ethaderu 3:78f223d34f36 7956 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
ethaderu 3:78f223d34f36 7957 /* TMR Bit Fields */
ethaderu 3:78f223d34f36 7958 #define I2S_TMR_TWM_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 7959 #define I2S_TMR_TWM_SHIFT 0
ethaderu 3:78f223d34f36 7960 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
ethaderu 3:78f223d34f36 7961 /* RCSR Bit Fields */
ethaderu 3:78f223d34f36 7962 #define I2S_RCSR_FRDE_MASK 0x1u
ethaderu 3:78f223d34f36 7963 #define I2S_RCSR_FRDE_SHIFT 0
ethaderu 3:78f223d34f36 7964 #define I2S_RCSR_FWDE_MASK 0x2u
ethaderu 3:78f223d34f36 7965 #define I2S_RCSR_FWDE_SHIFT 1
ethaderu 3:78f223d34f36 7966 #define I2S_RCSR_FRIE_MASK 0x100u
ethaderu 3:78f223d34f36 7967 #define I2S_RCSR_FRIE_SHIFT 8
ethaderu 3:78f223d34f36 7968 #define I2S_RCSR_FWIE_MASK 0x200u
ethaderu 3:78f223d34f36 7969 #define I2S_RCSR_FWIE_SHIFT 9
ethaderu 3:78f223d34f36 7970 #define I2S_RCSR_FEIE_MASK 0x400u
ethaderu 3:78f223d34f36 7971 #define I2S_RCSR_FEIE_SHIFT 10
ethaderu 3:78f223d34f36 7972 #define I2S_RCSR_SEIE_MASK 0x800u
ethaderu 3:78f223d34f36 7973 #define I2S_RCSR_SEIE_SHIFT 11
ethaderu 3:78f223d34f36 7974 #define I2S_RCSR_WSIE_MASK 0x1000u
ethaderu 3:78f223d34f36 7975 #define I2S_RCSR_WSIE_SHIFT 12
ethaderu 3:78f223d34f36 7976 #define I2S_RCSR_FRF_MASK 0x10000u
ethaderu 3:78f223d34f36 7977 #define I2S_RCSR_FRF_SHIFT 16
ethaderu 3:78f223d34f36 7978 #define I2S_RCSR_FWF_MASK 0x20000u
ethaderu 3:78f223d34f36 7979 #define I2S_RCSR_FWF_SHIFT 17
ethaderu 3:78f223d34f36 7980 #define I2S_RCSR_FEF_MASK 0x40000u
ethaderu 3:78f223d34f36 7981 #define I2S_RCSR_FEF_SHIFT 18
ethaderu 3:78f223d34f36 7982 #define I2S_RCSR_SEF_MASK 0x80000u
ethaderu 3:78f223d34f36 7983 #define I2S_RCSR_SEF_SHIFT 19
ethaderu 3:78f223d34f36 7984 #define I2S_RCSR_WSF_MASK 0x100000u
ethaderu 3:78f223d34f36 7985 #define I2S_RCSR_WSF_SHIFT 20
ethaderu 3:78f223d34f36 7986 #define I2S_RCSR_SR_MASK 0x1000000u
ethaderu 3:78f223d34f36 7987 #define I2S_RCSR_SR_SHIFT 24
ethaderu 3:78f223d34f36 7988 #define I2S_RCSR_FR_MASK 0x2000000u
ethaderu 3:78f223d34f36 7989 #define I2S_RCSR_FR_SHIFT 25
ethaderu 3:78f223d34f36 7990 #define I2S_RCSR_BCE_MASK 0x10000000u
ethaderu 3:78f223d34f36 7991 #define I2S_RCSR_BCE_SHIFT 28
ethaderu 3:78f223d34f36 7992 #define I2S_RCSR_DBGE_MASK 0x20000000u
ethaderu 3:78f223d34f36 7993 #define I2S_RCSR_DBGE_SHIFT 29
ethaderu 3:78f223d34f36 7994 #define I2S_RCSR_STOPE_MASK 0x40000000u
ethaderu 3:78f223d34f36 7995 #define I2S_RCSR_STOPE_SHIFT 30
ethaderu 3:78f223d34f36 7996 #define I2S_RCSR_RE_MASK 0x80000000u
ethaderu 3:78f223d34f36 7997 #define I2S_RCSR_RE_SHIFT 31
ethaderu 3:78f223d34f36 7998 /* RCR1 Bit Fields */
ethaderu 3:78f223d34f36 7999 #define I2S_RCR1_RFW_MASK 0x7u
ethaderu 3:78f223d34f36 8000 #define I2S_RCR1_RFW_SHIFT 0
ethaderu 3:78f223d34f36 8001 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
ethaderu 3:78f223d34f36 8002 /* RCR2 Bit Fields */
ethaderu 3:78f223d34f36 8003 #define I2S_RCR2_DIV_MASK 0xFFu
ethaderu 3:78f223d34f36 8004 #define I2S_RCR2_DIV_SHIFT 0
ethaderu 3:78f223d34f36 8005 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
ethaderu 3:78f223d34f36 8006 #define I2S_RCR2_BCD_MASK 0x1000000u
ethaderu 3:78f223d34f36 8007 #define I2S_RCR2_BCD_SHIFT 24
ethaderu 3:78f223d34f36 8008 #define I2S_RCR2_BCP_MASK 0x2000000u
ethaderu 3:78f223d34f36 8009 #define I2S_RCR2_BCP_SHIFT 25
ethaderu 3:78f223d34f36 8010 #define I2S_RCR2_MSEL_MASK 0xC000000u
ethaderu 3:78f223d34f36 8011 #define I2S_RCR2_MSEL_SHIFT 26
ethaderu 3:78f223d34f36 8012 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
ethaderu 3:78f223d34f36 8013 #define I2S_RCR2_BCI_MASK 0x10000000u
ethaderu 3:78f223d34f36 8014 #define I2S_RCR2_BCI_SHIFT 28
ethaderu 3:78f223d34f36 8015 #define I2S_RCR2_BCS_MASK 0x20000000u
ethaderu 3:78f223d34f36 8016 #define I2S_RCR2_BCS_SHIFT 29
ethaderu 3:78f223d34f36 8017 #define I2S_RCR2_SYNC_MASK 0xC0000000u
ethaderu 3:78f223d34f36 8018 #define I2S_RCR2_SYNC_SHIFT 30
ethaderu 3:78f223d34f36 8019 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
ethaderu 3:78f223d34f36 8020 /* RCR3 Bit Fields */
ethaderu 3:78f223d34f36 8021 #define I2S_RCR3_WDFL_MASK 0x1Fu
ethaderu 3:78f223d34f36 8022 #define I2S_RCR3_WDFL_SHIFT 0
ethaderu 3:78f223d34f36 8023 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
ethaderu 3:78f223d34f36 8024 #define I2S_RCR3_RCE_MASK 0x30000u
ethaderu 3:78f223d34f36 8025 #define I2S_RCR3_RCE_SHIFT 16
ethaderu 3:78f223d34f36 8026 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
ethaderu 3:78f223d34f36 8027 /* RCR4 Bit Fields */
ethaderu 3:78f223d34f36 8028 #define I2S_RCR4_FSD_MASK 0x1u
ethaderu 3:78f223d34f36 8029 #define I2S_RCR4_FSD_SHIFT 0
ethaderu 3:78f223d34f36 8030 #define I2S_RCR4_FSP_MASK 0x2u
ethaderu 3:78f223d34f36 8031 #define I2S_RCR4_FSP_SHIFT 1
ethaderu 3:78f223d34f36 8032 #define I2S_RCR4_FSE_MASK 0x8u
ethaderu 3:78f223d34f36 8033 #define I2S_RCR4_FSE_SHIFT 3
ethaderu 3:78f223d34f36 8034 #define I2S_RCR4_MF_MASK 0x10u
ethaderu 3:78f223d34f36 8035 #define I2S_RCR4_MF_SHIFT 4
ethaderu 3:78f223d34f36 8036 #define I2S_RCR4_SYWD_MASK 0x1F00u
ethaderu 3:78f223d34f36 8037 #define I2S_RCR4_SYWD_SHIFT 8
ethaderu 3:78f223d34f36 8038 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
ethaderu 3:78f223d34f36 8039 #define I2S_RCR4_FRSZ_MASK 0x1F0000u
ethaderu 3:78f223d34f36 8040 #define I2S_RCR4_FRSZ_SHIFT 16
ethaderu 3:78f223d34f36 8041 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
ethaderu 3:78f223d34f36 8042 /* RCR5 Bit Fields */
ethaderu 3:78f223d34f36 8043 #define I2S_RCR5_FBT_MASK 0x1F00u
ethaderu 3:78f223d34f36 8044 #define I2S_RCR5_FBT_SHIFT 8
ethaderu 3:78f223d34f36 8045 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
ethaderu 3:78f223d34f36 8046 #define I2S_RCR5_W0W_MASK 0x1F0000u
ethaderu 3:78f223d34f36 8047 #define I2S_RCR5_W0W_SHIFT 16
ethaderu 3:78f223d34f36 8048 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
ethaderu 3:78f223d34f36 8049 #define I2S_RCR5_WNW_MASK 0x1F000000u
ethaderu 3:78f223d34f36 8050 #define I2S_RCR5_WNW_SHIFT 24
ethaderu 3:78f223d34f36 8051 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
ethaderu 3:78f223d34f36 8052 /* RDR Bit Fields */
ethaderu 3:78f223d34f36 8053 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 8054 #define I2S_RDR_RDR_SHIFT 0
ethaderu 3:78f223d34f36 8055 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
ethaderu 3:78f223d34f36 8056 /* RFR Bit Fields */
ethaderu 3:78f223d34f36 8057 #define I2S_RFR_RFP_MASK 0xFu
ethaderu 3:78f223d34f36 8058 #define I2S_RFR_RFP_SHIFT 0
ethaderu 3:78f223d34f36 8059 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
ethaderu 3:78f223d34f36 8060 #define I2S_RFR_WFP_MASK 0xF0000u
ethaderu 3:78f223d34f36 8061 #define I2S_RFR_WFP_SHIFT 16
ethaderu 3:78f223d34f36 8062 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
ethaderu 3:78f223d34f36 8063 /* RMR Bit Fields */
ethaderu 3:78f223d34f36 8064 #define I2S_RMR_RWM_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 8065 #define I2S_RMR_RWM_SHIFT 0
ethaderu 3:78f223d34f36 8066 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
ethaderu 3:78f223d34f36 8067 /* MCR Bit Fields */
ethaderu 3:78f223d34f36 8068 #define I2S_MCR_MICS_MASK 0x3000000u
ethaderu 3:78f223d34f36 8069 #define I2S_MCR_MICS_SHIFT 24
ethaderu 3:78f223d34f36 8070 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
ethaderu 3:78f223d34f36 8071 #define I2S_MCR_MOE_MASK 0x40000000u
ethaderu 3:78f223d34f36 8072 #define I2S_MCR_MOE_SHIFT 30
ethaderu 3:78f223d34f36 8073 #define I2S_MCR_DUF_MASK 0x80000000u
ethaderu 3:78f223d34f36 8074 #define I2S_MCR_DUF_SHIFT 31
ethaderu 3:78f223d34f36 8075 /* MDR Bit Fields */
ethaderu 3:78f223d34f36 8076 #define I2S_MDR_DIVIDE_MASK 0xFFFu
ethaderu 3:78f223d34f36 8077 #define I2S_MDR_DIVIDE_SHIFT 0
ethaderu 3:78f223d34f36 8078 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
ethaderu 3:78f223d34f36 8079 #define I2S_MDR_FRACT_MASK 0xFF000u
ethaderu 3:78f223d34f36 8080 #define I2S_MDR_FRACT_SHIFT 12
ethaderu 3:78f223d34f36 8081 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
ethaderu 3:78f223d34f36 8082
ethaderu 3:78f223d34f36 8083 /*!
ethaderu 3:78f223d34f36 8084 * @}
ethaderu 3:78f223d34f36 8085 */ /* end of group I2S_Register_Masks */
ethaderu 3:78f223d34f36 8086
ethaderu 3:78f223d34f36 8087
ethaderu 3:78f223d34f36 8088 /* I2S - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 8089 /** Peripheral I2S0 base address */
ethaderu 3:78f223d34f36 8090 #define I2S0_BASE (0x4002F000u)
ethaderu 3:78f223d34f36 8091 /** Peripheral I2S0 base pointer */
ethaderu 3:78f223d34f36 8092 #define I2S0 ((I2S_Type *)I2S0_BASE)
ethaderu 3:78f223d34f36 8093 #define I2S0_BASE_PTR (I2S0)
ethaderu 3:78f223d34f36 8094 /** Array initializer of I2S peripheral base addresses */
ethaderu 3:78f223d34f36 8095 #define I2S_BASE_ADDRS { I2S0_BASE }
ethaderu 3:78f223d34f36 8096 /** Array initializer of I2S peripheral base pointers */
ethaderu 3:78f223d34f36 8097 #define I2S_BASE_PTRS { I2S0 }
ethaderu 3:78f223d34f36 8098 /** Interrupt vectors for the I2S peripheral type */
ethaderu 3:78f223d34f36 8099 #define I2S_RX_IRQS { I2S0_Rx_IRQn }
ethaderu 3:78f223d34f36 8100 #define I2S_TX_IRQS { I2S0_Tx_IRQn }
ethaderu 3:78f223d34f36 8101
ethaderu 3:78f223d34f36 8102 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 8103 -- I2S - Register accessor macros
ethaderu 3:78f223d34f36 8104 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 8105
ethaderu 3:78f223d34f36 8106 /*!
ethaderu 3:78f223d34f36 8107 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
ethaderu 3:78f223d34f36 8108 * @{
ethaderu 3:78f223d34f36 8109 */
ethaderu 3:78f223d34f36 8110
ethaderu 3:78f223d34f36 8111
ethaderu 3:78f223d34f36 8112 /* I2S - Register instance definitions */
ethaderu 3:78f223d34f36 8113 /* I2S0 */
ethaderu 3:78f223d34f36 8114 #define I2S0_TCSR I2S_TCSR_REG(I2S0)
ethaderu 3:78f223d34f36 8115 #define I2S0_TCR1 I2S_TCR1_REG(I2S0)
ethaderu 3:78f223d34f36 8116 #define I2S0_TCR2 I2S_TCR2_REG(I2S0)
ethaderu 3:78f223d34f36 8117 #define I2S0_TCR3 I2S_TCR3_REG(I2S0)
ethaderu 3:78f223d34f36 8118 #define I2S0_TCR4 I2S_TCR4_REG(I2S0)
ethaderu 3:78f223d34f36 8119 #define I2S0_TCR5 I2S_TCR5_REG(I2S0)
ethaderu 3:78f223d34f36 8120 #define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
ethaderu 3:78f223d34f36 8121 #define I2S0_TDR1 I2S_TDR_REG(I2S0,1)
ethaderu 3:78f223d34f36 8122 #define I2S0_TFR0 I2S_TFR_REG(I2S0,0)
ethaderu 3:78f223d34f36 8123 #define I2S0_TFR1 I2S_TFR_REG(I2S0,1)
ethaderu 3:78f223d34f36 8124 #define I2S0_TMR I2S_TMR_REG(I2S0)
ethaderu 3:78f223d34f36 8125 #define I2S0_RCSR I2S_RCSR_REG(I2S0)
ethaderu 3:78f223d34f36 8126 #define I2S0_RCR1 I2S_RCR1_REG(I2S0)
ethaderu 3:78f223d34f36 8127 #define I2S0_RCR2 I2S_RCR2_REG(I2S0)
ethaderu 3:78f223d34f36 8128 #define I2S0_RCR3 I2S_RCR3_REG(I2S0)
ethaderu 3:78f223d34f36 8129 #define I2S0_RCR4 I2S_RCR4_REG(I2S0)
ethaderu 3:78f223d34f36 8130 #define I2S0_RCR5 I2S_RCR5_REG(I2S0)
ethaderu 3:78f223d34f36 8131 #define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
ethaderu 3:78f223d34f36 8132 #define I2S0_RDR1 I2S_RDR_REG(I2S0,1)
ethaderu 3:78f223d34f36 8133 #define I2S0_RFR0 I2S_RFR_REG(I2S0,0)
ethaderu 3:78f223d34f36 8134 #define I2S0_RFR1 I2S_RFR_REG(I2S0,1)
ethaderu 3:78f223d34f36 8135 #define I2S0_RMR I2S_RMR_REG(I2S0)
ethaderu 3:78f223d34f36 8136 #define I2S0_MCR I2S_MCR_REG(I2S0)
ethaderu 3:78f223d34f36 8137 #define I2S0_MDR I2S_MDR_REG(I2S0)
ethaderu 3:78f223d34f36 8138
ethaderu 3:78f223d34f36 8139 /* I2S - Register array accessors */
ethaderu 3:78f223d34f36 8140 #define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
ethaderu 3:78f223d34f36 8141 #define I2S0_TFR(index) I2S_TFR_REG(I2S0,index)
ethaderu 3:78f223d34f36 8142 #define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
ethaderu 3:78f223d34f36 8143 #define I2S0_RFR(index) I2S_RFR_REG(I2S0,index)
ethaderu 3:78f223d34f36 8144
ethaderu 3:78f223d34f36 8145 /*!
ethaderu 3:78f223d34f36 8146 * @}
ethaderu 3:78f223d34f36 8147 */ /* end of group I2S_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 8148
ethaderu 3:78f223d34f36 8149
ethaderu 3:78f223d34f36 8150 /*!
ethaderu 3:78f223d34f36 8151 * @}
ethaderu 3:78f223d34f36 8152 */ /* end of group I2S_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 8153
ethaderu 3:78f223d34f36 8154
ethaderu 3:78f223d34f36 8155 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 8156 -- LLWU Peripheral Access Layer
ethaderu 3:78f223d34f36 8157 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 8158
ethaderu 3:78f223d34f36 8159 /*!
ethaderu 3:78f223d34f36 8160 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
ethaderu 3:78f223d34f36 8161 * @{
ethaderu 3:78f223d34f36 8162 */
ethaderu 3:78f223d34f36 8163
ethaderu 3:78f223d34f36 8164 /** LLWU - Register Layout Typedef */
ethaderu 3:78f223d34f36 8165 typedef struct {
ethaderu 3:78f223d34f36 8166 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
ethaderu 3:78f223d34f36 8167 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
ethaderu 3:78f223d34f36 8168 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
ethaderu 3:78f223d34f36 8169 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
ethaderu 3:78f223d34f36 8170 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
ethaderu 3:78f223d34f36 8171 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
ethaderu 3:78f223d34f36 8172 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
ethaderu 3:78f223d34f36 8173 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
ethaderu 3:78f223d34f36 8174 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
ethaderu 3:78f223d34f36 8175 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
ethaderu 3:78f223d34f36 8176 __IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */
ethaderu 3:78f223d34f36 8177 } LLWU_Type, *LLWU_MemMapPtr;
ethaderu 3:78f223d34f36 8178
ethaderu 3:78f223d34f36 8179 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 8180 -- LLWU - Register accessor macros
ethaderu 3:78f223d34f36 8181 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 8182
ethaderu 3:78f223d34f36 8183 /*!
ethaderu 3:78f223d34f36 8184 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
ethaderu 3:78f223d34f36 8185 * @{
ethaderu 3:78f223d34f36 8186 */
ethaderu 3:78f223d34f36 8187
ethaderu 3:78f223d34f36 8188
ethaderu 3:78f223d34f36 8189 /* LLWU - Register accessors */
ethaderu 3:78f223d34f36 8190 #define LLWU_PE1_REG(base) ((base)->PE1)
ethaderu 3:78f223d34f36 8191 #define LLWU_PE2_REG(base) ((base)->PE2)
ethaderu 3:78f223d34f36 8192 #define LLWU_PE3_REG(base) ((base)->PE3)
ethaderu 3:78f223d34f36 8193 #define LLWU_PE4_REG(base) ((base)->PE4)
ethaderu 3:78f223d34f36 8194 #define LLWU_ME_REG(base) ((base)->ME)
ethaderu 3:78f223d34f36 8195 #define LLWU_F1_REG(base) ((base)->F1)
ethaderu 3:78f223d34f36 8196 #define LLWU_F2_REG(base) ((base)->F2)
ethaderu 3:78f223d34f36 8197 #define LLWU_F3_REG(base) ((base)->F3)
ethaderu 3:78f223d34f36 8198 #define LLWU_FILT1_REG(base) ((base)->FILT1)
ethaderu 3:78f223d34f36 8199 #define LLWU_FILT2_REG(base) ((base)->FILT2)
ethaderu 3:78f223d34f36 8200 #define LLWU_RST_REG(base) ((base)->RST)
ethaderu 3:78f223d34f36 8201
ethaderu 3:78f223d34f36 8202 /*!
ethaderu 3:78f223d34f36 8203 * @}
ethaderu 3:78f223d34f36 8204 */ /* end of group LLWU_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 8205
ethaderu 3:78f223d34f36 8206
ethaderu 3:78f223d34f36 8207 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 8208 -- LLWU Register Masks
ethaderu 3:78f223d34f36 8209 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 8210
ethaderu 3:78f223d34f36 8211 /*!
ethaderu 3:78f223d34f36 8212 * @addtogroup LLWU_Register_Masks LLWU Register Masks
ethaderu 3:78f223d34f36 8213 * @{
ethaderu 3:78f223d34f36 8214 */
ethaderu 3:78f223d34f36 8215
ethaderu 3:78f223d34f36 8216 /* PE1 Bit Fields */
ethaderu 3:78f223d34f36 8217 #define LLWU_PE1_WUPE0_MASK 0x3u
ethaderu 3:78f223d34f36 8218 #define LLWU_PE1_WUPE0_SHIFT 0
ethaderu 3:78f223d34f36 8219 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
ethaderu 3:78f223d34f36 8220 #define LLWU_PE1_WUPE1_MASK 0xCu
ethaderu 3:78f223d34f36 8221 #define LLWU_PE1_WUPE1_SHIFT 2
ethaderu 3:78f223d34f36 8222 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
ethaderu 3:78f223d34f36 8223 #define LLWU_PE1_WUPE2_MASK 0x30u
ethaderu 3:78f223d34f36 8224 #define LLWU_PE1_WUPE2_SHIFT 4
ethaderu 3:78f223d34f36 8225 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
ethaderu 3:78f223d34f36 8226 #define LLWU_PE1_WUPE3_MASK 0xC0u
ethaderu 3:78f223d34f36 8227 #define LLWU_PE1_WUPE3_SHIFT 6
ethaderu 3:78f223d34f36 8228 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
ethaderu 3:78f223d34f36 8229 /* PE2 Bit Fields */
ethaderu 3:78f223d34f36 8230 #define LLWU_PE2_WUPE4_MASK 0x3u
ethaderu 3:78f223d34f36 8231 #define LLWU_PE2_WUPE4_SHIFT 0
ethaderu 3:78f223d34f36 8232 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
ethaderu 3:78f223d34f36 8233 #define LLWU_PE2_WUPE5_MASK 0xCu
ethaderu 3:78f223d34f36 8234 #define LLWU_PE2_WUPE5_SHIFT 2
ethaderu 3:78f223d34f36 8235 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
ethaderu 3:78f223d34f36 8236 #define LLWU_PE2_WUPE6_MASK 0x30u
ethaderu 3:78f223d34f36 8237 #define LLWU_PE2_WUPE6_SHIFT 4
ethaderu 3:78f223d34f36 8238 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
ethaderu 3:78f223d34f36 8239 #define LLWU_PE2_WUPE7_MASK 0xC0u
ethaderu 3:78f223d34f36 8240 #define LLWU_PE2_WUPE7_SHIFT 6
ethaderu 3:78f223d34f36 8241 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
ethaderu 3:78f223d34f36 8242 /* PE3 Bit Fields */
ethaderu 3:78f223d34f36 8243 #define LLWU_PE3_WUPE8_MASK 0x3u
ethaderu 3:78f223d34f36 8244 #define LLWU_PE3_WUPE8_SHIFT 0
ethaderu 3:78f223d34f36 8245 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
ethaderu 3:78f223d34f36 8246 #define LLWU_PE3_WUPE9_MASK 0xCu
ethaderu 3:78f223d34f36 8247 #define LLWU_PE3_WUPE9_SHIFT 2
ethaderu 3:78f223d34f36 8248 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
ethaderu 3:78f223d34f36 8249 #define LLWU_PE3_WUPE10_MASK 0x30u
ethaderu 3:78f223d34f36 8250 #define LLWU_PE3_WUPE10_SHIFT 4
ethaderu 3:78f223d34f36 8251 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
ethaderu 3:78f223d34f36 8252 #define LLWU_PE3_WUPE11_MASK 0xC0u
ethaderu 3:78f223d34f36 8253 #define LLWU_PE3_WUPE11_SHIFT 6
ethaderu 3:78f223d34f36 8254 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
ethaderu 3:78f223d34f36 8255 /* PE4 Bit Fields */
ethaderu 3:78f223d34f36 8256 #define LLWU_PE4_WUPE12_MASK 0x3u
ethaderu 3:78f223d34f36 8257 #define LLWU_PE4_WUPE12_SHIFT 0
ethaderu 3:78f223d34f36 8258 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
ethaderu 3:78f223d34f36 8259 #define LLWU_PE4_WUPE13_MASK 0xCu
ethaderu 3:78f223d34f36 8260 #define LLWU_PE4_WUPE13_SHIFT 2
ethaderu 3:78f223d34f36 8261 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
ethaderu 3:78f223d34f36 8262 #define LLWU_PE4_WUPE14_MASK 0x30u
ethaderu 3:78f223d34f36 8263 #define LLWU_PE4_WUPE14_SHIFT 4
ethaderu 3:78f223d34f36 8264 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
ethaderu 3:78f223d34f36 8265 #define LLWU_PE4_WUPE15_MASK 0xC0u
ethaderu 3:78f223d34f36 8266 #define LLWU_PE4_WUPE15_SHIFT 6
ethaderu 3:78f223d34f36 8267 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
ethaderu 3:78f223d34f36 8268 /* ME Bit Fields */
ethaderu 3:78f223d34f36 8269 #define LLWU_ME_WUME0_MASK 0x1u
ethaderu 3:78f223d34f36 8270 #define LLWU_ME_WUME0_SHIFT 0
ethaderu 3:78f223d34f36 8271 #define LLWU_ME_WUME1_MASK 0x2u
ethaderu 3:78f223d34f36 8272 #define LLWU_ME_WUME1_SHIFT 1
ethaderu 3:78f223d34f36 8273 #define LLWU_ME_WUME2_MASK 0x4u
ethaderu 3:78f223d34f36 8274 #define LLWU_ME_WUME2_SHIFT 2
ethaderu 3:78f223d34f36 8275 #define LLWU_ME_WUME3_MASK 0x8u
ethaderu 3:78f223d34f36 8276 #define LLWU_ME_WUME3_SHIFT 3
ethaderu 3:78f223d34f36 8277 #define LLWU_ME_WUME4_MASK 0x10u
ethaderu 3:78f223d34f36 8278 #define LLWU_ME_WUME4_SHIFT 4
ethaderu 3:78f223d34f36 8279 #define LLWU_ME_WUME5_MASK 0x20u
ethaderu 3:78f223d34f36 8280 #define LLWU_ME_WUME5_SHIFT 5
ethaderu 3:78f223d34f36 8281 #define LLWU_ME_WUME6_MASK 0x40u
ethaderu 3:78f223d34f36 8282 #define LLWU_ME_WUME6_SHIFT 6
ethaderu 3:78f223d34f36 8283 #define LLWU_ME_WUME7_MASK 0x80u
ethaderu 3:78f223d34f36 8284 #define LLWU_ME_WUME7_SHIFT 7
ethaderu 3:78f223d34f36 8285 /* F1 Bit Fields */
ethaderu 3:78f223d34f36 8286 #define LLWU_F1_WUF0_MASK 0x1u
ethaderu 3:78f223d34f36 8287 #define LLWU_F1_WUF0_SHIFT 0
ethaderu 3:78f223d34f36 8288 #define LLWU_F1_WUF1_MASK 0x2u
ethaderu 3:78f223d34f36 8289 #define LLWU_F1_WUF1_SHIFT 1
ethaderu 3:78f223d34f36 8290 #define LLWU_F1_WUF2_MASK 0x4u
ethaderu 3:78f223d34f36 8291 #define LLWU_F1_WUF2_SHIFT 2
ethaderu 3:78f223d34f36 8292 #define LLWU_F1_WUF3_MASK 0x8u
ethaderu 3:78f223d34f36 8293 #define LLWU_F1_WUF3_SHIFT 3
ethaderu 3:78f223d34f36 8294 #define LLWU_F1_WUF4_MASK 0x10u
ethaderu 3:78f223d34f36 8295 #define LLWU_F1_WUF4_SHIFT 4
ethaderu 3:78f223d34f36 8296 #define LLWU_F1_WUF5_MASK 0x20u
ethaderu 3:78f223d34f36 8297 #define LLWU_F1_WUF5_SHIFT 5
ethaderu 3:78f223d34f36 8298 #define LLWU_F1_WUF6_MASK 0x40u
ethaderu 3:78f223d34f36 8299 #define LLWU_F1_WUF6_SHIFT 6
ethaderu 3:78f223d34f36 8300 #define LLWU_F1_WUF7_MASK 0x80u
ethaderu 3:78f223d34f36 8301 #define LLWU_F1_WUF7_SHIFT 7
ethaderu 3:78f223d34f36 8302 /* F2 Bit Fields */
ethaderu 3:78f223d34f36 8303 #define LLWU_F2_WUF8_MASK 0x1u
ethaderu 3:78f223d34f36 8304 #define LLWU_F2_WUF8_SHIFT 0
ethaderu 3:78f223d34f36 8305 #define LLWU_F2_WUF9_MASK 0x2u
ethaderu 3:78f223d34f36 8306 #define LLWU_F2_WUF9_SHIFT 1
ethaderu 3:78f223d34f36 8307 #define LLWU_F2_WUF10_MASK 0x4u
ethaderu 3:78f223d34f36 8308 #define LLWU_F2_WUF10_SHIFT 2
ethaderu 3:78f223d34f36 8309 #define LLWU_F2_WUF11_MASK 0x8u
ethaderu 3:78f223d34f36 8310 #define LLWU_F2_WUF11_SHIFT 3
ethaderu 3:78f223d34f36 8311 #define LLWU_F2_WUF12_MASK 0x10u
ethaderu 3:78f223d34f36 8312 #define LLWU_F2_WUF12_SHIFT 4
ethaderu 3:78f223d34f36 8313 #define LLWU_F2_WUF13_MASK 0x20u
ethaderu 3:78f223d34f36 8314 #define LLWU_F2_WUF13_SHIFT 5
ethaderu 3:78f223d34f36 8315 #define LLWU_F2_WUF14_MASK 0x40u
ethaderu 3:78f223d34f36 8316 #define LLWU_F2_WUF14_SHIFT 6
ethaderu 3:78f223d34f36 8317 #define LLWU_F2_WUF15_MASK 0x80u
ethaderu 3:78f223d34f36 8318 #define LLWU_F2_WUF15_SHIFT 7
ethaderu 3:78f223d34f36 8319 /* F3 Bit Fields */
ethaderu 3:78f223d34f36 8320 #define LLWU_F3_MWUF0_MASK 0x1u
ethaderu 3:78f223d34f36 8321 #define LLWU_F3_MWUF0_SHIFT 0
ethaderu 3:78f223d34f36 8322 #define LLWU_F3_MWUF1_MASK 0x2u
ethaderu 3:78f223d34f36 8323 #define LLWU_F3_MWUF1_SHIFT 1
ethaderu 3:78f223d34f36 8324 #define LLWU_F3_MWUF2_MASK 0x4u
ethaderu 3:78f223d34f36 8325 #define LLWU_F3_MWUF2_SHIFT 2
ethaderu 3:78f223d34f36 8326 #define LLWU_F3_MWUF3_MASK 0x8u
ethaderu 3:78f223d34f36 8327 #define LLWU_F3_MWUF3_SHIFT 3
ethaderu 3:78f223d34f36 8328 #define LLWU_F3_MWUF4_MASK 0x10u
ethaderu 3:78f223d34f36 8329 #define LLWU_F3_MWUF4_SHIFT 4
ethaderu 3:78f223d34f36 8330 #define LLWU_F3_MWUF5_MASK 0x20u
ethaderu 3:78f223d34f36 8331 #define LLWU_F3_MWUF5_SHIFT 5
ethaderu 3:78f223d34f36 8332 #define LLWU_F3_MWUF6_MASK 0x40u
ethaderu 3:78f223d34f36 8333 #define LLWU_F3_MWUF6_SHIFT 6
ethaderu 3:78f223d34f36 8334 #define LLWU_F3_MWUF7_MASK 0x80u
ethaderu 3:78f223d34f36 8335 #define LLWU_F3_MWUF7_SHIFT 7
ethaderu 3:78f223d34f36 8336 /* FILT1 Bit Fields */
ethaderu 3:78f223d34f36 8337 #define LLWU_FILT1_FILTSEL_MASK 0xFu
ethaderu 3:78f223d34f36 8338 #define LLWU_FILT1_FILTSEL_SHIFT 0
ethaderu 3:78f223d34f36 8339 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
ethaderu 3:78f223d34f36 8340 #define LLWU_FILT1_FILTE_MASK 0x60u
ethaderu 3:78f223d34f36 8341 #define LLWU_FILT1_FILTE_SHIFT 5
ethaderu 3:78f223d34f36 8342 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
ethaderu 3:78f223d34f36 8343 #define LLWU_FILT1_FILTF_MASK 0x80u
ethaderu 3:78f223d34f36 8344 #define LLWU_FILT1_FILTF_SHIFT 7
ethaderu 3:78f223d34f36 8345 /* FILT2 Bit Fields */
ethaderu 3:78f223d34f36 8346 #define LLWU_FILT2_FILTSEL_MASK 0xFu
ethaderu 3:78f223d34f36 8347 #define LLWU_FILT2_FILTSEL_SHIFT 0
ethaderu 3:78f223d34f36 8348 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
ethaderu 3:78f223d34f36 8349 #define LLWU_FILT2_FILTE_MASK 0x60u
ethaderu 3:78f223d34f36 8350 #define LLWU_FILT2_FILTE_SHIFT 5
ethaderu 3:78f223d34f36 8351 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
ethaderu 3:78f223d34f36 8352 #define LLWU_FILT2_FILTF_MASK 0x80u
ethaderu 3:78f223d34f36 8353 #define LLWU_FILT2_FILTF_SHIFT 7
ethaderu 3:78f223d34f36 8354 /* RST Bit Fields */
ethaderu 3:78f223d34f36 8355 #define LLWU_RST_RSTFILT_MASK 0x1u
ethaderu 3:78f223d34f36 8356 #define LLWU_RST_RSTFILT_SHIFT 0
ethaderu 3:78f223d34f36 8357 #define LLWU_RST_LLRSTE_MASK 0x2u
ethaderu 3:78f223d34f36 8358 #define LLWU_RST_LLRSTE_SHIFT 1
ethaderu 3:78f223d34f36 8359
ethaderu 3:78f223d34f36 8360 /*!
ethaderu 3:78f223d34f36 8361 * @}
ethaderu 3:78f223d34f36 8362 */ /* end of group LLWU_Register_Masks */
ethaderu 3:78f223d34f36 8363
ethaderu 3:78f223d34f36 8364
ethaderu 3:78f223d34f36 8365 /* LLWU - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 8366 /** Peripheral LLWU base address */
ethaderu 3:78f223d34f36 8367 #define LLWU_BASE (0x4007C000u)
ethaderu 3:78f223d34f36 8368 /** Peripheral LLWU base pointer */
ethaderu 3:78f223d34f36 8369 #define LLWU ((LLWU_Type *)LLWU_BASE)
ethaderu 3:78f223d34f36 8370 #define LLWU_BASE_PTR (LLWU)
ethaderu 3:78f223d34f36 8371 /** Array initializer of LLWU peripheral base addresses */
ethaderu 3:78f223d34f36 8372 #define LLWU_BASE_ADDRS { LLWU_BASE }
ethaderu 3:78f223d34f36 8373 /** Array initializer of LLWU peripheral base pointers */
ethaderu 3:78f223d34f36 8374 #define LLWU_BASE_PTRS { LLWU }
ethaderu 3:78f223d34f36 8375 /** Interrupt vectors for the LLWU peripheral type */
ethaderu 3:78f223d34f36 8376 #define LLWU_IRQS { LLW_IRQn }
ethaderu 3:78f223d34f36 8377
ethaderu 3:78f223d34f36 8378 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 8379 -- LLWU - Register accessor macros
ethaderu 3:78f223d34f36 8380 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 8381
ethaderu 3:78f223d34f36 8382 /*!
ethaderu 3:78f223d34f36 8383 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
ethaderu 3:78f223d34f36 8384 * @{
ethaderu 3:78f223d34f36 8385 */
ethaderu 3:78f223d34f36 8386
ethaderu 3:78f223d34f36 8387
ethaderu 3:78f223d34f36 8388 /* LLWU - Register instance definitions */
ethaderu 3:78f223d34f36 8389 /* LLWU */
ethaderu 3:78f223d34f36 8390 #define LLWU_PE1 LLWU_PE1_REG(LLWU)
ethaderu 3:78f223d34f36 8391 #define LLWU_PE2 LLWU_PE2_REG(LLWU)
ethaderu 3:78f223d34f36 8392 #define LLWU_PE3 LLWU_PE3_REG(LLWU)
ethaderu 3:78f223d34f36 8393 #define LLWU_PE4 LLWU_PE4_REG(LLWU)
ethaderu 3:78f223d34f36 8394 #define LLWU_ME LLWU_ME_REG(LLWU)
ethaderu 3:78f223d34f36 8395 #define LLWU_F1 LLWU_F1_REG(LLWU)
ethaderu 3:78f223d34f36 8396 #define LLWU_F2 LLWU_F2_REG(LLWU)
ethaderu 3:78f223d34f36 8397 #define LLWU_F3 LLWU_F3_REG(LLWU)
ethaderu 3:78f223d34f36 8398 #define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
ethaderu 3:78f223d34f36 8399 #define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
ethaderu 3:78f223d34f36 8400 #define LLWU_RST LLWU_RST_REG(LLWU)
ethaderu 3:78f223d34f36 8401
ethaderu 3:78f223d34f36 8402 /*!
ethaderu 3:78f223d34f36 8403 * @}
ethaderu 3:78f223d34f36 8404 */ /* end of group LLWU_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 8405
ethaderu 3:78f223d34f36 8406
ethaderu 3:78f223d34f36 8407 /*!
ethaderu 3:78f223d34f36 8408 * @}
ethaderu 3:78f223d34f36 8409 */ /* end of group LLWU_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 8410
ethaderu 3:78f223d34f36 8411
ethaderu 3:78f223d34f36 8412 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 8413 -- LPTMR Peripheral Access Layer
ethaderu 3:78f223d34f36 8414 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 8415
ethaderu 3:78f223d34f36 8416 /*!
ethaderu 3:78f223d34f36 8417 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
ethaderu 3:78f223d34f36 8418 * @{
ethaderu 3:78f223d34f36 8419 */
ethaderu 3:78f223d34f36 8420
ethaderu 3:78f223d34f36 8421 /** LPTMR - Register Layout Typedef */
ethaderu 3:78f223d34f36 8422 typedef struct {
ethaderu 3:78f223d34f36 8423 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
ethaderu 3:78f223d34f36 8424 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
ethaderu 3:78f223d34f36 8425 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
ethaderu 3:78f223d34f36 8426 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
ethaderu 3:78f223d34f36 8427 } LPTMR_Type, *LPTMR_MemMapPtr;
ethaderu 3:78f223d34f36 8428
ethaderu 3:78f223d34f36 8429 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 8430 -- LPTMR - Register accessor macros
ethaderu 3:78f223d34f36 8431 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 8432
ethaderu 3:78f223d34f36 8433 /*!
ethaderu 3:78f223d34f36 8434 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
ethaderu 3:78f223d34f36 8435 * @{
ethaderu 3:78f223d34f36 8436 */
ethaderu 3:78f223d34f36 8437
ethaderu 3:78f223d34f36 8438
ethaderu 3:78f223d34f36 8439 /* LPTMR - Register accessors */
ethaderu 3:78f223d34f36 8440 #define LPTMR_CSR_REG(base) ((base)->CSR)
ethaderu 3:78f223d34f36 8441 #define LPTMR_PSR_REG(base) ((base)->PSR)
ethaderu 3:78f223d34f36 8442 #define LPTMR_CMR_REG(base) ((base)->CMR)
ethaderu 3:78f223d34f36 8443 #define LPTMR_CNR_REG(base) ((base)->CNR)
ethaderu 3:78f223d34f36 8444
ethaderu 3:78f223d34f36 8445 /*!
ethaderu 3:78f223d34f36 8446 * @}
ethaderu 3:78f223d34f36 8447 */ /* end of group LPTMR_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 8448
ethaderu 3:78f223d34f36 8449
ethaderu 3:78f223d34f36 8450 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 8451 -- LPTMR Register Masks
ethaderu 3:78f223d34f36 8452 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 8453
ethaderu 3:78f223d34f36 8454 /*!
ethaderu 3:78f223d34f36 8455 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
ethaderu 3:78f223d34f36 8456 * @{
ethaderu 3:78f223d34f36 8457 */
ethaderu 3:78f223d34f36 8458
ethaderu 3:78f223d34f36 8459 /* CSR Bit Fields */
ethaderu 3:78f223d34f36 8460 #define LPTMR_CSR_TEN_MASK 0x1u
ethaderu 3:78f223d34f36 8461 #define LPTMR_CSR_TEN_SHIFT 0
ethaderu 3:78f223d34f36 8462 #define LPTMR_CSR_TMS_MASK 0x2u
ethaderu 3:78f223d34f36 8463 #define LPTMR_CSR_TMS_SHIFT 1
ethaderu 3:78f223d34f36 8464 #define LPTMR_CSR_TFC_MASK 0x4u
ethaderu 3:78f223d34f36 8465 #define LPTMR_CSR_TFC_SHIFT 2
ethaderu 3:78f223d34f36 8466 #define LPTMR_CSR_TPP_MASK 0x8u
ethaderu 3:78f223d34f36 8467 #define LPTMR_CSR_TPP_SHIFT 3
ethaderu 3:78f223d34f36 8468 #define LPTMR_CSR_TPS_MASK 0x30u
ethaderu 3:78f223d34f36 8469 #define LPTMR_CSR_TPS_SHIFT 4
ethaderu 3:78f223d34f36 8470 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
ethaderu 3:78f223d34f36 8471 #define LPTMR_CSR_TIE_MASK 0x40u
ethaderu 3:78f223d34f36 8472 #define LPTMR_CSR_TIE_SHIFT 6
ethaderu 3:78f223d34f36 8473 #define LPTMR_CSR_TCF_MASK 0x80u
ethaderu 3:78f223d34f36 8474 #define LPTMR_CSR_TCF_SHIFT 7
ethaderu 3:78f223d34f36 8475 /* PSR Bit Fields */
ethaderu 3:78f223d34f36 8476 #define LPTMR_PSR_PCS_MASK 0x3u
ethaderu 3:78f223d34f36 8477 #define LPTMR_PSR_PCS_SHIFT 0
ethaderu 3:78f223d34f36 8478 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
ethaderu 3:78f223d34f36 8479 #define LPTMR_PSR_PBYP_MASK 0x4u
ethaderu 3:78f223d34f36 8480 #define LPTMR_PSR_PBYP_SHIFT 2
ethaderu 3:78f223d34f36 8481 #define LPTMR_PSR_PRESCALE_MASK 0x78u
ethaderu 3:78f223d34f36 8482 #define LPTMR_PSR_PRESCALE_SHIFT 3
ethaderu 3:78f223d34f36 8483 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
ethaderu 3:78f223d34f36 8484 /* CMR Bit Fields */
ethaderu 3:78f223d34f36 8485 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
ethaderu 3:78f223d34f36 8486 #define LPTMR_CMR_COMPARE_SHIFT 0
ethaderu 3:78f223d34f36 8487 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
ethaderu 3:78f223d34f36 8488 /* CNR Bit Fields */
ethaderu 3:78f223d34f36 8489 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
ethaderu 3:78f223d34f36 8490 #define LPTMR_CNR_COUNTER_SHIFT 0
ethaderu 3:78f223d34f36 8491 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
ethaderu 3:78f223d34f36 8492
ethaderu 3:78f223d34f36 8493 /*!
ethaderu 3:78f223d34f36 8494 * @}
ethaderu 3:78f223d34f36 8495 */ /* end of group LPTMR_Register_Masks */
ethaderu 3:78f223d34f36 8496
ethaderu 3:78f223d34f36 8497
ethaderu 3:78f223d34f36 8498 /* LPTMR - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 8499 /** Peripheral LPTMR0 base address */
ethaderu 3:78f223d34f36 8500 #define LPTMR0_BASE (0x40040000u)
ethaderu 3:78f223d34f36 8501 /** Peripheral LPTMR0 base pointer */
ethaderu 3:78f223d34f36 8502 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
ethaderu 3:78f223d34f36 8503 #define LPTMR0_BASE_PTR (LPTMR0)
ethaderu 3:78f223d34f36 8504 /** Array initializer of LPTMR peripheral base addresses */
ethaderu 3:78f223d34f36 8505 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
ethaderu 3:78f223d34f36 8506 /** Array initializer of LPTMR peripheral base pointers */
ethaderu 3:78f223d34f36 8507 #define LPTMR_BASE_PTRS { LPTMR0 }
ethaderu 3:78f223d34f36 8508 /** Interrupt vectors for the LPTMR peripheral type */
ethaderu 3:78f223d34f36 8509 #define LPTMR_IRQS { LPTimer_IRQn }
ethaderu 3:78f223d34f36 8510
ethaderu 3:78f223d34f36 8511 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 8512 -- LPTMR - Register accessor macros
ethaderu 3:78f223d34f36 8513 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 8514
ethaderu 3:78f223d34f36 8515 /*!
ethaderu 3:78f223d34f36 8516 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
ethaderu 3:78f223d34f36 8517 * @{
ethaderu 3:78f223d34f36 8518 */
ethaderu 3:78f223d34f36 8519
ethaderu 3:78f223d34f36 8520
ethaderu 3:78f223d34f36 8521 /* LPTMR - Register instance definitions */
ethaderu 3:78f223d34f36 8522 /* LPTMR0 */
ethaderu 3:78f223d34f36 8523 #define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
ethaderu 3:78f223d34f36 8524 #define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
ethaderu 3:78f223d34f36 8525 #define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
ethaderu 3:78f223d34f36 8526 #define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
ethaderu 3:78f223d34f36 8527
ethaderu 3:78f223d34f36 8528 /*!
ethaderu 3:78f223d34f36 8529 * @}
ethaderu 3:78f223d34f36 8530 */ /* end of group LPTMR_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 8531
ethaderu 3:78f223d34f36 8532
ethaderu 3:78f223d34f36 8533 /*!
ethaderu 3:78f223d34f36 8534 * @}
ethaderu 3:78f223d34f36 8535 */ /* end of group LPTMR_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 8536
ethaderu 3:78f223d34f36 8537
ethaderu 3:78f223d34f36 8538 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 8539 -- MCG Peripheral Access Layer
ethaderu 3:78f223d34f36 8540 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 8541
ethaderu 3:78f223d34f36 8542 /*!
ethaderu 3:78f223d34f36 8543 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
ethaderu 3:78f223d34f36 8544 * @{
ethaderu 3:78f223d34f36 8545 */
ethaderu 3:78f223d34f36 8546
ethaderu 3:78f223d34f36 8547 /** MCG - Register Layout Typedef */
ethaderu 3:78f223d34f36 8548 typedef struct {
ethaderu 3:78f223d34f36 8549 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
ethaderu 3:78f223d34f36 8550 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
ethaderu 3:78f223d34f36 8551 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
ethaderu 3:78f223d34f36 8552 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
ethaderu 3:78f223d34f36 8553 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
ethaderu 3:78f223d34f36 8554 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
ethaderu 3:78f223d34f36 8555 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
ethaderu 3:78f223d34f36 8556 uint8_t RESERVED_0[1];
ethaderu 3:78f223d34f36 8557 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
ethaderu 3:78f223d34f36 8558 uint8_t RESERVED_1[1];
ethaderu 3:78f223d34f36 8559 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
ethaderu 3:78f223d34f36 8560 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
ethaderu 3:78f223d34f36 8561 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
ethaderu 3:78f223d34f36 8562 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
ethaderu 3:78f223d34f36 8563 } MCG_Type, *MCG_MemMapPtr;
ethaderu 3:78f223d34f36 8564
ethaderu 3:78f223d34f36 8565 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 8566 -- MCG - Register accessor macros
ethaderu 3:78f223d34f36 8567 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 8568
ethaderu 3:78f223d34f36 8569 /*!
ethaderu 3:78f223d34f36 8570 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
ethaderu 3:78f223d34f36 8571 * @{
ethaderu 3:78f223d34f36 8572 */
ethaderu 3:78f223d34f36 8573
ethaderu 3:78f223d34f36 8574
ethaderu 3:78f223d34f36 8575 /* MCG - Register accessors */
ethaderu 3:78f223d34f36 8576 #define MCG_C1_REG(base) ((base)->C1)
ethaderu 3:78f223d34f36 8577 #define MCG_C2_REG(base) ((base)->C2)
ethaderu 3:78f223d34f36 8578 #define MCG_C3_REG(base) ((base)->C3)
ethaderu 3:78f223d34f36 8579 #define MCG_C4_REG(base) ((base)->C4)
ethaderu 3:78f223d34f36 8580 #define MCG_C5_REG(base) ((base)->C5)
ethaderu 3:78f223d34f36 8581 #define MCG_C6_REG(base) ((base)->C6)
ethaderu 3:78f223d34f36 8582 #define MCG_S_REG(base) ((base)->S)
ethaderu 3:78f223d34f36 8583 #define MCG_SC_REG(base) ((base)->SC)
ethaderu 3:78f223d34f36 8584 #define MCG_ATCVH_REG(base) ((base)->ATCVH)
ethaderu 3:78f223d34f36 8585 #define MCG_ATCVL_REG(base) ((base)->ATCVL)
ethaderu 3:78f223d34f36 8586 #define MCG_C7_REG(base) ((base)->C7)
ethaderu 3:78f223d34f36 8587 #define MCG_C8_REG(base) ((base)->C8)
ethaderu 3:78f223d34f36 8588
ethaderu 3:78f223d34f36 8589 /*!
ethaderu 3:78f223d34f36 8590 * @}
ethaderu 3:78f223d34f36 8591 */ /* end of group MCG_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 8592
ethaderu 3:78f223d34f36 8593
ethaderu 3:78f223d34f36 8594 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 8595 -- MCG Register Masks
ethaderu 3:78f223d34f36 8596 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 8597
ethaderu 3:78f223d34f36 8598 /*!
ethaderu 3:78f223d34f36 8599 * @addtogroup MCG_Register_Masks MCG Register Masks
ethaderu 3:78f223d34f36 8600 * @{
ethaderu 3:78f223d34f36 8601 */
ethaderu 3:78f223d34f36 8602
ethaderu 3:78f223d34f36 8603 /* C1 Bit Fields */
ethaderu 3:78f223d34f36 8604 #define MCG_C1_IREFSTEN_MASK 0x1u
ethaderu 3:78f223d34f36 8605 #define MCG_C1_IREFSTEN_SHIFT 0
ethaderu 3:78f223d34f36 8606 #define MCG_C1_IRCLKEN_MASK 0x2u
ethaderu 3:78f223d34f36 8607 #define MCG_C1_IRCLKEN_SHIFT 1
ethaderu 3:78f223d34f36 8608 #define MCG_C1_IREFS_MASK 0x4u
ethaderu 3:78f223d34f36 8609 #define MCG_C1_IREFS_SHIFT 2
ethaderu 3:78f223d34f36 8610 #define MCG_C1_FRDIV_MASK 0x38u
ethaderu 3:78f223d34f36 8611 #define MCG_C1_FRDIV_SHIFT 3
ethaderu 3:78f223d34f36 8612 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
ethaderu 3:78f223d34f36 8613 #define MCG_C1_CLKS_MASK 0xC0u
ethaderu 3:78f223d34f36 8614 #define MCG_C1_CLKS_SHIFT 6
ethaderu 3:78f223d34f36 8615 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
ethaderu 3:78f223d34f36 8616 /* C2 Bit Fields */
ethaderu 3:78f223d34f36 8617 #define MCG_C2_IRCS_MASK 0x1u
ethaderu 3:78f223d34f36 8618 #define MCG_C2_IRCS_SHIFT 0
ethaderu 3:78f223d34f36 8619 #define MCG_C2_LP_MASK 0x2u
ethaderu 3:78f223d34f36 8620 #define MCG_C2_LP_SHIFT 1
ethaderu 3:78f223d34f36 8621 #define MCG_C2_EREFS_MASK 0x4u
ethaderu 3:78f223d34f36 8622 #define MCG_C2_EREFS_SHIFT 2
ethaderu 3:78f223d34f36 8623 #define MCG_C2_HGO_MASK 0x8u
ethaderu 3:78f223d34f36 8624 #define MCG_C2_HGO_SHIFT 3
ethaderu 3:78f223d34f36 8625 #define MCG_C2_RANGE_MASK 0x30u
ethaderu 3:78f223d34f36 8626 #define MCG_C2_RANGE_SHIFT 4
ethaderu 3:78f223d34f36 8627 #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
ethaderu 3:78f223d34f36 8628 #define MCG_C2_FCFTRIM_MASK 0x40u
ethaderu 3:78f223d34f36 8629 #define MCG_C2_FCFTRIM_SHIFT 6
ethaderu 3:78f223d34f36 8630 #define MCG_C2_LOCRE0_MASK 0x80u
ethaderu 3:78f223d34f36 8631 #define MCG_C2_LOCRE0_SHIFT 7
ethaderu 3:78f223d34f36 8632 /* C3 Bit Fields */
ethaderu 3:78f223d34f36 8633 #define MCG_C3_SCTRIM_MASK 0xFFu
ethaderu 3:78f223d34f36 8634 #define MCG_C3_SCTRIM_SHIFT 0
ethaderu 3:78f223d34f36 8635 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
ethaderu 3:78f223d34f36 8636 /* C4 Bit Fields */
ethaderu 3:78f223d34f36 8637 #define MCG_C4_SCFTRIM_MASK 0x1u
ethaderu 3:78f223d34f36 8638 #define MCG_C4_SCFTRIM_SHIFT 0
ethaderu 3:78f223d34f36 8639 #define MCG_C4_FCTRIM_MASK 0x1Eu
ethaderu 3:78f223d34f36 8640 #define MCG_C4_FCTRIM_SHIFT 1
ethaderu 3:78f223d34f36 8641 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
ethaderu 3:78f223d34f36 8642 #define MCG_C4_DRST_DRS_MASK 0x60u
ethaderu 3:78f223d34f36 8643 #define MCG_C4_DRST_DRS_SHIFT 5
ethaderu 3:78f223d34f36 8644 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
ethaderu 3:78f223d34f36 8645 #define MCG_C4_DMX32_MASK 0x80u
ethaderu 3:78f223d34f36 8646 #define MCG_C4_DMX32_SHIFT 7
ethaderu 3:78f223d34f36 8647 /* C5 Bit Fields */
ethaderu 3:78f223d34f36 8648 #define MCG_C5_PRDIV0_MASK 0x1Fu
ethaderu 3:78f223d34f36 8649 #define MCG_C5_PRDIV0_SHIFT 0
ethaderu 3:78f223d34f36 8650 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
ethaderu 3:78f223d34f36 8651 #define MCG_C5_PLLSTEN0_MASK 0x20u
ethaderu 3:78f223d34f36 8652 #define MCG_C5_PLLSTEN0_SHIFT 5
ethaderu 3:78f223d34f36 8653 #define MCG_C5_PLLCLKEN0_MASK 0x40u
ethaderu 3:78f223d34f36 8654 #define MCG_C5_PLLCLKEN0_SHIFT 6
ethaderu 3:78f223d34f36 8655 /* C6 Bit Fields */
ethaderu 3:78f223d34f36 8656 #define MCG_C6_VDIV0_MASK 0x1Fu
ethaderu 3:78f223d34f36 8657 #define MCG_C6_VDIV0_SHIFT 0
ethaderu 3:78f223d34f36 8658 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
ethaderu 3:78f223d34f36 8659 #define MCG_C6_CME0_MASK 0x20u
ethaderu 3:78f223d34f36 8660 #define MCG_C6_CME0_SHIFT 5
ethaderu 3:78f223d34f36 8661 #define MCG_C6_PLLS_MASK 0x40u
ethaderu 3:78f223d34f36 8662 #define MCG_C6_PLLS_SHIFT 6
ethaderu 3:78f223d34f36 8663 #define MCG_C6_LOLIE0_MASK 0x80u
ethaderu 3:78f223d34f36 8664 #define MCG_C6_LOLIE0_SHIFT 7
ethaderu 3:78f223d34f36 8665 /* S Bit Fields */
ethaderu 3:78f223d34f36 8666 #define MCG_S_IRCST_MASK 0x1u
ethaderu 3:78f223d34f36 8667 #define MCG_S_IRCST_SHIFT 0
ethaderu 3:78f223d34f36 8668 #define MCG_S_OSCINIT0_MASK 0x2u
ethaderu 3:78f223d34f36 8669 #define MCG_S_OSCINIT0_SHIFT 1
ethaderu 3:78f223d34f36 8670 #define MCG_S_CLKST_MASK 0xCu
ethaderu 3:78f223d34f36 8671 #define MCG_S_CLKST_SHIFT 2
ethaderu 3:78f223d34f36 8672 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
ethaderu 3:78f223d34f36 8673 #define MCG_S_IREFST_MASK 0x10u
ethaderu 3:78f223d34f36 8674 #define MCG_S_IREFST_SHIFT 4
ethaderu 3:78f223d34f36 8675 #define MCG_S_PLLST_MASK 0x20u
ethaderu 3:78f223d34f36 8676 #define MCG_S_PLLST_SHIFT 5
ethaderu 3:78f223d34f36 8677 #define MCG_S_LOCK0_MASK 0x40u
ethaderu 3:78f223d34f36 8678 #define MCG_S_LOCK0_SHIFT 6
ethaderu 3:78f223d34f36 8679 #define MCG_S_LOLS0_MASK 0x80u
ethaderu 3:78f223d34f36 8680 #define MCG_S_LOLS0_SHIFT 7
ethaderu 3:78f223d34f36 8681 /* SC Bit Fields */
ethaderu 3:78f223d34f36 8682 #define MCG_SC_LOCS0_MASK 0x1u
ethaderu 3:78f223d34f36 8683 #define MCG_SC_LOCS0_SHIFT 0
ethaderu 3:78f223d34f36 8684 #define MCG_SC_FCRDIV_MASK 0xEu
ethaderu 3:78f223d34f36 8685 #define MCG_SC_FCRDIV_SHIFT 1
ethaderu 3:78f223d34f36 8686 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
ethaderu 3:78f223d34f36 8687 #define MCG_SC_FLTPRSRV_MASK 0x10u
ethaderu 3:78f223d34f36 8688 #define MCG_SC_FLTPRSRV_SHIFT 4
ethaderu 3:78f223d34f36 8689 #define MCG_SC_ATMF_MASK 0x20u
ethaderu 3:78f223d34f36 8690 #define MCG_SC_ATMF_SHIFT 5
ethaderu 3:78f223d34f36 8691 #define MCG_SC_ATMS_MASK 0x40u
ethaderu 3:78f223d34f36 8692 #define MCG_SC_ATMS_SHIFT 6
ethaderu 3:78f223d34f36 8693 #define MCG_SC_ATME_MASK 0x80u
ethaderu 3:78f223d34f36 8694 #define MCG_SC_ATME_SHIFT 7
ethaderu 3:78f223d34f36 8695 /* ATCVH Bit Fields */
ethaderu 3:78f223d34f36 8696 #define MCG_ATCVH_ATCVH_MASK 0xFFu
ethaderu 3:78f223d34f36 8697 #define MCG_ATCVH_ATCVH_SHIFT 0
ethaderu 3:78f223d34f36 8698 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
ethaderu 3:78f223d34f36 8699 /* ATCVL Bit Fields */
ethaderu 3:78f223d34f36 8700 #define MCG_ATCVL_ATCVL_MASK 0xFFu
ethaderu 3:78f223d34f36 8701 #define MCG_ATCVL_ATCVL_SHIFT 0
ethaderu 3:78f223d34f36 8702 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
ethaderu 3:78f223d34f36 8703 /* C7 Bit Fields */
ethaderu 3:78f223d34f36 8704 #define MCG_C7_OSCSEL_MASK 0x3u
ethaderu 3:78f223d34f36 8705 #define MCG_C7_OSCSEL_SHIFT 0
ethaderu 3:78f223d34f36 8706 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
ethaderu 3:78f223d34f36 8707 /* C8 Bit Fields */
ethaderu 3:78f223d34f36 8708 #define MCG_C8_LOCS1_MASK 0x1u
ethaderu 3:78f223d34f36 8709 #define MCG_C8_LOCS1_SHIFT 0
ethaderu 3:78f223d34f36 8710 #define MCG_C8_CME1_MASK 0x20u
ethaderu 3:78f223d34f36 8711 #define MCG_C8_CME1_SHIFT 5
ethaderu 3:78f223d34f36 8712 #define MCG_C8_LOLRE_MASK 0x40u
ethaderu 3:78f223d34f36 8713 #define MCG_C8_LOLRE_SHIFT 6
ethaderu 3:78f223d34f36 8714 #define MCG_C8_LOCRE1_MASK 0x80u
ethaderu 3:78f223d34f36 8715 #define MCG_C8_LOCRE1_SHIFT 7
ethaderu 3:78f223d34f36 8716
ethaderu 3:78f223d34f36 8717 /*!
ethaderu 3:78f223d34f36 8718 * @}
ethaderu 3:78f223d34f36 8719 */ /* end of group MCG_Register_Masks */
ethaderu 3:78f223d34f36 8720
ethaderu 3:78f223d34f36 8721
ethaderu 3:78f223d34f36 8722 /* MCG - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 8723 /** Peripheral MCG base address */
ethaderu 3:78f223d34f36 8724 #define MCG_BASE (0x40064000u)
ethaderu 3:78f223d34f36 8725 /** Peripheral MCG base pointer */
ethaderu 3:78f223d34f36 8726 #define MCG ((MCG_Type *)MCG_BASE)
ethaderu 3:78f223d34f36 8727 #define MCG_BASE_PTR (MCG)
ethaderu 3:78f223d34f36 8728 /** Array initializer of MCG peripheral base addresses */
ethaderu 3:78f223d34f36 8729 #define MCG_BASE_ADDRS { MCG_BASE }
ethaderu 3:78f223d34f36 8730 /** Array initializer of MCG peripheral base pointers */
ethaderu 3:78f223d34f36 8731 #define MCG_BASE_PTRS { MCG }
ethaderu 3:78f223d34f36 8732
ethaderu 3:78f223d34f36 8733 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 8734 -- MCG - Register accessor macros
ethaderu 3:78f223d34f36 8735 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 8736
ethaderu 3:78f223d34f36 8737 /*!
ethaderu 3:78f223d34f36 8738 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
ethaderu 3:78f223d34f36 8739 * @{
ethaderu 3:78f223d34f36 8740 */
ethaderu 3:78f223d34f36 8741
ethaderu 3:78f223d34f36 8742
ethaderu 3:78f223d34f36 8743 /* MCG - Register instance definitions */
ethaderu 3:78f223d34f36 8744 /* MCG */
ethaderu 3:78f223d34f36 8745 #define MCG_C1 MCG_C1_REG(MCG)
ethaderu 3:78f223d34f36 8746 #define MCG_C2 MCG_C2_REG(MCG)
ethaderu 3:78f223d34f36 8747 #define MCG_C3 MCG_C3_REG(MCG)
ethaderu 3:78f223d34f36 8748 #define MCG_C4 MCG_C4_REG(MCG)
ethaderu 3:78f223d34f36 8749 #define MCG_C5 MCG_C5_REG(MCG)
ethaderu 3:78f223d34f36 8750 #define MCG_C6 MCG_C6_REG(MCG)
ethaderu 3:78f223d34f36 8751 #define MCG_S MCG_S_REG(MCG)
ethaderu 3:78f223d34f36 8752 #define MCG_SC MCG_SC_REG(MCG)
ethaderu 3:78f223d34f36 8753 #define MCG_ATCVH MCG_ATCVH_REG(MCG)
ethaderu 3:78f223d34f36 8754 #define MCG_ATCVL MCG_ATCVL_REG(MCG)
ethaderu 3:78f223d34f36 8755 #define MCG_C7 MCG_C7_REG(MCG)
ethaderu 3:78f223d34f36 8756 #define MCG_C8 MCG_C8_REG(MCG)
ethaderu 3:78f223d34f36 8757
ethaderu 3:78f223d34f36 8758 /*!
ethaderu 3:78f223d34f36 8759 * @}
ethaderu 3:78f223d34f36 8760 */ /* end of group MCG_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 8761
ethaderu 3:78f223d34f36 8762
ethaderu 3:78f223d34f36 8763 /*!
ethaderu 3:78f223d34f36 8764 * @}
ethaderu 3:78f223d34f36 8765 */ /* end of group MCG_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 8766
ethaderu 3:78f223d34f36 8767
ethaderu 3:78f223d34f36 8768 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 8769 -- MCM Peripheral Access Layer
ethaderu 3:78f223d34f36 8770 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 8771
ethaderu 3:78f223d34f36 8772 /*!
ethaderu 3:78f223d34f36 8773 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
ethaderu 3:78f223d34f36 8774 * @{
ethaderu 3:78f223d34f36 8775 */
ethaderu 3:78f223d34f36 8776
ethaderu 3:78f223d34f36 8777 /** MCM - Register Layout Typedef */
ethaderu 3:78f223d34f36 8778 typedef struct {
ethaderu 3:78f223d34f36 8779 uint8_t RESERVED_0[8];
ethaderu 3:78f223d34f36 8780 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
ethaderu 3:78f223d34f36 8781 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
ethaderu 3:78f223d34f36 8782 __IO uint32_t CR; /**< Control Register, offset: 0xC */
ethaderu 3:78f223d34f36 8783 __IO uint32_t ISCR; /**< Interrupt Status Register, offset: 0x10 */
ethaderu 3:78f223d34f36 8784 __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */
ethaderu 3:78f223d34f36 8785 __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */
ethaderu 3:78f223d34f36 8786 __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */
ethaderu 3:78f223d34f36 8787 uint8_t RESERVED_1[16];
ethaderu 3:78f223d34f36 8788 __IO uint32_t PID; /**< Process ID register, offset: 0x30 */
ethaderu 3:78f223d34f36 8789 } MCM_Type, *MCM_MemMapPtr;
ethaderu 3:78f223d34f36 8790
ethaderu 3:78f223d34f36 8791 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 8792 -- MCM - Register accessor macros
ethaderu 3:78f223d34f36 8793 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 8794
ethaderu 3:78f223d34f36 8795 /*!
ethaderu 3:78f223d34f36 8796 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
ethaderu 3:78f223d34f36 8797 * @{
ethaderu 3:78f223d34f36 8798 */
ethaderu 3:78f223d34f36 8799
ethaderu 3:78f223d34f36 8800
ethaderu 3:78f223d34f36 8801 /* MCM - Register accessors */
ethaderu 3:78f223d34f36 8802 #define MCM_PLASC_REG(base) ((base)->PLASC)
ethaderu 3:78f223d34f36 8803 #define MCM_PLAMC_REG(base) ((base)->PLAMC)
ethaderu 3:78f223d34f36 8804 #define MCM_CR_REG(base) ((base)->CR)
ethaderu 3:78f223d34f36 8805 #define MCM_ISCR_REG(base) ((base)->ISCR)
ethaderu 3:78f223d34f36 8806 #define MCM_ETBCC_REG(base) ((base)->ETBCC)
ethaderu 3:78f223d34f36 8807 #define MCM_ETBRL_REG(base) ((base)->ETBRL)
ethaderu 3:78f223d34f36 8808 #define MCM_ETBCNT_REG(base) ((base)->ETBCNT)
ethaderu 3:78f223d34f36 8809 #define MCM_PID_REG(base) ((base)->PID)
ethaderu 3:78f223d34f36 8810
ethaderu 3:78f223d34f36 8811 /*!
ethaderu 3:78f223d34f36 8812 * @}
ethaderu 3:78f223d34f36 8813 */ /* end of group MCM_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 8814
ethaderu 3:78f223d34f36 8815
ethaderu 3:78f223d34f36 8816 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 8817 -- MCM Register Masks
ethaderu 3:78f223d34f36 8818 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 8819
ethaderu 3:78f223d34f36 8820 /*!
ethaderu 3:78f223d34f36 8821 * @addtogroup MCM_Register_Masks MCM Register Masks
ethaderu 3:78f223d34f36 8822 * @{
ethaderu 3:78f223d34f36 8823 */
ethaderu 3:78f223d34f36 8824
ethaderu 3:78f223d34f36 8825 /* PLASC Bit Fields */
ethaderu 3:78f223d34f36 8826 #define MCM_PLASC_ASC_MASK 0xFFu
ethaderu 3:78f223d34f36 8827 #define MCM_PLASC_ASC_SHIFT 0
ethaderu 3:78f223d34f36 8828 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
ethaderu 3:78f223d34f36 8829 /* PLAMC Bit Fields */
ethaderu 3:78f223d34f36 8830 #define MCM_PLAMC_AMC_MASK 0xFFu
ethaderu 3:78f223d34f36 8831 #define MCM_PLAMC_AMC_SHIFT 0
ethaderu 3:78f223d34f36 8832 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
ethaderu 3:78f223d34f36 8833 /* CR Bit Fields */
ethaderu 3:78f223d34f36 8834 #define MCM_CR_SRAMUAP_MASK 0x3000000u
ethaderu 3:78f223d34f36 8835 #define MCM_CR_SRAMUAP_SHIFT 24
ethaderu 3:78f223d34f36 8836 #define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUAP_SHIFT))&MCM_CR_SRAMUAP_MASK)
ethaderu 3:78f223d34f36 8837 #define MCM_CR_SRAMUWP_MASK 0x4000000u
ethaderu 3:78f223d34f36 8838 #define MCM_CR_SRAMUWP_SHIFT 26
ethaderu 3:78f223d34f36 8839 #define MCM_CR_SRAMLAP_MASK 0x30000000u
ethaderu 3:78f223d34f36 8840 #define MCM_CR_SRAMLAP_SHIFT 28
ethaderu 3:78f223d34f36 8841 #define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLAP_SHIFT))&MCM_CR_SRAMLAP_MASK)
ethaderu 3:78f223d34f36 8842 #define MCM_CR_SRAMLWP_MASK 0x40000000u
ethaderu 3:78f223d34f36 8843 #define MCM_CR_SRAMLWP_SHIFT 30
ethaderu 3:78f223d34f36 8844 /* ISCR Bit Fields */
ethaderu 3:78f223d34f36 8845 #define MCM_ISCR_IRQ_MASK 0x2u
ethaderu 3:78f223d34f36 8846 #define MCM_ISCR_IRQ_SHIFT 1
ethaderu 3:78f223d34f36 8847 #define MCM_ISCR_NMI_MASK 0x4u
ethaderu 3:78f223d34f36 8848 #define MCM_ISCR_NMI_SHIFT 2
ethaderu 3:78f223d34f36 8849 #define MCM_ISCR_DHREQ_MASK 0x8u
ethaderu 3:78f223d34f36 8850 #define MCM_ISCR_DHREQ_SHIFT 3
ethaderu 3:78f223d34f36 8851 #define MCM_ISCR_FIOC_MASK 0x100u
ethaderu 3:78f223d34f36 8852 #define MCM_ISCR_FIOC_SHIFT 8
ethaderu 3:78f223d34f36 8853 #define MCM_ISCR_FDZC_MASK 0x200u
ethaderu 3:78f223d34f36 8854 #define MCM_ISCR_FDZC_SHIFT 9
ethaderu 3:78f223d34f36 8855 #define MCM_ISCR_FOFC_MASK 0x400u
ethaderu 3:78f223d34f36 8856 #define MCM_ISCR_FOFC_SHIFT 10
ethaderu 3:78f223d34f36 8857 #define MCM_ISCR_FUFC_MASK 0x800u
ethaderu 3:78f223d34f36 8858 #define MCM_ISCR_FUFC_SHIFT 11
ethaderu 3:78f223d34f36 8859 #define MCM_ISCR_FIXC_MASK 0x1000u
ethaderu 3:78f223d34f36 8860 #define MCM_ISCR_FIXC_SHIFT 12
ethaderu 3:78f223d34f36 8861 #define MCM_ISCR_FIDC_MASK 0x8000u
ethaderu 3:78f223d34f36 8862 #define MCM_ISCR_FIDC_SHIFT 15
ethaderu 3:78f223d34f36 8863 #define MCM_ISCR_FIOCE_MASK 0x1000000u
ethaderu 3:78f223d34f36 8864 #define MCM_ISCR_FIOCE_SHIFT 24
ethaderu 3:78f223d34f36 8865 #define MCM_ISCR_FDZCE_MASK 0x2000000u
ethaderu 3:78f223d34f36 8866 #define MCM_ISCR_FDZCE_SHIFT 25
ethaderu 3:78f223d34f36 8867 #define MCM_ISCR_FOFCE_MASK 0x4000000u
ethaderu 3:78f223d34f36 8868 #define MCM_ISCR_FOFCE_SHIFT 26
ethaderu 3:78f223d34f36 8869 #define MCM_ISCR_FUFCE_MASK 0x8000000u
ethaderu 3:78f223d34f36 8870 #define MCM_ISCR_FUFCE_SHIFT 27
ethaderu 3:78f223d34f36 8871 #define MCM_ISCR_FIXCE_MASK 0x10000000u
ethaderu 3:78f223d34f36 8872 #define MCM_ISCR_FIXCE_SHIFT 28
ethaderu 3:78f223d34f36 8873 #define MCM_ISCR_FIDCE_MASK 0x80000000u
ethaderu 3:78f223d34f36 8874 #define MCM_ISCR_FIDCE_SHIFT 31
ethaderu 3:78f223d34f36 8875 /* ETBCC Bit Fields */
ethaderu 3:78f223d34f36 8876 #define MCM_ETBCC_CNTEN_MASK 0x1u
ethaderu 3:78f223d34f36 8877 #define MCM_ETBCC_CNTEN_SHIFT 0
ethaderu 3:78f223d34f36 8878 #define MCM_ETBCC_RSPT_MASK 0x6u
ethaderu 3:78f223d34f36 8879 #define MCM_ETBCC_RSPT_SHIFT 1
ethaderu 3:78f223d34f36 8880 #define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
ethaderu 3:78f223d34f36 8881 #define MCM_ETBCC_RLRQ_MASK 0x8u
ethaderu 3:78f223d34f36 8882 #define MCM_ETBCC_RLRQ_SHIFT 3
ethaderu 3:78f223d34f36 8883 #define MCM_ETBCC_ETDIS_MASK 0x10u
ethaderu 3:78f223d34f36 8884 #define MCM_ETBCC_ETDIS_SHIFT 4
ethaderu 3:78f223d34f36 8885 #define MCM_ETBCC_ITDIS_MASK 0x20u
ethaderu 3:78f223d34f36 8886 #define MCM_ETBCC_ITDIS_SHIFT 5
ethaderu 3:78f223d34f36 8887 /* ETBRL Bit Fields */
ethaderu 3:78f223d34f36 8888 #define MCM_ETBRL_RELOAD_MASK 0x7FFu
ethaderu 3:78f223d34f36 8889 #define MCM_ETBRL_RELOAD_SHIFT 0
ethaderu 3:78f223d34f36 8890 #define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
ethaderu 3:78f223d34f36 8891 /* ETBCNT Bit Fields */
ethaderu 3:78f223d34f36 8892 #define MCM_ETBCNT_COUNTER_MASK 0x7FFu
ethaderu 3:78f223d34f36 8893 #define MCM_ETBCNT_COUNTER_SHIFT 0
ethaderu 3:78f223d34f36 8894 #define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
ethaderu 3:78f223d34f36 8895 /* PID Bit Fields */
ethaderu 3:78f223d34f36 8896 #define MCM_PID_PID_MASK 0xFFu
ethaderu 3:78f223d34f36 8897 #define MCM_PID_PID_SHIFT 0
ethaderu 3:78f223d34f36 8898 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
ethaderu 3:78f223d34f36 8899
ethaderu 3:78f223d34f36 8900 /*!
ethaderu 3:78f223d34f36 8901 * @}
ethaderu 3:78f223d34f36 8902 */ /* end of group MCM_Register_Masks */
ethaderu 3:78f223d34f36 8903
ethaderu 3:78f223d34f36 8904
ethaderu 3:78f223d34f36 8905 /* MCM - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 8906 /** Peripheral MCM base address */
ethaderu 3:78f223d34f36 8907 #define MCM_BASE (0xE0080000u)
ethaderu 3:78f223d34f36 8908 /** Peripheral MCM base pointer */
ethaderu 3:78f223d34f36 8909 #define MCM ((MCM_Type *)MCM_BASE)
ethaderu 3:78f223d34f36 8910 #define MCM_BASE_PTR (MCM)
ethaderu 3:78f223d34f36 8911 /** Array initializer of MCM peripheral base addresses */
ethaderu 3:78f223d34f36 8912 #define MCM_BASE_ADDRS { MCM_BASE }
ethaderu 3:78f223d34f36 8913 /** Array initializer of MCM peripheral base pointers */
ethaderu 3:78f223d34f36 8914 #define MCM_BASE_PTRS { MCM }
ethaderu 3:78f223d34f36 8915
ethaderu 3:78f223d34f36 8916 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 8917 -- MCM - Register accessor macros
ethaderu 3:78f223d34f36 8918 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 8919
ethaderu 3:78f223d34f36 8920 /*!
ethaderu 3:78f223d34f36 8921 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
ethaderu 3:78f223d34f36 8922 * @{
ethaderu 3:78f223d34f36 8923 */
ethaderu 3:78f223d34f36 8924
ethaderu 3:78f223d34f36 8925
ethaderu 3:78f223d34f36 8926 /* MCM - Register instance definitions */
ethaderu 3:78f223d34f36 8927 /* MCM */
ethaderu 3:78f223d34f36 8928 #define MCM_PLASC MCM_PLASC_REG(MCM)
ethaderu 3:78f223d34f36 8929 #define MCM_PLAMC MCM_PLAMC_REG(MCM)
ethaderu 3:78f223d34f36 8930 #define MCM_CR MCM_CR_REG(MCM)
ethaderu 3:78f223d34f36 8931 #define MCM_ISCR MCM_ISCR_REG(MCM)
ethaderu 3:78f223d34f36 8932 #define MCM_ETBCC MCM_ETBCC_REG(MCM)
ethaderu 3:78f223d34f36 8933 #define MCM_ETBRL MCM_ETBRL_REG(MCM)
ethaderu 3:78f223d34f36 8934 #define MCM_ETBCNT MCM_ETBCNT_REG(MCM)
ethaderu 3:78f223d34f36 8935 #define MCM_PID MCM_PID_REG(MCM)
ethaderu 3:78f223d34f36 8936
ethaderu 3:78f223d34f36 8937 /*!
ethaderu 3:78f223d34f36 8938 * @}
ethaderu 3:78f223d34f36 8939 */ /* end of group MCM_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 8940
ethaderu 3:78f223d34f36 8941
ethaderu 3:78f223d34f36 8942 /*!
ethaderu 3:78f223d34f36 8943 * @}
ethaderu 3:78f223d34f36 8944 */ /* end of group MCM_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 8945
ethaderu 3:78f223d34f36 8946
ethaderu 3:78f223d34f36 8947 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 8948 -- MPU Peripheral Access Layer
ethaderu 3:78f223d34f36 8949 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 8950
ethaderu 3:78f223d34f36 8951 /*!
ethaderu 3:78f223d34f36 8952 * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
ethaderu 3:78f223d34f36 8953 * @{
ethaderu 3:78f223d34f36 8954 */
ethaderu 3:78f223d34f36 8955
ethaderu 3:78f223d34f36 8956 /** MPU - Register Layout Typedef */
ethaderu 3:78f223d34f36 8957 typedef struct {
ethaderu 3:78f223d34f36 8958 __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
ethaderu 3:78f223d34f36 8959 uint8_t RESERVED_0[12];
ethaderu 3:78f223d34f36 8960 struct { /* offset: 0x10, array step: 0x8 */
ethaderu 3:78f223d34f36 8961 __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
ethaderu 3:78f223d34f36 8962 __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
ethaderu 3:78f223d34f36 8963 } SP[5];
ethaderu 3:78f223d34f36 8964 uint8_t RESERVED_1[968];
ethaderu 3:78f223d34f36 8965 __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
ethaderu 3:78f223d34f36 8966 uint8_t RESERVED_2[832];
ethaderu 3:78f223d34f36 8967 __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
ethaderu 3:78f223d34f36 8968 } MPU_Type, *MPU_MemMapPtr;
ethaderu 3:78f223d34f36 8969
ethaderu 3:78f223d34f36 8970 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 8971 -- MPU - Register accessor macros
ethaderu 3:78f223d34f36 8972 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 8973
ethaderu 3:78f223d34f36 8974 /*!
ethaderu 3:78f223d34f36 8975 * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
ethaderu 3:78f223d34f36 8976 * @{
ethaderu 3:78f223d34f36 8977 */
ethaderu 3:78f223d34f36 8978
ethaderu 3:78f223d34f36 8979
ethaderu 3:78f223d34f36 8980 /* MPU - Register accessors */
ethaderu 3:78f223d34f36 8981 #define MPU_CESR_REG(base) ((base)->CESR)
ethaderu 3:78f223d34f36 8982 #define MPU_EAR_REG(base,index) ((base)->SP[index].EAR)
ethaderu 3:78f223d34f36 8983 #define MPU_EDR_REG(base,index) ((base)->SP[index].EDR)
ethaderu 3:78f223d34f36 8984 #define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2])
ethaderu 3:78f223d34f36 8985 #define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index])
ethaderu 3:78f223d34f36 8986
ethaderu 3:78f223d34f36 8987 /*!
ethaderu 3:78f223d34f36 8988 * @}
ethaderu 3:78f223d34f36 8989 */ /* end of group MPU_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 8990
ethaderu 3:78f223d34f36 8991
ethaderu 3:78f223d34f36 8992 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 8993 -- MPU Register Masks
ethaderu 3:78f223d34f36 8994 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 8995
ethaderu 3:78f223d34f36 8996 /*!
ethaderu 3:78f223d34f36 8997 * @addtogroup MPU_Register_Masks MPU Register Masks
ethaderu 3:78f223d34f36 8998 * @{
ethaderu 3:78f223d34f36 8999 */
ethaderu 3:78f223d34f36 9000
ethaderu 3:78f223d34f36 9001 /* CESR Bit Fields */
ethaderu 3:78f223d34f36 9002 #define MPU_CESR_VLD_MASK 0x1u
ethaderu 3:78f223d34f36 9003 #define MPU_CESR_VLD_SHIFT 0
ethaderu 3:78f223d34f36 9004 #define MPU_CESR_NRGD_MASK 0xF00u
ethaderu 3:78f223d34f36 9005 #define MPU_CESR_NRGD_SHIFT 8
ethaderu 3:78f223d34f36 9006 #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
ethaderu 3:78f223d34f36 9007 #define MPU_CESR_NSP_MASK 0xF000u
ethaderu 3:78f223d34f36 9008 #define MPU_CESR_NSP_SHIFT 12
ethaderu 3:78f223d34f36 9009 #define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
ethaderu 3:78f223d34f36 9010 #define MPU_CESR_HRL_MASK 0xF0000u
ethaderu 3:78f223d34f36 9011 #define MPU_CESR_HRL_SHIFT 16
ethaderu 3:78f223d34f36 9012 #define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
ethaderu 3:78f223d34f36 9013 #define MPU_CESR_SPERR_MASK 0xF8000000u
ethaderu 3:78f223d34f36 9014 #define MPU_CESR_SPERR_SHIFT 27
ethaderu 3:78f223d34f36 9015 #define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
ethaderu 3:78f223d34f36 9016 /* EAR Bit Fields */
ethaderu 3:78f223d34f36 9017 #define MPU_EAR_EADDR_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 9018 #define MPU_EAR_EADDR_SHIFT 0
ethaderu 3:78f223d34f36 9019 #define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
ethaderu 3:78f223d34f36 9020 /* EDR Bit Fields */
ethaderu 3:78f223d34f36 9021 #define MPU_EDR_ERW_MASK 0x1u
ethaderu 3:78f223d34f36 9022 #define MPU_EDR_ERW_SHIFT 0
ethaderu 3:78f223d34f36 9023 #define MPU_EDR_EATTR_MASK 0xEu
ethaderu 3:78f223d34f36 9024 #define MPU_EDR_EATTR_SHIFT 1
ethaderu 3:78f223d34f36 9025 #define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
ethaderu 3:78f223d34f36 9026 #define MPU_EDR_EMN_MASK 0xF0u
ethaderu 3:78f223d34f36 9027 #define MPU_EDR_EMN_SHIFT 4
ethaderu 3:78f223d34f36 9028 #define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
ethaderu 3:78f223d34f36 9029 #define MPU_EDR_EPID_MASK 0xFF00u
ethaderu 3:78f223d34f36 9030 #define MPU_EDR_EPID_SHIFT 8
ethaderu 3:78f223d34f36 9031 #define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
ethaderu 3:78f223d34f36 9032 #define MPU_EDR_EACD_MASK 0xFFFF0000u
ethaderu 3:78f223d34f36 9033 #define MPU_EDR_EACD_SHIFT 16
ethaderu 3:78f223d34f36 9034 #define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
ethaderu 3:78f223d34f36 9035 /* WORD Bit Fields */
ethaderu 3:78f223d34f36 9036 #define MPU_WORD_VLD_MASK 0x1u
ethaderu 3:78f223d34f36 9037 #define MPU_WORD_VLD_SHIFT 0
ethaderu 3:78f223d34f36 9038 #define MPU_WORD_M0UM_MASK 0x7u
ethaderu 3:78f223d34f36 9039 #define MPU_WORD_M0UM_SHIFT 0
ethaderu 3:78f223d34f36 9040 #define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
ethaderu 3:78f223d34f36 9041 #define MPU_WORD_M0SM_MASK 0x18u
ethaderu 3:78f223d34f36 9042 #define MPU_WORD_M0SM_SHIFT 3
ethaderu 3:78f223d34f36 9043 #define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
ethaderu 3:78f223d34f36 9044 #define MPU_WORD_M0PE_MASK 0x20u
ethaderu 3:78f223d34f36 9045 #define MPU_WORD_M0PE_SHIFT 5
ethaderu 3:78f223d34f36 9046 #define MPU_WORD_ENDADDR_MASK 0xFFFFFFE0u
ethaderu 3:78f223d34f36 9047 #define MPU_WORD_ENDADDR_SHIFT 5
ethaderu 3:78f223d34f36 9048 #define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
ethaderu 3:78f223d34f36 9049 #define MPU_WORD_SRTADDR_MASK 0xFFFFFFE0u
ethaderu 3:78f223d34f36 9050 #define MPU_WORD_SRTADDR_SHIFT 5
ethaderu 3:78f223d34f36 9051 #define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
ethaderu 3:78f223d34f36 9052 #define MPU_WORD_M1UM_MASK 0x1C0u
ethaderu 3:78f223d34f36 9053 #define MPU_WORD_M1UM_SHIFT 6
ethaderu 3:78f223d34f36 9054 #define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
ethaderu 3:78f223d34f36 9055 #define MPU_WORD_M1SM_MASK 0x600u
ethaderu 3:78f223d34f36 9056 #define MPU_WORD_M1SM_SHIFT 9
ethaderu 3:78f223d34f36 9057 #define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
ethaderu 3:78f223d34f36 9058 #define MPU_WORD_M1PE_MASK 0x800u
ethaderu 3:78f223d34f36 9059 #define MPU_WORD_M1PE_SHIFT 11
ethaderu 3:78f223d34f36 9060 #define MPU_WORD_M2UM_MASK 0x7000u
ethaderu 3:78f223d34f36 9061 #define MPU_WORD_M2UM_SHIFT 12
ethaderu 3:78f223d34f36 9062 #define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
ethaderu 3:78f223d34f36 9063 #define MPU_WORD_M2SM_MASK 0x18000u
ethaderu 3:78f223d34f36 9064 #define MPU_WORD_M2SM_SHIFT 15
ethaderu 3:78f223d34f36 9065 #define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
ethaderu 3:78f223d34f36 9066 #define MPU_WORD_PIDMASK_MASK 0xFF0000u
ethaderu 3:78f223d34f36 9067 #define MPU_WORD_PIDMASK_SHIFT 16
ethaderu 3:78f223d34f36 9068 #define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PIDMASK_SHIFT))&MPU_WORD_PIDMASK_MASK)
ethaderu 3:78f223d34f36 9069 #define MPU_WORD_M2PE_MASK 0x20000u
ethaderu 3:78f223d34f36 9070 #define MPU_WORD_M2PE_SHIFT 17
ethaderu 3:78f223d34f36 9071 #define MPU_WORD_M3UM_MASK 0x1C0000u
ethaderu 3:78f223d34f36 9072 #define MPU_WORD_M3UM_SHIFT 18
ethaderu 3:78f223d34f36 9073 #define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
ethaderu 3:78f223d34f36 9074 #define MPU_WORD_M3SM_MASK 0x600000u
ethaderu 3:78f223d34f36 9075 #define MPU_WORD_M3SM_SHIFT 21
ethaderu 3:78f223d34f36 9076 #define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
ethaderu 3:78f223d34f36 9077 #define MPU_WORD_M3PE_MASK 0x800000u
ethaderu 3:78f223d34f36 9078 #define MPU_WORD_M3PE_SHIFT 23
ethaderu 3:78f223d34f36 9079 #define MPU_WORD_PID_MASK 0xFF000000u
ethaderu 3:78f223d34f36 9080 #define MPU_WORD_PID_SHIFT 24
ethaderu 3:78f223d34f36 9081 #define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PID_SHIFT))&MPU_WORD_PID_MASK)
ethaderu 3:78f223d34f36 9082 #define MPU_WORD_M4WE_MASK 0x1000000u
ethaderu 3:78f223d34f36 9083 #define MPU_WORD_M4WE_SHIFT 24
ethaderu 3:78f223d34f36 9084 #define MPU_WORD_M4RE_MASK 0x2000000u
ethaderu 3:78f223d34f36 9085 #define MPU_WORD_M4RE_SHIFT 25
ethaderu 3:78f223d34f36 9086 #define MPU_WORD_M5WE_MASK 0x4000000u
ethaderu 3:78f223d34f36 9087 #define MPU_WORD_M5WE_SHIFT 26
ethaderu 3:78f223d34f36 9088 #define MPU_WORD_M5RE_MASK 0x8000000u
ethaderu 3:78f223d34f36 9089 #define MPU_WORD_M5RE_SHIFT 27
ethaderu 3:78f223d34f36 9090 #define MPU_WORD_M6WE_MASK 0x10000000u
ethaderu 3:78f223d34f36 9091 #define MPU_WORD_M6WE_SHIFT 28
ethaderu 3:78f223d34f36 9092 #define MPU_WORD_M6RE_MASK 0x20000000u
ethaderu 3:78f223d34f36 9093 #define MPU_WORD_M6RE_SHIFT 29
ethaderu 3:78f223d34f36 9094 #define MPU_WORD_M7WE_MASK 0x40000000u
ethaderu 3:78f223d34f36 9095 #define MPU_WORD_M7WE_SHIFT 30
ethaderu 3:78f223d34f36 9096 #define MPU_WORD_M7RE_MASK 0x80000000u
ethaderu 3:78f223d34f36 9097 #define MPU_WORD_M7RE_SHIFT 31
ethaderu 3:78f223d34f36 9098 /* RGDAAC Bit Fields */
ethaderu 3:78f223d34f36 9099 #define MPU_RGDAAC_M0UM_MASK 0x7u
ethaderu 3:78f223d34f36 9100 #define MPU_RGDAAC_M0UM_SHIFT 0
ethaderu 3:78f223d34f36 9101 #define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
ethaderu 3:78f223d34f36 9102 #define MPU_RGDAAC_M0SM_MASK 0x18u
ethaderu 3:78f223d34f36 9103 #define MPU_RGDAAC_M0SM_SHIFT 3
ethaderu 3:78f223d34f36 9104 #define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
ethaderu 3:78f223d34f36 9105 #define MPU_RGDAAC_M0PE_MASK 0x20u
ethaderu 3:78f223d34f36 9106 #define MPU_RGDAAC_M0PE_SHIFT 5
ethaderu 3:78f223d34f36 9107 #define MPU_RGDAAC_M1UM_MASK 0x1C0u
ethaderu 3:78f223d34f36 9108 #define MPU_RGDAAC_M1UM_SHIFT 6
ethaderu 3:78f223d34f36 9109 #define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
ethaderu 3:78f223d34f36 9110 #define MPU_RGDAAC_M1SM_MASK 0x600u
ethaderu 3:78f223d34f36 9111 #define MPU_RGDAAC_M1SM_SHIFT 9
ethaderu 3:78f223d34f36 9112 #define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
ethaderu 3:78f223d34f36 9113 #define MPU_RGDAAC_M1PE_MASK 0x800u
ethaderu 3:78f223d34f36 9114 #define MPU_RGDAAC_M1PE_SHIFT 11
ethaderu 3:78f223d34f36 9115 #define MPU_RGDAAC_M2UM_MASK 0x7000u
ethaderu 3:78f223d34f36 9116 #define MPU_RGDAAC_M2UM_SHIFT 12
ethaderu 3:78f223d34f36 9117 #define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
ethaderu 3:78f223d34f36 9118 #define MPU_RGDAAC_M2SM_MASK 0x18000u
ethaderu 3:78f223d34f36 9119 #define MPU_RGDAAC_M2SM_SHIFT 15
ethaderu 3:78f223d34f36 9120 #define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
ethaderu 3:78f223d34f36 9121 #define MPU_RGDAAC_M2PE_MASK 0x20000u
ethaderu 3:78f223d34f36 9122 #define MPU_RGDAAC_M2PE_SHIFT 17
ethaderu 3:78f223d34f36 9123 #define MPU_RGDAAC_M3UM_MASK 0x1C0000u
ethaderu 3:78f223d34f36 9124 #define MPU_RGDAAC_M3UM_SHIFT 18
ethaderu 3:78f223d34f36 9125 #define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
ethaderu 3:78f223d34f36 9126 #define MPU_RGDAAC_M3SM_MASK 0x600000u
ethaderu 3:78f223d34f36 9127 #define MPU_RGDAAC_M3SM_SHIFT 21
ethaderu 3:78f223d34f36 9128 #define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
ethaderu 3:78f223d34f36 9129 #define MPU_RGDAAC_M3PE_MASK 0x800000u
ethaderu 3:78f223d34f36 9130 #define MPU_RGDAAC_M3PE_SHIFT 23
ethaderu 3:78f223d34f36 9131 #define MPU_RGDAAC_M4WE_MASK 0x1000000u
ethaderu 3:78f223d34f36 9132 #define MPU_RGDAAC_M4WE_SHIFT 24
ethaderu 3:78f223d34f36 9133 #define MPU_RGDAAC_M4RE_MASK 0x2000000u
ethaderu 3:78f223d34f36 9134 #define MPU_RGDAAC_M4RE_SHIFT 25
ethaderu 3:78f223d34f36 9135 #define MPU_RGDAAC_M5WE_MASK 0x4000000u
ethaderu 3:78f223d34f36 9136 #define MPU_RGDAAC_M5WE_SHIFT 26
ethaderu 3:78f223d34f36 9137 #define MPU_RGDAAC_M5RE_MASK 0x8000000u
ethaderu 3:78f223d34f36 9138 #define MPU_RGDAAC_M5RE_SHIFT 27
ethaderu 3:78f223d34f36 9139 #define MPU_RGDAAC_M6WE_MASK 0x10000000u
ethaderu 3:78f223d34f36 9140 #define MPU_RGDAAC_M6WE_SHIFT 28
ethaderu 3:78f223d34f36 9141 #define MPU_RGDAAC_M6RE_MASK 0x20000000u
ethaderu 3:78f223d34f36 9142 #define MPU_RGDAAC_M6RE_SHIFT 29
ethaderu 3:78f223d34f36 9143 #define MPU_RGDAAC_M7WE_MASK 0x40000000u
ethaderu 3:78f223d34f36 9144 #define MPU_RGDAAC_M7WE_SHIFT 30
ethaderu 3:78f223d34f36 9145 #define MPU_RGDAAC_M7RE_MASK 0x80000000u
ethaderu 3:78f223d34f36 9146 #define MPU_RGDAAC_M7RE_SHIFT 31
ethaderu 3:78f223d34f36 9147
ethaderu 3:78f223d34f36 9148 /*!
ethaderu 3:78f223d34f36 9149 * @}
ethaderu 3:78f223d34f36 9150 */ /* end of group MPU_Register_Masks */
ethaderu 3:78f223d34f36 9151
ethaderu 3:78f223d34f36 9152
ethaderu 3:78f223d34f36 9153 /* MPU - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 9154 /** Peripheral MPU base address */
ethaderu 3:78f223d34f36 9155 #define MPU_BASE (0x4000D000u)
ethaderu 3:78f223d34f36 9156 /** Peripheral MPU base pointer */
ethaderu 3:78f223d34f36 9157 #define MPU ((MPU_Type *)MPU_BASE)
ethaderu 3:78f223d34f36 9158 #define MPU_BASE_PTR (MPU)
ethaderu 3:78f223d34f36 9159 /** Array initializer of MPU peripheral base addresses */
ethaderu 3:78f223d34f36 9160 #define MPU_BASE_ADDRS { MPU_BASE }
ethaderu 3:78f223d34f36 9161 /** Array initializer of MPU peripheral base pointers */
ethaderu 3:78f223d34f36 9162 #define MPU_BASE_PTRS { MPU }
ethaderu 3:78f223d34f36 9163
ethaderu 3:78f223d34f36 9164 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 9165 -- MPU - Register accessor macros
ethaderu 3:78f223d34f36 9166 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 9167
ethaderu 3:78f223d34f36 9168 /*!
ethaderu 3:78f223d34f36 9169 * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
ethaderu 3:78f223d34f36 9170 * @{
ethaderu 3:78f223d34f36 9171 */
ethaderu 3:78f223d34f36 9172
ethaderu 3:78f223d34f36 9173
ethaderu 3:78f223d34f36 9174 /* MPU - Register instance definitions */
ethaderu 3:78f223d34f36 9175 /* MPU */
ethaderu 3:78f223d34f36 9176 #define MPU_CESR MPU_CESR_REG(MPU)
ethaderu 3:78f223d34f36 9177 #define MPU_EAR0 MPU_EAR_REG(MPU,0)
ethaderu 3:78f223d34f36 9178 #define MPU_EDR0 MPU_EDR_REG(MPU,0)
ethaderu 3:78f223d34f36 9179 #define MPU_EAR1 MPU_EAR_REG(MPU,1)
ethaderu 3:78f223d34f36 9180 #define MPU_EDR1 MPU_EDR_REG(MPU,1)
ethaderu 3:78f223d34f36 9181 #define MPU_EAR2 MPU_EAR_REG(MPU,2)
ethaderu 3:78f223d34f36 9182 #define MPU_EDR2 MPU_EDR_REG(MPU,2)
ethaderu 3:78f223d34f36 9183 #define MPU_EAR3 MPU_EAR_REG(MPU,3)
ethaderu 3:78f223d34f36 9184 #define MPU_EDR3 MPU_EDR_REG(MPU,3)
ethaderu 3:78f223d34f36 9185 #define MPU_EAR4 MPU_EAR_REG(MPU,4)
ethaderu 3:78f223d34f36 9186 #define MPU_EDR4 MPU_EDR_REG(MPU,4)
ethaderu 3:78f223d34f36 9187 #define MPU_RGD0_WORD0 MPU_WORD_REG(MPU,0,0)
ethaderu 3:78f223d34f36 9188 #define MPU_RGD0_WORD1 MPU_WORD_REG(MPU,0,1)
ethaderu 3:78f223d34f36 9189 #define MPU_RGD0_WORD2 MPU_WORD_REG(MPU,0,2)
ethaderu 3:78f223d34f36 9190 #define MPU_RGD0_WORD3 MPU_WORD_REG(MPU,0,3)
ethaderu 3:78f223d34f36 9191 #define MPU_RGD1_WORD0 MPU_WORD_REG(MPU,1,0)
ethaderu 3:78f223d34f36 9192 #define MPU_RGD1_WORD1 MPU_WORD_REG(MPU,1,1)
ethaderu 3:78f223d34f36 9193 #define MPU_RGD1_WORD2 MPU_WORD_REG(MPU,1,2)
ethaderu 3:78f223d34f36 9194 #define MPU_RGD1_WORD3 MPU_WORD_REG(MPU,1,3)
ethaderu 3:78f223d34f36 9195 #define MPU_RGD2_WORD0 MPU_WORD_REG(MPU,2,0)
ethaderu 3:78f223d34f36 9196 #define MPU_RGD2_WORD1 MPU_WORD_REG(MPU,2,1)
ethaderu 3:78f223d34f36 9197 #define MPU_RGD2_WORD2 MPU_WORD_REG(MPU,2,2)
ethaderu 3:78f223d34f36 9198 #define MPU_RGD2_WORD3 MPU_WORD_REG(MPU,2,3)
ethaderu 3:78f223d34f36 9199 #define MPU_RGD3_WORD0 MPU_WORD_REG(MPU,3,0)
ethaderu 3:78f223d34f36 9200 #define MPU_RGD3_WORD1 MPU_WORD_REG(MPU,3,1)
ethaderu 3:78f223d34f36 9201 #define MPU_RGD3_WORD2 MPU_WORD_REG(MPU,3,2)
ethaderu 3:78f223d34f36 9202 #define MPU_RGD3_WORD3 MPU_WORD_REG(MPU,3,3)
ethaderu 3:78f223d34f36 9203 #define MPU_RGD4_WORD0 MPU_WORD_REG(MPU,4,0)
ethaderu 3:78f223d34f36 9204 #define MPU_RGD4_WORD1 MPU_WORD_REG(MPU,4,1)
ethaderu 3:78f223d34f36 9205 #define MPU_RGD4_WORD2 MPU_WORD_REG(MPU,4,2)
ethaderu 3:78f223d34f36 9206 #define MPU_RGD4_WORD3 MPU_WORD_REG(MPU,4,3)
ethaderu 3:78f223d34f36 9207 #define MPU_RGD5_WORD0 MPU_WORD_REG(MPU,5,0)
ethaderu 3:78f223d34f36 9208 #define MPU_RGD5_WORD1 MPU_WORD_REG(MPU,5,1)
ethaderu 3:78f223d34f36 9209 #define MPU_RGD5_WORD2 MPU_WORD_REG(MPU,5,2)
ethaderu 3:78f223d34f36 9210 #define MPU_RGD5_WORD3 MPU_WORD_REG(MPU,5,3)
ethaderu 3:78f223d34f36 9211 #define MPU_RGD6_WORD0 MPU_WORD_REG(MPU,6,0)
ethaderu 3:78f223d34f36 9212 #define MPU_RGD6_WORD1 MPU_WORD_REG(MPU,6,1)
ethaderu 3:78f223d34f36 9213 #define MPU_RGD6_WORD2 MPU_WORD_REG(MPU,6,2)
ethaderu 3:78f223d34f36 9214 #define MPU_RGD6_WORD3 MPU_WORD_REG(MPU,6,3)
ethaderu 3:78f223d34f36 9215 #define MPU_RGD7_WORD0 MPU_WORD_REG(MPU,7,0)
ethaderu 3:78f223d34f36 9216 #define MPU_RGD7_WORD1 MPU_WORD_REG(MPU,7,1)
ethaderu 3:78f223d34f36 9217 #define MPU_RGD7_WORD2 MPU_WORD_REG(MPU,7,2)
ethaderu 3:78f223d34f36 9218 #define MPU_RGD7_WORD3 MPU_WORD_REG(MPU,7,3)
ethaderu 3:78f223d34f36 9219 #define MPU_RGD8_WORD0 MPU_WORD_REG(MPU,8,0)
ethaderu 3:78f223d34f36 9220 #define MPU_RGD8_WORD1 MPU_WORD_REG(MPU,8,1)
ethaderu 3:78f223d34f36 9221 #define MPU_RGD8_WORD2 MPU_WORD_REG(MPU,8,2)
ethaderu 3:78f223d34f36 9222 #define MPU_RGD8_WORD3 MPU_WORD_REG(MPU,8,3)
ethaderu 3:78f223d34f36 9223 #define MPU_RGD9_WORD0 MPU_WORD_REG(MPU,9,0)
ethaderu 3:78f223d34f36 9224 #define MPU_RGD9_WORD1 MPU_WORD_REG(MPU,9,1)
ethaderu 3:78f223d34f36 9225 #define MPU_RGD9_WORD2 MPU_WORD_REG(MPU,9,2)
ethaderu 3:78f223d34f36 9226 #define MPU_RGD9_WORD3 MPU_WORD_REG(MPU,9,3)
ethaderu 3:78f223d34f36 9227 #define MPU_RGD10_WORD0 MPU_WORD_REG(MPU,10,0)
ethaderu 3:78f223d34f36 9228 #define MPU_RGD10_WORD1 MPU_WORD_REG(MPU,10,1)
ethaderu 3:78f223d34f36 9229 #define MPU_RGD10_WORD2 MPU_WORD_REG(MPU,10,2)
ethaderu 3:78f223d34f36 9230 #define MPU_RGD10_WORD3 MPU_WORD_REG(MPU,10,3)
ethaderu 3:78f223d34f36 9231 #define MPU_RGD11_WORD0 MPU_WORD_REG(MPU,11,0)
ethaderu 3:78f223d34f36 9232 #define MPU_RGD11_WORD1 MPU_WORD_REG(MPU,11,1)
ethaderu 3:78f223d34f36 9233 #define MPU_RGD11_WORD2 MPU_WORD_REG(MPU,11,2)
ethaderu 3:78f223d34f36 9234 #define MPU_RGD11_WORD3 MPU_WORD_REG(MPU,11,3)
ethaderu 3:78f223d34f36 9235 #define MPU_RGDAAC0 MPU_RGDAAC_REG(MPU,0)
ethaderu 3:78f223d34f36 9236 #define MPU_RGDAAC1 MPU_RGDAAC_REG(MPU,1)
ethaderu 3:78f223d34f36 9237 #define MPU_RGDAAC2 MPU_RGDAAC_REG(MPU,2)
ethaderu 3:78f223d34f36 9238 #define MPU_RGDAAC3 MPU_RGDAAC_REG(MPU,3)
ethaderu 3:78f223d34f36 9239 #define MPU_RGDAAC4 MPU_RGDAAC_REG(MPU,4)
ethaderu 3:78f223d34f36 9240 #define MPU_RGDAAC5 MPU_RGDAAC_REG(MPU,5)
ethaderu 3:78f223d34f36 9241 #define MPU_RGDAAC6 MPU_RGDAAC_REG(MPU,6)
ethaderu 3:78f223d34f36 9242 #define MPU_RGDAAC7 MPU_RGDAAC_REG(MPU,7)
ethaderu 3:78f223d34f36 9243 #define MPU_RGDAAC8 MPU_RGDAAC_REG(MPU,8)
ethaderu 3:78f223d34f36 9244 #define MPU_RGDAAC9 MPU_RGDAAC_REG(MPU,9)
ethaderu 3:78f223d34f36 9245 #define MPU_RGDAAC10 MPU_RGDAAC_REG(MPU,10)
ethaderu 3:78f223d34f36 9246 #define MPU_RGDAAC11 MPU_RGDAAC_REG(MPU,11)
ethaderu 3:78f223d34f36 9247
ethaderu 3:78f223d34f36 9248 /* MPU - Register array accessors */
ethaderu 3:78f223d34f36 9249 #define MPU_EAR(index) MPU_EAR_REG(MPU,index)
ethaderu 3:78f223d34f36 9250 #define MPU_EDR(index) MPU_EDR_REG(MPU,index)
ethaderu 3:78f223d34f36 9251 #define MPU_WORD(index,index2) MPU_WORD_REG(MPU,index,index2)
ethaderu 3:78f223d34f36 9252 #define MPU_RGDAAC(index) MPU_RGDAAC_REG(MPU,index)
ethaderu 3:78f223d34f36 9253
ethaderu 3:78f223d34f36 9254 /*!
ethaderu 3:78f223d34f36 9255 * @}
ethaderu 3:78f223d34f36 9256 */ /* end of group MPU_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 9257
ethaderu 3:78f223d34f36 9258
ethaderu 3:78f223d34f36 9259 /*!
ethaderu 3:78f223d34f36 9260 * @}
ethaderu 3:78f223d34f36 9261 */ /* end of group MPU_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 9262
ethaderu 3:78f223d34f36 9263
ethaderu 3:78f223d34f36 9264 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 9265 -- NV Peripheral Access Layer
ethaderu 3:78f223d34f36 9266 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 9267
ethaderu 3:78f223d34f36 9268 /*!
ethaderu 3:78f223d34f36 9269 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
ethaderu 3:78f223d34f36 9270 * @{
ethaderu 3:78f223d34f36 9271 */
ethaderu 3:78f223d34f36 9272
ethaderu 3:78f223d34f36 9273 /** NV - Register Layout Typedef */
ethaderu 3:78f223d34f36 9274 typedef struct {
ethaderu 3:78f223d34f36 9275 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
ethaderu 3:78f223d34f36 9276 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
ethaderu 3:78f223d34f36 9277 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
ethaderu 3:78f223d34f36 9278 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
ethaderu 3:78f223d34f36 9279 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
ethaderu 3:78f223d34f36 9280 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
ethaderu 3:78f223d34f36 9281 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
ethaderu 3:78f223d34f36 9282 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
ethaderu 3:78f223d34f36 9283 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
ethaderu 3:78f223d34f36 9284 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
ethaderu 3:78f223d34f36 9285 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
ethaderu 3:78f223d34f36 9286 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
ethaderu 3:78f223d34f36 9287 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
ethaderu 3:78f223d34f36 9288 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
ethaderu 3:78f223d34f36 9289 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
ethaderu 3:78f223d34f36 9290 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
ethaderu 3:78f223d34f36 9291 } NV_Type, *NV_MemMapPtr;
ethaderu 3:78f223d34f36 9292
ethaderu 3:78f223d34f36 9293 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 9294 -- NV - Register accessor macros
ethaderu 3:78f223d34f36 9295 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 9296
ethaderu 3:78f223d34f36 9297 /*!
ethaderu 3:78f223d34f36 9298 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
ethaderu 3:78f223d34f36 9299 * @{
ethaderu 3:78f223d34f36 9300 */
ethaderu 3:78f223d34f36 9301
ethaderu 3:78f223d34f36 9302
ethaderu 3:78f223d34f36 9303 /* NV - Register accessors */
ethaderu 3:78f223d34f36 9304 #define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
ethaderu 3:78f223d34f36 9305 #define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
ethaderu 3:78f223d34f36 9306 #define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
ethaderu 3:78f223d34f36 9307 #define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
ethaderu 3:78f223d34f36 9308 #define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
ethaderu 3:78f223d34f36 9309 #define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
ethaderu 3:78f223d34f36 9310 #define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
ethaderu 3:78f223d34f36 9311 #define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
ethaderu 3:78f223d34f36 9312 #define NV_FPROT3_REG(base) ((base)->FPROT3)
ethaderu 3:78f223d34f36 9313 #define NV_FPROT2_REG(base) ((base)->FPROT2)
ethaderu 3:78f223d34f36 9314 #define NV_FPROT1_REG(base) ((base)->FPROT1)
ethaderu 3:78f223d34f36 9315 #define NV_FPROT0_REG(base) ((base)->FPROT0)
ethaderu 3:78f223d34f36 9316 #define NV_FSEC_REG(base) ((base)->FSEC)
ethaderu 3:78f223d34f36 9317 #define NV_FOPT_REG(base) ((base)->FOPT)
ethaderu 3:78f223d34f36 9318 #define NV_FEPROT_REG(base) ((base)->FEPROT)
ethaderu 3:78f223d34f36 9319 #define NV_FDPROT_REG(base) ((base)->FDPROT)
ethaderu 3:78f223d34f36 9320
ethaderu 3:78f223d34f36 9321 /*!
ethaderu 3:78f223d34f36 9322 * @}
ethaderu 3:78f223d34f36 9323 */ /* end of group NV_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 9324
ethaderu 3:78f223d34f36 9325
ethaderu 3:78f223d34f36 9326 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 9327 -- NV Register Masks
ethaderu 3:78f223d34f36 9328 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 9329
ethaderu 3:78f223d34f36 9330 /*!
ethaderu 3:78f223d34f36 9331 * @addtogroup NV_Register_Masks NV Register Masks
ethaderu 3:78f223d34f36 9332 * @{
ethaderu 3:78f223d34f36 9333 */
ethaderu 3:78f223d34f36 9334
ethaderu 3:78f223d34f36 9335 /* BACKKEY3 Bit Fields */
ethaderu 3:78f223d34f36 9336 #define NV_BACKKEY3_KEY_MASK 0xFFu
ethaderu 3:78f223d34f36 9337 #define NV_BACKKEY3_KEY_SHIFT 0
ethaderu 3:78f223d34f36 9338 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
ethaderu 3:78f223d34f36 9339 /* BACKKEY2 Bit Fields */
ethaderu 3:78f223d34f36 9340 #define NV_BACKKEY2_KEY_MASK 0xFFu
ethaderu 3:78f223d34f36 9341 #define NV_BACKKEY2_KEY_SHIFT 0
ethaderu 3:78f223d34f36 9342 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
ethaderu 3:78f223d34f36 9343 /* BACKKEY1 Bit Fields */
ethaderu 3:78f223d34f36 9344 #define NV_BACKKEY1_KEY_MASK 0xFFu
ethaderu 3:78f223d34f36 9345 #define NV_BACKKEY1_KEY_SHIFT 0
ethaderu 3:78f223d34f36 9346 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
ethaderu 3:78f223d34f36 9347 /* BACKKEY0 Bit Fields */
ethaderu 3:78f223d34f36 9348 #define NV_BACKKEY0_KEY_MASK 0xFFu
ethaderu 3:78f223d34f36 9349 #define NV_BACKKEY0_KEY_SHIFT 0
ethaderu 3:78f223d34f36 9350 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
ethaderu 3:78f223d34f36 9351 /* BACKKEY7 Bit Fields */
ethaderu 3:78f223d34f36 9352 #define NV_BACKKEY7_KEY_MASK 0xFFu
ethaderu 3:78f223d34f36 9353 #define NV_BACKKEY7_KEY_SHIFT 0
ethaderu 3:78f223d34f36 9354 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
ethaderu 3:78f223d34f36 9355 /* BACKKEY6 Bit Fields */
ethaderu 3:78f223d34f36 9356 #define NV_BACKKEY6_KEY_MASK 0xFFu
ethaderu 3:78f223d34f36 9357 #define NV_BACKKEY6_KEY_SHIFT 0
ethaderu 3:78f223d34f36 9358 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
ethaderu 3:78f223d34f36 9359 /* BACKKEY5 Bit Fields */
ethaderu 3:78f223d34f36 9360 #define NV_BACKKEY5_KEY_MASK 0xFFu
ethaderu 3:78f223d34f36 9361 #define NV_BACKKEY5_KEY_SHIFT 0
ethaderu 3:78f223d34f36 9362 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
ethaderu 3:78f223d34f36 9363 /* BACKKEY4 Bit Fields */
ethaderu 3:78f223d34f36 9364 #define NV_BACKKEY4_KEY_MASK 0xFFu
ethaderu 3:78f223d34f36 9365 #define NV_BACKKEY4_KEY_SHIFT 0
ethaderu 3:78f223d34f36 9366 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
ethaderu 3:78f223d34f36 9367 /* FPROT3 Bit Fields */
ethaderu 3:78f223d34f36 9368 #define NV_FPROT3_PROT_MASK 0xFFu
ethaderu 3:78f223d34f36 9369 #define NV_FPROT3_PROT_SHIFT 0
ethaderu 3:78f223d34f36 9370 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
ethaderu 3:78f223d34f36 9371 /* FPROT2 Bit Fields */
ethaderu 3:78f223d34f36 9372 #define NV_FPROT2_PROT_MASK 0xFFu
ethaderu 3:78f223d34f36 9373 #define NV_FPROT2_PROT_SHIFT 0
ethaderu 3:78f223d34f36 9374 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
ethaderu 3:78f223d34f36 9375 /* FPROT1 Bit Fields */
ethaderu 3:78f223d34f36 9376 #define NV_FPROT1_PROT_MASK 0xFFu
ethaderu 3:78f223d34f36 9377 #define NV_FPROT1_PROT_SHIFT 0
ethaderu 3:78f223d34f36 9378 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
ethaderu 3:78f223d34f36 9379 /* FPROT0 Bit Fields */
ethaderu 3:78f223d34f36 9380 #define NV_FPROT0_PROT_MASK 0xFFu
ethaderu 3:78f223d34f36 9381 #define NV_FPROT0_PROT_SHIFT 0
ethaderu 3:78f223d34f36 9382 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
ethaderu 3:78f223d34f36 9383 /* FSEC Bit Fields */
ethaderu 3:78f223d34f36 9384 #define NV_FSEC_SEC_MASK 0x3u
ethaderu 3:78f223d34f36 9385 #define NV_FSEC_SEC_SHIFT 0
ethaderu 3:78f223d34f36 9386 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
ethaderu 3:78f223d34f36 9387 #define NV_FSEC_FSLACC_MASK 0xCu
ethaderu 3:78f223d34f36 9388 #define NV_FSEC_FSLACC_SHIFT 2
ethaderu 3:78f223d34f36 9389 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
ethaderu 3:78f223d34f36 9390 #define NV_FSEC_MEEN_MASK 0x30u
ethaderu 3:78f223d34f36 9391 #define NV_FSEC_MEEN_SHIFT 4
ethaderu 3:78f223d34f36 9392 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
ethaderu 3:78f223d34f36 9393 #define NV_FSEC_KEYEN_MASK 0xC0u
ethaderu 3:78f223d34f36 9394 #define NV_FSEC_KEYEN_SHIFT 6
ethaderu 3:78f223d34f36 9395 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
ethaderu 3:78f223d34f36 9396 /* FOPT Bit Fields */
ethaderu 3:78f223d34f36 9397 #define NV_FOPT_LPBOOT_MASK 0x1u
ethaderu 3:78f223d34f36 9398 #define NV_FOPT_LPBOOT_SHIFT 0
ethaderu 3:78f223d34f36 9399 #define NV_FOPT_EZPORT_DIS_MASK 0x2u
ethaderu 3:78f223d34f36 9400 #define NV_FOPT_EZPORT_DIS_SHIFT 1
ethaderu 3:78f223d34f36 9401 /* FEPROT Bit Fields */
ethaderu 3:78f223d34f36 9402 #define NV_FEPROT_EPROT_MASK 0xFFu
ethaderu 3:78f223d34f36 9403 #define NV_FEPROT_EPROT_SHIFT 0
ethaderu 3:78f223d34f36 9404 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
ethaderu 3:78f223d34f36 9405 /* FDPROT Bit Fields */
ethaderu 3:78f223d34f36 9406 #define NV_FDPROT_DPROT_MASK 0xFFu
ethaderu 3:78f223d34f36 9407 #define NV_FDPROT_DPROT_SHIFT 0
ethaderu 3:78f223d34f36 9408 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
ethaderu 3:78f223d34f36 9409
ethaderu 3:78f223d34f36 9410 /*!
ethaderu 3:78f223d34f36 9411 * @}
ethaderu 3:78f223d34f36 9412 */ /* end of group NV_Register_Masks */
ethaderu 3:78f223d34f36 9413
ethaderu 3:78f223d34f36 9414
ethaderu 3:78f223d34f36 9415 /* NV - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 9416 /** Peripheral FTFE_FlashConfig base address */
ethaderu 3:78f223d34f36 9417 #define FTFE_FlashConfig_BASE (0x400u)
ethaderu 3:78f223d34f36 9418 /** Peripheral FTFE_FlashConfig base pointer */
ethaderu 3:78f223d34f36 9419 #define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE)
ethaderu 3:78f223d34f36 9420 #define FTFE_FlashConfig_BASE_PTR (FTFE_FlashConfig)
ethaderu 3:78f223d34f36 9421 /** Array initializer of NV peripheral base addresses */
ethaderu 3:78f223d34f36 9422 #define NV_BASE_ADDRS { FTFE_FlashConfig_BASE }
ethaderu 3:78f223d34f36 9423 /** Array initializer of NV peripheral base pointers */
ethaderu 3:78f223d34f36 9424 #define NV_BASE_PTRS { FTFE_FlashConfig }
ethaderu 3:78f223d34f36 9425
ethaderu 3:78f223d34f36 9426 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 9427 -- NV - Register accessor macros
ethaderu 3:78f223d34f36 9428 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 9429
ethaderu 3:78f223d34f36 9430 /*!
ethaderu 3:78f223d34f36 9431 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
ethaderu 3:78f223d34f36 9432 * @{
ethaderu 3:78f223d34f36 9433 */
ethaderu 3:78f223d34f36 9434
ethaderu 3:78f223d34f36 9435
ethaderu 3:78f223d34f36 9436 /* NV - Register instance definitions */
ethaderu 3:78f223d34f36 9437 /* FTFE_FlashConfig */
ethaderu 3:78f223d34f36 9438 #define NV_BACKKEY3 NV_BACKKEY3_REG(FTFE_FlashConfig)
ethaderu 3:78f223d34f36 9439 #define NV_BACKKEY2 NV_BACKKEY2_REG(FTFE_FlashConfig)
ethaderu 3:78f223d34f36 9440 #define NV_BACKKEY1 NV_BACKKEY1_REG(FTFE_FlashConfig)
ethaderu 3:78f223d34f36 9441 #define NV_BACKKEY0 NV_BACKKEY0_REG(FTFE_FlashConfig)
ethaderu 3:78f223d34f36 9442 #define NV_BACKKEY7 NV_BACKKEY7_REG(FTFE_FlashConfig)
ethaderu 3:78f223d34f36 9443 #define NV_BACKKEY6 NV_BACKKEY6_REG(FTFE_FlashConfig)
ethaderu 3:78f223d34f36 9444 #define NV_BACKKEY5 NV_BACKKEY5_REG(FTFE_FlashConfig)
ethaderu 3:78f223d34f36 9445 #define NV_BACKKEY4 NV_BACKKEY4_REG(FTFE_FlashConfig)
ethaderu 3:78f223d34f36 9446 #define NV_FPROT3 NV_FPROT3_REG(FTFE_FlashConfig)
ethaderu 3:78f223d34f36 9447 #define NV_FPROT2 NV_FPROT2_REG(FTFE_FlashConfig)
ethaderu 3:78f223d34f36 9448 #define NV_FPROT1 NV_FPROT1_REG(FTFE_FlashConfig)
ethaderu 3:78f223d34f36 9449 #define NV_FPROT0 NV_FPROT0_REG(FTFE_FlashConfig)
ethaderu 3:78f223d34f36 9450 #define NV_FSEC NV_FSEC_REG(FTFE_FlashConfig)
ethaderu 3:78f223d34f36 9451 #define NV_FOPT NV_FOPT_REG(FTFE_FlashConfig)
ethaderu 3:78f223d34f36 9452 #define NV_FEPROT NV_FEPROT_REG(FTFE_FlashConfig)
ethaderu 3:78f223d34f36 9453 #define NV_FDPROT NV_FDPROT_REG(FTFE_FlashConfig)
ethaderu 3:78f223d34f36 9454
ethaderu 3:78f223d34f36 9455 /*!
ethaderu 3:78f223d34f36 9456 * @}
ethaderu 3:78f223d34f36 9457 */ /* end of group NV_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 9458
ethaderu 3:78f223d34f36 9459
ethaderu 3:78f223d34f36 9460 /*!
ethaderu 3:78f223d34f36 9461 * @}
ethaderu 3:78f223d34f36 9462 */ /* end of group NV_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 9463
ethaderu 3:78f223d34f36 9464
ethaderu 3:78f223d34f36 9465 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 9466 -- OSC Peripheral Access Layer
ethaderu 3:78f223d34f36 9467 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 9468
ethaderu 3:78f223d34f36 9469 /*!
ethaderu 3:78f223d34f36 9470 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
ethaderu 3:78f223d34f36 9471 * @{
ethaderu 3:78f223d34f36 9472 */
ethaderu 3:78f223d34f36 9473
ethaderu 3:78f223d34f36 9474 /** OSC - Register Layout Typedef */
ethaderu 3:78f223d34f36 9475 typedef struct {
ethaderu 3:78f223d34f36 9476 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
ethaderu 3:78f223d34f36 9477 } OSC_Type, *OSC_MemMapPtr;
ethaderu 3:78f223d34f36 9478
ethaderu 3:78f223d34f36 9479 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 9480 -- OSC - Register accessor macros
ethaderu 3:78f223d34f36 9481 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 9482
ethaderu 3:78f223d34f36 9483 /*!
ethaderu 3:78f223d34f36 9484 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
ethaderu 3:78f223d34f36 9485 * @{
ethaderu 3:78f223d34f36 9486 */
ethaderu 3:78f223d34f36 9487
ethaderu 3:78f223d34f36 9488
ethaderu 3:78f223d34f36 9489 /* OSC - Register accessors */
ethaderu 3:78f223d34f36 9490 #define OSC_CR_REG(base) ((base)->CR)
ethaderu 3:78f223d34f36 9491
ethaderu 3:78f223d34f36 9492 /*!
ethaderu 3:78f223d34f36 9493 * @}
ethaderu 3:78f223d34f36 9494 */ /* end of group OSC_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 9495
ethaderu 3:78f223d34f36 9496
ethaderu 3:78f223d34f36 9497 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 9498 -- OSC Register Masks
ethaderu 3:78f223d34f36 9499 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 9500
ethaderu 3:78f223d34f36 9501 /*!
ethaderu 3:78f223d34f36 9502 * @addtogroup OSC_Register_Masks OSC Register Masks
ethaderu 3:78f223d34f36 9503 * @{
ethaderu 3:78f223d34f36 9504 */
ethaderu 3:78f223d34f36 9505
ethaderu 3:78f223d34f36 9506 /* CR Bit Fields */
ethaderu 3:78f223d34f36 9507 #define OSC_CR_SC16P_MASK 0x1u
ethaderu 3:78f223d34f36 9508 #define OSC_CR_SC16P_SHIFT 0
ethaderu 3:78f223d34f36 9509 #define OSC_CR_SC8P_MASK 0x2u
ethaderu 3:78f223d34f36 9510 #define OSC_CR_SC8P_SHIFT 1
ethaderu 3:78f223d34f36 9511 #define OSC_CR_SC4P_MASK 0x4u
ethaderu 3:78f223d34f36 9512 #define OSC_CR_SC4P_SHIFT 2
ethaderu 3:78f223d34f36 9513 #define OSC_CR_SC2P_MASK 0x8u
ethaderu 3:78f223d34f36 9514 #define OSC_CR_SC2P_SHIFT 3
ethaderu 3:78f223d34f36 9515 #define OSC_CR_EREFSTEN_MASK 0x20u
ethaderu 3:78f223d34f36 9516 #define OSC_CR_EREFSTEN_SHIFT 5
ethaderu 3:78f223d34f36 9517 #define OSC_CR_ERCLKEN_MASK 0x80u
ethaderu 3:78f223d34f36 9518 #define OSC_CR_ERCLKEN_SHIFT 7
ethaderu 3:78f223d34f36 9519
ethaderu 3:78f223d34f36 9520 /*!
ethaderu 3:78f223d34f36 9521 * @}
ethaderu 3:78f223d34f36 9522 */ /* end of group OSC_Register_Masks */
ethaderu 3:78f223d34f36 9523
ethaderu 3:78f223d34f36 9524
ethaderu 3:78f223d34f36 9525 /* OSC - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 9526 /** Peripheral OSC base address */
ethaderu 3:78f223d34f36 9527 #define OSC_BASE (0x40065000u)
ethaderu 3:78f223d34f36 9528 /** Peripheral OSC base pointer */
ethaderu 3:78f223d34f36 9529 #define OSC ((OSC_Type *)OSC_BASE)
ethaderu 3:78f223d34f36 9530 #define OSC_BASE_PTR (OSC)
ethaderu 3:78f223d34f36 9531 /** Array initializer of OSC peripheral base addresses */
ethaderu 3:78f223d34f36 9532 #define OSC_BASE_ADDRS { OSC_BASE }
ethaderu 3:78f223d34f36 9533 /** Array initializer of OSC peripheral base pointers */
ethaderu 3:78f223d34f36 9534 #define OSC_BASE_PTRS { OSC }
ethaderu 3:78f223d34f36 9535
ethaderu 3:78f223d34f36 9536 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 9537 -- OSC - Register accessor macros
ethaderu 3:78f223d34f36 9538 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 9539
ethaderu 3:78f223d34f36 9540 /*!
ethaderu 3:78f223d34f36 9541 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
ethaderu 3:78f223d34f36 9542 * @{
ethaderu 3:78f223d34f36 9543 */
ethaderu 3:78f223d34f36 9544
ethaderu 3:78f223d34f36 9545
ethaderu 3:78f223d34f36 9546 /* OSC - Register instance definitions */
ethaderu 3:78f223d34f36 9547 /* OSC */
ethaderu 3:78f223d34f36 9548 #define OSC_CR OSC_CR_REG(OSC)
ethaderu 3:78f223d34f36 9549
ethaderu 3:78f223d34f36 9550 /*!
ethaderu 3:78f223d34f36 9551 * @}
ethaderu 3:78f223d34f36 9552 */ /* end of group OSC_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 9553
ethaderu 3:78f223d34f36 9554
ethaderu 3:78f223d34f36 9555 /*!
ethaderu 3:78f223d34f36 9556 * @}
ethaderu 3:78f223d34f36 9557 */ /* end of group OSC_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 9558
ethaderu 3:78f223d34f36 9559
ethaderu 3:78f223d34f36 9560 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 9561 -- PDB Peripheral Access Layer
ethaderu 3:78f223d34f36 9562 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 9563
ethaderu 3:78f223d34f36 9564 /*!
ethaderu 3:78f223d34f36 9565 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
ethaderu 3:78f223d34f36 9566 * @{
ethaderu 3:78f223d34f36 9567 */
ethaderu 3:78f223d34f36 9568
ethaderu 3:78f223d34f36 9569 /** PDB - Register Layout Typedef */
ethaderu 3:78f223d34f36 9570 typedef struct {
ethaderu 3:78f223d34f36 9571 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
ethaderu 3:78f223d34f36 9572 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
ethaderu 3:78f223d34f36 9573 __I uint32_t CNT; /**< Counter register, offset: 0x8 */
ethaderu 3:78f223d34f36 9574 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
ethaderu 3:78f223d34f36 9575 struct { /* offset: 0x10, array step: 0x28 */
ethaderu 3:78f223d34f36 9576 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
ethaderu 3:78f223d34f36 9577 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
ethaderu 3:78f223d34f36 9578 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
ethaderu 3:78f223d34f36 9579 uint8_t RESERVED_0[24];
ethaderu 3:78f223d34f36 9580 } CH[2];
ethaderu 3:78f223d34f36 9581 uint8_t RESERVED_0[240];
ethaderu 3:78f223d34f36 9582 struct { /* offset: 0x150, array step: 0x8 */
ethaderu 3:78f223d34f36 9583 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
ethaderu 3:78f223d34f36 9584 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
ethaderu 3:78f223d34f36 9585 } DAC[2];
ethaderu 3:78f223d34f36 9586 uint8_t RESERVED_1[48];
ethaderu 3:78f223d34f36 9587 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
ethaderu 3:78f223d34f36 9588 __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
ethaderu 3:78f223d34f36 9589 } PDB_Type, *PDB_MemMapPtr;
ethaderu 3:78f223d34f36 9590
ethaderu 3:78f223d34f36 9591 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 9592 -- PDB - Register accessor macros
ethaderu 3:78f223d34f36 9593 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 9594
ethaderu 3:78f223d34f36 9595 /*!
ethaderu 3:78f223d34f36 9596 * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
ethaderu 3:78f223d34f36 9597 * @{
ethaderu 3:78f223d34f36 9598 */
ethaderu 3:78f223d34f36 9599
ethaderu 3:78f223d34f36 9600
ethaderu 3:78f223d34f36 9601 /* PDB - Register accessors */
ethaderu 3:78f223d34f36 9602 #define PDB_SC_REG(base) ((base)->SC)
ethaderu 3:78f223d34f36 9603 #define PDB_MOD_REG(base) ((base)->MOD)
ethaderu 3:78f223d34f36 9604 #define PDB_CNT_REG(base) ((base)->CNT)
ethaderu 3:78f223d34f36 9605 #define PDB_IDLY_REG(base) ((base)->IDLY)
ethaderu 3:78f223d34f36 9606 #define PDB_C1_REG(base,index) ((base)->CH[index].C1)
ethaderu 3:78f223d34f36 9607 #define PDB_S_REG(base,index) ((base)->CH[index].S)
ethaderu 3:78f223d34f36 9608 #define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2])
ethaderu 3:78f223d34f36 9609 #define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC)
ethaderu 3:78f223d34f36 9610 #define PDB_INT_REG(base,index) ((base)->DAC[index].INT)
ethaderu 3:78f223d34f36 9611 #define PDB_POEN_REG(base) ((base)->POEN)
ethaderu 3:78f223d34f36 9612 #define PDB_PODLY_REG(base,index) ((base)->PODLY[index])
ethaderu 3:78f223d34f36 9613
ethaderu 3:78f223d34f36 9614 /*!
ethaderu 3:78f223d34f36 9615 * @}
ethaderu 3:78f223d34f36 9616 */ /* end of group PDB_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 9617
ethaderu 3:78f223d34f36 9618
ethaderu 3:78f223d34f36 9619 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 9620 -- PDB Register Masks
ethaderu 3:78f223d34f36 9621 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 9622
ethaderu 3:78f223d34f36 9623 /*!
ethaderu 3:78f223d34f36 9624 * @addtogroup PDB_Register_Masks PDB Register Masks
ethaderu 3:78f223d34f36 9625 * @{
ethaderu 3:78f223d34f36 9626 */
ethaderu 3:78f223d34f36 9627
ethaderu 3:78f223d34f36 9628 /* SC Bit Fields */
ethaderu 3:78f223d34f36 9629 #define PDB_SC_LDOK_MASK 0x1u
ethaderu 3:78f223d34f36 9630 #define PDB_SC_LDOK_SHIFT 0
ethaderu 3:78f223d34f36 9631 #define PDB_SC_CONT_MASK 0x2u
ethaderu 3:78f223d34f36 9632 #define PDB_SC_CONT_SHIFT 1
ethaderu 3:78f223d34f36 9633 #define PDB_SC_MULT_MASK 0xCu
ethaderu 3:78f223d34f36 9634 #define PDB_SC_MULT_SHIFT 2
ethaderu 3:78f223d34f36 9635 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
ethaderu 3:78f223d34f36 9636 #define PDB_SC_PDBIE_MASK 0x20u
ethaderu 3:78f223d34f36 9637 #define PDB_SC_PDBIE_SHIFT 5
ethaderu 3:78f223d34f36 9638 #define PDB_SC_PDBIF_MASK 0x40u
ethaderu 3:78f223d34f36 9639 #define PDB_SC_PDBIF_SHIFT 6
ethaderu 3:78f223d34f36 9640 #define PDB_SC_PDBEN_MASK 0x80u
ethaderu 3:78f223d34f36 9641 #define PDB_SC_PDBEN_SHIFT 7
ethaderu 3:78f223d34f36 9642 #define PDB_SC_TRGSEL_MASK 0xF00u
ethaderu 3:78f223d34f36 9643 #define PDB_SC_TRGSEL_SHIFT 8
ethaderu 3:78f223d34f36 9644 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
ethaderu 3:78f223d34f36 9645 #define PDB_SC_PRESCALER_MASK 0x7000u
ethaderu 3:78f223d34f36 9646 #define PDB_SC_PRESCALER_SHIFT 12
ethaderu 3:78f223d34f36 9647 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
ethaderu 3:78f223d34f36 9648 #define PDB_SC_DMAEN_MASK 0x8000u
ethaderu 3:78f223d34f36 9649 #define PDB_SC_DMAEN_SHIFT 15
ethaderu 3:78f223d34f36 9650 #define PDB_SC_SWTRIG_MASK 0x10000u
ethaderu 3:78f223d34f36 9651 #define PDB_SC_SWTRIG_SHIFT 16
ethaderu 3:78f223d34f36 9652 #define PDB_SC_PDBEIE_MASK 0x20000u
ethaderu 3:78f223d34f36 9653 #define PDB_SC_PDBEIE_SHIFT 17
ethaderu 3:78f223d34f36 9654 #define PDB_SC_LDMOD_MASK 0xC0000u
ethaderu 3:78f223d34f36 9655 #define PDB_SC_LDMOD_SHIFT 18
ethaderu 3:78f223d34f36 9656 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
ethaderu 3:78f223d34f36 9657 /* MOD Bit Fields */
ethaderu 3:78f223d34f36 9658 #define PDB_MOD_MOD_MASK 0xFFFFu
ethaderu 3:78f223d34f36 9659 #define PDB_MOD_MOD_SHIFT 0
ethaderu 3:78f223d34f36 9660 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
ethaderu 3:78f223d34f36 9661 /* CNT Bit Fields */
ethaderu 3:78f223d34f36 9662 #define PDB_CNT_CNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 9663 #define PDB_CNT_CNT_SHIFT 0
ethaderu 3:78f223d34f36 9664 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
ethaderu 3:78f223d34f36 9665 /* IDLY Bit Fields */
ethaderu 3:78f223d34f36 9666 #define PDB_IDLY_IDLY_MASK 0xFFFFu
ethaderu 3:78f223d34f36 9667 #define PDB_IDLY_IDLY_SHIFT 0
ethaderu 3:78f223d34f36 9668 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
ethaderu 3:78f223d34f36 9669 /* C1 Bit Fields */
ethaderu 3:78f223d34f36 9670 #define PDB_C1_EN_MASK 0xFFu
ethaderu 3:78f223d34f36 9671 #define PDB_C1_EN_SHIFT 0
ethaderu 3:78f223d34f36 9672 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
ethaderu 3:78f223d34f36 9673 #define PDB_C1_TOS_MASK 0xFF00u
ethaderu 3:78f223d34f36 9674 #define PDB_C1_TOS_SHIFT 8
ethaderu 3:78f223d34f36 9675 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
ethaderu 3:78f223d34f36 9676 #define PDB_C1_BB_MASK 0xFF0000u
ethaderu 3:78f223d34f36 9677 #define PDB_C1_BB_SHIFT 16
ethaderu 3:78f223d34f36 9678 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
ethaderu 3:78f223d34f36 9679 /* S Bit Fields */
ethaderu 3:78f223d34f36 9680 #define PDB_S_ERR_MASK 0xFFu
ethaderu 3:78f223d34f36 9681 #define PDB_S_ERR_SHIFT 0
ethaderu 3:78f223d34f36 9682 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
ethaderu 3:78f223d34f36 9683 #define PDB_S_CF_MASK 0xFF0000u
ethaderu 3:78f223d34f36 9684 #define PDB_S_CF_SHIFT 16
ethaderu 3:78f223d34f36 9685 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
ethaderu 3:78f223d34f36 9686 /* DLY Bit Fields */
ethaderu 3:78f223d34f36 9687 #define PDB_DLY_DLY_MASK 0xFFFFu
ethaderu 3:78f223d34f36 9688 #define PDB_DLY_DLY_SHIFT 0
ethaderu 3:78f223d34f36 9689 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
ethaderu 3:78f223d34f36 9690 /* INTC Bit Fields */
ethaderu 3:78f223d34f36 9691 #define PDB_INTC_TOE_MASK 0x1u
ethaderu 3:78f223d34f36 9692 #define PDB_INTC_TOE_SHIFT 0
ethaderu 3:78f223d34f36 9693 #define PDB_INTC_EXT_MASK 0x2u
ethaderu 3:78f223d34f36 9694 #define PDB_INTC_EXT_SHIFT 1
ethaderu 3:78f223d34f36 9695 /* INT Bit Fields */
ethaderu 3:78f223d34f36 9696 #define PDB_INT_INT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 9697 #define PDB_INT_INT_SHIFT 0
ethaderu 3:78f223d34f36 9698 #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
ethaderu 3:78f223d34f36 9699 /* POEN Bit Fields */
ethaderu 3:78f223d34f36 9700 #define PDB_POEN_POEN_MASK 0xFFu
ethaderu 3:78f223d34f36 9701 #define PDB_POEN_POEN_SHIFT 0
ethaderu 3:78f223d34f36 9702 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
ethaderu 3:78f223d34f36 9703 /* PODLY Bit Fields */
ethaderu 3:78f223d34f36 9704 #define PDB_PODLY_DLY2_MASK 0xFFFFu
ethaderu 3:78f223d34f36 9705 #define PDB_PODLY_DLY2_SHIFT 0
ethaderu 3:78f223d34f36 9706 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
ethaderu 3:78f223d34f36 9707 #define PDB_PODLY_DLY1_MASK 0xFFFF0000u
ethaderu 3:78f223d34f36 9708 #define PDB_PODLY_DLY1_SHIFT 16
ethaderu 3:78f223d34f36 9709 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
ethaderu 3:78f223d34f36 9710
ethaderu 3:78f223d34f36 9711 /*!
ethaderu 3:78f223d34f36 9712 * @}
ethaderu 3:78f223d34f36 9713 */ /* end of group PDB_Register_Masks */
ethaderu 3:78f223d34f36 9714
ethaderu 3:78f223d34f36 9715
ethaderu 3:78f223d34f36 9716 /* PDB - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 9717 /** Peripheral PDB0 base address */
ethaderu 3:78f223d34f36 9718 #define PDB0_BASE (0x40036000u)
ethaderu 3:78f223d34f36 9719 /** Peripheral PDB0 base pointer */
ethaderu 3:78f223d34f36 9720 #define PDB0 ((PDB_Type *)PDB0_BASE)
ethaderu 3:78f223d34f36 9721 #define PDB0_BASE_PTR (PDB0)
ethaderu 3:78f223d34f36 9722 /** Array initializer of PDB peripheral base addresses */
ethaderu 3:78f223d34f36 9723 #define PDB_BASE_ADDRS { PDB0_BASE }
ethaderu 3:78f223d34f36 9724 /** Array initializer of PDB peripheral base pointers */
ethaderu 3:78f223d34f36 9725 #define PDB_BASE_PTRS { PDB0 }
ethaderu 3:78f223d34f36 9726 /** Interrupt vectors for the PDB peripheral type */
ethaderu 3:78f223d34f36 9727 #define PDB_IRQS { PDB0_IRQn }
ethaderu 3:78f223d34f36 9728
ethaderu 3:78f223d34f36 9729 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 9730 -- PDB - Register accessor macros
ethaderu 3:78f223d34f36 9731 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 9732
ethaderu 3:78f223d34f36 9733 /*!
ethaderu 3:78f223d34f36 9734 * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
ethaderu 3:78f223d34f36 9735 * @{
ethaderu 3:78f223d34f36 9736 */
ethaderu 3:78f223d34f36 9737
ethaderu 3:78f223d34f36 9738
ethaderu 3:78f223d34f36 9739 /* PDB - Register instance definitions */
ethaderu 3:78f223d34f36 9740 /* PDB0 */
ethaderu 3:78f223d34f36 9741 #define PDB0_SC PDB_SC_REG(PDB0)
ethaderu 3:78f223d34f36 9742 #define PDB0_MOD PDB_MOD_REG(PDB0)
ethaderu 3:78f223d34f36 9743 #define PDB0_CNT PDB_CNT_REG(PDB0)
ethaderu 3:78f223d34f36 9744 #define PDB0_IDLY PDB_IDLY_REG(PDB0)
ethaderu 3:78f223d34f36 9745 #define PDB0_CH0C1 PDB_C1_REG(PDB0,0)
ethaderu 3:78f223d34f36 9746 #define PDB0_CH0S PDB_S_REG(PDB0,0)
ethaderu 3:78f223d34f36 9747 #define PDB0_CH0DLY0 PDB_DLY_REG(PDB0,0,0)
ethaderu 3:78f223d34f36 9748 #define PDB0_CH0DLY1 PDB_DLY_REG(PDB0,0,1)
ethaderu 3:78f223d34f36 9749 #define PDB0_CH1C1 PDB_C1_REG(PDB0,1)
ethaderu 3:78f223d34f36 9750 #define PDB0_CH1S PDB_S_REG(PDB0,1)
ethaderu 3:78f223d34f36 9751 #define PDB0_CH1DLY0 PDB_DLY_REG(PDB0,1,0)
ethaderu 3:78f223d34f36 9752 #define PDB0_CH1DLY1 PDB_DLY_REG(PDB0,1,1)
ethaderu 3:78f223d34f36 9753 #define PDB0_DACINTC0 PDB_INTC_REG(PDB0,0)
ethaderu 3:78f223d34f36 9754 #define PDB0_DACINT0 PDB_INT_REG(PDB0,0)
ethaderu 3:78f223d34f36 9755 #define PDB0_DACINTC1 PDB_INTC_REG(PDB0,1)
ethaderu 3:78f223d34f36 9756 #define PDB0_DACINT1 PDB_INT_REG(PDB0,1)
ethaderu 3:78f223d34f36 9757 #define PDB0_POEN PDB_POEN_REG(PDB0)
ethaderu 3:78f223d34f36 9758 #define PDB0_PO0DLY PDB_PODLY_REG(PDB0,0)
ethaderu 3:78f223d34f36 9759 #define PDB0_PO1DLY PDB_PODLY_REG(PDB0,1)
ethaderu 3:78f223d34f36 9760 #define PDB0_PO2DLY PDB_PODLY_REG(PDB0,2)
ethaderu 3:78f223d34f36 9761
ethaderu 3:78f223d34f36 9762 /* PDB - Register array accessors */
ethaderu 3:78f223d34f36 9763 #define PDB0_C1(index) PDB_C1_REG(PDB0,index)
ethaderu 3:78f223d34f36 9764 #define PDB0_S(index) PDB_S_REG(PDB0,index)
ethaderu 3:78f223d34f36 9765 #define PDB0_DLY(index,index2) PDB_DLY_REG(PDB0,index,index2)
ethaderu 3:78f223d34f36 9766 #define PDB0_INTC(index) PDB_INTC_REG(PDB0,index)
ethaderu 3:78f223d34f36 9767 #define PDB0_INT(index) PDB_INT_REG(PDB0,index)
ethaderu 3:78f223d34f36 9768 #define PDB0_PODLY(index) PDB_PODLY_REG(PDB0,index)
ethaderu 3:78f223d34f36 9769
ethaderu 3:78f223d34f36 9770 /*!
ethaderu 3:78f223d34f36 9771 * @}
ethaderu 3:78f223d34f36 9772 */ /* end of group PDB_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 9773
ethaderu 3:78f223d34f36 9774
ethaderu 3:78f223d34f36 9775 /*!
ethaderu 3:78f223d34f36 9776 * @}
ethaderu 3:78f223d34f36 9777 */ /* end of group PDB_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 9778
ethaderu 3:78f223d34f36 9779
ethaderu 3:78f223d34f36 9780 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 9781 -- PIT Peripheral Access Layer
ethaderu 3:78f223d34f36 9782 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 9783
ethaderu 3:78f223d34f36 9784 /*!
ethaderu 3:78f223d34f36 9785 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
ethaderu 3:78f223d34f36 9786 * @{
ethaderu 3:78f223d34f36 9787 */
ethaderu 3:78f223d34f36 9788
ethaderu 3:78f223d34f36 9789 /** PIT - Register Layout Typedef */
ethaderu 3:78f223d34f36 9790 typedef struct {
ethaderu 3:78f223d34f36 9791 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
ethaderu 3:78f223d34f36 9792 uint8_t RESERVED_0[252];
ethaderu 3:78f223d34f36 9793 struct { /* offset: 0x100, array step: 0x10 */
ethaderu 3:78f223d34f36 9794 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
ethaderu 3:78f223d34f36 9795 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
ethaderu 3:78f223d34f36 9796 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
ethaderu 3:78f223d34f36 9797 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
ethaderu 3:78f223d34f36 9798 } CHANNEL[4];
ethaderu 3:78f223d34f36 9799 } PIT_Type, *PIT_MemMapPtr;
ethaderu 3:78f223d34f36 9800
ethaderu 3:78f223d34f36 9801 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 9802 -- PIT - Register accessor macros
ethaderu 3:78f223d34f36 9803 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 9804
ethaderu 3:78f223d34f36 9805 /*!
ethaderu 3:78f223d34f36 9806 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
ethaderu 3:78f223d34f36 9807 * @{
ethaderu 3:78f223d34f36 9808 */
ethaderu 3:78f223d34f36 9809
ethaderu 3:78f223d34f36 9810
ethaderu 3:78f223d34f36 9811 /* PIT - Register accessors */
ethaderu 3:78f223d34f36 9812 #define PIT_MCR_REG(base) ((base)->MCR)
ethaderu 3:78f223d34f36 9813 #define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
ethaderu 3:78f223d34f36 9814 #define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
ethaderu 3:78f223d34f36 9815 #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
ethaderu 3:78f223d34f36 9816 #define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
ethaderu 3:78f223d34f36 9817
ethaderu 3:78f223d34f36 9818 /*!
ethaderu 3:78f223d34f36 9819 * @}
ethaderu 3:78f223d34f36 9820 */ /* end of group PIT_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 9821
ethaderu 3:78f223d34f36 9822
ethaderu 3:78f223d34f36 9823 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 9824 -- PIT Register Masks
ethaderu 3:78f223d34f36 9825 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 9826
ethaderu 3:78f223d34f36 9827 /*!
ethaderu 3:78f223d34f36 9828 * @addtogroup PIT_Register_Masks PIT Register Masks
ethaderu 3:78f223d34f36 9829 * @{
ethaderu 3:78f223d34f36 9830 */
ethaderu 3:78f223d34f36 9831
ethaderu 3:78f223d34f36 9832 /* MCR Bit Fields */
ethaderu 3:78f223d34f36 9833 #define PIT_MCR_FRZ_MASK 0x1u
ethaderu 3:78f223d34f36 9834 #define PIT_MCR_FRZ_SHIFT 0
ethaderu 3:78f223d34f36 9835 #define PIT_MCR_MDIS_MASK 0x2u
ethaderu 3:78f223d34f36 9836 #define PIT_MCR_MDIS_SHIFT 1
ethaderu 3:78f223d34f36 9837 /* LDVAL Bit Fields */
ethaderu 3:78f223d34f36 9838 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 9839 #define PIT_LDVAL_TSV_SHIFT 0
ethaderu 3:78f223d34f36 9840 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
ethaderu 3:78f223d34f36 9841 /* CVAL Bit Fields */
ethaderu 3:78f223d34f36 9842 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 9843 #define PIT_CVAL_TVL_SHIFT 0
ethaderu 3:78f223d34f36 9844 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
ethaderu 3:78f223d34f36 9845 /* TCTRL Bit Fields */
ethaderu 3:78f223d34f36 9846 #define PIT_TCTRL_TEN_MASK 0x1u
ethaderu 3:78f223d34f36 9847 #define PIT_TCTRL_TEN_SHIFT 0
ethaderu 3:78f223d34f36 9848 #define PIT_TCTRL_TIE_MASK 0x2u
ethaderu 3:78f223d34f36 9849 #define PIT_TCTRL_TIE_SHIFT 1
ethaderu 3:78f223d34f36 9850 #define PIT_TCTRL_CHN_MASK 0x4u
ethaderu 3:78f223d34f36 9851 #define PIT_TCTRL_CHN_SHIFT 2
ethaderu 3:78f223d34f36 9852 /* TFLG Bit Fields */
ethaderu 3:78f223d34f36 9853 #define PIT_TFLG_TIF_MASK 0x1u
ethaderu 3:78f223d34f36 9854 #define PIT_TFLG_TIF_SHIFT 0
ethaderu 3:78f223d34f36 9855
ethaderu 3:78f223d34f36 9856 /*!
ethaderu 3:78f223d34f36 9857 * @}
ethaderu 3:78f223d34f36 9858 */ /* end of group PIT_Register_Masks */
ethaderu 3:78f223d34f36 9859
ethaderu 3:78f223d34f36 9860
ethaderu 3:78f223d34f36 9861 /* PIT - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 9862 /** Peripheral PIT base address */
ethaderu 3:78f223d34f36 9863 #define PIT_BASE (0x40037000u)
ethaderu 3:78f223d34f36 9864 /** Peripheral PIT base pointer */
ethaderu 3:78f223d34f36 9865 #define PIT ((PIT_Type *)PIT_BASE)
ethaderu 3:78f223d34f36 9866 #define PIT_BASE_PTR (PIT)
ethaderu 3:78f223d34f36 9867 /** Array initializer of PIT peripheral base addresses */
ethaderu 3:78f223d34f36 9868 #define PIT_BASE_ADDRS { PIT_BASE }
ethaderu 3:78f223d34f36 9869 /** Array initializer of PIT peripheral base pointers */
ethaderu 3:78f223d34f36 9870 #define PIT_BASE_PTRS { PIT }
ethaderu 3:78f223d34f36 9871 /** Interrupt vectors for the PIT peripheral type */
ethaderu 3:78f223d34f36 9872 #define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
ethaderu 3:78f223d34f36 9873
ethaderu 3:78f223d34f36 9874 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 9875 -- PIT - Register accessor macros
ethaderu 3:78f223d34f36 9876 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 9877
ethaderu 3:78f223d34f36 9878 /*!
ethaderu 3:78f223d34f36 9879 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
ethaderu 3:78f223d34f36 9880 * @{
ethaderu 3:78f223d34f36 9881 */
ethaderu 3:78f223d34f36 9882
ethaderu 3:78f223d34f36 9883
ethaderu 3:78f223d34f36 9884 /* PIT - Register instance definitions */
ethaderu 3:78f223d34f36 9885 /* PIT */
ethaderu 3:78f223d34f36 9886 #define PIT_MCR PIT_MCR_REG(PIT)
ethaderu 3:78f223d34f36 9887 #define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
ethaderu 3:78f223d34f36 9888 #define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
ethaderu 3:78f223d34f36 9889 #define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
ethaderu 3:78f223d34f36 9890 #define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
ethaderu 3:78f223d34f36 9891 #define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
ethaderu 3:78f223d34f36 9892 #define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
ethaderu 3:78f223d34f36 9893 #define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
ethaderu 3:78f223d34f36 9894 #define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
ethaderu 3:78f223d34f36 9895 #define PIT_LDVAL2 PIT_LDVAL_REG(PIT,2)
ethaderu 3:78f223d34f36 9896 #define PIT_CVAL2 PIT_CVAL_REG(PIT,2)
ethaderu 3:78f223d34f36 9897 #define PIT_TCTRL2 PIT_TCTRL_REG(PIT,2)
ethaderu 3:78f223d34f36 9898 #define PIT_TFLG2 PIT_TFLG_REG(PIT,2)
ethaderu 3:78f223d34f36 9899 #define PIT_LDVAL3 PIT_LDVAL_REG(PIT,3)
ethaderu 3:78f223d34f36 9900 #define PIT_CVAL3 PIT_CVAL_REG(PIT,3)
ethaderu 3:78f223d34f36 9901 #define PIT_TCTRL3 PIT_TCTRL_REG(PIT,3)
ethaderu 3:78f223d34f36 9902 #define PIT_TFLG3 PIT_TFLG_REG(PIT,3)
ethaderu 3:78f223d34f36 9903
ethaderu 3:78f223d34f36 9904 /* PIT - Register array accessors */
ethaderu 3:78f223d34f36 9905 #define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
ethaderu 3:78f223d34f36 9906 #define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
ethaderu 3:78f223d34f36 9907 #define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
ethaderu 3:78f223d34f36 9908 #define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
ethaderu 3:78f223d34f36 9909
ethaderu 3:78f223d34f36 9910 /*!
ethaderu 3:78f223d34f36 9911 * @}
ethaderu 3:78f223d34f36 9912 */ /* end of group PIT_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 9913
ethaderu 3:78f223d34f36 9914
ethaderu 3:78f223d34f36 9915 /*!
ethaderu 3:78f223d34f36 9916 * @}
ethaderu 3:78f223d34f36 9917 */ /* end of group PIT_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 9918
ethaderu 3:78f223d34f36 9919
ethaderu 3:78f223d34f36 9920 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 9921 -- PMC Peripheral Access Layer
ethaderu 3:78f223d34f36 9922 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 9923
ethaderu 3:78f223d34f36 9924 /*!
ethaderu 3:78f223d34f36 9925 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
ethaderu 3:78f223d34f36 9926 * @{
ethaderu 3:78f223d34f36 9927 */
ethaderu 3:78f223d34f36 9928
ethaderu 3:78f223d34f36 9929 /** PMC - Register Layout Typedef */
ethaderu 3:78f223d34f36 9930 typedef struct {
ethaderu 3:78f223d34f36 9931 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
ethaderu 3:78f223d34f36 9932 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
ethaderu 3:78f223d34f36 9933 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
ethaderu 3:78f223d34f36 9934 } PMC_Type, *PMC_MemMapPtr;
ethaderu 3:78f223d34f36 9935
ethaderu 3:78f223d34f36 9936 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 9937 -- PMC - Register accessor macros
ethaderu 3:78f223d34f36 9938 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 9939
ethaderu 3:78f223d34f36 9940 /*!
ethaderu 3:78f223d34f36 9941 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
ethaderu 3:78f223d34f36 9942 * @{
ethaderu 3:78f223d34f36 9943 */
ethaderu 3:78f223d34f36 9944
ethaderu 3:78f223d34f36 9945
ethaderu 3:78f223d34f36 9946 /* PMC - Register accessors */
ethaderu 3:78f223d34f36 9947 #define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
ethaderu 3:78f223d34f36 9948 #define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
ethaderu 3:78f223d34f36 9949 #define PMC_REGSC_REG(base) ((base)->REGSC)
ethaderu 3:78f223d34f36 9950
ethaderu 3:78f223d34f36 9951 /*!
ethaderu 3:78f223d34f36 9952 * @}
ethaderu 3:78f223d34f36 9953 */ /* end of group PMC_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 9954
ethaderu 3:78f223d34f36 9955
ethaderu 3:78f223d34f36 9956 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 9957 -- PMC Register Masks
ethaderu 3:78f223d34f36 9958 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 9959
ethaderu 3:78f223d34f36 9960 /*!
ethaderu 3:78f223d34f36 9961 * @addtogroup PMC_Register_Masks PMC Register Masks
ethaderu 3:78f223d34f36 9962 * @{
ethaderu 3:78f223d34f36 9963 */
ethaderu 3:78f223d34f36 9964
ethaderu 3:78f223d34f36 9965 /* LVDSC1 Bit Fields */
ethaderu 3:78f223d34f36 9966 #define PMC_LVDSC1_LVDV_MASK 0x3u
ethaderu 3:78f223d34f36 9967 #define PMC_LVDSC1_LVDV_SHIFT 0
ethaderu 3:78f223d34f36 9968 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
ethaderu 3:78f223d34f36 9969 #define PMC_LVDSC1_LVDRE_MASK 0x10u
ethaderu 3:78f223d34f36 9970 #define PMC_LVDSC1_LVDRE_SHIFT 4
ethaderu 3:78f223d34f36 9971 #define PMC_LVDSC1_LVDIE_MASK 0x20u
ethaderu 3:78f223d34f36 9972 #define PMC_LVDSC1_LVDIE_SHIFT 5
ethaderu 3:78f223d34f36 9973 #define PMC_LVDSC1_LVDACK_MASK 0x40u
ethaderu 3:78f223d34f36 9974 #define PMC_LVDSC1_LVDACK_SHIFT 6
ethaderu 3:78f223d34f36 9975 #define PMC_LVDSC1_LVDF_MASK 0x80u
ethaderu 3:78f223d34f36 9976 #define PMC_LVDSC1_LVDF_SHIFT 7
ethaderu 3:78f223d34f36 9977 /* LVDSC2 Bit Fields */
ethaderu 3:78f223d34f36 9978 #define PMC_LVDSC2_LVWV_MASK 0x3u
ethaderu 3:78f223d34f36 9979 #define PMC_LVDSC2_LVWV_SHIFT 0
ethaderu 3:78f223d34f36 9980 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
ethaderu 3:78f223d34f36 9981 #define PMC_LVDSC2_LVWIE_MASK 0x20u
ethaderu 3:78f223d34f36 9982 #define PMC_LVDSC2_LVWIE_SHIFT 5
ethaderu 3:78f223d34f36 9983 #define PMC_LVDSC2_LVWACK_MASK 0x40u
ethaderu 3:78f223d34f36 9984 #define PMC_LVDSC2_LVWACK_SHIFT 6
ethaderu 3:78f223d34f36 9985 #define PMC_LVDSC2_LVWF_MASK 0x80u
ethaderu 3:78f223d34f36 9986 #define PMC_LVDSC2_LVWF_SHIFT 7
ethaderu 3:78f223d34f36 9987 /* REGSC Bit Fields */
ethaderu 3:78f223d34f36 9988 #define PMC_REGSC_BGBE_MASK 0x1u
ethaderu 3:78f223d34f36 9989 #define PMC_REGSC_BGBE_SHIFT 0
ethaderu 3:78f223d34f36 9990 #define PMC_REGSC_REGONS_MASK 0x4u
ethaderu 3:78f223d34f36 9991 #define PMC_REGSC_REGONS_SHIFT 2
ethaderu 3:78f223d34f36 9992 #define PMC_REGSC_ACKISO_MASK 0x8u
ethaderu 3:78f223d34f36 9993 #define PMC_REGSC_ACKISO_SHIFT 3
ethaderu 3:78f223d34f36 9994 #define PMC_REGSC_BGEN_MASK 0x10u
ethaderu 3:78f223d34f36 9995 #define PMC_REGSC_BGEN_SHIFT 4
ethaderu 3:78f223d34f36 9996
ethaderu 3:78f223d34f36 9997 /*!
ethaderu 3:78f223d34f36 9998 * @}
ethaderu 3:78f223d34f36 9999 */ /* end of group PMC_Register_Masks */
ethaderu 3:78f223d34f36 10000
ethaderu 3:78f223d34f36 10001
ethaderu 3:78f223d34f36 10002 /* PMC - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 10003 /** Peripheral PMC base address */
ethaderu 3:78f223d34f36 10004 #define PMC_BASE (0x4007D000u)
ethaderu 3:78f223d34f36 10005 /** Peripheral PMC base pointer */
ethaderu 3:78f223d34f36 10006 #define PMC ((PMC_Type *)PMC_BASE)
ethaderu 3:78f223d34f36 10007 #define PMC_BASE_PTR (PMC)
ethaderu 3:78f223d34f36 10008 /** Array initializer of PMC peripheral base addresses */
ethaderu 3:78f223d34f36 10009 #define PMC_BASE_ADDRS { PMC_BASE }
ethaderu 3:78f223d34f36 10010 /** Array initializer of PMC peripheral base pointers */
ethaderu 3:78f223d34f36 10011 #define PMC_BASE_PTRS { PMC }
ethaderu 3:78f223d34f36 10012 /** Interrupt vectors for the PMC peripheral type */
ethaderu 3:78f223d34f36 10013 #define PMC_IRQS { LVD_LVW_IRQn }
ethaderu 3:78f223d34f36 10014
ethaderu 3:78f223d34f36 10015 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10016 -- PMC - Register accessor macros
ethaderu 3:78f223d34f36 10017 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10018
ethaderu 3:78f223d34f36 10019 /*!
ethaderu 3:78f223d34f36 10020 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
ethaderu 3:78f223d34f36 10021 * @{
ethaderu 3:78f223d34f36 10022 */
ethaderu 3:78f223d34f36 10023
ethaderu 3:78f223d34f36 10024
ethaderu 3:78f223d34f36 10025 /* PMC - Register instance definitions */
ethaderu 3:78f223d34f36 10026 /* PMC */
ethaderu 3:78f223d34f36 10027 #define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
ethaderu 3:78f223d34f36 10028 #define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
ethaderu 3:78f223d34f36 10029 #define PMC_REGSC PMC_REGSC_REG(PMC)
ethaderu 3:78f223d34f36 10030
ethaderu 3:78f223d34f36 10031 /*!
ethaderu 3:78f223d34f36 10032 * @}
ethaderu 3:78f223d34f36 10033 */ /* end of group PMC_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 10034
ethaderu 3:78f223d34f36 10035
ethaderu 3:78f223d34f36 10036 /*!
ethaderu 3:78f223d34f36 10037 * @}
ethaderu 3:78f223d34f36 10038 */ /* end of group PMC_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 10039
ethaderu 3:78f223d34f36 10040
ethaderu 3:78f223d34f36 10041 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10042 -- PORT Peripheral Access Layer
ethaderu 3:78f223d34f36 10043 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10044
ethaderu 3:78f223d34f36 10045 /*!
ethaderu 3:78f223d34f36 10046 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
ethaderu 3:78f223d34f36 10047 * @{
ethaderu 3:78f223d34f36 10048 */
ethaderu 3:78f223d34f36 10049
ethaderu 3:78f223d34f36 10050 /** PORT - Register Layout Typedef */
ethaderu 3:78f223d34f36 10051 typedef struct {
ethaderu 3:78f223d34f36 10052 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
ethaderu 3:78f223d34f36 10053 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
ethaderu 3:78f223d34f36 10054 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
ethaderu 3:78f223d34f36 10055 uint8_t RESERVED_0[24];
ethaderu 3:78f223d34f36 10056 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
ethaderu 3:78f223d34f36 10057 uint8_t RESERVED_1[28];
ethaderu 3:78f223d34f36 10058 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
ethaderu 3:78f223d34f36 10059 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
ethaderu 3:78f223d34f36 10060 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
ethaderu 3:78f223d34f36 10061 } PORT_Type, *PORT_MemMapPtr;
ethaderu 3:78f223d34f36 10062
ethaderu 3:78f223d34f36 10063 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10064 -- PORT - Register accessor macros
ethaderu 3:78f223d34f36 10065 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10066
ethaderu 3:78f223d34f36 10067 /*!
ethaderu 3:78f223d34f36 10068 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
ethaderu 3:78f223d34f36 10069 * @{
ethaderu 3:78f223d34f36 10070 */
ethaderu 3:78f223d34f36 10071
ethaderu 3:78f223d34f36 10072
ethaderu 3:78f223d34f36 10073 /* PORT - Register accessors */
ethaderu 3:78f223d34f36 10074 #define PORT_PCR_REG(base,index) ((base)->PCR[index])
ethaderu 3:78f223d34f36 10075 #define PORT_GPCLR_REG(base) ((base)->GPCLR)
ethaderu 3:78f223d34f36 10076 #define PORT_GPCHR_REG(base) ((base)->GPCHR)
ethaderu 3:78f223d34f36 10077 #define PORT_ISFR_REG(base) ((base)->ISFR)
ethaderu 3:78f223d34f36 10078 #define PORT_DFER_REG(base) ((base)->DFER)
ethaderu 3:78f223d34f36 10079 #define PORT_DFCR_REG(base) ((base)->DFCR)
ethaderu 3:78f223d34f36 10080 #define PORT_DFWR_REG(base) ((base)->DFWR)
ethaderu 3:78f223d34f36 10081
ethaderu 3:78f223d34f36 10082 /*!
ethaderu 3:78f223d34f36 10083 * @}
ethaderu 3:78f223d34f36 10084 */ /* end of group PORT_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 10085
ethaderu 3:78f223d34f36 10086
ethaderu 3:78f223d34f36 10087 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10088 -- PORT Register Masks
ethaderu 3:78f223d34f36 10089 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10090
ethaderu 3:78f223d34f36 10091 /*!
ethaderu 3:78f223d34f36 10092 * @addtogroup PORT_Register_Masks PORT Register Masks
ethaderu 3:78f223d34f36 10093 * @{
ethaderu 3:78f223d34f36 10094 */
ethaderu 3:78f223d34f36 10095
ethaderu 3:78f223d34f36 10096 /* PCR Bit Fields */
ethaderu 3:78f223d34f36 10097 #define PORT_PCR_PS_MASK 0x1u
ethaderu 3:78f223d34f36 10098 #define PORT_PCR_PS_SHIFT 0
ethaderu 3:78f223d34f36 10099 #define PORT_PCR_PE_MASK 0x2u
ethaderu 3:78f223d34f36 10100 #define PORT_PCR_PE_SHIFT 1
ethaderu 3:78f223d34f36 10101 #define PORT_PCR_SRE_MASK 0x4u
ethaderu 3:78f223d34f36 10102 #define PORT_PCR_SRE_SHIFT 2
ethaderu 3:78f223d34f36 10103 #define PORT_PCR_PFE_MASK 0x10u
ethaderu 3:78f223d34f36 10104 #define PORT_PCR_PFE_SHIFT 4
ethaderu 3:78f223d34f36 10105 #define PORT_PCR_ODE_MASK 0x20u
ethaderu 3:78f223d34f36 10106 #define PORT_PCR_ODE_SHIFT 5
ethaderu 3:78f223d34f36 10107 #define PORT_PCR_DSE_MASK 0x40u
ethaderu 3:78f223d34f36 10108 #define PORT_PCR_DSE_SHIFT 6
ethaderu 3:78f223d34f36 10109 #define PORT_PCR_MUX_MASK 0x700u
ethaderu 3:78f223d34f36 10110 #define PORT_PCR_MUX_SHIFT 8
ethaderu 3:78f223d34f36 10111 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
ethaderu 3:78f223d34f36 10112 #define PORT_PCR_LK_MASK 0x8000u
ethaderu 3:78f223d34f36 10113 #define PORT_PCR_LK_SHIFT 15
ethaderu 3:78f223d34f36 10114 #define PORT_PCR_IRQC_MASK 0xF0000u
ethaderu 3:78f223d34f36 10115 #define PORT_PCR_IRQC_SHIFT 16
ethaderu 3:78f223d34f36 10116 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
ethaderu 3:78f223d34f36 10117 #define PORT_PCR_ISF_MASK 0x1000000u
ethaderu 3:78f223d34f36 10118 #define PORT_PCR_ISF_SHIFT 24
ethaderu 3:78f223d34f36 10119 /* GPCLR Bit Fields */
ethaderu 3:78f223d34f36 10120 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
ethaderu 3:78f223d34f36 10121 #define PORT_GPCLR_GPWD_SHIFT 0
ethaderu 3:78f223d34f36 10122 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
ethaderu 3:78f223d34f36 10123 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
ethaderu 3:78f223d34f36 10124 #define PORT_GPCLR_GPWE_SHIFT 16
ethaderu 3:78f223d34f36 10125 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
ethaderu 3:78f223d34f36 10126 /* GPCHR Bit Fields */
ethaderu 3:78f223d34f36 10127 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
ethaderu 3:78f223d34f36 10128 #define PORT_GPCHR_GPWD_SHIFT 0
ethaderu 3:78f223d34f36 10129 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
ethaderu 3:78f223d34f36 10130 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
ethaderu 3:78f223d34f36 10131 #define PORT_GPCHR_GPWE_SHIFT 16
ethaderu 3:78f223d34f36 10132 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
ethaderu 3:78f223d34f36 10133 /* ISFR Bit Fields */
ethaderu 3:78f223d34f36 10134 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 10135 #define PORT_ISFR_ISF_SHIFT 0
ethaderu 3:78f223d34f36 10136 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
ethaderu 3:78f223d34f36 10137 /* DFER Bit Fields */
ethaderu 3:78f223d34f36 10138 #define PORT_DFER_DFE_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 10139 #define PORT_DFER_DFE_SHIFT 0
ethaderu 3:78f223d34f36 10140 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
ethaderu 3:78f223d34f36 10141 /* DFCR Bit Fields */
ethaderu 3:78f223d34f36 10142 #define PORT_DFCR_CS_MASK 0x1u
ethaderu 3:78f223d34f36 10143 #define PORT_DFCR_CS_SHIFT 0
ethaderu 3:78f223d34f36 10144 /* DFWR Bit Fields */
ethaderu 3:78f223d34f36 10145 #define PORT_DFWR_FILT_MASK 0x1Fu
ethaderu 3:78f223d34f36 10146 #define PORT_DFWR_FILT_SHIFT 0
ethaderu 3:78f223d34f36 10147 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
ethaderu 3:78f223d34f36 10148
ethaderu 3:78f223d34f36 10149 /*!
ethaderu 3:78f223d34f36 10150 * @}
ethaderu 3:78f223d34f36 10151 */ /* end of group PORT_Register_Masks */
ethaderu 3:78f223d34f36 10152
ethaderu 3:78f223d34f36 10153
ethaderu 3:78f223d34f36 10154 /* PORT - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 10155 /** Peripheral PORTA base address */
ethaderu 3:78f223d34f36 10156 #define PORTA_BASE (0x40049000u)
ethaderu 3:78f223d34f36 10157 /** Peripheral PORTA base pointer */
ethaderu 3:78f223d34f36 10158 #define PORTA ((PORT_Type *)PORTA_BASE)
ethaderu 3:78f223d34f36 10159 #define PORTA_BASE_PTR (PORTA)
ethaderu 3:78f223d34f36 10160 /** Peripheral PORTB base address */
ethaderu 3:78f223d34f36 10161 #define PORTB_BASE (0x4004A000u)
ethaderu 3:78f223d34f36 10162 /** Peripheral PORTB base pointer */
ethaderu 3:78f223d34f36 10163 #define PORTB ((PORT_Type *)PORTB_BASE)
ethaderu 3:78f223d34f36 10164 #define PORTB_BASE_PTR (PORTB)
ethaderu 3:78f223d34f36 10165 /** Peripheral PORTC base address */
ethaderu 3:78f223d34f36 10166 #define PORTC_BASE (0x4004B000u)
ethaderu 3:78f223d34f36 10167 /** Peripheral PORTC base pointer */
ethaderu 3:78f223d34f36 10168 #define PORTC ((PORT_Type *)PORTC_BASE)
ethaderu 3:78f223d34f36 10169 #define PORTC_BASE_PTR (PORTC)
ethaderu 3:78f223d34f36 10170 /** Peripheral PORTD base address */
ethaderu 3:78f223d34f36 10171 #define PORTD_BASE (0x4004C000u)
ethaderu 3:78f223d34f36 10172 /** Peripheral PORTD base pointer */
ethaderu 3:78f223d34f36 10173 #define PORTD ((PORT_Type *)PORTD_BASE)
ethaderu 3:78f223d34f36 10174 #define PORTD_BASE_PTR (PORTD)
ethaderu 3:78f223d34f36 10175 /** Peripheral PORTE base address */
ethaderu 3:78f223d34f36 10176 #define PORTE_BASE (0x4004D000u)
ethaderu 3:78f223d34f36 10177 /** Peripheral PORTE base pointer */
ethaderu 3:78f223d34f36 10178 #define PORTE ((PORT_Type *)PORTE_BASE)
ethaderu 3:78f223d34f36 10179 #define PORTE_BASE_PTR (PORTE)
ethaderu 3:78f223d34f36 10180 /** Array initializer of PORT peripheral base addresses */
ethaderu 3:78f223d34f36 10181 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
ethaderu 3:78f223d34f36 10182 /** Array initializer of PORT peripheral base pointers */
ethaderu 3:78f223d34f36 10183 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
ethaderu 3:78f223d34f36 10184 /** Interrupt vectors for the PORT peripheral type */
ethaderu 3:78f223d34f36 10185 #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
ethaderu 3:78f223d34f36 10186
ethaderu 3:78f223d34f36 10187 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10188 -- PORT - Register accessor macros
ethaderu 3:78f223d34f36 10189 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10190
ethaderu 3:78f223d34f36 10191 /*!
ethaderu 3:78f223d34f36 10192 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
ethaderu 3:78f223d34f36 10193 * @{
ethaderu 3:78f223d34f36 10194 */
ethaderu 3:78f223d34f36 10195
ethaderu 3:78f223d34f36 10196
ethaderu 3:78f223d34f36 10197 /* PORT - Register instance definitions */
ethaderu 3:78f223d34f36 10198 /* PORTA */
ethaderu 3:78f223d34f36 10199 #define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
ethaderu 3:78f223d34f36 10200 #define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
ethaderu 3:78f223d34f36 10201 #define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
ethaderu 3:78f223d34f36 10202 #define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
ethaderu 3:78f223d34f36 10203 #define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
ethaderu 3:78f223d34f36 10204 #define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
ethaderu 3:78f223d34f36 10205 #define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
ethaderu 3:78f223d34f36 10206 #define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
ethaderu 3:78f223d34f36 10207 #define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
ethaderu 3:78f223d34f36 10208 #define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
ethaderu 3:78f223d34f36 10209 #define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
ethaderu 3:78f223d34f36 10210 #define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
ethaderu 3:78f223d34f36 10211 #define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
ethaderu 3:78f223d34f36 10212 #define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
ethaderu 3:78f223d34f36 10213 #define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
ethaderu 3:78f223d34f36 10214 #define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
ethaderu 3:78f223d34f36 10215 #define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
ethaderu 3:78f223d34f36 10216 #define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
ethaderu 3:78f223d34f36 10217 #define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
ethaderu 3:78f223d34f36 10218 #define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
ethaderu 3:78f223d34f36 10219 #define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
ethaderu 3:78f223d34f36 10220 #define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
ethaderu 3:78f223d34f36 10221 #define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
ethaderu 3:78f223d34f36 10222 #define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
ethaderu 3:78f223d34f36 10223 #define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
ethaderu 3:78f223d34f36 10224 #define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
ethaderu 3:78f223d34f36 10225 #define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
ethaderu 3:78f223d34f36 10226 #define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
ethaderu 3:78f223d34f36 10227 #define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
ethaderu 3:78f223d34f36 10228 #define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
ethaderu 3:78f223d34f36 10229 #define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
ethaderu 3:78f223d34f36 10230 #define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
ethaderu 3:78f223d34f36 10231 #define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
ethaderu 3:78f223d34f36 10232 #define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
ethaderu 3:78f223d34f36 10233 #define PORTA_ISFR PORT_ISFR_REG(PORTA)
ethaderu 3:78f223d34f36 10234 /* PORTB */
ethaderu 3:78f223d34f36 10235 #define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
ethaderu 3:78f223d34f36 10236 #define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
ethaderu 3:78f223d34f36 10237 #define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
ethaderu 3:78f223d34f36 10238 #define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
ethaderu 3:78f223d34f36 10239 #define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
ethaderu 3:78f223d34f36 10240 #define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
ethaderu 3:78f223d34f36 10241 #define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
ethaderu 3:78f223d34f36 10242 #define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
ethaderu 3:78f223d34f36 10243 #define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
ethaderu 3:78f223d34f36 10244 #define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
ethaderu 3:78f223d34f36 10245 #define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
ethaderu 3:78f223d34f36 10246 #define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
ethaderu 3:78f223d34f36 10247 #define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
ethaderu 3:78f223d34f36 10248 #define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
ethaderu 3:78f223d34f36 10249 #define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
ethaderu 3:78f223d34f36 10250 #define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
ethaderu 3:78f223d34f36 10251 #define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
ethaderu 3:78f223d34f36 10252 #define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
ethaderu 3:78f223d34f36 10253 #define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
ethaderu 3:78f223d34f36 10254 #define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
ethaderu 3:78f223d34f36 10255 #define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
ethaderu 3:78f223d34f36 10256 #define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
ethaderu 3:78f223d34f36 10257 #define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
ethaderu 3:78f223d34f36 10258 #define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
ethaderu 3:78f223d34f36 10259 #define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
ethaderu 3:78f223d34f36 10260 #define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
ethaderu 3:78f223d34f36 10261 #define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
ethaderu 3:78f223d34f36 10262 #define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
ethaderu 3:78f223d34f36 10263 #define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
ethaderu 3:78f223d34f36 10264 #define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
ethaderu 3:78f223d34f36 10265 #define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
ethaderu 3:78f223d34f36 10266 #define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
ethaderu 3:78f223d34f36 10267 #define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
ethaderu 3:78f223d34f36 10268 #define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
ethaderu 3:78f223d34f36 10269 #define PORTB_ISFR PORT_ISFR_REG(PORTB)
ethaderu 3:78f223d34f36 10270 /* PORTC */
ethaderu 3:78f223d34f36 10271 #define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
ethaderu 3:78f223d34f36 10272 #define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
ethaderu 3:78f223d34f36 10273 #define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
ethaderu 3:78f223d34f36 10274 #define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
ethaderu 3:78f223d34f36 10275 #define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
ethaderu 3:78f223d34f36 10276 #define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
ethaderu 3:78f223d34f36 10277 #define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
ethaderu 3:78f223d34f36 10278 #define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
ethaderu 3:78f223d34f36 10279 #define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
ethaderu 3:78f223d34f36 10280 #define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
ethaderu 3:78f223d34f36 10281 #define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
ethaderu 3:78f223d34f36 10282 #define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
ethaderu 3:78f223d34f36 10283 #define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
ethaderu 3:78f223d34f36 10284 #define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
ethaderu 3:78f223d34f36 10285 #define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
ethaderu 3:78f223d34f36 10286 #define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
ethaderu 3:78f223d34f36 10287 #define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
ethaderu 3:78f223d34f36 10288 #define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
ethaderu 3:78f223d34f36 10289 #define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
ethaderu 3:78f223d34f36 10290 #define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
ethaderu 3:78f223d34f36 10291 #define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
ethaderu 3:78f223d34f36 10292 #define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
ethaderu 3:78f223d34f36 10293 #define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
ethaderu 3:78f223d34f36 10294 #define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
ethaderu 3:78f223d34f36 10295 #define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
ethaderu 3:78f223d34f36 10296 #define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
ethaderu 3:78f223d34f36 10297 #define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
ethaderu 3:78f223d34f36 10298 #define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
ethaderu 3:78f223d34f36 10299 #define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
ethaderu 3:78f223d34f36 10300 #define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
ethaderu 3:78f223d34f36 10301 #define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
ethaderu 3:78f223d34f36 10302 #define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
ethaderu 3:78f223d34f36 10303 #define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
ethaderu 3:78f223d34f36 10304 #define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
ethaderu 3:78f223d34f36 10305 #define PORTC_ISFR PORT_ISFR_REG(PORTC)
ethaderu 3:78f223d34f36 10306 /* PORTD */
ethaderu 3:78f223d34f36 10307 #define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
ethaderu 3:78f223d34f36 10308 #define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
ethaderu 3:78f223d34f36 10309 #define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
ethaderu 3:78f223d34f36 10310 #define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
ethaderu 3:78f223d34f36 10311 #define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
ethaderu 3:78f223d34f36 10312 #define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
ethaderu 3:78f223d34f36 10313 #define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
ethaderu 3:78f223d34f36 10314 #define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
ethaderu 3:78f223d34f36 10315 #define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
ethaderu 3:78f223d34f36 10316 #define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
ethaderu 3:78f223d34f36 10317 #define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
ethaderu 3:78f223d34f36 10318 #define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
ethaderu 3:78f223d34f36 10319 #define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
ethaderu 3:78f223d34f36 10320 #define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
ethaderu 3:78f223d34f36 10321 #define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
ethaderu 3:78f223d34f36 10322 #define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
ethaderu 3:78f223d34f36 10323 #define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
ethaderu 3:78f223d34f36 10324 #define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
ethaderu 3:78f223d34f36 10325 #define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
ethaderu 3:78f223d34f36 10326 #define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
ethaderu 3:78f223d34f36 10327 #define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
ethaderu 3:78f223d34f36 10328 #define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
ethaderu 3:78f223d34f36 10329 #define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
ethaderu 3:78f223d34f36 10330 #define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
ethaderu 3:78f223d34f36 10331 #define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
ethaderu 3:78f223d34f36 10332 #define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
ethaderu 3:78f223d34f36 10333 #define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
ethaderu 3:78f223d34f36 10334 #define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
ethaderu 3:78f223d34f36 10335 #define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
ethaderu 3:78f223d34f36 10336 #define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
ethaderu 3:78f223d34f36 10337 #define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
ethaderu 3:78f223d34f36 10338 #define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
ethaderu 3:78f223d34f36 10339 #define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
ethaderu 3:78f223d34f36 10340 #define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
ethaderu 3:78f223d34f36 10341 #define PORTD_ISFR PORT_ISFR_REG(PORTD)
ethaderu 3:78f223d34f36 10342 #define PORTD_DFER PORT_DFER_REG(PORTD)
ethaderu 3:78f223d34f36 10343 #define PORTD_DFCR PORT_DFCR_REG(PORTD)
ethaderu 3:78f223d34f36 10344 #define PORTD_DFWR PORT_DFWR_REG(PORTD)
ethaderu 3:78f223d34f36 10345 /* PORTE */
ethaderu 3:78f223d34f36 10346 #define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
ethaderu 3:78f223d34f36 10347 #define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
ethaderu 3:78f223d34f36 10348 #define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
ethaderu 3:78f223d34f36 10349 #define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
ethaderu 3:78f223d34f36 10350 #define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
ethaderu 3:78f223d34f36 10351 #define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
ethaderu 3:78f223d34f36 10352 #define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
ethaderu 3:78f223d34f36 10353 #define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
ethaderu 3:78f223d34f36 10354 #define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
ethaderu 3:78f223d34f36 10355 #define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
ethaderu 3:78f223d34f36 10356 #define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
ethaderu 3:78f223d34f36 10357 #define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
ethaderu 3:78f223d34f36 10358 #define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
ethaderu 3:78f223d34f36 10359 #define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
ethaderu 3:78f223d34f36 10360 #define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
ethaderu 3:78f223d34f36 10361 #define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
ethaderu 3:78f223d34f36 10362 #define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
ethaderu 3:78f223d34f36 10363 #define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
ethaderu 3:78f223d34f36 10364 #define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
ethaderu 3:78f223d34f36 10365 #define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
ethaderu 3:78f223d34f36 10366 #define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
ethaderu 3:78f223d34f36 10367 #define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
ethaderu 3:78f223d34f36 10368 #define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
ethaderu 3:78f223d34f36 10369 #define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
ethaderu 3:78f223d34f36 10370 #define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
ethaderu 3:78f223d34f36 10371 #define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
ethaderu 3:78f223d34f36 10372 #define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
ethaderu 3:78f223d34f36 10373 #define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
ethaderu 3:78f223d34f36 10374 #define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
ethaderu 3:78f223d34f36 10375 #define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
ethaderu 3:78f223d34f36 10376 #define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
ethaderu 3:78f223d34f36 10377 #define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
ethaderu 3:78f223d34f36 10378 #define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
ethaderu 3:78f223d34f36 10379 #define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
ethaderu 3:78f223d34f36 10380 #define PORTE_ISFR PORT_ISFR_REG(PORTE)
ethaderu 3:78f223d34f36 10381
ethaderu 3:78f223d34f36 10382 /* PORT - Register array accessors */
ethaderu 3:78f223d34f36 10383 #define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
ethaderu 3:78f223d34f36 10384 #define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
ethaderu 3:78f223d34f36 10385 #define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
ethaderu 3:78f223d34f36 10386 #define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
ethaderu 3:78f223d34f36 10387 #define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
ethaderu 3:78f223d34f36 10388
ethaderu 3:78f223d34f36 10389 /*!
ethaderu 3:78f223d34f36 10390 * @}
ethaderu 3:78f223d34f36 10391 */ /* end of group PORT_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 10392
ethaderu 3:78f223d34f36 10393
ethaderu 3:78f223d34f36 10394 /*!
ethaderu 3:78f223d34f36 10395 * @}
ethaderu 3:78f223d34f36 10396 */ /* end of group PORT_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 10397
ethaderu 3:78f223d34f36 10398
ethaderu 3:78f223d34f36 10399 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10400 -- RCM Peripheral Access Layer
ethaderu 3:78f223d34f36 10401 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10402
ethaderu 3:78f223d34f36 10403 /*!
ethaderu 3:78f223d34f36 10404 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
ethaderu 3:78f223d34f36 10405 * @{
ethaderu 3:78f223d34f36 10406 */
ethaderu 3:78f223d34f36 10407
ethaderu 3:78f223d34f36 10408 /** RCM - Register Layout Typedef */
ethaderu 3:78f223d34f36 10409 typedef struct {
ethaderu 3:78f223d34f36 10410 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
ethaderu 3:78f223d34f36 10411 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
ethaderu 3:78f223d34f36 10412 uint8_t RESERVED_0[2];
ethaderu 3:78f223d34f36 10413 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
ethaderu 3:78f223d34f36 10414 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
ethaderu 3:78f223d34f36 10415 uint8_t RESERVED_1[1];
ethaderu 3:78f223d34f36 10416 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
ethaderu 3:78f223d34f36 10417 } RCM_Type, *RCM_MemMapPtr;
ethaderu 3:78f223d34f36 10418
ethaderu 3:78f223d34f36 10419 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10420 -- RCM - Register accessor macros
ethaderu 3:78f223d34f36 10421 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10422
ethaderu 3:78f223d34f36 10423 /*!
ethaderu 3:78f223d34f36 10424 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
ethaderu 3:78f223d34f36 10425 * @{
ethaderu 3:78f223d34f36 10426 */
ethaderu 3:78f223d34f36 10427
ethaderu 3:78f223d34f36 10428
ethaderu 3:78f223d34f36 10429 /* RCM - Register accessors */
ethaderu 3:78f223d34f36 10430 #define RCM_SRS0_REG(base) ((base)->SRS0)
ethaderu 3:78f223d34f36 10431 #define RCM_SRS1_REG(base) ((base)->SRS1)
ethaderu 3:78f223d34f36 10432 #define RCM_RPFC_REG(base) ((base)->RPFC)
ethaderu 3:78f223d34f36 10433 #define RCM_RPFW_REG(base) ((base)->RPFW)
ethaderu 3:78f223d34f36 10434 #define RCM_MR_REG(base) ((base)->MR)
ethaderu 3:78f223d34f36 10435
ethaderu 3:78f223d34f36 10436 /*!
ethaderu 3:78f223d34f36 10437 * @}
ethaderu 3:78f223d34f36 10438 */ /* end of group RCM_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 10439
ethaderu 3:78f223d34f36 10440
ethaderu 3:78f223d34f36 10441 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10442 -- RCM Register Masks
ethaderu 3:78f223d34f36 10443 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10444
ethaderu 3:78f223d34f36 10445 /*!
ethaderu 3:78f223d34f36 10446 * @addtogroup RCM_Register_Masks RCM Register Masks
ethaderu 3:78f223d34f36 10447 * @{
ethaderu 3:78f223d34f36 10448 */
ethaderu 3:78f223d34f36 10449
ethaderu 3:78f223d34f36 10450 /* SRS0 Bit Fields */
ethaderu 3:78f223d34f36 10451 #define RCM_SRS0_WAKEUP_MASK 0x1u
ethaderu 3:78f223d34f36 10452 #define RCM_SRS0_WAKEUP_SHIFT 0
ethaderu 3:78f223d34f36 10453 #define RCM_SRS0_LVD_MASK 0x2u
ethaderu 3:78f223d34f36 10454 #define RCM_SRS0_LVD_SHIFT 1
ethaderu 3:78f223d34f36 10455 #define RCM_SRS0_LOC_MASK 0x4u
ethaderu 3:78f223d34f36 10456 #define RCM_SRS0_LOC_SHIFT 2
ethaderu 3:78f223d34f36 10457 #define RCM_SRS0_LOL_MASK 0x8u
ethaderu 3:78f223d34f36 10458 #define RCM_SRS0_LOL_SHIFT 3
ethaderu 3:78f223d34f36 10459 #define RCM_SRS0_WDOG_MASK 0x20u
ethaderu 3:78f223d34f36 10460 #define RCM_SRS0_WDOG_SHIFT 5
ethaderu 3:78f223d34f36 10461 #define RCM_SRS0_PIN_MASK 0x40u
ethaderu 3:78f223d34f36 10462 #define RCM_SRS0_PIN_SHIFT 6
ethaderu 3:78f223d34f36 10463 #define RCM_SRS0_POR_MASK 0x80u
ethaderu 3:78f223d34f36 10464 #define RCM_SRS0_POR_SHIFT 7
ethaderu 3:78f223d34f36 10465 /* SRS1 Bit Fields */
ethaderu 3:78f223d34f36 10466 #define RCM_SRS1_JTAG_MASK 0x1u
ethaderu 3:78f223d34f36 10467 #define RCM_SRS1_JTAG_SHIFT 0
ethaderu 3:78f223d34f36 10468 #define RCM_SRS1_LOCKUP_MASK 0x2u
ethaderu 3:78f223d34f36 10469 #define RCM_SRS1_LOCKUP_SHIFT 1
ethaderu 3:78f223d34f36 10470 #define RCM_SRS1_SW_MASK 0x4u
ethaderu 3:78f223d34f36 10471 #define RCM_SRS1_SW_SHIFT 2
ethaderu 3:78f223d34f36 10472 #define RCM_SRS1_MDM_AP_MASK 0x8u
ethaderu 3:78f223d34f36 10473 #define RCM_SRS1_MDM_AP_SHIFT 3
ethaderu 3:78f223d34f36 10474 #define RCM_SRS1_EZPT_MASK 0x10u
ethaderu 3:78f223d34f36 10475 #define RCM_SRS1_EZPT_SHIFT 4
ethaderu 3:78f223d34f36 10476 #define RCM_SRS1_SACKERR_MASK 0x20u
ethaderu 3:78f223d34f36 10477 #define RCM_SRS1_SACKERR_SHIFT 5
ethaderu 3:78f223d34f36 10478 /* RPFC Bit Fields */
ethaderu 3:78f223d34f36 10479 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
ethaderu 3:78f223d34f36 10480 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
ethaderu 3:78f223d34f36 10481 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
ethaderu 3:78f223d34f36 10482 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
ethaderu 3:78f223d34f36 10483 #define RCM_RPFC_RSTFLTSS_SHIFT 2
ethaderu 3:78f223d34f36 10484 /* RPFW Bit Fields */
ethaderu 3:78f223d34f36 10485 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
ethaderu 3:78f223d34f36 10486 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
ethaderu 3:78f223d34f36 10487 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
ethaderu 3:78f223d34f36 10488 /* MR Bit Fields */
ethaderu 3:78f223d34f36 10489 #define RCM_MR_EZP_MS_MASK 0x2u
ethaderu 3:78f223d34f36 10490 #define RCM_MR_EZP_MS_SHIFT 1
ethaderu 3:78f223d34f36 10491
ethaderu 3:78f223d34f36 10492 /*!
ethaderu 3:78f223d34f36 10493 * @}
ethaderu 3:78f223d34f36 10494 */ /* end of group RCM_Register_Masks */
ethaderu 3:78f223d34f36 10495
ethaderu 3:78f223d34f36 10496
ethaderu 3:78f223d34f36 10497 /* RCM - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 10498 /** Peripheral RCM base address */
ethaderu 3:78f223d34f36 10499 #define RCM_BASE (0x4007F000u)
ethaderu 3:78f223d34f36 10500 /** Peripheral RCM base pointer */
ethaderu 3:78f223d34f36 10501 #define RCM ((RCM_Type *)RCM_BASE)
ethaderu 3:78f223d34f36 10502 #define RCM_BASE_PTR (RCM)
ethaderu 3:78f223d34f36 10503 /** Array initializer of RCM peripheral base addresses */
ethaderu 3:78f223d34f36 10504 #define RCM_BASE_ADDRS { RCM_BASE }
ethaderu 3:78f223d34f36 10505 /** Array initializer of RCM peripheral base pointers */
ethaderu 3:78f223d34f36 10506 #define RCM_BASE_PTRS { RCM }
ethaderu 3:78f223d34f36 10507
ethaderu 3:78f223d34f36 10508 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10509 -- RCM - Register accessor macros
ethaderu 3:78f223d34f36 10510 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10511
ethaderu 3:78f223d34f36 10512 /*!
ethaderu 3:78f223d34f36 10513 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
ethaderu 3:78f223d34f36 10514 * @{
ethaderu 3:78f223d34f36 10515 */
ethaderu 3:78f223d34f36 10516
ethaderu 3:78f223d34f36 10517
ethaderu 3:78f223d34f36 10518 /* RCM - Register instance definitions */
ethaderu 3:78f223d34f36 10519 /* RCM */
ethaderu 3:78f223d34f36 10520 #define RCM_SRS0 RCM_SRS0_REG(RCM)
ethaderu 3:78f223d34f36 10521 #define RCM_SRS1 RCM_SRS1_REG(RCM)
ethaderu 3:78f223d34f36 10522 #define RCM_RPFC RCM_RPFC_REG(RCM)
ethaderu 3:78f223d34f36 10523 #define RCM_RPFW RCM_RPFW_REG(RCM)
ethaderu 3:78f223d34f36 10524 #define RCM_MR RCM_MR_REG(RCM)
ethaderu 3:78f223d34f36 10525
ethaderu 3:78f223d34f36 10526 /*!
ethaderu 3:78f223d34f36 10527 * @}
ethaderu 3:78f223d34f36 10528 */ /* end of group RCM_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 10529
ethaderu 3:78f223d34f36 10530
ethaderu 3:78f223d34f36 10531 /*!
ethaderu 3:78f223d34f36 10532 * @}
ethaderu 3:78f223d34f36 10533 */ /* end of group RCM_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 10534
ethaderu 3:78f223d34f36 10535
ethaderu 3:78f223d34f36 10536 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10537 -- RFSYS Peripheral Access Layer
ethaderu 3:78f223d34f36 10538 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10539
ethaderu 3:78f223d34f36 10540 /*!
ethaderu 3:78f223d34f36 10541 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
ethaderu 3:78f223d34f36 10542 * @{
ethaderu 3:78f223d34f36 10543 */
ethaderu 3:78f223d34f36 10544
ethaderu 3:78f223d34f36 10545 /** RFSYS - Register Layout Typedef */
ethaderu 3:78f223d34f36 10546 typedef struct {
ethaderu 3:78f223d34f36 10547 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
ethaderu 3:78f223d34f36 10548 } RFSYS_Type, *RFSYS_MemMapPtr;
ethaderu 3:78f223d34f36 10549
ethaderu 3:78f223d34f36 10550 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10551 -- RFSYS - Register accessor macros
ethaderu 3:78f223d34f36 10552 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10553
ethaderu 3:78f223d34f36 10554 /*!
ethaderu 3:78f223d34f36 10555 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
ethaderu 3:78f223d34f36 10556 * @{
ethaderu 3:78f223d34f36 10557 */
ethaderu 3:78f223d34f36 10558
ethaderu 3:78f223d34f36 10559
ethaderu 3:78f223d34f36 10560 /* RFSYS - Register accessors */
ethaderu 3:78f223d34f36 10561 #define RFSYS_REG_REG(base,index) ((base)->REG[index])
ethaderu 3:78f223d34f36 10562
ethaderu 3:78f223d34f36 10563 /*!
ethaderu 3:78f223d34f36 10564 * @}
ethaderu 3:78f223d34f36 10565 */ /* end of group RFSYS_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 10566
ethaderu 3:78f223d34f36 10567
ethaderu 3:78f223d34f36 10568 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10569 -- RFSYS Register Masks
ethaderu 3:78f223d34f36 10570 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10571
ethaderu 3:78f223d34f36 10572 /*!
ethaderu 3:78f223d34f36 10573 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
ethaderu 3:78f223d34f36 10574 * @{
ethaderu 3:78f223d34f36 10575 */
ethaderu 3:78f223d34f36 10576
ethaderu 3:78f223d34f36 10577 /* REG Bit Fields */
ethaderu 3:78f223d34f36 10578 #define RFSYS_REG_LL_MASK 0xFFu
ethaderu 3:78f223d34f36 10579 #define RFSYS_REG_LL_SHIFT 0
ethaderu 3:78f223d34f36 10580 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
ethaderu 3:78f223d34f36 10581 #define RFSYS_REG_LH_MASK 0xFF00u
ethaderu 3:78f223d34f36 10582 #define RFSYS_REG_LH_SHIFT 8
ethaderu 3:78f223d34f36 10583 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
ethaderu 3:78f223d34f36 10584 #define RFSYS_REG_HL_MASK 0xFF0000u
ethaderu 3:78f223d34f36 10585 #define RFSYS_REG_HL_SHIFT 16
ethaderu 3:78f223d34f36 10586 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
ethaderu 3:78f223d34f36 10587 #define RFSYS_REG_HH_MASK 0xFF000000u
ethaderu 3:78f223d34f36 10588 #define RFSYS_REG_HH_SHIFT 24
ethaderu 3:78f223d34f36 10589 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
ethaderu 3:78f223d34f36 10590
ethaderu 3:78f223d34f36 10591 /*!
ethaderu 3:78f223d34f36 10592 * @}
ethaderu 3:78f223d34f36 10593 */ /* end of group RFSYS_Register_Masks */
ethaderu 3:78f223d34f36 10594
ethaderu 3:78f223d34f36 10595
ethaderu 3:78f223d34f36 10596 /* RFSYS - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 10597 /** Peripheral RFSYS base address */
ethaderu 3:78f223d34f36 10598 #define RFSYS_BASE (0x40041000u)
ethaderu 3:78f223d34f36 10599 /** Peripheral RFSYS base pointer */
ethaderu 3:78f223d34f36 10600 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
ethaderu 3:78f223d34f36 10601 #define RFSYS_BASE_PTR (RFSYS)
ethaderu 3:78f223d34f36 10602 /** Array initializer of RFSYS peripheral base addresses */
ethaderu 3:78f223d34f36 10603 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
ethaderu 3:78f223d34f36 10604 /** Array initializer of RFSYS peripheral base pointers */
ethaderu 3:78f223d34f36 10605 #define RFSYS_BASE_PTRS { RFSYS }
ethaderu 3:78f223d34f36 10606
ethaderu 3:78f223d34f36 10607 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10608 -- RFSYS - Register accessor macros
ethaderu 3:78f223d34f36 10609 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10610
ethaderu 3:78f223d34f36 10611 /*!
ethaderu 3:78f223d34f36 10612 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
ethaderu 3:78f223d34f36 10613 * @{
ethaderu 3:78f223d34f36 10614 */
ethaderu 3:78f223d34f36 10615
ethaderu 3:78f223d34f36 10616
ethaderu 3:78f223d34f36 10617 /* RFSYS - Register instance definitions */
ethaderu 3:78f223d34f36 10618 /* RFSYS */
ethaderu 3:78f223d34f36 10619 #define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
ethaderu 3:78f223d34f36 10620 #define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
ethaderu 3:78f223d34f36 10621 #define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
ethaderu 3:78f223d34f36 10622 #define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
ethaderu 3:78f223d34f36 10623 #define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
ethaderu 3:78f223d34f36 10624 #define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
ethaderu 3:78f223d34f36 10625 #define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
ethaderu 3:78f223d34f36 10626 #define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
ethaderu 3:78f223d34f36 10627
ethaderu 3:78f223d34f36 10628 /* RFSYS - Register array accessors */
ethaderu 3:78f223d34f36 10629 #define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
ethaderu 3:78f223d34f36 10630
ethaderu 3:78f223d34f36 10631 /*!
ethaderu 3:78f223d34f36 10632 * @}
ethaderu 3:78f223d34f36 10633 */ /* end of group RFSYS_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 10634
ethaderu 3:78f223d34f36 10635
ethaderu 3:78f223d34f36 10636 /*!
ethaderu 3:78f223d34f36 10637 * @}
ethaderu 3:78f223d34f36 10638 */ /* end of group RFSYS_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 10639
ethaderu 3:78f223d34f36 10640
ethaderu 3:78f223d34f36 10641 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10642 -- RFVBAT Peripheral Access Layer
ethaderu 3:78f223d34f36 10643 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10644
ethaderu 3:78f223d34f36 10645 /*!
ethaderu 3:78f223d34f36 10646 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
ethaderu 3:78f223d34f36 10647 * @{
ethaderu 3:78f223d34f36 10648 */
ethaderu 3:78f223d34f36 10649
ethaderu 3:78f223d34f36 10650 /** RFVBAT - Register Layout Typedef */
ethaderu 3:78f223d34f36 10651 typedef struct {
ethaderu 3:78f223d34f36 10652 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
ethaderu 3:78f223d34f36 10653 } RFVBAT_Type, *RFVBAT_MemMapPtr;
ethaderu 3:78f223d34f36 10654
ethaderu 3:78f223d34f36 10655 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10656 -- RFVBAT - Register accessor macros
ethaderu 3:78f223d34f36 10657 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10658
ethaderu 3:78f223d34f36 10659 /*!
ethaderu 3:78f223d34f36 10660 * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
ethaderu 3:78f223d34f36 10661 * @{
ethaderu 3:78f223d34f36 10662 */
ethaderu 3:78f223d34f36 10663
ethaderu 3:78f223d34f36 10664
ethaderu 3:78f223d34f36 10665 /* RFVBAT - Register accessors */
ethaderu 3:78f223d34f36 10666 #define RFVBAT_REG_REG(base,index) ((base)->REG[index])
ethaderu 3:78f223d34f36 10667
ethaderu 3:78f223d34f36 10668 /*!
ethaderu 3:78f223d34f36 10669 * @}
ethaderu 3:78f223d34f36 10670 */ /* end of group RFVBAT_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 10671
ethaderu 3:78f223d34f36 10672
ethaderu 3:78f223d34f36 10673 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10674 -- RFVBAT Register Masks
ethaderu 3:78f223d34f36 10675 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10676
ethaderu 3:78f223d34f36 10677 /*!
ethaderu 3:78f223d34f36 10678 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
ethaderu 3:78f223d34f36 10679 * @{
ethaderu 3:78f223d34f36 10680 */
ethaderu 3:78f223d34f36 10681
ethaderu 3:78f223d34f36 10682 /* REG Bit Fields */
ethaderu 3:78f223d34f36 10683 #define RFVBAT_REG_LL_MASK 0xFFu
ethaderu 3:78f223d34f36 10684 #define RFVBAT_REG_LL_SHIFT 0
ethaderu 3:78f223d34f36 10685 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
ethaderu 3:78f223d34f36 10686 #define RFVBAT_REG_LH_MASK 0xFF00u
ethaderu 3:78f223d34f36 10687 #define RFVBAT_REG_LH_SHIFT 8
ethaderu 3:78f223d34f36 10688 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
ethaderu 3:78f223d34f36 10689 #define RFVBAT_REG_HL_MASK 0xFF0000u
ethaderu 3:78f223d34f36 10690 #define RFVBAT_REG_HL_SHIFT 16
ethaderu 3:78f223d34f36 10691 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
ethaderu 3:78f223d34f36 10692 #define RFVBAT_REG_HH_MASK 0xFF000000u
ethaderu 3:78f223d34f36 10693 #define RFVBAT_REG_HH_SHIFT 24
ethaderu 3:78f223d34f36 10694 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
ethaderu 3:78f223d34f36 10695
ethaderu 3:78f223d34f36 10696 /*!
ethaderu 3:78f223d34f36 10697 * @}
ethaderu 3:78f223d34f36 10698 */ /* end of group RFVBAT_Register_Masks */
ethaderu 3:78f223d34f36 10699
ethaderu 3:78f223d34f36 10700
ethaderu 3:78f223d34f36 10701 /* RFVBAT - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 10702 /** Peripheral RFVBAT base address */
ethaderu 3:78f223d34f36 10703 #define RFVBAT_BASE (0x4003E000u)
ethaderu 3:78f223d34f36 10704 /** Peripheral RFVBAT base pointer */
ethaderu 3:78f223d34f36 10705 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
ethaderu 3:78f223d34f36 10706 #define RFVBAT_BASE_PTR (RFVBAT)
ethaderu 3:78f223d34f36 10707 /** Array initializer of RFVBAT peripheral base addresses */
ethaderu 3:78f223d34f36 10708 #define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
ethaderu 3:78f223d34f36 10709 /** Array initializer of RFVBAT peripheral base pointers */
ethaderu 3:78f223d34f36 10710 #define RFVBAT_BASE_PTRS { RFVBAT }
ethaderu 3:78f223d34f36 10711
ethaderu 3:78f223d34f36 10712 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10713 -- RFVBAT - Register accessor macros
ethaderu 3:78f223d34f36 10714 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10715
ethaderu 3:78f223d34f36 10716 /*!
ethaderu 3:78f223d34f36 10717 * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
ethaderu 3:78f223d34f36 10718 * @{
ethaderu 3:78f223d34f36 10719 */
ethaderu 3:78f223d34f36 10720
ethaderu 3:78f223d34f36 10721
ethaderu 3:78f223d34f36 10722 /* RFVBAT - Register instance definitions */
ethaderu 3:78f223d34f36 10723 /* RFVBAT */
ethaderu 3:78f223d34f36 10724 #define RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT,0)
ethaderu 3:78f223d34f36 10725 #define RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT,1)
ethaderu 3:78f223d34f36 10726 #define RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT,2)
ethaderu 3:78f223d34f36 10727 #define RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT,3)
ethaderu 3:78f223d34f36 10728 #define RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT,4)
ethaderu 3:78f223d34f36 10729 #define RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT,5)
ethaderu 3:78f223d34f36 10730 #define RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT,6)
ethaderu 3:78f223d34f36 10731 #define RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT,7)
ethaderu 3:78f223d34f36 10732
ethaderu 3:78f223d34f36 10733 /* RFVBAT - Register array accessors */
ethaderu 3:78f223d34f36 10734 #define RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT,index)
ethaderu 3:78f223d34f36 10735
ethaderu 3:78f223d34f36 10736 /*!
ethaderu 3:78f223d34f36 10737 * @}
ethaderu 3:78f223d34f36 10738 */ /* end of group RFVBAT_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 10739
ethaderu 3:78f223d34f36 10740
ethaderu 3:78f223d34f36 10741 /*!
ethaderu 3:78f223d34f36 10742 * @}
ethaderu 3:78f223d34f36 10743 */ /* end of group RFVBAT_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 10744
ethaderu 3:78f223d34f36 10745
ethaderu 3:78f223d34f36 10746 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10747 -- RNG Peripheral Access Layer
ethaderu 3:78f223d34f36 10748 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10749
ethaderu 3:78f223d34f36 10750 /*!
ethaderu 3:78f223d34f36 10751 * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
ethaderu 3:78f223d34f36 10752 * @{
ethaderu 3:78f223d34f36 10753 */
ethaderu 3:78f223d34f36 10754
ethaderu 3:78f223d34f36 10755 /** RNG - Register Layout Typedef */
ethaderu 3:78f223d34f36 10756 typedef struct {
ethaderu 3:78f223d34f36 10757 __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
ethaderu 3:78f223d34f36 10758 __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
ethaderu 3:78f223d34f36 10759 __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
ethaderu 3:78f223d34f36 10760 __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
ethaderu 3:78f223d34f36 10761 } RNG_Type, *RNG_MemMapPtr;
ethaderu 3:78f223d34f36 10762
ethaderu 3:78f223d34f36 10763 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10764 -- RNG - Register accessor macros
ethaderu 3:78f223d34f36 10765 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10766
ethaderu 3:78f223d34f36 10767 /*!
ethaderu 3:78f223d34f36 10768 * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
ethaderu 3:78f223d34f36 10769 * @{
ethaderu 3:78f223d34f36 10770 */
ethaderu 3:78f223d34f36 10771
ethaderu 3:78f223d34f36 10772
ethaderu 3:78f223d34f36 10773 /* RNG - Register accessors */
ethaderu 3:78f223d34f36 10774 #define RNG_CR_REG(base) ((base)->CR)
ethaderu 3:78f223d34f36 10775 #define RNG_SR_REG(base) ((base)->SR)
ethaderu 3:78f223d34f36 10776 #define RNG_ER_REG(base) ((base)->ER)
ethaderu 3:78f223d34f36 10777 #define RNG_OR_REG(base) ((base)->OR)
ethaderu 3:78f223d34f36 10778
ethaderu 3:78f223d34f36 10779 /*!
ethaderu 3:78f223d34f36 10780 * @}
ethaderu 3:78f223d34f36 10781 */ /* end of group RNG_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 10782
ethaderu 3:78f223d34f36 10783
ethaderu 3:78f223d34f36 10784 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10785 -- RNG Register Masks
ethaderu 3:78f223d34f36 10786 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10787
ethaderu 3:78f223d34f36 10788 /*!
ethaderu 3:78f223d34f36 10789 * @addtogroup RNG_Register_Masks RNG Register Masks
ethaderu 3:78f223d34f36 10790 * @{
ethaderu 3:78f223d34f36 10791 */
ethaderu 3:78f223d34f36 10792
ethaderu 3:78f223d34f36 10793 /* CR Bit Fields */
ethaderu 3:78f223d34f36 10794 #define RNG_CR_GO_MASK 0x1u
ethaderu 3:78f223d34f36 10795 #define RNG_CR_GO_SHIFT 0
ethaderu 3:78f223d34f36 10796 #define RNG_CR_HA_MASK 0x2u
ethaderu 3:78f223d34f36 10797 #define RNG_CR_HA_SHIFT 1
ethaderu 3:78f223d34f36 10798 #define RNG_CR_INTM_MASK 0x4u
ethaderu 3:78f223d34f36 10799 #define RNG_CR_INTM_SHIFT 2
ethaderu 3:78f223d34f36 10800 #define RNG_CR_CLRI_MASK 0x8u
ethaderu 3:78f223d34f36 10801 #define RNG_CR_CLRI_SHIFT 3
ethaderu 3:78f223d34f36 10802 #define RNG_CR_SLP_MASK 0x10u
ethaderu 3:78f223d34f36 10803 #define RNG_CR_SLP_SHIFT 4
ethaderu 3:78f223d34f36 10804 /* SR Bit Fields */
ethaderu 3:78f223d34f36 10805 #define RNG_SR_SECV_MASK 0x1u
ethaderu 3:78f223d34f36 10806 #define RNG_SR_SECV_SHIFT 0
ethaderu 3:78f223d34f36 10807 #define RNG_SR_LRS_MASK 0x2u
ethaderu 3:78f223d34f36 10808 #define RNG_SR_LRS_SHIFT 1
ethaderu 3:78f223d34f36 10809 #define RNG_SR_ORU_MASK 0x4u
ethaderu 3:78f223d34f36 10810 #define RNG_SR_ORU_SHIFT 2
ethaderu 3:78f223d34f36 10811 #define RNG_SR_ERRI_MASK 0x8u
ethaderu 3:78f223d34f36 10812 #define RNG_SR_ERRI_SHIFT 3
ethaderu 3:78f223d34f36 10813 #define RNG_SR_SLP_MASK 0x10u
ethaderu 3:78f223d34f36 10814 #define RNG_SR_SLP_SHIFT 4
ethaderu 3:78f223d34f36 10815 #define RNG_SR_OREG_LVL_MASK 0xFF00u
ethaderu 3:78f223d34f36 10816 #define RNG_SR_OREG_LVL_SHIFT 8
ethaderu 3:78f223d34f36 10817 #define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
ethaderu 3:78f223d34f36 10818 #define RNG_SR_OREG_SIZE_MASK 0xFF0000u
ethaderu 3:78f223d34f36 10819 #define RNG_SR_OREG_SIZE_SHIFT 16
ethaderu 3:78f223d34f36 10820 #define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
ethaderu 3:78f223d34f36 10821 /* ER Bit Fields */
ethaderu 3:78f223d34f36 10822 #define RNG_ER_EXT_ENT_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 10823 #define RNG_ER_EXT_ENT_SHIFT 0
ethaderu 3:78f223d34f36 10824 #define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
ethaderu 3:78f223d34f36 10825 /* OR Bit Fields */
ethaderu 3:78f223d34f36 10826 #define RNG_OR_RANDOUT_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 10827 #define RNG_OR_RANDOUT_SHIFT 0
ethaderu 3:78f223d34f36 10828 #define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
ethaderu 3:78f223d34f36 10829
ethaderu 3:78f223d34f36 10830 /*!
ethaderu 3:78f223d34f36 10831 * @}
ethaderu 3:78f223d34f36 10832 */ /* end of group RNG_Register_Masks */
ethaderu 3:78f223d34f36 10833
ethaderu 3:78f223d34f36 10834
ethaderu 3:78f223d34f36 10835 /* RNG - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 10836 /** Peripheral RNG base address */
ethaderu 3:78f223d34f36 10837 #define RNG_BASE (0x40029000u)
ethaderu 3:78f223d34f36 10838 /** Peripheral RNG base pointer */
ethaderu 3:78f223d34f36 10839 #define RNG ((RNG_Type *)RNG_BASE)
ethaderu 3:78f223d34f36 10840 #define RNG_BASE_PTR (RNG)
ethaderu 3:78f223d34f36 10841 /** Array initializer of RNG peripheral base addresses */
ethaderu 3:78f223d34f36 10842 #define RNG_BASE_ADDRS { RNG_BASE }
ethaderu 3:78f223d34f36 10843 /** Array initializer of RNG peripheral base pointers */
ethaderu 3:78f223d34f36 10844 #define RNG_BASE_PTRS { RNG }
ethaderu 3:78f223d34f36 10845 /** Interrupt vectors for the RNG peripheral type */
ethaderu 3:78f223d34f36 10846 #define RNG_IRQS { RNG_IRQn }
ethaderu 3:78f223d34f36 10847
ethaderu 3:78f223d34f36 10848 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10849 -- RNG - Register accessor macros
ethaderu 3:78f223d34f36 10850 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10851
ethaderu 3:78f223d34f36 10852 /*!
ethaderu 3:78f223d34f36 10853 * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
ethaderu 3:78f223d34f36 10854 * @{
ethaderu 3:78f223d34f36 10855 */
ethaderu 3:78f223d34f36 10856
ethaderu 3:78f223d34f36 10857
ethaderu 3:78f223d34f36 10858 /* RNG - Register instance definitions */
ethaderu 3:78f223d34f36 10859 /* RNG */
ethaderu 3:78f223d34f36 10860 #define RNG_CR RNG_CR_REG(RNG)
ethaderu 3:78f223d34f36 10861 #define RNG_SR RNG_SR_REG(RNG)
ethaderu 3:78f223d34f36 10862 #define RNG_ER RNG_ER_REG(RNG)
ethaderu 3:78f223d34f36 10863 #define RNG_OR RNG_OR_REG(RNG)
ethaderu 3:78f223d34f36 10864
ethaderu 3:78f223d34f36 10865 /*!
ethaderu 3:78f223d34f36 10866 * @}
ethaderu 3:78f223d34f36 10867 */ /* end of group RNG_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 10868
ethaderu 3:78f223d34f36 10869
ethaderu 3:78f223d34f36 10870 /*!
ethaderu 3:78f223d34f36 10871 * @}
ethaderu 3:78f223d34f36 10872 */ /* end of group RNG_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 10873
ethaderu 3:78f223d34f36 10874
ethaderu 3:78f223d34f36 10875 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10876 -- RTC Peripheral Access Layer
ethaderu 3:78f223d34f36 10877 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10878
ethaderu 3:78f223d34f36 10879 /*!
ethaderu 3:78f223d34f36 10880 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
ethaderu 3:78f223d34f36 10881 * @{
ethaderu 3:78f223d34f36 10882 */
ethaderu 3:78f223d34f36 10883
ethaderu 3:78f223d34f36 10884 /** RTC - Register Layout Typedef */
ethaderu 3:78f223d34f36 10885 typedef struct {
ethaderu 3:78f223d34f36 10886 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
ethaderu 3:78f223d34f36 10887 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
ethaderu 3:78f223d34f36 10888 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
ethaderu 3:78f223d34f36 10889 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
ethaderu 3:78f223d34f36 10890 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
ethaderu 3:78f223d34f36 10891 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
ethaderu 3:78f223d34f36 10892 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
ethaderu 3:78f223d34f36 10893 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
ethaderu 3:78f223d34f36 10894 uint8_t RESERVED_0[2016];
ethaderu 3:78f223d34f36 10895 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
ethaderu 3:78f223d34f36 10896 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
ethaderu 3:78f223d34f36 10897 } RTC_Type, *RTC_MemMapPtr;
ethaderu 3:78f223d34f36 10898
ethaderu 3:78f223d34f36 10899 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10900 -- RTC - Register accessor macros
ethaderu 3:78f223d34f36 10901 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10902
ethaderu 3:78f223d34f36 10903 /*!
ethaderu 3:78f223d34f36 10904 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
ethaderu 3:78f223d34f36 10905 * @{
ethaderu 3:78f223d34f36 10906 */
ethaderu 3:78f223d34f36 10907
ethaderu 3:78f223d34f36 10908
ethaderu 3:78f223d34f36 10909 /* RTC - Register accessors */
ethaderu 3:78f223d34f36 10910 #define RTC_TSR_REG(base) ((base)->TSR)
ethaderu 3:78f223d34f36 10911 #define RTC_TPR_REG(base) ((base)->TPR)
ethaderu 3:78f223d34f36 10912 #define RTC_TAR_REG(base) ((base)->TAR)
ethaderu 3:78f223d34f36 10913 #define RTC_TCR_REG(base) ((base)->TCR)
ethaderu 3:78f223d34f36 10914 #define RTC_CR_REG(base) ((base)->CR)
ethaderu 3:78f223d34f36 10915 #define RTC_SR_REG(base) ((base)->SR)
ethaderu 3:78f223d34f36 10916 #define RTC_LR_REG(base) ((base)->LR)
ethaderu 3:78f223d34f36 10917 #define RTC_IER_REG(base) ((base)->IER)
ethaderu 3:78f223d34f36 10918 #define RTC_WAR_REG(base) ((base)->WAR)
ethaderu 3:78f223d34f36 10919 #define RTC_RAR_REG(base) ((base)->RAR)
ethaderu 3:78f223d34f36 10920
ethaderu 3:78f223d34f36 10921 /*!
ethaderu 3:78f223d34f36 10922 * @}
ethaderu 3:78f223d34f36 10923 */ /* end of group RTC_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 10924
ethaderu 3:78f223d34f36 10925
ethaderu 3:78f223d34f36 10926 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 10927 -- RTC Register Masks
ethaderu 3:78f223d34f36 10928 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 10929
ethaderu 3:78f223d34f36 10930 /*!
ethaderu 3:78f223d34f36 10931 * @addtogroup RTC_Register_Masks RTC Register Masks
ethaderu 3:78f223d34f36 10932 * @{
ethaderu 3:78f223d34f36 10933 */
ethaderu 3:78f223d34f36 10934
ethaderu 3:78f223d34f36 10935 /* TSR Bit Fields */
ethaderu 3:78f223d34f36 10936 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 10937 #define RTC_TSR_TSR_SHIFT 0
ethaderu 3:78f223d34f36 10938 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
ethaderu 3:78f223d34f36 10939 /* TPR Bit Fields */
ethaderu 3:78f223d34f36 10940 #define RTC_TPR_TPR_MASK 0xFFFFu
ethaderu 3:78f223d34f36 10941 #define RTC_TPR_TPR_SHIFT 0
ethaderu 3:78f223d34f36 10942 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
ethaderu 3:78f223d34f36 10943 /* TAR Bit Fields */
ethaderu 3:78f223d34f36 10944 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 10945 #define RTC_TAR_TAR_SHIFT 0
ethaderu 3:78f223d34f36 10946 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
ethaderu 3:78f223d34f36 10947 /* TCR Bit Fields */
ethaderu 3:78f223d34f36 10948 #define RTC_TCR_TCR_MASK 0xFFu
ethaderu 3:78f223d34f36 10949 #define RTC_TCR_TCR_SHIFT 0
ethaderu 3:78f223d34f36 10950 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
ethaderu 3:78f223d34f36 10951 #define RTC_TCR_CIR_MASK 0xFF00u
ethaderu 3:78f223d34f36 10952 #define RTC_TCR_CIR_SHIFT 8
ethaderu 3:78f223d34f36 10953 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
ethaderu 3:78f223d34f36 10954 #define RTC_TCR_TCV_MASK 0xFF0000u
ethaderu 3:78f223d34f36 10955 #define RTC_TCR_TCV_SHIFT 16
ethaderu 3:78f223d34f36 10956 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
ethaderu 3:78f223d34f36 10957 #define RTC_TCR_CIC_MASK 0xFF000000u
ethaderu 3:78f223d34f36 10958 #define RTC_TCR_CIC_SHIFT 24
ethaderu 3:78f223d34f36 10959 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
ethaderu 3:78f223d34f36 10960 /* CR Bit Fields */
ethaderu 3:78f223d34f36 10961 #define RTC_CR_SWR_MASK 0x1u
ethaderu 3:78f223d34f36 10962 #define RTC_CR_SWR_SHIFT 0
ethaderu 3:78f223d34f36 10963 #define RTC_CR_WPE_MASK 0x2u
ethaderu 3:78f223d34f36 10964 #define RTC_CR_WPE_SHIFT 1
ethaderu 3:78f223d34f36 10965 #define RTC_CR_SUP_MASK 0x4u
ethaderu 3:78f223d34f36 10966 #define RTC_CR_SUP_SHIFT 2
ethaderu 3:78f223d34f36 10967 #define RTC_CR_UM_MASK 0x8u
ethaderu 3:78f223d34f36 10968 #define RTC_CR_UM_SHIFT 3
ethaderu 3:78f223d34f36 10969 #define RTC_CR_WPS_MASK 0x10u
ethaderu 3:78f223d34f36 10970 #define RTC_CR_WPS_SHIFT 4
ethaderu 3:78f223d34f36 10971 #define RTC_CR_OSCE_MASK 0x100u
ethaderu 3:78f223d34f36 10972 #define RTC_CR_OSCE_SHIFT 8
ethaderu 3:78f223d34f36 10973 #define RTC_CR_CLKO_MASK 0x200u
ethaderu 3:78f223d34f36 10974 #define RTC_CR_CLKO_SHIFT 9
ethaderu 3:78f223d34f36 10975 #define RTC_CR_SC16P_MASK 0x400u
ethaderu 3:78f223d34f36 10976 #define RTC_CR_SC16P_SHIFT 10
ethaderu 3:78f223d34f36 10977 #define RTC_CR_SC8P_MASK 0x800u
ethaderu 3:78f223d34f36 10978 #define RTC_CR_SC8P_SHIFT 11
ethaderu 3:78f223d34f36 10979 #define RTC_CR_SC4P_MASK 0x1000u
ethaderu 3:78f223d34f36 10980 #define RTC_CR_SC4P_SHIFT 12
ethaderu 3:78f223d34f36 10981 #define RTC_CR_SC2P_MASK 0x2000u
ethaderu 3:78f223d34f36 10982 #define RTC_CR_SC2P_SHIFT 13
ethaderu 3:78f223d34f36 10983 /* SR Bit Fields */
ethaderu 3:78f223d34f36 10984 #define RTC_SR_TIF_MASK 0x1u
ethaderu 3:78f223d34f36 10985 #define RTC_SR_TIF_SHIFT 0
ethaderu 3:78f223d34f36 10986 #define RTC_SR_TOF_MASK 0x2u
ethaderu 3:78f223d34f36 10987 #define RTC_SR_TOF_SHIFT 1
ethaderu 3:78f223d34f36 10988 #define RTC_SR_TAF_MASK 0x4u
ethaderu 3:78f223d34f36 10989 #define RTC_SR_TAF_SHIFT 2
ethaderu 3:78f223d34f36 10990 #define RTC_SR_TCE_MASK 0x10u
ethaderu 3:78f223d34f36 10991 #define RTC_SR_TCE_SHIFT 4
ethaderu 3:78f223d34f36 10992 /* LR Bit Fields */
ethaderu 3:78f223d34f36 10993 #define RTC_LR_TCL_MASK 0x8u
ethaderu 3:78f223d34f36 10994 #define RTC_LR_TCL_SHIFT 3
ethaderu 3:78f223d34f36 10995 #define RTC_LR_CRL_MASK 0x10u
ethaderu 3:78f223d34f36 10996 #define RTC_LR_CRL_SHIFT 4
ethaderu 3:78f223d34f36 10997 #define RTC_LR_SRL_MASK 0x20u
ethaderu 3:78f223d34f36 10998 #define RTC_LR_SRL_SHIFT 5
ethaderu 3:78f223d34f36 10999 #define RTC_LR_LRL_MASK 0x40u
ethaderu 3:78f223d34f36 11000 #define RTC_LR_LRL_SHIFT 6
ethaderu 3:78f223d34f36 11001 /* IER Bit Fields */
ethaderu 3:78f223d34f36 11002 #define RTC_IER_TIIE_MASK 0x1u
ethaderu 3:78f223d34f36 11003 #define RTC_IER_TIIE_SHIFT 0
ethaderu 3:78f223d34f36 11004 #define RTC_IER_TOIE_MASK 0x2u
ethaderu 3:78f223d34f36 11005 #define RTC_IER_TOIE_SHIFT 1
ethaderu 3:78f223d34f36 11006 #define RTC_IER_TAIE_MASK 0x4u
ethaderu 3:78f223d34f36 11007 #define RTC_IER_TAIE_SHIFT 2
ethaderu 3:78f223d34f36 11008 #define RTC_IER_TSIE_MASK 0x10u
ethaderu 3:78f223d34f36 11009 #define RTC_IER_TSIE_SHIFT 4
ethaderu 3:78f223d34f36 11010 #define RTC_IER_WPON_MASK 0x80u
ethaderu 3:78f223d34f36 11011 #define RTC_IER_WPON_SHIFT 7
ethaderu 3:78f223d34f36 11012 /* WAR Bit Fields */
ethaderu 3:78f223d34f36 11013 #define RTC_WAR_TSRW_MASK 0x1u
ethaderu 3:78f223d34f36 11014 #define RTC_WAR_TSRW_SHIFT 0
ethaderu 3:78f223d34f36 11015 #define RTC_WAR_TPRW_MASK 0x2u
ethaderu 3:78f223d34f36 11016 #define RTC_WAR_TPRW_SHIFT 1
ethaderu 3:78f223d34f36 11017 #define RTC_WAR_TARW_MASK 0x4u
ethaderu 3:78f223d34f36 11018 #define RTC_WAR_TARW_SHIFT 2
ethaderu 3:78f223d34f36 11019 #define RTC_WAR_TCRW_MASK 0x8u
ethaderu 3:78f223d34f36 11020 #define RTC_WAR_TCRW_SHIFT 3
ethaderu 3:78f223d34f36 11021 #define RTC_WAR_CRW_MASK 0x10u
ethaderu 3:78f223d34f36 11022 #define RTC_WAR_CRW_SHIFT 4
ethaderu 3:78f223d34f36 11023 #define RTC_WAR_SRW_MASK 0x20u
ethaderu 3:78f223d34f36 11024 #define RTC_WAR_SRW_SHIFT 5
ethaderu 3:78f223d34f36 11025 #define RTC_WAR_LRW_MASK 0x40u
ethaderu 3:78f223d34f36 11026 #define RTC_WAR_LRW_SHIFT 6
ethaderu 3:78f223d34f36 11027 #define RTC_WAR_IERW_MASK 0x80u
ethaderu 3:78f223d34f36 11028 #define RTC_WAR_IERW_SHIFT 7
ethaderu 3:78f223d34f36 11029 /* RAR Bit Fields */
ethaderu 3:78f223d34f36 11030 #define RTC_RAR_TSRR_MASK 0x1u
ethaderu 3:78f223d34f36 11031 #define RTC_RAR_TSRR_SHIFT 0
ethaderu 3:78f223d34f36 11032 #define RTC_RAR_TPRR_MASK 0x2u
ethaderu 3:78f223d34f36 11033 #define RTC_RAR_TPRR_SHIFT 1
ethaderu 3:78f223d34f36 11034 #define RTC_RAR_TARR_MASK 0x4u
ethaderu 3:78f223d34f36 11035 #define RTC_RAR_TARR_SHIFT 2
ethaderu 3:78f223d34f36 11036 #define RTC_RAR_TCRR_MASK 0x8u
ethaderu 3:78f223d34f36 11037 #define RTC_RAR_TCRR_SHIFT 3
ethaderu 3:78f223d34f36 11038 #define RTC_RAR_CRR_MASK 0x10u
ethaderu 3:78f223d34f36 11039 #define RTC_RAR_CRR_SHIFT 4
ethaderu 3:78f223d34f36 11040 #define RTC_RAR_SRR_MASK 0x20u
ethaderu 3:78f223d34f36 11041 #define RTC_RAR_SRR_SHIFT 5
ethaderu 3:78f223d34f36 11042 #define RTC_RAR_LRR_MASK 0x40u
ethaderu 3:78f223d34f36 11043 #define RTC_RAR_LRR_SHIFT 6
ethaderu 3:78f223d34f36 11044 #define RTC_RAR_IERR_MASK 0x80u
ethaderu 3:78f223d34f36 11045 #define RTC_RAR_IERR_SHIFT 7
ethaderu 3:78f223d34f36 11046
ethaderu 3:78f223d34f36 11047 /*!
ethaderu 3:78f223d34f36 11048 * @}
ethaderu 3:78f223d34f36 11049 */ /* end of group RTC_Register_Masks */
ethaderu 3:78f223d34f36 11050
ethaderu 3:78f223d34f36 11051
ethaderu 3:78f223d34f36 11052 /* RTC - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 11053 /** Peripheral RTC base address */
ethaderu 3:78f223d34f36 11054 #define RTC_BASE (0x4003D000u)
ethaderu 3:78f223d34f36 11055 /** Peripheral RTC base pointer */
ethaderu 3:78f223d34f36 11056 #define RTC ((RTC_Type *)RTC_BASE)
ethaderu 3:78f223d34f36 11057 #define RTC_BASE_PTR (RTC)
ethaderu 3:78f223d34f36 11058 /** Array initializer of RTC peripheral base addresses */
ethaderu 3:78f223d34f36 11059 #define RTC_BASE_ADDRS { RTC_BASE }
ethaderu 3:78f223d34f36 11060 /** Array initializer of RTC peripheral base pointers */
ethaderu 3:78f223d34f36 11061 #define RTC_BASE_PTRS { RTC }
ethaderu 3:78f223d34f36 11062 /** Interrupt vectors for the RTC peripheral type */
ethaderu 3:78f223d34f36 11063 #define RTC_IRQS { RTC_IRQn }
ethaderu 3:78f223d34f36 11064 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
ethaderu 3:78f223d34f36 11065
ethaderu 3:78f223d34f36 11066 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 11067 -- RTC - Register accessor macros
ethaderu 3:78f223d34f36 11068 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 11069
ethaderu 3:78f223d34f36 11070 /*!
ethaderu 3:78f223d34f36 11071 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
ethaderu 3:78f223d34f36 11072 * @{
ethaderu 3:78f223d34f36 11073 */
ethaderu 3:78f223d34f36 11074
ethaderu 3:78f223d34f36 11075
ethaderu 3:78f223d34f36 11076 /* RTC - Register instance definitions */
ethaderu 3:78f223d34f36 11077 /* RTC */
ethaderu 3:78f223d34f36 11078 #define RTC_TSR RTC_TSR_REG(RTC)
ethaderu 3:78f223d34f36 11079 #define RTC_TPR RTC_TPR_REG(RTC)
ethaderu 3:78f223d34f36 11080 #define RTC_TAR RTC_TAR_REG(RTC)
ethaderu 3:78f223d34f36 11081 #define RTC_TCR RTC_TCR_REG(RTC)
ethaderu 3:78f223d34f36 11082 #define RTC_CR RTC_CR_REG(RTC)
ethaderu 3:78f223d34f36 11083 #define RTC_SR RTC_SR_REG(RTC)
ethaderu 3:78f223d34f36 11084 #define RTC_LR RTC_LR_REG(RTC)
ethaderu 3:78f223d34f36 11085 #define RTC_IER RTC_IER_REG(RTC)
ethaderu 3:78f223d34f36 11086 #define RTC_WAR RTC_WAR_REG(RTC)
ethaderu 3:78f223d34f36 11087 #define RTC_RAR RTC_RAR_REG(RTC)
ethaderu 3:78f223d34f36 11088
ethaderu 3:78f223d34f36 11089 /*!
ethaderu 3:78f223d34f36 11090 * @}
ethaderu 3:78f223d34f36 11091 */ /* end of group RTC_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 11092
ethaderu 3:78f223d34f36 11093
ethaderu 3:78f223d34f36 11094 /*!
ethaderu 3:78f223d34f36 11095 * @}
ethaderu 3:78f223d34f36 11096 */ /* end of group RTC_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 11097
ethaderu 3:78f223d34f36 11098
ethaderu 3:78f223d34f36 11099 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 11100 -- SDHC Peripheral Access Layer
ethaderu 3:78f223d34f36 11101 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 11102
ethaderu 3:78f223d34f36 11103 /*!
ethaderu 3:78f223d34f36 11104 * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
ethaderu 3:78f223d34f36 11105 * @{
ethaderu 3:78f223d34f36 11106 */
ethaderu 3:78f223d34f36 11107
ethaderu 3:78f223d34f36 11108 /** SDHC - Register Layout Typedef */
ethaderu 3:78f223d34f36 11109 typedef struct {
ethaderu 3:78f223d34f36 11110 __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */
ethaderu 3:78f223d34f36 11111 __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */
ethaderu 3:78f223d34f36 11112 __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */
ethaderu 3:78f223d34f36 11113 __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */
ethaderu 3:78f223d34f36 11114 __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
ethaderu 3:78f223d34f36 11115 __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */
ethaderu 3:78f223d34f36 11116 __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */
ethaderu 3:78f223d34f36 11117 __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */
ethaderu 3:78f223d34f36 11118 __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */
ethaderu 3:78f223d34f36 11119 __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */
ethaderu 3:78f223d34f36 11120 __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */
ethaderu 3:78f223d34f36 11121 __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */
ethaderu 3:78f223d34f36 11122 __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
ethaderu 3:78f223d34f36 11123 __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
ethaderu 3:78f223d34f36 11124 __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
ethaderu 3:78f223d34f36 11125 uint8_t RESERVED_0[8];
ethaderu 3:78f223d34f36 11126 __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */
ethaderu 3:78f223d34f36 11127 __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */
ethaderu 3:78f223d34f36 11128 __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */
ethaderu 3:78f223d34f36 11129 uint8_t RESERVED_1[100];
ethaderu 3:78f223d34f36 11130 __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */
ethaderu 3:78f223d34f36 11131 __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
ethaderu 3:78f223d34f36 11132 uint8_t RESERVED_2[52];
ethaderu 3:78f223d34f36 11133 __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
ethaderu 3:78f223d34f36 11134 } SDHC_Type, *SDHC_MemMapPtr;
ethaderu 3:78f223d34f36 11135
ethaderu 3:78f223d34f36 11136 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 11137 -- SDHC - Register accessor macros
ethaderu 3:78f223d34f36 11138 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 11139
ethaderu 3:78f223d34f36 11140 /*!
ethaderu 3:78f223d34f36 11141 * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
ethaderu 3:78f223d34f36 11142 * @{
ethaderu 3:78f223d34f36 11143 */
ethaderu 3:78f223d34f36 11144
ethaderu 3:78f223d34f36 11145
ethaderu 3:78f223d34f36 11146 /* SDHC - Register accessors */
ethaderu 3:78f223d34f36 11147 #define SDHC_DSADDR_REG(base) ((base)->DSADDR)
ethaderu 3:78f223d34f36 11148 #define SDHC_BLKATTR_REG(base) ((base)->BLKATTR)
ethaderu 3:78f223d34f36 11149 #define SDHC_CMDARG_REG(base) ((base)->CMDARG)
ethaderu 3:78f223d34f36 11150 #define SDHC_XFERTYP_REG(base) ((base)->XFERTYP)
ethaderu 3:78f223d34f36 11151 #define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index])
ethaderu 3:78f223d34f36 11152 #define SDHC_DATPORT_REG(base) ((base)->DATPORT)
ethaderu 3:78f223d34f36 11153 #define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT)
ethaderu 3:78f223d34f36 11154 #define SDHC_PROCTL_REG(base) ((base)->PROCTL)
ethaderu 3:78f223d34f36 11155 #define SDHC_SYSCTL_REG(base) ((base)->SYSCTL)
ethaderu 3:78f223d34f36 11156 #define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT)
ethaderu 3:78f223d34f36 11157 #define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN)
ethaderu 3:78f223d34f36 11158 #define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN)
ethaderu 3:78f223d34f36 11159 #define SDHC_AC12ERR_REG(base) ((base)->AC12ERR)
ethaderu 3:78f223d34f36 11160 #define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT)
ethaderu 3:78f223d34f36 11161 #define SDHC_WML_REG(base) ((base)->WML)
ethaderu 3:78f223d34f36 11162 #define SDHC_FEVT_REG(base) ((base)->FEVT)
ethaderu 3:78f223d34f36 11163 #define SDHC_ADMAES_REG(base) ((base)->ADMAES)
ethaderu 3:78f223d34f36 11164 #define SDHC_ADSADDR_REG(base) ((base)->ADSADDR)
ethaderu 3:78f223d34f36 11165 #define SDHC_VENDOR_REG(base) ((base)->VENDOR)
ethaderu 3:78f223d34f36 11166 #define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT)
ethaderu 3:78f223d34f36 11167 #define SDHC_HOSTVER_REG(base) ((base)->HOSTVER)
ethaderu 3:78f223d34f36 11168
ethaderu 3:78f223d34f36 11169 /*!
ethaderu 3:78f223d34f36 11170 * @}
ethaderu 3:78f223d34f36 11171 */ /* end of group SDHC_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 11172
ethaderu 3:78f223d34f36 11173
ethaderu 3:78f223d34f36 11174 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 11175 -- SDHC Register Masks
ethaderu 3:78f223d34f36 11176 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 11177
ethaderu 3:78f223d34f36 11178 /*!
ethaderu 3:78f223d34f36 11179 * @addtogroup SDHC_Register_Masks SDHC Register Masks
ethaderu 3:78f223d34f36 11180 * @{
ethaderu 3:78f223d34f36 11181 */
ethaderu 3:78f223d34f36 11182
ethaderu 3:78f223d34f36 11183 /* DSADDR Bit Fields */
ethaderu 3:78f223d34f36 11184 #define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu
ethaderu 3:78f223d34f36 11185 #define SDHC_DSADDR_DSADDR_SHIFT 2
ethaderu 3:78f223d34f36 11186 #define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
ethaderu 3:78f223d34f36 11187 /* BLKATTR Bit Fields */
ethaderu 3:78f223d34f36 11188 #define SDHC_BLKATTR_BLKSIZE_MASK 0x1FFFu
ethaderu 3:78f223d34f36 11189 #define SDHC_BLKATTR_BLKSIZE_SHIFT 0
ethaderu 3:78f223d34f36 11190 #define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
ethaderu 3:78f223d34f36 11191 #define SDHC_BLKATTR_BLKCNT_MASK 0xFFFF0000u
ethaderu 3:78f223d34f36 11192 #define SDHC_BLKATTR_BLKCNT_SHIFT 16
ethaderu 3:78f223d34f36 11193 #define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
ethaderu 3:78f223d34f36 11194 /* CMDARG Bit Fields */
ethaderu 3:78f223d34f36 11195 #define SDHC_CMDARG_CMDARG_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 11196 #define SDHC_CMDARG_CMDARG_SHIFT 0
ethaderu 3:78f223d34f36 11197 #define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
ethaderu 3:78f223d34f36 11198 /* XFERTYP Bit Fields */
ethaderu 3:78f223d34f36 11199 #define SDHC_XFERTYP_DMAEN_MASK 0x1u
ethaderu 3:78f223d34f36 11200 #define SDHC_XFERTYP_DMAEN_SHIFT 0
ethaderu 3:78f223d34f36 11201 #define SDHC_XFERTYP_BCEN_MASK 0x2u
ethaderu 3:78f223d34f36 11202 #define SDHC_XFERTYP_BCEN_SHIFT 1
ethaderu 3:78f223d34f36 11203 #define SDHC_XFERTYP_AC12EN_MASK 0x4u
ethaderu 3:78f223d34f36 11204 #define SDHC_XFERTYP_AC12EN_SHIFT 2
ethaderu 3:78f223d34f36 11205 #define SDHC_XFERTYP_DTDSEL_MASK 0x10u
ethaderu 3:78f223d34f36 11206 #define SDHC_XFERTYP_DTDSEL_SHIFT 4
ethaderu 3:78f223d34f36 11207 #define SDHC_XFERTYP_MSBSEL_MASK 0x20u
ethaderu 3:78f223d34f36 11208 #define SDHC_XFERTYP_MSBSEL_SHIFT 5
ethaderu 3:78f223d34f36 11209 #define SDHC_XFERTYP_RSPTYP_MASK 0x30000u
ethaderu 3:78f223d34f36 11210 #define SDHC_XFERTYP_RSPTYP_SHIFT 16
ethaderu 3:78f223d34f36 11211 #define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
ethaderu 3:78f223d34f36 11212 #define SDHC_XFERTYP_CCCEN_MASK 0x80000u
ethaderu 3:78f223d34f36 11213 #define SDHC_XFERTYP_CCCEN_SHIFT 19
ethaderu 3:78f223d34f36 11214 #define SDHC_XFERTYP_CICEN_MASK 0x100000u
ethaderu 3:78f223d34f36 11215 #define SDHC_XFERTYP_CICEN_SHIFT 20
ethaderu 3:78f223d34f36 11216 #define SDHC_XFERTYP_DPSEL_MASK 0x200000u
ethaderu 3:78f223d34f36 11217 #define SDHC_XFERTYP_DPSEL_SHIFT 21
ethaderu 3:78f223d34f36 11218 #define SDHC_XFERTYP_CMDTYP_MASK 0xC00000u
ethaderu 3:78f223d34f36 11219 #define SDHC_XFERTYP_CMDTYP_SHIFT 22
ethaderu 3:78f223d34f36 11220 #define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
ethaderu 3:78f223d34f36 11221 #define SDHC_XFERTYP_CMDINX_MASK 0x3F000000u
ethaderu 3:78f223d34f36 11222 #define SDHC_XFERTYP_CMDINX_SHIFT 24
ethaderu 3:78f223d34f36 11223 #define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
ethaderu 3:78f223d34f36 11224 /* CMDRSP Bit Fields */
ethaderu 3:78f223d34f36 11225 #define SDHC_CMDRSP_CMDRSP0_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 11226 #define SDHC_CMDRSP_CMDRSP0_SHIFT 0
ethaderu 3:78f223d34f36 11227 #define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
ethaderu 3:78f223d34f36 11228 #define SDHC_CMDRSP_CMDRSP1_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 11229 #define SDHC_CMDRSP_CMDRSP1_SHIFT 0
ethaderu 3:78f223d34f36 11230 #define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
ethaderu 3:78f223d34f36 11231 #define SDHC_CMDRSP_CMDRSP2_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 11232 #define SDHC_CMDRSP_CMDRSP2_SHIFT 0
ethaderu 3:78f223d34f36 11233 #define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
ethaderu 3:78f223d34f36 11234 #define SDHC_CMDRSP_CMDRSP3_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 11235 #define SDHC_CMDRSP_CMDRSP3_SHIFT 0
ethaderu 3:78f223d34f36 11236 #define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
ethaderu 3:78f223d34f36 11237 /* DATPORT Bit Fields */
ethaderu 3:78f223d34f36 11238 #define SDHC_DATPORT_DATCONT_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 11239 #define SDHC_DATPORT_DATCONT_SHIFT 0
ethaderu 3:78f223d34f36 11240 #define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
ethaderu 3:78f223d34f36 11241 /* PRSSTAT Bit Fields */
ethaderu 3:78f223d34f36 11242 #define SDHC_PRSSTAT_CIHB_MASK 0x1u
ethaderu 3:78f223d34f36 11243 #define SDHC_PRSSTAT_CIHB_SHIFT 0
ethaderu 3:78f223d34f36 11244 #define SDHC_PRSSTAT_CDIHB_MASK 0x2u
ethaderu 3:78f223d34f36 11245 #define SDHC_PRSSTAT_CDIHB_SHIFT 1
ethaderu 3:78f223d34f36 11246 #define SDHC_PRSSTAT_DLA_MASK 0x4u
ethaderu 3:78f223d34f36 11247 #define SDHC_PRSSTAT_DLA_SHIFT 2
ethaderu 3:78f223d34f36 11248 #define SDHC_PRSSTAT_SDSTB_MASK 0x8u
ethaderu 3:78f223d34f36 11249 #define SDHC_PRSSTAT_SDSTB_SHIFT 3
ethaderu 3:78f223d34f36 11250 #define SDHC_PRSSTAT_IPGOFF_MASK 0x10u
ethaderu 3:78f223d34f36 11251 #define SDHC_PRSSTAT_IPGOFF_SHIFT 4
ethaderu 3:78f223d34f36 11252 #define SDHC_PRSSTAT_HCKOFF_MASK 0x20u
ethaderu 3:78f223d34f36 11253 #define SDHC_PRSSTAT_HCKOFF_SHIFT 5
ethaderu 3:78f223d34f36 11254 #define SDHC_PRSSTAT_PEROFF_MASK 0x40u
ethaderu 3:78f223d34f36 11255 #define SDHC_PRSSTAT_PEROFF_SHIFT 6
ethaderu 3:78f223d34f36 11256 #define SDHC_PRSSTAT_SDOFF_MASK 0x80u
ethaderu 3:78f223d34f36 11257 #define SDHC_PRSSTAT_SDOFF_SHIFT 7
ethaderu 3:78f223d34f36 11258 #define SDHC_PRSSTAT_WTA_MASK 0x100u
ethaderu 3:78f223d34f36 11259 #define SDHC_PRSSTAT_WTA_SHIFT 8
ethaderu 3:78f223d34f36 11260 #define SDHC_PRSSTAT_RTA_MASK 0x200u
ethaderu 3:78f223d34f36 11261 #define SDHC_PRSSTAT_RTA_SHIFT 9
ethaderu 3:78f223d34f36 11262 #define SDHC_PRSSTAT_BWEN_MASK 0x400u
ethaderu 3:78f223d34f36 11263 #define SDHC_PRSSTAT_BWEN_SHIFT 10
ethaderu 3:78f223d34f36 11264 #define SDHC_PRSSTAT_BREN_MASK 0x800u
ethaderu 3:78f223d34f36 11265 #define SDHC_PRSSTAT_BREN_SHIFT 11
ethaderu 3:78f223d34f36 11266 #define SDHC_PRSSTAT_CINS_MASK 0x10000u
ethaderu 3:78f223d34f36 11267 #define SDHC_PRSSTAT_CINS_SHIFT 16
ethaderu 3:78f223d34f36 11268 #define SDHC_PRSSTAT_CLSL_MASK 0x800000u
ethaderu 3:78f223d34f36 11269 #define SDHC_PRSSTAT_CLSL_SHIFT 23
ethaderu 3:78f223d34f36 11270 #define SDHC_PRSSTAT_DLSL_MASK 0xFF000000u
ethaderu 3:78f223d34f36 11271 #define SDHC_PRSSTAT_DLSL_SHIFT 24
ethaderu 3:78f223d34f36 11272 #define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
ethaderu 3:78f223d34f36 11273 /* PROCTL Bit Fields */
ethaderu 3:78f223d34f36 11274 #define SDHC_PROCTL_LCTL_MASK 0x1u
ethaderu 3:78f223d34f36 11275 #define SDHC_PROCTL_LCTL_SHIFT 0
ethaderu 3:78f223d34f36 11276 #define SDHC_PROCTL_DTW_MASK 0x6u
ethaderu 3:78f223d34f36 11277 #define SDHC_PROCTL_DTW_SHIFT 1
ethaderu 3:78f223d34f36 11278 #define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
ethaderu 3:78f223d34f36 11279 #define SDHC_PROCTL_D3CD_MASK 0x8u
ethaderu 3:78f223d34f36 11280 #define SDHC_PROCTL_D3CD_SHIFT 3
ethaderu 3:78f223d34f36 11281 #define SDHC_PROCTL_EMODE_MASK 0x30u
ethaderu 3:78f223d34f36 11282 #define SDHC_PROCTL_EMODE_SHIFT 4
ethaderu 3:78f223d34f36 11283 #define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
ethaderu 3:78f223d34f36 11284 #define SDHC_PROCTL_CDTL_MASK 0x40u
ethaderu 3:78f223d34f36 11285 #define SDHC_PROCTL_CDTL_SHIFT 6
ethaderu 3:78f223d34f36 11286 #define SDHC_PROCTL_CDSS_MASK 0x80u
ethaderu 3:78f223d34f36 11287 #define SDHC_PROCTL_CDSS_SHIFT 7
ethaderu 3:78f223d34f36 11288 #define SDHC_PROCTL_DMAS_MASK 0x300u
ethaderu 3:78f223d34f36 11289 #define SDHC_PROCTL_DMAS_SHIFT 8
ethaderu 3:78f223d34f36 11290 #define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
ethaderu 3:78f223d34f36 11291 #define SDHC_PROCTL_SABGREQ_MASK 0x10000u
ethaderu 3:78f223d34f36 11292 #define SDHC_PROCTL_SABGREQ_SHIFT 16
ethaderu 3:78f223d34f36 11293 #define SDHC_PROCTL_CREQ_MASK 0x20000u
ethaderu 3:78f223d34f36 11294 #define SDHC_PROCTL_CREQ_SHIFT 17
ethaderu 3:78f223d34f36 11295 #define SDHC_PROCTL_RWCTL_MASK 0x40000u
ethaderu 3:78f223d34f36 11296 #define SDHC_PROCTL_RWCTL_SHIFT 18
ethaderu 3:78f223d34f36 11297 #define SDHC_PROCTL_IABG_MASK 0x80000u
ethaderu 3:78f223d34f36 11298 #define SDHC_PROCTL_IABG_SHIFT 19
ethaderu 3:78f223d34f36 11299 #define SDHC_PROCTL_WECINT_MASK 0x1000000u
ethaderu 3:78f223d34f36 11300 #define SDHC_PROCTL_WECINT_SHIFT 24
ethaderu 3:78f223d34f36 11301 #define SDHC_PROCTL_WECINS_MASK 0x2000000u
ethaderu 3:78f223d34f36 11302 #define SDHC_PROCTL_WECINS_SHIFT 25
ethaderu 3:78f223d34f36 11303 #define SDHC_PROCTL_WECRM_MASK 0x4000000u
ethaderu 3:78f223d34f36 11304 #define SDHC_PROCTL_WECRM_SHIFT 26
ethaderu 3:78f223d34f36 11305 /* SYSCTL Bit Fields */
ethaderu 3:78f223d34f36 11306 #define SDHC_SYSCTL_IPGEN_MASK 0x1u
ethaderu 3:78f223d34f36 11307 #define SDHC_SYSCTL_IPGEN_SHIFT 0
ethaderu 3:78f223d34f36 11308 #define SDHC_SYSCTL_HCKEN_MASK 0x2u
ethaderu 3:78f223d34f36 11309 #define SDHC_SYSCTL_HCKEN_SHIFT 1
ethaderu 3:78f223d34f36 11310 #define SDHC_SYSCTL_PEREN_MASK 0x4u
ethaderu 3:78f223d34f36 11311 #define SDHC_SYSCTL_PEREN_SHIFT 2
ethaderu 3:78f223d34f36 11312 #define SDHC_SYSCTL_SDCLKEN_MASK 0x8u
ethaderu 3:78f223d34f36 11313 #define SDHC_SYSCTL_SDCLKEN_SHIFT 3
ethaderu 3:78f223d34f36 11314 #define SDHC_SYSCTL_DVS_MASK 0xF0u
ethaderu 3:78f223d34f36 11315 #define SDHC_SYSCTL_DVS_SHIFT 4
ethaderu 3:78f223d34f36 11316 #define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
ethaderu 3:78f223d34f36 11317 #define SDHC_SYSCTL_SDCLKFS_MASK 0xFF00u
ethaderu 3:78f223d34f36 11318 #define SDHC_SYSCTL_SDCLKFS_SHIFT 8
ethaderu 3:78f223d34f36 11319 #define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
ethaderu 3:78f223d34f36 11320 #define SDHC_SYSCTL_DTOCV_MASK 0xF0000u
ethaderu 3:78f223d34f36 11321 #define SDHC_SYSCTL_DTOCV_SHIFT 16
ethaderu 3:78f223d34f36 11322 #define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
ethaderu 3:78f223d34f36 11323 #define SDHC_SYSCTL_RSTA_MASK 0x1000000u
ethaderu 3:78f223d34f36 11324 #define SDHC_SYSCTL_RSTA_SHIFT 24
ethaderu 3:78f223d34f36 11325 #define SDHC_SYSCTL_RSTC_MASK 0x2000000u
ethaderu 3:78f223d34f36 11326 #define SDHC_SYSCTL_RSTC_SHIFT 25
ethaderu 3:78f223d34f36 11327 #define SDHC_SYSCTL_RSTD_MASK 0x4000000u
ethaderu 3:78f223d34f36 11328 #define SDHC_SYSCTL_RSTD_SHIFT 26
ethaderu 3:78f223d34f36 11329 #define SDHC_SYSCTL_INITA_MASK 0x8000000u
ethaderu 3:78f223d34f36 11330 #define SDHC_SYSCTL_INITA_SHIFT 27
ethaderu 3:78f223d34f36 11331 /* IRQSTAT Bit Fields */
ethaderu 3:78f223d34f36 11332 #define SDHC_IRQSTAT_CC_MASK 0x1u
ethaderu 3:78f223d34f36 11333 #define SDHC_IRQSTAT_CC_SHIFT 0
ethaderu 3:78f223d34f36 11334 #define SDHC_IRQSTAT_TC_MASK 0x2u
ethaderu 3:78f223d34f36 11335 #define SDHC_IRQSTAT_TC_SHIFT 1
ethaderu 3:78f223d34f36 11336 #define SDHC_IRQSTAT_BGE_MASK 0x4u
ethaderu 3:78f223d34f36 11337 #define SDHC_IRQSTAT_BGE_SHIFT 2
ethaderu 3:78f223d34f36 11338 #define SDHC_IRQSTAT_DINT_MASK 0x8u
ethaderu 3:78f223d34f36 11339 #define SDHC_IRQSTAT_DINT_SHIFT 3
ethaderu 3:78f223d34f36 11340 #define SDHC_IRQSTAT_BWR_MASK 0x10u
ethaderu 3:78f223d34f36 11341 #define SDHC_IRQSTAT_BWR_SHIFT 4
ethaderu 3:78f223d34f36 11342 #define SDHC_IRQSTAT_BRR_MASK 0x20u
ethaderu 3:78f223d34f36 11343 #define SDHC_IRQSTAT_BRR_SHIFT 5
ethaderu 3:78f223d34f36 11344 #define SDHC_IRQSTAT_CINS_MASK 0x40u
ethaderu 3:78f223d34f36 11345 #define SDHC_IRQSTAT_CINS_SHIFT 6
ethaderu 3:78f223d34f36 11346 #define SDHC_IRQSTAT_CRM_MASK 0x80u
ethaderu 3:78f223d34f36 11347 #define SDHC_IRQSTAT_CRM_SHIFT 7
ethaderu 3:78f223d34f36 11348 #define SDHC_IRQSTAT_CINT_MASK 0x100u
ethaderu 3:78f223d34f36 11349 #define SDHC_IRQSTAT_CINT_SHIFT 8
ethaderu 3:78f223d34f36 11350 #define SDHC_IRQSTAT_CTOE_MASK 0x10000u
ethaderu 3:78f223d34f36 11351 #define SDHC_IRQSTAT_CTOE_SHIFT 16
ethaderu 3:78f223d34f36 11352 #define SDHC_IRQSTAT_CCE_MASK 0x20000u
ethaderu 3:78f223d34f36 11353 #define SDHC_IRQSTAT_CCE_SHIFT 17
ethaderu 3:78f223d34f36 11354 #define SDHC_IRQSTAT_CEBE_MASK 0x40000u
ethaderu 3:78f223d34f36 11355 #define SDHC_IRQSTAT_CEBE_SHIFT 18
ethaderu 3:78f223d34f36 11356 #define SDHC_IRQSTAT_CIE_MASK 0x80000u
ethaderu 3:78f223d34f36 11357 #define SDHC_IRQSTAT_CIE_SHIFT 19
ethaderu 3:78f223d34f36 11358 #define SDHC_IRQSTAT_DTOE_MASK 0x100000u
ethaderu 3:78f223d34f36 11359 #define SDHC_IRQSTAT_DTOE_SHIFT 20
ethaderu 3:78f223d34f36 11360 #define SDHC_IRQSTAT_DCE_MASK 0x200000u
ethaderu 3:78f223d34f36 11361 #define SDHC_IRQSTAT_DCE_SHIFT 21
ethaderu 3:78f223d34f36 11362 #define SDHC_IRQSTAT_DEBE_MASK 0x400000u
ethaderu 3:78f223d34f36 11363 #define SDHC_IRQSTAT_DEBE_SHIFT 22
ethaderu 3:78f223d34f36 11364 #define SDHC_IRQSTAT_AC12E_MASK 0x1000000u
ethaderu 3:78f223d34f36 11365 #define SDHC_IRQSTAT_AC12E_SHIFT 24
ethaderu 3:78f223d34f36 11366 #define SDHC_IRQSTAT_DMAE_MASK 0x10000000u
ethaderu 3:78f223d34f36 11367 #define SDHC_IRQSTAT_DMAE_SHIFT 28
ethaderu 3:78f223d34f36 11368 /* IRQSTATEN Bit Fields */
ethaderu 3:78f223d34f36 11369 #define SDHC_IRQSTATEN_CCSEN_MASK 0x1u
ethaderu 3:78f223d34f36 11370 #define SDHC_IRQSTATEN_CCSEN_SHIFT 0
ethaderu 3:78f223d34f36 11371 #define SDHC_IRQSTATEN_TCSEN_MASK 0x2u
ethaderu 3:78f223d34f36 11372 #define SDHC_IRQSTATEN_TCSEN_SHIFT 1
ethaderu 3:78f223d34f36 11373 #define SDHC_IRQSTATEN_BGESEN_MASK 0x4u
ethaderu 3:78f223d34f36 11374 #define SDHC_IRQSTATEN_BGESEN_SHIFT 2
ethaderu 3:78f223d34f36 11375 #define SDHC_IRQSTATEN_DINTSEN_MASK 0x8u
ethaderu 3:78f223d34f36 11376 #define SDHC_IRQSTATEN_DINTSEN_SHIFT 3
ethaderu 3:78f223d34f36 11377 #define SDHC_IRQSTATEN_BWRSEN_MASK 0x10u
ethaderu 3:78f223d34f36 11378 #define SDHC_IRQSTATEN_BWRSEN_SHIFT 4
ethaderu 3:78f223d34f36 11379 #define SDHC_IRQSTATEN_BRRSEN_MASK 0x20u
ethaderu 3:78f223d34f36 11380 #define SDHC_IRQSTATEN_BRRSEN_SHIFT 5
ethaderu 3:78f223d34f36 11381 #define SDHC_IRQSTATEN_CINSEN_MASK 0x40u
ethaderu 3:78f223d34f36 11382 #define SDHC_IRQSTATEN_CINSEN_SHIFT 6
ethaderu 3:78f223d34f36 11383 #define SDHC_IRQSTATEN_CRMSEN_MASK 0x80u
ethaderu 3:78f223d34f36 11384 #define SDHC_IRQSTATEN_CRMSEN_SHIFT 7
ethaderu 3:78f223d34f36 11385 #define SDHC_IRQSTATEN_CINTSEN_MASK 0x100u
ethaderu 3:78f223d34f36 11386 #define SDHC_IRQSTATEN_CINTSEN_SHIFT 8
ethaderu 3:78f223d34f36 11387 #define SDHC_IRQSTATEN_CTOESEN_MASK 0x10000u
ethaderu 3:78f223d34f36 11388 #define SDHC_IRQSTATEN_CTOESEN_SHIFT 16
ethaderu 3:78f223d34f36 11389 #define SDHC_IRQSTATEN_CCESEN_MASK 0x20000u
ethaderu 3:78f223d34f36 11390 #define SDHC_IRQSTATEN_CCESEN_SHIFT 17
ethaderu 3:78f223d34f36 11391 #define SDHC_IRQSTATEN_CEBESEN_MASK 0x40000u
ethaderu 3:78f223d34f36 11392 #define SDHC_IRQSTATEN_CEBESEN_SHIFT 18
ethaderu 3:78f223d34f36 11393 #define SDHC_IRQSTATEN_CIESEN_MASK 0x80000u
ethaderu 3:78f223d34f36 11394 #define SDHC_IRQSTATEN_CIESEN_SHIFT 19
ethaderu 3:78f223d34f36 11395 #define SDHC_IRQSTATEN_DTOESEN_MASK 0x100000u
ethaderu 3:78f223d34f36 11396 #define SDHC_IRQSTATEN_DTOESEN_SHIFT 20
ethaderu 3:78f223d34f36 11397 #define SDHC_IRQSTATEN_DCESEN_MASK 0x200000u
ethaderu 3:78f223d34f36 11398 #define SDHC_IRQSTATEN_DCESEN_SHIFT 21
ethaderu 3:78f223d34f36 11399 #define SDHC_IRQSTATEN_DEBESEN_MASK 0x400000u
ethaderu 3:78f223d34f36 11400 #define SDHC_IRQSTATEN_DEBESEN_SHIFT 22
ethaderu 3:78f223d34f36 11401 #define SDHC_IRQSTATEN_AC12ESEN_MASK 0x1000000u
ethaderu 3:78f223d34f36 11402 #define SDHC_IRQSTATEN_AC12ESEN_SHIFT 24
ethaderu 3:78f223d34f36 11403 #define SDHC_IRQSTATEN_DMAESEN_MASK 0x10000000u
ethaderu 3:78f223d34f36 11404 #define SDHC_IRQSTATEN_DMAESEN_SHIFT 28
ethaderu 3:78f223d34f36 11405 /* IRQSIGEN Bit Fields */
ethaderu 3:78f223d34f36 11406 #define SDHC_IRQSIGEN_CCIEN_MASK 0x1u
ethaderu 3:78f223d34f36 11407 #define SDHC_IRQSIGEN_CCIEN_SHIFT 0
ethaderu 3:78f223d34f36 11408 #define SDHC_IRQSIGEN_TCIEN_MASK 0x2u
ethaderu 3:78f223d34f36 11409 #define SDHC_IRQSIGEN_TCIEN_SHIFT 1
ethaderu 3:78f223d34f36 11410 #define SDHC_IRQSIGEN_BGEIEN_MASK 0x4u
ethaderu 3:78f223d34f36 11411 #define SDHC_IRQSIGEN_BGEIEN_SHIFT 2
ethaderu 3:78f223d34f36 11412 #define SDHC_IRQSIGEN_DINTIEN_MASK 0x8u
ethaderu 3:78f223d34f36 11413 #define SDHC_IRQSIGEN_DINTIEN_SHIFT 3
ethaderu 3:78f223d34f36 11414 #define SDHC_IRQSIGEN_BWRIEN_MASK 0x10u
ethaderu 3:78f223d34f36 11415 #define SDHC_IRQSIGEN_BWRIEN_SHIFT 4
ethaderu 3:78f223d34f36 11416 #define SDHC_IRQSIGEN_BRRIEN_MASK 0x20u
ethaderu 3:78f223d34f36 11417 #define SDHC_IRQSIGEN_BRRIEN_SHIFT 5
ethaderu 3:78f223d34f36 11418 #define SDHC_IRQSIGEN_CINSIEN_MASK 0x40u
ethaderu 3:78f223d34f36 11419 #define SDHC_IRQSIGEN_CINSIEN_SHIFT 6
ethaderu 3:78f223d34f36 11420 #define SDHC_IRQSIGEN_CRMIEN_MASK 0x80u
ethaderu 3:78f223d34f36 11421 #define SDHC_IRQSIGEN_CRMIEN_SHIFT 7
ethaderu 3:78f223d34f36 11422 #define SDHC_IRQSIGEN_CINTIEN_MASK 0x100u
ethaderu 3:78f223d34f36 11423 #define SDHC_IRQSIGEN_CINTIEN_SHIFT 8
ethaderu 3:78f223d34f36 11424 #define SDHC_IRQSIGEN_CTOEIEN_MASK 0x10000u
ethaderu 3:78f223d34f36 11425 #define SDHC_IRQSIGEN_CTOEIEN_SHIFT 16
ethaderu 3:78f223d34f36 11426 #define SDHC_IRQSIGEN_CCEIEN_MASK 0x20000u
ethaderu 3:78f223d34f36 11427 #define SDHC_IRQSIGEN_CCEIEN_SHIFT 17
ethaderu 3:78f223d34f36 11428 #define SDHC_IRQSIGEN_CEBEIEN_MASK 0x40000u
ethaderu 3:78f223d34f36 11429 #define SDHC_IRQSIGEN_CEBEIEN_SHIFT 18
ethaderu 3:78f223d34f36 11430 #define SDHC_IRQSIGEN_CIEIEN_MASK 0x80000u
ethaderu 3:78f223d34f36 11431 #define SDHC_IRQSIGEN_CIEIEN_SHIFT 19
ethaderu 3:78f223d34f36 11432 #define SDHC_IRQSIGEN_DTOEIEN_MASK 0x100000u
ethaderu 3:78f223d34f36 11433 #define SDHC_IRQSIGEN_DTOEIEN_SHIFT 20
ethaderu 3:78f223d34f36 11434 #define SDHC_IRQSIGEN_DCEIEN_MASK 0x200000u
ethaderu 3:78f223d34f36 11435 #define SDHC_IRQSIGEN_DCEIEN_SHIFT 21
ethaderu 3:78f223d34f36 11436 #define SDHC_IRQSIGEN_DEBEIEN_MASK 0x400000u
ethaderu 3:78f223d34f36 11437 #define SDHC_IRQSIGEN_DEBEIEN_SHIFT 22
ethaderu 3:78f223d34f36 11438 #define SDHC_IRQSIGEN_AC12EIEN_MASK 0x1000000u
ethaderu 3:78f223d34f36 11439 #define SDHC_IRQSIGEN_AC12EIEN_SHIFT 24
ethaderu 3:78f223d34f36 11440 #define SDHC_IRQSIGEN_DMAEIEN_MASK 0x10000000u
ethaderu 3:78f223d34f36 11441 #define SDHC_IRQSIGEN_DMAEIEN_SHIFT 28
ethaderu 3:78f223d34f36 11442 /* AC12ERR Bit Fields */
ethaderu 3:78f223d34f36 11443 #define SDHC_AC12ERR_AC12NE_MASK 0x1u
ethaderu 3:78f223d34f36 11444 #define SDHC_AC12ERR_AC12NE_SHIFT 0
ethaderu 3:78f223d34f36 11445 #define SDHC_AC12ERR_AC12TOE_MASK 0x2u
ethaderu 3:78f223d34f36 11446 #define SDHC_AC12ERR_AC12TOE_SHIFT 1
ethaderu 3:78f223d34f36 11447 #define SDHC_AC12ERR_AC12EBE_MASK 0x4u
ethaderu 3:78f223d34f36 11448 #define SDHC_AC12ERR_AC12EBE_SHIFT 2
ethaderu 3:78f223d34f36 11449 #define SDHC_AC12ERR_AC12CE_MASK 0x8u
ethaderu 3:78f223d34f36 11450 #define SDHC_AC12ERR_AC12CE_SHIFT 3
ethaderu 3:78f223d34f36 11451 #define SDHC_AC12ERR_AC12IE_MASK 0x10u
ethaderu 3:78f223d34f36 11452 #define SDHC_AC12ERR_AC12IE_SHIFT 4
ethaderu 3:78f223d34f36 11453 #define SDHC_AC12ERR_CNIBAC12E_MASK 0x80u
ethaderu 3:78f223d34f36 11454 #define SDHC_AC12ERR_CNIBAC12E_SHIFT 7
ethaderu 3:78f223d34f36 11455 /* HTCAPBLT Bit Fields */
ethaderu 3:78f223d34f36 11456 #define SDHC_HTCAPBLT_MBL_MASK 0x70000u
ethaderu 3:78f223d34f36 11457 #define SDHC_HTCAPBLT_MBL_SHIFT 16
ethaderu 3:78f223d34f36 11458 #define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
ethaderu 3:78f223d34f36 11459 #define SDHC_HTCAPBLT_ADMAS_MASK 0x100000u
ethaderu 3:78f223d34f36 11460 #define SDHC_HTCAPBLT_ADMAS_SHIFT 20
ethaderu 3:78f223d34f36 11461 #define SDHC_HTCAPBLT_HSS_MASK 0x200000u
ethaderu 3:78f223d34f36 11462 #define SDHC_HTCAPBLT_HSS_SHIFT 21
ethaderu 3:78f223d34f36 11463 #define SDHC_HTCAPBLT_DMAS_MASK 0x400000u
ethaderu 3:78f223d34f36 11464 #define SDHC_HTCAPBLT_DMAS_SHIFT 22
ethaderu 3:78f223d34f36 11465 #define SDHC_HTCAPBLT_SRS_MASK 0x800000u
ethaderu 3:78f223d34f36 11466 #define SDHC_HTCAPBLT_SRS_SHIFT 23
ethaderu 3:78f223d34f36 11467 #define SDHC_HTCAPBLT_VS33_MASK 0x1000000u
ethaderu 3:78f223d34f36 11468 #define SDHC_HTCAPBLT_VS33_SHIFT 24
ethaderu 3:78f223d34f36 11469 /* WML Bit Fields */
ethaderu 3:78f223d34f36 11470 #define SDHC_WML_RDWML_MASK 0xFFu
ethaderu 3:78f223d34f36 11471 #define SDHC_WML_RDWML_SHIFT 0
ethaderu 3:78f223d34f36 11472 #define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
ethaderu 3:78f223d34f36 11473 #define SDHC_WML_WRWML_MASK 0xFF0000u
ethaderu 3:78f223d34f36 11474 #define SDHC_WML_WRWML_SHIFT 16
ethaderu 3:78f223d34f36 11475 #define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
ethaderu 3:78f223d34f36 11476 /* FEVT Bit Fields */
ethaderu 3:78f223d34f36 11477 #define SDHC_FEVT_AC12NE_MASK 0x1u
ethaderu 3:78f223d34f36 11478 #define SDHC_FEVT_AC12NE_SHIFT 0
ethaderu 3:78f223d34f36 11479 #define SDHC_FEVT_AC12TOE_MASK 0x2u
ethaderu 3:78f223d34f36 11480 #define SDHC_FEVT_AC12TOE_SHIFT 1
ethaderu 3:78f223d34f36 11481 #define SDHC_FEVT_AC12CE_MASK 0x4u
ethaderu 3:78f223d34f36 11482 #define SDHC_FEVT_AC12CE_SHIFT 2
ethaderu 3:78f223d34f36 11483 #define SDHC_FEVT_AC12EBE_MASK 0x8u
ethaderu 3:78f223d34f36 11484 #define SDHC_FEVT_AC12EBE_SHIFT 3
ethaderu 3:78f223d34f36 11485 #define SDHC_FEVT_AC12IE_MASK 0x10u
ethaderu 3:78f223d34f36 11486 #define SDHC_FEVT_AC12IE_SHIFT 4
ethaderu 3:78f223d34f36 11487 #define SDHC_FEVT_CNIBAC12E_MASK 0x80u
ethaderu 3:78f223d34f36 11488 #define SDHC_FEVT_CNIBAC12E_SHIFT 7
ethaderu 3:78f223d34f36 11489 #define SDHC_FEVT_CTOE_MASK 0x10000u
ethaderu 3:78f223d34f36 11490 #define SDHC_FEVT_CTOE_SHIFT 16
ethaderu 3:78f223d34f36 11491 #define SDHC_FEVT_CCE_MASK 0x20000u
ethaderu 3:78f223d34f36 11492 #define SDHC_FEVT_CCE_SHIFT 17
ethaderu 3:78f223d34f36 11493 #define SDHC_FEVT_CEBE_MASK 0x40000u
ethaderu 3:78f223d34f36 11494 #define SDHC_FEVT_CEBE_SHIFT 18
ethaderu 3:78f223d34f36 11495 #define SDHC_FEVT_CIE_MASK 0x80000u
ethaderu 3:78f223d34f36 11496 #define SDHC_FEVT_CIE_SHIFT 19
ethaderu 3:78f223d34f36 11497 #define SDHC_FEVT_DTOE_MASK 0x100000u
ethaderu 3:78f223d34f36 11498 #define SDHC_FEVT_DTOE_SHIFT 20
ethaderu 3:78f223d34f36 11499 #define SDHC_FEVT_DCE_MASK 0x200000u
ethaderu 3:78f223d34f36 11500 #define SDHC_FEVT_DCE_SHIFT 21
ethaderu 3:78f223d34f36 11501 #define SDHC_FEVT_DEBE_MASK 0x400000u
ethaderu 3:78f223d34f36 11502 #define SDHC_FEVT_DEBE_SHIFT 22
ethaderu 3:78f223d34f36 11503 #define SDHC_FEVT_AC12E_MASK 0x1000000u
ethaderu 3:78f223d34f36 11504 #define SDHC_FEVT_AC12E_SHIFT 24
ethaderu 3:78f223d34f36 11505 #define SDHC_FEVT_DMAE_MASK 0x10000000u
ethaderu 3:78f223d34f36 11506 #define SDHC_FEVT_DMAE_SHIFT 28
ethaderu 3:78f223d34f36 11507 #define SDHC_FEVT_CINT_MASK 0x80000000u
ethaderu 3:78f223d34f36 11508 #define SDHC_FEVT_CINT_SHIFT 31
ethaderu 3:78f223d34f36 11509 /* ADMAES Bit Fields */
ethaderu 3:78f223d34f36 11510 #define SDHC_ADMAES_ADMAES_MASK 0x3u
ethaderu 3:78f223d34f36 11511 #define SDHC_ADMAES_ADMAES_SHIFT 0
ethaderu 3:78f223d34f36 11512 #define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
ethaderu 3:78f223d34f36 11513 #define SDHC_ADMAES_ADMALME_MASK 0x4u
ethaderu 3:78f223d34f36 11514 #define SDHC_ADMAES_ADMALME_SHIFT 2
ethaderu 3:78f223d34f36 11515 #define SDHC_ADMAES_ADMADCE_MASK 0x8u
ethaderu 3:78f223d34f36 11516 #define SDHC_ADMAES_ADMADCE_SHIFT 3
ethaderu 3:78f223d34f36 11517 /* ADSADDR Bit Fields */
ethaderu 3:78f223d34f36 11518 #define SDHC_ADSADDR_ADSADDR_MASK 0xFFFFFFFCu
ethaderu 3:78f223d34f36 11519 #define SDHC_ADSADDR_ADSADDR_SHIFT 2
ethaderu 3:78f223d34f36 11520 #define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
ethaderu 3:78f223d34f36 11521 /* VENDOR Bit Fields */
ethaderu 3:78f223d34f36 11522 #define SDHC_VENDOR_EXTDMAEN_MASK 0x1u
ethaderu 3:78f223d34f36 11523 #define SDHC_VENDOR_EXTDMAEN_SHIFT 0
ethaderu 3:78f223d34f36 11524 #define SDHC_VENDOR_EXBLKNU_MASK 0x2u
ethaderu 3:78f223d34f36 11525 #define SDHC_VENDOR_EXBLKNU_SHIFT 1
ethaderu 3:78f223d34f36 11526 #define SDHC_VENDOR_INTSTVAL_MASK 0xFF0000u
ethaderu 3:78f223d34f36 11527 #define SDHC_VENDOR_INTSTVAL_SHIFT 16
ethaderu 3:78f223d34f36 11528 #define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
ethaderu 3:78f223d34f36 11529 /* MMCBOOT Bit Fields */
ethaderu 3:78f223d34f36 11530 #define SDHC_MMCBOOT_DTOCVACK_MASK 0xFu
ethaderu 3:78f223d34f36 11531 #define SDHC_MMCBOOT_DTOCVACK_SHIFT 0
ethaderu 3:78f223d34f36 11532 #define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
ethaderu 3:78f223d34f36 11533 #define SDHC_MMCBOOT_BOOTACK_MASK 0x10u
ethaderu 3:78f223d34f36 11534 #define SDHC_MMCBOOT_BOOTACK_SHIFT 4
ethaderu 3:78f223d34f36 11535 #define SDHC_MMCBOOT_BOOTMODE_MASK 0x20u
ethaderu 3:78f223d34f36 11536 #define SDHC_MMCBOOT_BOOTMODE_SHIFT 5
ethaderu 3:78f223d34f36 11537 #define SDHC_MMCBOOT_BOOTEN_MASK 0x40u
ethaderu 3:78f223d34f36 11538 #define SDHC_MMCBOOT_BOOTEN_SHIFT 6
ethaderu 3:78f223d34f36 11539 #define SDHC_MMCBOOT_AUTOSABGEN_MASK 0x80u
ethaderu 3:78f223d34f36 11540 #define SDHC_MMCBOOT_AUTOSABGEN_SHIFT 7
ethaderu 3:78f223d34f36 11541 #define SDHC_MMCBOOT_BOOTBLKCNT_MASK 0xFFFF0000u
ethaderu 3:78f223d34f36 11542 #define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT 16
ethaderu 3:78f223d34f36 11543 #define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
ethaderu 3:78f223d34f36 11544 /* HOSTVER Bit Fields */
ethaderu 3:78f223d34f36 11545 #define SDHC_HOSTVER_SVN_MASK 0xFFu
ethaderu 3:78f223d34f36 11546 #define SDHC_HOSTVER_SVN_SHIFT 0
ethaderu 3:78f223d34f36 11547 #define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
ethaderu 3:78f223d34f36 11548 #define SDHC_HOSTVER_VVN_MASK 0xFF00u
ethaderu 3:78f223d34f36 11549 #define SDHC_HOSTVER_VVN_SHIFT 8
ethaderu 3:78f223d34f36 11550 #define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
ethaderu 3:78f223d34f36 11551
ethaderu 3:78f223d34f36 11552 /*!
ethaderu 3:78f223d34f36 11553 * @}
ethaderu 3:78f223d34f36 11554 */ /* end of group SDHC_Register_Masks */
ethaderu 3:78f223d34f36 11555
ethaderu 3:78f223d34f36 11556
ethaderu 3:78f223d34f36 11557 /* SDHC - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 11558 /** Peripheral SDHC base address */
ethaderu 3:78f223d34f36 11559 #define SDHC_BASE (0x400B1000u)
ethaderu 3:78f223d34f36 11560 /** Peripheral SDHC base pointer */
ethaderu 3:78f223d34f36 11561 #define SDHC ((SDHC_Type *)SDHC_BASE)
ethaderu 3:78f223d34f36 11562 #define SDHC_BASE_PTR (SDHC)
ethaderu 3:78f223d34f36 11563 /** Array initializer of SDHC peripheral base addresses */
ethaderu 3:78f223d34f36 11564 #define SDHC_BASE_ADDRS { SDHC_BASE }
ethaderu 3:78f223d34f36 11565 /** Array initializer of SDHC peripheral base pointers */
ethaderu 3:78f223d34f36 11566 #define SDHC_BASE_PTRS { SDHC }
ethaderu 3:78f223d34f36 11567 /** Interrupt vectors for the SDHC peripheral type */
ethaderu 3:78f223d34f36 11568 #define SDHC_IRQS { SDHC_IRQn }
ethaderu 3:78f223d34f36 11569
ethaderu 3:78f223d34f36 11570 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 11571 -- SDHC - Register accessor macros
ethaderu 3:78f223d34f36 11572 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 11573
ethaderu 3:78f223d34f36 11574 /*!
ethaderu 3:78f223d34f36 11575 * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
ethaderu 3:78f223d34f36 11576 * @{
ethaderu 3:78f223d34f36 11577 */
ethaderu 3:78f223d34f36 11578
ethaderu 3:78f223d34f36 11579
ethaderu 3:78f223d34f36 11580 /* SDHC - Register instance definitions */
ethaderu 3:78f223d34f36 11581 /* SDHC */
ethaderu 3:78f223d34f36 11582 #define SDHC_DSADDR SDHC_DSADDR_REG(SDHC)
ethaderu 3:78f223d34f36 11583 #define SDHC_BLKATTR SDHC_BLKATTR_REG(SDHC)
ethaderu 3:78f223d34f36 11584 #define SDHC_CMDARG SDHC_CMDARG_REG(SDHC)
ethaderu 3:78f223d34f36 11585 #define SDHC_XFERTYP SDHC_XFERTYP_REG(SDHC)
ethaderu 3:78f223d34f36 11586 #define SDHC_CMDRSP0 SDHC_CMDRSP_REG(SDHC,0)
ethaderu 3:78f223d34f36 11587 #define SDHC_CMDRSP1 SDHC_CMDRSP_REG(SDHC,1)
ethaderu 3:78f223d34f36 11588 #define SDHC_CMDRSP2 SDHC_CMDRSP_REG(SDHC,2)
ethaderu 3:78f223d34f36 11589 #define SDHC_CMDRSP3 SDHC_CMDRSP_REG(SDHC,3)
ethaderu 3:78f223d34f36 11590 #define SDHC_DATPORT SDHC_DATPORT_REG(SDHC)
ethaderu 3:78f223d34f36 11591 #define SDHC_PRSSTAT SDHC_PRSSTAT_REG(SDHC)
ethaderu 3:78f223d34f36 11592 #define SDHC_PROCTL SDHC_PROCTL_REG(SDHC)
ethaderu 3:78f223d34f36 11593 #define SDHC_SYSCTL SDHC_SYSCTL_REG(SDHC)
ethaderu 3:78f223d34f36 11594 #define SDHC_IRQSTAT SDHC_IRQSTAT_REG(SDHC)
ethaderu 3:78f223d34f36 11595 #define SDHC_IRQSTATEN SDHC_IRQSTATEN_REG(SDHC)
ethaderu 3:78f223d34f36 11596 #define SDHC_IRQSIGEN SDHC_IRQSIGEN_REG(SDHC)
ethaderu 3:78f223d34f36 11597 #define SDHC_AC12ERR SDHC_AC12ERR_REG(SDHC)
ethaderu 3:78f223d34f36 11598 #define SDHC_HTCAPBLT SDHC_HTCAPBLT_REG(SDHC)
ethaderu 3:78f223d34f36 11599 #define SDHC_WML SDHC_WML_REG(SDHC)
ethaderu 3:78f223d34f36 11600 #define SDHC_FEVT SDHC_FEVT_REG(SDHC)
ethaderu 3:78f223d34f36 11601 #define SDHC_ADMAES SDHC_ADMAES_REG(SDHC)
ethaderu 3:78f223d34f36 11602 #define SDHC_ADSADDR SDHC_ADSADDR_REG(SDHC)
ethaderu 3:78f223d34f36 11603 #define SDHC_VENDOR SDHC_VENDOR_REG(SDHC)
ethaderu 3:78f223d34f36 11604 #define SDHC_MMCBOOT SDHC_MMCBOOT_REG(SDHC)
ethaderu 3:78f223d34f36 11605 #define SDHC_HOSTVER SDHC_HOSTVER_REG(SDHC)
ethaderu 3:78f223d34f36 11606
ethaderu 3:78f223d34f36 11607 /* SDHC - Register array accessors */
ethaderu 3:78f223d34f36 11608 #define SDHC_CMDRSP(index) SDHC_CMDRSP_REG(SDHC,index)
ethaderu 3:78f223d34f36 11609
ethaderu 3:78f223d34f36 11610 /*!
ethaderu 3:78f223d34f36 11611 * @}
ethaderu 3:78f223d34f36 11612 */ /* end of group SDHC_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 11613
ethaderu 3:78f223d34f36 11614
ethaderu 3:78f223d34f36 11615 /*!
ethaderu 3:78f223d34f36 11616 * @}
ethaderu 3:78f223d34f36 11617 */ /* end of group SDHC_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 11618
ethaderu 3:78f223d34f36 11619
ethaderu 3:78f223d34f36 11620 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 11621 -- SIM Peripheral Access Layer
ethaderu 3:78f223d34f36 11622 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 11623
ethaderu 3:78f223d34f36 11624 /*!
ethaderu 3:78f223d34f36 11625 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
ethaderu 3:78f223d34f36 11626 * @{
ethaderu 3:78f223d34f36 11627 */
ethaderu 3:78f223d34f36 11628
ethaderu 3:78f223d34f36 11629 /** SIM - Register Layout Typedef */
ethaderu 3:78f223d34f36 11630 typedef struct {
ethaderu 3:78f223d34f36 11631 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
ethaderu 3:78f223d34f36 11632 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
ethaderu 3:78f223d34f36 11633 uint8_t RESERVED_0[4092];
ethaderu 3:78f223d34f36 11634 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
ethaderu 3:78f223d34f36 11635 uint8_t RESERVED_1[4];
ethaderu 3:78f223d34f36 11636 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
ethaderu 3:78f223d34f36 11637 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
ethaderu 3:78f223d34f36 11638 uint8_t RESERVED_2[4];
ethaderu 3:78f223d34f36 11639 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
ethaderu 3:78f223d34f36 11640 uint8_t RESERVED_3[8];
ethaderu 3:78f223d34f36 11641 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
ethaderu 3:78f223d34f36 11642 __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
ethaderu 3:78f223d34f36 11643 __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
ethaderu 3:78f223d34f36 11644 __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
ethaderu 3:78f223d34f36 11645 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
ethaderu 3:78f223d34f36 11646 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
ethaderu 3:78f223d34f36 11647 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
ethaderu 3:78f223d34f36 11648 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
ethaderu 3:78f223d34f36 11649 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
ethaderu 3:78f223d34f36 11650 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
ethaderu 3:78f223d34f36 11651 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
ethaderu 3:78f223d34f36 11652 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
ethaderu 3:78f223d34f36 11653 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
ethaderu 3:78f223d34f36 11654 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
ethaderu 3:78f223d34f36 11655 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
ethaderu 3:78f223d34f36 11656 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
ethaderu 3:78f223d34f36 11657 } SIM_Type, *SIM_MemMapPtr;
ethaderu 3:78f223d34f36 11658
ethaderu 3:78f223d34f36 11659 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 11660 -- SIM - Register accessor macros
ethaderu 3:78f223d34f36 11661 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 11662
ethaderu 3:78f223d34f36 11663 /*!
ethaderu 3:78f223d34f36 11664 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
ethaderu 3:78f223d34f36 11665 * @{
ethaderu 3:78f223d34f36 11666 */
ethaderu 3:78f223d34f36 11667
ethaderu 3:78f223d34f36 11668
ethaderu 3:78f223d34f36 11669 /* SIM - Register accessors */
ethaderu 3:78f223d34f36 11670 #define SIM_SOPT1_REG(base) ((base)->SOPT1)
ethaderu 3:78f223d34f36 11671 #define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
ethaderu 3:78f223d34f36 11672 #define SIM_SOPT2_REG(base) ((base)->SOPT2)
ethaderu 3:78f223d34f36 11673 #define SIM_SOPT4_REG(base) ((base)->SOPT4)
ethaderu 3:78f223d34f36 11674 #define SIM_SOPT5_REG(base) ((base)->SOPT5)
ethaderu 3:78f223d34f36 11675 #define SIM_SOPT7_REG(base) ((base)->SOPT7)
ethaderu 3:78f223d34f36 11676 #define SIM_SDID_REG(base) ((base)->SDID)
ethaderu 3:78f223d34f36 11677 #define SIM_SCGC1_REG(base) ((base)->SCGC1)
ethaderu 3:78f223d34f36 11678 #define SIM_SCGC2_REG(base) ((base)->SCGC2)
ethaderu 3:78f223d34f36 11679 #define SIM_SCGC3_REG(base) ((base)->SCGC3)
ethaderu 3:78f223d34f36 11680 #define SIM_SCGC4_REG(base) ((base)->SCGC4)
ethaderu 3:78f223d34f36 11681 #define SIM_SCGC5_REG(base) ((base)->SCGC5)
ethaderu 3:78f223d34f36 11682 #define SIM_SCGC6_REG(base) ((base)->SCGC6)
ethaderu 3:78f223d34f36 11683 #define SIM_SCGC7_REG(base) ((base)->SCGC7)
ethaderu 3:78f223d34f36 11684 #define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
ethaderu 3:78f223d34f36 11685 #define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)
ethaderu 3:78f223d34f36 11686 #define SIM_FCFG1_REG(base) ((base)->FCFG1)
ethaderu 3:78f223d34f36 11687 #define SIM_FCFG2_REG(base) ((base)->FCFG2)
ethaderu 3:78f223d34f36 11688 #define SIM_UIDH_REG(base) ((base)->UIDH)
ethaderu 3:78f223d34f36 11689 #define SIM_UIDMH_REG(base) ((base)->UIDMH)
ethaderu 3:78f223d34f36 11690 #define SIM_UIDML_REG(base) ((base)->UIDML)
ethaderu 3:78f223d34f36 11691 #define SIM_UIDL_REG(base) ((base)->UIDL)
ethaderu 3:78f223d34f36 11692
ethaderu 3:78f223d34f36 11693 /*!
ethaderu 3:78f223d34f36 11694 * @}
ethaderu 3:78f223d34f36 11695 */ /* end of group SIM_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 11696
ethaderu 3:78f223d34f36 11697
ethaderu 3:78f223d34f36 11698 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 11699 -- SIM Register Masks
ethaderu 3:78f223d34f36 11700 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 11701
ethaderu 3:78f223d34f36 11702 /*!
ethaderu 3:78f223d34f36 11703 * @addtogroup SIM_Register_Masks SIM Register Masks
ethaderu 3:78f223d34f36 11704 * @{
ethaderu 3:78f223d34f36 11705 */
ethaderu 3:78f223d34f36 11706
ethaderu 3:78f223d34f36 11707 /* SOPT1 Bit Fields */
ethaderu 3:78f223d34f36 11708 #define SIM_SOPT1_RAMSIZE_MASK 0xF000u
ethaderu 3:78f223d34f36 11709 #define SIM_SOPT1_RAMSIZE_SHIFT 12
ethaderu 3:78f223d34f36 11710 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
ethaderu 3:78f223d34f36 11711 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
ethaderu 3:78f223d34f36 11712 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
ethaderu 3:78f223d34f36 11713 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
ethaderu 3:78f223d34f36 11714 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
ethaderu 3:78f223d34f36 11715 #define SIM_SOPT1_USBVSTBY_SHIFT 29
ethaderu 3:78f223d34f36 11716 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
ethaderu 3:78f223d34f36 11717 #define SIM_SOPT1_USBSSTBY_SHIFT 30
ethaderu 3:78f223d34f36 11718 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
ethaderu 3:78f223d34f36 11719 #define SIM_SOPT1_USBREGEN_SHIFT 31
ethaderu 3:78f223d34f36 11720 /* SOPT1CFG Bit Fields */
ethaderu 3:78f223d34f36 11721 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
ethaderu 3:78f223d34f36 11722 #define SIM_SOPT1CFG_URWE_SHIFT 24
ethaderu 3:78f223d34f36 11723 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
ethaderu 3:78f223d34f36 11724 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
ethaderu 3:78f223d34f36 11725 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
ethaderu 3:78f223d34f36 11726 #define SIM_SOPT1CFG_USSWE_SHIFT 26
ethaderu 3:78f223d34f36 11727 /* SOPT2 Bit Fields */
ethaderu 3:78f223d34f36 11728 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
ethaderu 3:78f223d34f36 11729 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
ethaderu 3:78f223d34f36 11730 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
ethaderu 3:78f223d34f36 11731 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
ethaderu 3:78f223d34f36 11732 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
ethaderu 3:78f223d34f36 11733 #define SIM_SOPT2_FBSL_MASK 0x300u
ethaderu 3:78f223d34f36 11734 #define SIM_SOPT2_FBSL_SHIFT 8
ethaderu 3:78f223d34f36 11735 #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
ethaderu 3:78f223d34f36 11736 #define SIM_SOPT2_PTD7PAD_MASK 0x800u
ethaderu 3:78f223d34f36 11737 #define SIM_SOPT2_PTD7PAD_SHIFT 11
ethaderu 3:78f223d34f36 11738 #define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
ethaderu 3:78f223d34f36 11739 #define SIM_SOPT2_TRACECLKSEL_SHIFT 12
ethaderu 3:78f223d34f36 11740 #define SIM_SOPT2_PLLFLLSEL_MASK 0x30000u
ethaderu 3:78f223d34f36 11741 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
ethaderu 3:78f223d34f36 11742 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
ethaderu 3:78f223d34f36 11743 #define SIM_SOPT2_USBSRC_MASK 0x40000u
ethaderu 3:78f223d34f36 11744 #define SIM_SOPT2_USBSRC_SHIFT 18
ethaderu 3:78f223d34f36 11745 #define SIM_SOPT2_RMIISRC_MASK 0x80000u
ethaderu 3:78f223d34f36 11746 #define SIM_SOPT2_RMIISRC_SHIFT 19
ethaderu 3:78f223d34f36 11747 #define SIM_SOPT2_TIMESRC_MASK 0x300000u
ethaderu 3:78f223d34f36 11748 #define SIM_SOPT2_TIMESRC_SHIFT 20
ethaderu 3:78f223d34f36 11749 #define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)
ethaderu 3:78f223d34f36 11750 #define SIM_SOPT2_SDHCSRC_MASK 0x30000000u
ethaderu 3:78f223d34f36 11751 #define SIM_SOPT2_SDHCSRC_SHIFT 28
ethaderu 3:78f223d34f36 11752 #define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
ethaderu 3:78f223d34f36 11753 /* SOPT4 Bit Fields */
ethaderu 3:78f223d34f36 11754 #define SIM_SOPT4_FTM0FLT0_MASK 0x1u
ethaderu 3:78f223d34f36 11755 #define SIM_SOPT4_FTM0FLT0_SHIFT 0
ethaderu 3:78f223d34f36 11756 #define SIM_SOPT4_FTM0FLT1_MASK 0x2u
ethaderu 3:78f223d34f36 11757 #define SIM_SOPT4_FTM0FLT1_SHIFT 1
ethaderu 3:78f223d34f36 11758 #define SIM_SOPT4_FTM0FLT2_MASK 0x4u
ethaderu 3:78f223d34f36 11759 #define SIM_SOPT4_FTM0FLT2_SHIFT 2
ethaderu 3:78f223d34f36 11760 #define SIM_SOPT4_FTM1FLT0_MASK 0x10u
ethaderu 3:78f223d34f36 11761 #define SIM_SOPT4_FTM1FLT0_SHIFT 4
ethaderu 3:78f223d34f36 11762 #define SIM_SOPT4_FTM2FLT0_MASK 0x100u
ethaderu 3:78f223d34f36 11763 #define SIM_SOPT4_FTM2FLT0_SHIFT 8
ethaderu 3:78f223d34f36 11764 #define SIM_SOPT4_FTM3FLT0_MASK 0x1000u
ethaderu 3:78f223d34f36 11765 #define SIM_SOPT4_FTM3FLT0_SHIFT 12
ethaderu 3:78f223d34f36 11766 #define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
ethaderu 3:78f223d34f36 11767 #define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
ethaderu 3:78f223d34f36 11768 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
ethaderu 3:78f223d34f36 11769 #define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
ethaderu 3:78f223d34f36 11770 #define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
ethaderu 3:78f223d34f36 11771 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
ethaderu 3:78f223d34f36 11772 #define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
ethaderu 3:78f223d34f36 11773 #define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
ethaderu 3:78f223d34f36 11774 #define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
ethaderu 3:78f223d34f36 11775 #define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
ethaderu 3:78f223d34f36 11776 #define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
ethaderu 3:78f223d34f36 11777 #define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
ethaderu 3:78f223d34f36 11778 #define SIM_SOPT4_FTM3CLKSEL_MASK 0x8000000u
ethaderu 3:78f223d34f36 11779 #define SIM_SOPT4_FTM3CLKSEL_SHIFT 27
ethaderu 3:78f223d34f36 11780 #define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
ethaderu 3:78f223d34f36 11781 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
ethaderu 3:78f223d34f36 11782 #define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
ethaderu 3:78f223d34f36 11783 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
ethaderu 3:78f223d34f36 11784 #define SIM_SOPT4_FTM3TRG0SRC_MASK 0x40000000u
ethaderu 3:78f223d34f36 11785 #define SIM_SOPT4_FTM3TRG0SRC_SHIFT 30
ethaderu 3:78f223d34f36 11786 #define SIM_SOPT4_FTM3TRG1SRC_MASK 0x80000000u
ethaderu 3:78f223d34f36 11787 #define SIM_SOPT4_FTM3TRG1SRC_SHIFT 31
ethaderu 3:78f223d34f36 11788 /* SOPT5 Bit Fields */
ethaderu 3:78f223d34f36 11789 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
ethaderu 3:78f223d34f36 11790 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
ethaderu 3:78f223d34f36 11791 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
ethaderu 3:78f223d34f36 11792 #define SIM_SOPT5_UART0RXSRC_MASK 0xCu
ethaderu 3:78f223d34f36 11793 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
ethaderu 3:78f223d34f36 11794 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
ethaderu 3:78f223d34f36 11795 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
ethaderu 3:78f223d34f36 11796 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
ethaderu 3:78f223d34f36 11797 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
ethaderu 3:78f223d34f36 11798 #define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
ethaderu 3:78f223d34f36 11799 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
ethaderu 3:78f223d34f36 11800 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
ethaderu 3:78f223d34f36 11801 /* SOPT7 Bit Fields */
ethaderu 3:78f223d34f36 11802 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
ethaderu 3:78f223d34f36 11803 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
ethaderu 3:78f223d34f36 11804 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
ethaderu 3:78f223d34f36 11805 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
ethaderu 3:78f223d34f36 11806 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
ethaderu 3:78f223d34f36 11807 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
ethaderu 3:78f223d34f36 11808 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
ethaderu 3:78f223d34f36 11809 #define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
ethaderu 3:78f223d34f36 11810 #define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
ethaderu 3:78f223d34f36 11811 #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
ethaderu 3:78f223d34f36 11812 #define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
ethaderu 3:78f223d34f36 11813 #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
ethaderu 3:78f223d34f36 11814 #define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
ethaderu 3:78f223d34f36 11815 #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
ethaderu 3:78f223d34f36 11816 /* SDID Bit Fields */
ethaderu 3:78f223d34f36 11817 #define SIM_SDID_PINID_MASK 0xFu
ethaderu 3:78f223d34f36 11818 #define SIM_SDID_PINID_SHIFT 0
ethaderu 3:78f223d34f36 11819 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
ethaderu 3:78f223d34f36 11820 #define SIM_SDID_FAMID_MASK 0x70u
ethaderu 3:78f223d34f36 11821 #define SIM_SDID_FAMID_SHIFT 4
ethaderu 3:78f223d34f36 11822 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
ethaderu 3:78f223d34f36 11823 #define SIM_SDID_DIEID_MASK 0xF80u
ethaderu 3:78f223d34f36 11824 #define SIM_SDID_DIEID_SHIFT 7
ethaderu 3:78f223d34f36 11825 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
ethaderu 3:78f223d34f36 11826 #define SIM_SDID_REVID_MASK 0xF000u
ethaderu 3:78f223d34f36 11827 #define SIM_SDID_REVID_SHIFT 12
ethaderu 3:78f223d34f36 11828 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
ethaderu 3:78f223d34f36 11829 #define SIM_SDID_SERIESID_MASK 0xF00000u
ethaderu 3:78f223d34f36 11830 #define SIM_SDID_SERIESID_SHIFT 20
ethaderu 3:78f223d34f36 11831 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
ethaderu 3:78f223d34f36 11832 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
ethaderu 3:78f223d34f36 11833 #define SIM_SDID_SUBFAMID_SHIFT 24
ethaderu 3:78f223d34f36 11834 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
ethaderu 3:78f223d34f36 11835 #define SIM_SDID_FAMILYID_MASK 0xF0000000u
ethaderu 3:78f223d34f36 11836 #define SIM_SDID_FAMILYID_SHIFT 28
ethaderu 3:78f223d34f36 11837 #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
ethaderu 3:78f223d34f36 11838 /* SCGC1 Bit Fields */
ethaderu 3:78f223d34f36 11839 #define SIM_SCGC1_I2C2_MASK 0x40u
ethaderu 3:78f223d34f36 11840 #define SIM_SCGC1_I2C2_SHIFT 6
ethaderu 3:78f223d34f36 11841 #define SIM_SCGC1_UART4_MASK 0x400u
ethaderu 3:78f223d34f36 11842 #define SIM_SCGC1_UART4_SHIFT 10
ethaderu 3:78f223d34f36 11843 #define SIM_SCGC1_UART5_MASK 0x800u
ethaderu 3:78f223d34f36 11844 #define SIM_SCGC1_UART5_SHIFT 11
ethaderu 3:78f223d34f36 11845 /* SCGC2 Bit Fields */
ethaderu 3:78f223d34f36 11846 #define SIM_SCGC2_ENET_MASK 0x1u
ethaderu 3:78f223d34f36 11847 #define SIM_SCGC2_ENET_SHIFT 0
ethaderu 3:78f223d34f36 11848 #define SIM_SCGC2_DAC0_MASK 0x1000u
ethaderu 3:78f223d34f36 11849 #define SIM_SCGC2_DAC0_SHIFT 12
ethaderu 3:78f223d34f36 11850 #define SIM_SCGC2_DAC1_MASK 0x2000u
ethaderu 3:78f223d34f36 11851 #define SIM_SCGC2_DAC1_SHIFT 13
ethaderu 3:78f223d34f36 11852 /* SCGC3 Bit Fields */
ethaderu 3:78f223d34f36 11853 #define SIM_SCGC3_RNGA_MASK 0x1u
ethaderu 3:78f223d34f36 11854 #define SIM_SCGC3_RNGA_SHIFT 0
ethaderu 3:78f223d34f36 11855 #define SIM_SCGC3_SPI2_MASK 0x1000u
ethaderu 3:78f223d34f36 11856 #define SIM_SCGC3_SPI2_SHIFT 12
ethaderu 3:78f223d34f36 11857 #define SIM_SCGC3_SDHC_MASK 0x20000u
ethaderu 3:78f223d34f36 11858 #define SIM_SCGC3_SDHC_SHIFT 17
ethaderu 3:78f223d34f36 11859 #define SIM_SCGC3_FTM2_MASK 0x1000000u
ethaderu 3:78f223d34f36 11860 #define SIM_SCGC3_FTM2_SHIFT 24
ethaderu 3:78f223d34f36 11861 #define SIM_SCGC3_FTM3_MASK 0x2000000u
ethaderu 3:78f223d34f36 11862 #define SIM_SCGC3_FTM3_SHIFT 25
ethaderu 3:78f223d34f36 11863 #define SIM_SCGC3_ADC1_MASK 0x8000000u
ethaderu 3:78f223d34f36 11864 #define SIM_SCGC3_ADC1_SHIFT 27
ethaderu 3:78f223d34f36 11865 /* SCGC4 Bit Fields */
ethaderu 3:78f223d34f36 11866 #define SIM_SCGC4_EWM_MASK 0x2u
ethaderu 3:78f223d34f36 11867 #define SIM_SCGC4_EWM_SHIFT 1
ethaderu 3:78f223d34f36 11868 #define SIM_SCGC4_CMT_MASK 0x4u
ethaderu 3:78f223d34f36 11869 #define SIM_SCGC4_CMT_SHIFT 2
ethaderu 3:78f223d34f36 11870 #define SIM_SCGC4_I2C0_MASK 0x40u
ethaderu 3:78f223d34f36 11871 #define SIM_SCGC4_I2C0_SHIFT 6
ethaderu 3:78f223d34f36 11872 #define SIM_SCGC4_I2C1_MASK 0x80u
ethaderu 3:78f223d34f36 11873 #define SIM_SCGC4_I2C1_SHIFT 7
ethaderu 3:78f223d34f36 11874 #define SIM_SCGC4_UART0_MASK 0x400u
ethaderu 3:78f223d34f36 11875 #define SIM_SCGC4_UART0_SHIFT 10
ethaderu 3:78f223d34f36 11876 #define SIM_SCGC4_UART1_MASK 0x800u
ethaderu 3:78f223d34f36 11877 #define SIM_SCGC4_UART1_SHIFT 11
ethaderu 3:78f223d34f36 11878 #define SIM_SCGC4_UART2_MASK 0x1000u
ethaderu 3:78f223d34f36 11879 #define SIM_SCGC4_UART2_SHIFT 12
ethaderu 3:78f223d34f36 11880 #define SIM_SCGC4_UART3_MASK 0x2000u
ethaderu 3:78f223d34f36 11881 #define SIM_SCGC4_UART3_SHIFT 13
ethaderu 3:78f223d34f36 11882 #define SIM_SCGC4_USBOTG_MASK 0x40000u
ethaderu 3:78f223d34f36 11883 #define SIM_SCGC4_USBOTG_SHIFT 18
ethaderu 3:78f223d34f36 11884 #define SIM_SCGC4_CMP_MASK 0x80000u
ethaderu 3:78f223d34f36 11885 #define SIM_SCGC4_CMP_SHIFT 19
ethaderu 3:78f223d34f36 11886 #define SIM_SCGC4_VREF_MASK 0x100000u
ethaderu 3:78f223d34f36 11887 #define SIM_SCGC4_VREF_SHIFT 20
ethaderu 3:78f223d34f36 11888 /* SCGC5 Bit Fields */
ethaderu 3:78f223d34f36 11889 #define SIM_SCGC5_LPTMR_MASK 0x1u
ethaderu 3:78f223d34f36 11890 #define SIM_SCGC5_LPTMR_SHIFT 0
ethaderu 3:78f223d34f36 11891 #define SIM_SCGC5_PORTA_MASK 0x200u
ethaderu 3:78f223d34f36 11892 #define SIM_SCGC5_PORTA_SHIFT 9
ethaderu 3:78f223d34f36 11893 #define SIM_SCGC5_PORTB_MASK 0x400u
ethaderu 3:78f223d34f36 11894 #define SIM_SCGC5_PORTB_SHIFT 10
ethaderu 3:78f223d34f36 11895 #define SIM_SCGC5_PORTC_MASK 0x800u
ethaderu 3:78f223d34f36 11896 #define SIM_SCGC5_PORTC_SHIFT 11
ethaderu 3:78f223d34f36 11897 #define SIM_SCGC5_PORTD_MASK 0x1000u
ethaderu 3:78f223d34f36 11898 #define SIM_SCGC5_PORTD_SHIFT 12
ethaderu 3:78f223d34f36 11899 #define SIM_SCGC5_PORTE_MASK 0x2000u
ethaderu 3:78f223d34f36 11900 #define SIM_SCGC5_PORTE_SHIFT 13
ethaderu 3:78f223d34f36 11901 /* SCGC6 Bit Fields */
ethaderu 3:78f223d34f36 11902 #define SIM_SCGC6_FTF_MASK 0x1u
ethaderu 3:78f223d34f36 11903 #define SIM_SCGC6_FTF_SHIFT 0
ethaderu 3:78f223d34f36 11904 #define SIM_SCGC6_DMAMUX_MASK 0x2u
ethaderu 3:78f223d34f36 11905 #define SIM_SCGC6_DMAMUX_SHIFT 1
ethaderu 3:78f223d34f36 11906 #define SIM_SCGC6_FLEXCAN0_MASK 0x10u
ethaderu 3:78f223d34f36 11907 #define SIM_SCGC6_FLEXCAN0_SHIFT 4
ethaderu 3:78f223d34f36 11908 #define SIM_SCGC6_RNGA_MASK 0x200u
ethaderu 3:78f223d34f36 11909 #define SIM_SCGC6_RNGA_SHIFT 9
ethaderu 3:78f223d34f36 11910 #define SIM_SCGC6_SPI0_MASK 0x1000u
ethaderu 3:78f223d34f36 11911 #define SIM_SCGC6_SPI0_SHIFT 12
ethaderu 3:78f223d34f36 11912 #define SIM_SCGC6_SPI1_MASK 0x2000u
ethaderu 3:78f223d34f36 11913 #define SIM_SCGC6_SPI1_SHIFT 13
ethaderu 3:78f223d34f36 11914 #define SIM_SCGC6_I2S_MASK 0x8000u
ethaderu 3:78f223d34f36 11915 #define SIM_SCGC6_I2S_SHIFT 15
ethaderu 3:78f223d34f36 11916 #define SIM_SCGC6_CRC_MASK 0x40000u
ethaderu 3:78f223d34f36 11917 #define SIM_SCGC6_CRC_SHIFT 18
ethaderu 3:78f223d34f36 11918 #define SIM_SCGC6_USBDCD_MASK 0x200000u
ethaderu 3:78f223d34f36 11919 #define SIM_SCGC6_USBDCD_SHIFT 21
ethaderu 3:78f223d34f36 11920 #define SIM_SCGC6_PDB_MASK 0x400000u
ethaderu 3:78f223d34f36 11921 #define SIM_SCGC6_PDB_SHIFT 22
ethaderu 3:78f223d34f36 11922 #define SIM_SCGC6_PIT_MASK 0x800000u
ethaderu 3:78f223d34f36 11923 #define SIM_SCGC6_PIT_SHIFT 23
ethaderu 3:78f223d34f36 11924 #define SIM_SCGC6_FTM0_MASK 0x1000000u
ethaderu 3:78f223d34f36 11925 #define SIM_SCGC6_FTM0_SHIFT 24
ethaderu 3:78f223d34f36 11926 #define SIM_SCGC6_FTM1_MASK 0x2000000u
ethaderu 3:78f223d34f36 11927 #define SIM_SCGC6_FTM1_SHIFT 25
ethaderu 3:78f223d34f36 11928 #define SIM_SCGC6_FTM2_MASK 0x4000000u
ethaderu 3:78f223d34f36 11929 #define SIM_SCGC6_FTM2_SHIFT 26
ethaderu 3:78f223d34f36 11930 #define SIM_SCGC6_ADC0_MASK 0x8000000u
ethaderu 3:78f223d34f36 11931 #define SIM_SCGC6_ADC0_SHIFT 27
ethaderu 3:78f223d34f36 11932 #define SIM_SCGC6_RTC_MASK 0x20000000u
ethaderu 3:78f223d34f36 11933 #define SIM_SCGC6_RTC_SHIFT 29
ethaderu 3:78f223d34f36 11934 #define SIM_SCGC6_DAC0_MASK 0x80000000u
ethaderu 3:78f223d34f36 11935 #define SIM_SCGC6_DAC0_SHIFT 31
ethaderu 3:78f223d34f36 11936 /* SCGC7 Bit Fields */
ethaderu 3:78f223d34f36 11937 #define SIM_SCGC7_FLEXBUS_MASK 0x1u
ethaderu 3:78f223d34f36 11938 #define SIM_SCGC7_FLEXBUS_SHIFT 0
ethaderu 3:78f223d34f36 11939 #define SIM_SCGC7_DMA_MASK 0x2u
ethaderu 3:78f223d34f36 11940 #define SIM_SCGC7_DMA_SHIFT 1
ethaderu 3:78f223d34f36 11941 #define SIM_SCGC7_MPU_MASK 0x4u
ethaderu 3:78f223d34f36 11942 #define SIM_SCGC7_MPU_SHIFT 2
ethaderu 3:78f223d34f36 11943 /* CLKDIV1 Bit Fields */
ethaderu 3:78f223d34f36 11944 #define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
ethaderu 3:78f223d34f36 11945 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
ethaderu 3:78f223d34f36 11946 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
ethaderu 3:78f223d34f36 11947 #define SIM_CLKDIV1_OUTDIV3_MASK 0xF00000u
ethaderu 3:78f223d34f36 11948 #define SIM_CLKDIV1_OUTDIV3_SHIFT 20
ethaderu 3:78f223d34f36 11949 #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
ethaderu 3:78f223d34f36 11950 #define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
ethaderu 3:78f223d34f36 11951 #define SIM_CLKDIV1_OUTDIV2_SHIFT 24
ethaderu 3:78f223d34f36 11952 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
ethaderu 3:78f223d34f36 11953 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
ethaderu 3:78f223d34f36 11954 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
ethaderu 3:78f223d34f36 11955 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
ethaderu 3:78f223d34f36 11956 /* CLKDIV2 Bit Fields */
ethaderu 3:78f223d34f36 11957 #define SIM_CLKDIV2_USBFRAC_MASK 0x1u
ethaderu 3:78f223d34f36 11958 #define SIM_CLKDIV2_USBFRAC_SHIFT 0
ethaderu 3:78f223d34f36 11959 #define SIM_CLKDIV2_USBDIV_MASK 0xEu
ethaderu 3:78f223d34f36 11960 #define SIM_CLKDIV2_USBDIV_SHIFT 1
ethaderu 3:78f223d34f36 11961 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
ethaderu 3:78f223d34f36 11962 /* FCFG1 Bit Fields */
ethaderu 3:78f223d34f36 11963 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
ethaderu 3:78f223d34f36 11964 #define SIM_FCFG1_FLASHDIS_SHIFT 0
ethaderu 3:78f223d34f36 11965 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
ethaderu 3:78f223d34f36 11966 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
ethaderu 3:78f223d34f36 11967 #define SIM_FCFG1_DEPART_MASK 0xF00u
ethaderu 3:78f223d34f36 11968 #define SIM_FCFG1_DEPART_SHIFT 8
ethaderu 3:78f223d34f36 11969 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
ethaderu 3:78f223d34f36 11970 #define SIM_FCFG1_EESIZE_MASK 0xF0000u
ethaderu 3:78f223d34f36 11971 #define SIM_FCFG1_EESIZE_SHIFT 16
ethaderu 3:78f223d34f36 11972 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
ethaderu 3:78f223d34f36 11973 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
ethaderu 3:78f223d34f36 11974 #define SIM_FCFG1_PFSIZE_SHIFT 24
ethaderu 3:78f223d34f36 11975 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
ethaderu 3:78f223d34f36 11976 #define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
ethaderu 3:78f223d34f36 11977 #define SIM_FCFG1_NVMSIZE_SHIFT 28
ethaderu 3:78f223d34f36 11978 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
ethaderu 3:78f223d34f36 11979 /* FCFG2 Bit Fields */
ethaderu 3:78f223d34f36 11980 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
ethaderu 3:78f223d34f36 11981 #define SIM_FCFG2_MAXADDR1_SHIFT 16
ethaderu 3:78f223d34f36 11982 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
ethaderu 3:78f223d34f36 11983 #define SIM_FCFG2_PFLSH_MASK 0x800000u
ethaderu 3:78f223d34f36 11984 #define SIM_FCFG2_PFLSH_SHIFT 23
ethaderu 3:78f223d34f36 11985 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
ethaderu 3:78f223d34f36 11986 #define SIM_FCFG2_MAXADDR0_SHIFT 24
ethaderu 3:78f223d34f36 11987 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
ethaderu 3:78f223d34f36 11988 /* UIDH Bit Fields */
ethaderu 3:78f223d34f36 11989 #define SIM_UIDH_UID_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 11990 #define SIM_UIDH_UID_SHIFT 0
ethaderu 3:78f223d34f36 11991 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
ethaderu 3:78f223d34f36 11992 /* UIDMH Bit Fields */
ethaderu 3:78f223d34f36 11993 #define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 11994 #define SIM_UIDMH_UID_SHIFT 0
ethaderu 3:78f223d34f36 11995 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
ethaderu 3:78f223d34f36 11996 /* UIDML Bit Fields */
ethaderu 3:78f223d34f36 11997 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 11998 #define SIM_UIDML_UID_SHIFT 0
ethaderu 3:78f223d34f36 11999 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
ethaderu 3:78f223d34f36 12000 /* UIDL Bit Fields */
ethaderu 3:78f223d34f36 12001 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 12002 #define SIM_UIDL_UID_SHIFT 0
ethaderu 3:78f223d34f36 12003 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
ethaderu 3:78f223d34f36 12004
ethaderu 3:78f223d34f36 12005 /*!
ethaderu 3:78f223d34f36 12006 * @}
ethaderu 3:78f223d34f36 12007 */ /* end of group SIM_Register_Masks */
ethaderu 3:78f223d34f36 12008
ethaderu 3:78f223d34f36 12009
ethaderu 3:78f223d34f36 12010 /* SIM - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 12011 /** Peripheral SIM base address */
ethaderu 3:78f223d34f36 12012 #define SIM_BASE (0x40047000u)
ethaderu 3:78f223d34f36 12013 /** Peripheral SIM base pointer */
ethaderu 3:78f223d34f36 12014 #define SIM ((SIM_Type *)SIM_BASE)
ethaderu 3:78f223d34f36 12015 #define SIM_BASE_PTR (SIM)
ethaderu 3:78f223d34f36 12016 /** Array initializer of SIM peripheral base addresses */
ethaderu 3:78f223d34f36 12017 #define SIM_BASE_ADDRS { SIM_BASE }
ethaderu 3:78f223d34f36 12018 /** Array initializer of SIM peripheral base pointers */
ethaderu 3:78f223d34f36 12019 #define SIM_BASE_PTRS { SIM }
ethaderu 3:78f223d34f36 12020
ethaderu 3:78f223d34f36 12021 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 12022 -- SIM - Register accessor macros
ethaderu 3:78f223d34f36 12023 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 12024
ethaderu 3:78f223d34f36 12025 /*!
ethaderu 3:78f223d34f36 12026 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
ethaderu 3:78f223d34f36 12027 * @{
ethaderu 3:78f223d34f36 12028 */
ethaderu 3:78f223d34f36 12029
ethaderu 3:78f223d34f36 12030
ethaderu 3:78f223d34f36 12031 /* SIM - Register instance definitions */
ethaderu 3:78f223d34f36 12032 /* SIM */
ethaderu 3:78f223d34f36 12033 #define SIM_SOPT1 SIM_SOPT1_REG(SIM)
ethaderu 3:78f223d34f36 12034 #define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
ethaderu 3:78f223d34f36 12035 #define SIM_SOPT2 SIM_SOPT2_REG(SIM)
ethaderu 3:78f223d34f36 12036 #define SIM_SOPT4 SIM_SOPT4_REG(SIM)
ethaderu 3:78f223d34f36 12037 #define SIM_SOPT5 SIM_SOPT5_REG(SIM)
ethaderu 3:78f223d34f36 12038 #define SIM_SOPT7 SIM_SOPT7_REG(SIM)
ethaderu 3:78f223d34f36 12039 #define SIM_SDID SIM_SDID_REG(SIM)
ethaderu 3:78f223d34f36 12040 #define SIM_SCGC1 SIM_SCGC1_REG(SIM)
ethaderu 3:78f223d34f36 12041 #define SIM_SCGC2 SIM_SCGC2_REG(SIM)
ethaderu 3:78f223d34f36 12042 #define SIM_SCGC3 SIM_SCGC3_REG(SIM)
ethaderu 3:78f223d34f36 12043 #define SIM_SCGC4 SIM_SCGC4_REG(SIM)
ethaderu 3:78f223d34f36 12044 #define SIM_SCGC5 SIM_SCGC5_REG(SIM)
ethaderu 3:78f223d34f36 12045 #define SIM_SCGC6 SIM_SCGC6_REG(SIM)
ethaderu 3:78f223d34f36 12046 #define SIM_SCGC7 SIM_SCGC7_REG(SIM)
ethaderu 3:78f223d34f36 12047 #define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
ethaderu 3:78f223d34f36 12048 #define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM)
ethaderu 3:78f223d34f36 12049 #define SIM_FCFG1 SIM_FCFG1_REG(SIM)
ethaderu 3:78f223d34f36 12050 #define SIM_FCFG2 SIM_FCFG2_REG(SIM)
ethaderu 3:78f223d34f36 12051 #define SIM_UIDH SIM_UIDH_REG(SIM)
ethaderu 3:78f223d34f36 12052 #define SIM_UIDMH SIM_UIDMH_REG(SIM)
ethaderu 3:78f223d34f36 12053 #define SIM_UIDML SIM_UIDML_REG(SIM)
ethaderu 3:78f223d34f36 12054 #define SIM_UIDL SIM_UIDL_REG(SIM)
ethaderu 3:78f223d34f36 12055
ethaderu 3:78f223d34f36 12056 /*!
ethaderu 3:78f223d34f36 12057 * @}
ethaderu 3:78f223d34f36 12058 */ /* end of group SIM_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 12059
ethaderu 3:78f223d34f36 12060
ethaderu 3:78f223d34f36 12061 /*!
ethaderu 3:78f223d34f36 12062 * @}
ethaderu 3:78f223d34f36 12063 */ /* end of group SIM_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 12064
ethaderu 3:78f223d34f36 12065
ethaderu 3:78f223d34f36 12066 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 12067 -- SMC Peripheral Access Layer
ethaderu 3:78f223d34f36 12068 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 12069
ethaderu 3:78f223d34f36 12070 /*!
ethaderu 3:78f223d34f36 12071 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
ethaderu 3:78f223d34f36 12072 * @{
ethaderu 3:78f223d34f36 12073 */
ethaderu 3:78f223d34f36 12074
ethaderu 3:78f223d34f36 12075 /** SMC - Register Layout Typedef */
ethaderu 3:78f223d34f36 12076 typedef struct {
ethaderu 3:78f223d34f36 12077 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
ethaderu 3:78f223d34f36 12078 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
ethaderu 3:78f223d34f36 12079 __IO uint8_t VLLSCTRL; /**< VLLS Control register, offset: 0x2 */
ethaderu 3:78f223d34f36 12080 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
ethaderu 3:78f223d34f36 12081 } SMC_Type, *SMC_MemMapPtr;
ethaderu 3:78f223d34f36 12082
ethaderu 3:78f223d34f36 12083 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 12084 -- SMC - Register accessor macros
ethaderu 3:78f223d34f36 12085 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 12086
ethaderu 3:78f223d34f36 12087 /*!
ethaderu 3:78f223d34f36 12088 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
ethaderu 3:78f223d34f36 12089 * @{
ethaderu 3:78f223d34f36 12090 */
ethaderu 3:78f223d34f36 12091
ethaderu 3:78f223d34f36 12092
ethaderu 3:78f223d34f36 12093 /* SMC - Register accessors */
ethaderu 3:78f223d34f36 12094 #define SMC_PMPROT_REG(base) ((base)->PMPROT)
ethaderu 3:78f223d34f36 12095 #define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
ethaderu 3:78f223d34f36 12096 #define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL)
ethaderu 3:78f223d34f36 12097 #define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
ethaderu 3:78f223d34f36 12098
ethaderu 3:78f223d34f36 12099 /*!
ethaderu 3:78f223d34f36 12100 * @}
ethaderu 3:78f223d34f36 12101 */ /* end of group SMC_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 12102
ethaderu 3:78f223d34f36 12103
ethaderu 3:78f223d34f36 12104 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 12105 -- SMC Register Masks
ethaderu 3:78f223d34f36 12106 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 12107
ethaderu 3:78f223d34f36 12108 /*!
ethaderu 3:78f223d34f36 12109 * @addtogroup SMC_Register_Masks SMC Register Masks
ethaderu 3:78f223d34f36 12110 * @{
ethaderu 3:78f223d34f36 12111 */
ethaderu 3:78f223d34f36 12112
ethaderu 3:78f223d34f36 12113 /* PMPROT Bit Fields */
ethaderu 3:78f223d34f36 12114 #define SMC_PMPROT_AVLLS_MASK 0x2u
ethaderu 3:78f223d34f36 12115 #define SMC_PMPROT_AVLLS_SHIFT 1
ethaderu 3:78f223d34f36 12116 #define SMC_PMPROT_ALLS_MASK 0x8u
ethaderu 3:78f223d34f36 12117 #define SMC_PMPROT_ALLS_SHIFT 3
ethaderu 3:78f223d34f36 12118 #define SMC_PMPROT_AVLP_MASK 0x20u
ethaderu 3:78f223d34f36 12119 #define SMC_PMPROT_AVLP_SHIFT 5
ethaderu 3:78f223d34f36 12120 /* PMCTRL Bit Fields */
ethaderu 3:78f223d34f36 12121 #define SMC_PMCTRL_STOPM_MASK 0x7u
ethaderu 3:78f223d34f36 12122 #define SMC_PMCTRL_STOPM_SHIFT 0
ethaderu 3:78f223d34f36 12123 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
ethaderu 3:78f223d34f36 12124 #define SMC_PMCTRL_STOPA_MASK 0x8u
ethaderu 3:78f223d34f36 12125 #define SMC_PMCTRL_STOPA_SHIFT 3
ethaderu 3:78f223d34f36 12126 #define SMC_PMCTRL_RUNM_MASK 0x60u
ethaderu 3:78f223d34f36 12127 #define SMC_PMCTRL_RUNM_SHIFT 5
ethaderu 3:78f223d34f36 12128 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
ethaderu 3:78f223d34f36 12129 #define SMC_PMCTRL_LPWUI_MASK 0x80u
ethaderu 3:78f223d34f36 12130 #define SMC_PMCTRL_LPWUI_SHIFT 7
ethaderu 3:78f223d34f36 12131 /* VLLSCTRL Bit Fields */
ethaderu 3:78f223d34f36 12132 #define SMC_VLLSCTRL_VLLSM_MASK 0x7u
ethaderu 3:78f223d34f36 12133 #define SMC_VLLSCTRL_VLLSM_SHIFT 0
ethaderu 3:78f223d34f36 12134 #define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
ethaderu 3:78f223d34f36 12135 #define SMC_VLLSCTRL_PORPO_MASK 0x20u
ethaderu 3:78f223d34f36 12136 #define SMC_VLLSCTRL_PORPO_SHIFT 5
ethaderu 3:78f223d34f36 12137 /* PMSTAT Bit Fields */
ethaderu 3:78f223d34f36 12138 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
ethaderu 3:78f223d34f36 12139 #define SMC_PMSTAT_PMSTAT_SHIFT 0
ethaderu 3:78f223d34f36 12140 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
ethaderu 3:78f223d34f36 12141
ethaderu 3:78f223d34f36 12142 /*!
ethaderu 3:78f223d34f36 12143 * @}
ethaderu 3:78f223d34f36 12144 */ /* end of group SMC_Register_Masks */
ethaderu 3:78f223d34f36 12145
ethaderu 3:78f223d34f36 12146
ethaderu 3:78f223d34f36 12147 /* SMC - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 12148 /** Peripheral SMC base address */
ethaderu 3:78f223d34f36 12149 #define SMC_BASE (0x4007E000u)
ethaderu 3:78f223d34f36 12150 /** Peripheral SMC base pointer */
ethaderu 3:78f223d34f36 12151 #define SMC ((SMC_Type *)SMC_BASE)
ethaderu 3:78f223d34f36 12152 #define SMC_BASE_PTR (SMC)
ethaderu 3:78f223d34f36 12153 /** Array initializer of SMC peripheral base addresses */
ethaderu 3:78f223d34f36 12154 #define SMC_BASE_ADDRS { SMC_BASE }
ethaderu 3:78f223d34f36 12155 /** Array initializer of SMC peripheral base pointers */
ethaderu 3:78f223d34f36 12156 #define SMC_BASE_PTRS { SMC }
ethaderu 3:78f223d34f36 12157
ethaderu 3:78f223d34f36 12158 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 12159 -- SMC - Register accessor macros
ethaderu 3:78f223d34f36 12160 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 12161
ethaderu 3:78f223d34f36 12162 /*!
ethaderu 3:78f223d34f36 12163 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
ethaderu 3:78f223d34f36 12164 * @{
ethaderu 3:78f223d34f36 12165 */
ethaderu 3:78f223d34f36 12166
ethaderu 3:78f223d34f36 12167
ethaderu 3:78f223d34f36 12168 /* SMC - Register instance definitions */
ethaderu 3:78f223d34f36 12169 /* SMC */
ethaderu 3:78f223d34f36 12170 #define SMC_PMPROT SMC_PMPROT_REG(SMC)
ethaderu 3:78f223d34f36 12171 #define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
ethaderu 3:78f223d34f36 12172 #define SMC_VLLSCTRL SMC_VLLSCTRL_REG(SMC)
ethaderu 3:78f223d34f36 12173 #define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
ethaderu 3:78f223d34f36 12174
ethaderu 3:78f223d34f36 12175 /*!
ethaderu 3:78f223d34f36 12176 * @}
ethaderu 3:78f223d34f36 12177 */ /* end of group SMC_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 12178
ethaderu 3:78f223d34f36 12179
ethaderu 3:78f223d34f36 12180 /*!
ethaderu 3:78f223d34f36 12181 * @}
ethaderu 3:78f223d34f36 12182 */ /* end of group SMC_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 12183
ethaderu 3:78f223d34f36 12184
ethaderu 3:78f223d34f36 12185 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 12186 -- SPI Peripheral Access Layer
ethaderu 3:78f223d34f36 12187 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 12188
ethaderu 3:78f223d34f36 12189 /*!
ethaderu 3:78f223d34f36 12190 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
ethaderu 3:78f223d34f36 12191 * @{
ethaderu 3:78f223d34f36 12192 */
ethaderu 3:78f223d34f36 12193
ethaderu 3:78f223d34f36 12194 /** SPI - Register Layout Typedef */
ethaderu 3:78f223d34f36 12195 typedef struct {
ethaderu 3:78f223d34f36 12196 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
ethaderu 3:78f223d34f36 12197 uint8_t RESERVED_0[4];
ethaderu 3:78f223d34f36 12198 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
ethaderu 3:78f223d34f36 12199 union { /* offset: 0xC */
ethaderu 3:78f223d34f36 12200 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
ethaderu 3:78f223d34f36 12201 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
ethaderu 3:78f223d34f36 12202 };
ethaderu 3:78f223d34f36 12203 uint8_t RESERVED_1[24];
ethaderu 3:78f223d34f36 12204 __IO uint32_t SR; /**< Status Register, offset: 0x2C */
ethaderu 3:78f223d34f36 12205 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
ethaderu 3:78f223d34f36 12206 union { /* offset: 0x34 */
ethaderu 3:78f223d34f36 12207 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
ethaderu 3:78f223d34f36 12208 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
ethaderu 3:78f223d34f36 12209 };
ethaderu 3:78f223d34f36 12210 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
ethaderu 3:78f223d34f36 12211 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
ethaderu 3:78f223d34f36 12212 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
ethaderu 3:78f223d34f36 12213 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
ethaderu 3:78f223d34f36 12214 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
ethaderu 3:78f223d34f36 12215 uint8_t RESERVED_2[48];
ethaderu 3:78f223d34f36 12216 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
ethaderu 3:78f223d34f36 12217 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
ethaderu 3:78f223d34f36 12218 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
ethaderu 3:78f223d34f36 12219 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
ethaderu 3:78f223d34f36 12220 } SPI_Type, *SPI_MemMapPtr;
ethaderu 3:78f223d34f36 12221
ethaderu 3:78f223d34f36 12222 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 12223 -- SPI - Register accessor macros
ethaderu 3:78f223d34f36 12224 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 12225
ethaderu 3:78f223d34f36 12226 /*!
ethaderu 3:78f223d34f36 12227 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
ethaderu 3:78f223d34f36 12228 * @{
ethaderu 3:78f223d34f36 12229 */
ethaderu 3:78f223d34f36 12230
ethaderu 3:78f223d34f36 12231
ethaderu 3:78f223d34f36 12232 /* SPI - Register accessors */
ethaderu 3:78f223d34f36 12233 #define SPI_MCR_REG(base) ((base)->MCR)
ethaderu 3:78f223d34f36 12234 #define SPI_TCR_REG(base) ((base)->TCR)
ethaderu 3:78f223d34f36 12235 #define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2])
ethaderu 3:78f223d34f36 12236 #define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2])
ethaderu 3:78f223d34f36 12237 #define SPI_SR_REG(base) ((base)->SR)
ethaderu 3:78f223d34f36 12238 #define SPI_RSER_REG(base) ((base)->RSER)
ethaderu 3:78f223d34f36 12239 #define SPI_PUSHR_REG(base) ((base)->PUSHR)
ethaderu 3:78f223d34f36 12240 #define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)
ethaderu 3:78f223d34f36 12241 #define SPI_POPR_REG(base) ((base)->POPR)
ethaderu 3:78f223d34f36 12242 #define SPI_TXFR0_REG(base) ((base)->TXFR0)
ethaderu 3:78f223d34f36 12243 #define SPI_TXFR1_REG(base) ((base)->TXFR1)
ethaderu 3:78f223d34f36 12244 #define SPI_TXFR2_REG(base) ((base)->TXFR2)
ethaderu 3:78f223d34f36 12245 #define SPI_TXFR3_REG(base) ((base)->TXFR3)
ethaderu 3:78f223d34f36 12246 #define SPI_RXFR0_REG(base) ((base)->RXFR0)
ethaderu 3:78f223d34f36 12247 #define SPI_RXFR1_REG(base) ((base)->RXFR1)
ethaderu 3:78f223d34f36 12248 #define SPI_RXFR2_REG(base) ((base)->RXFR2)
ethaderu 3:78f223d34f36 12249 #define SPI_RXFR3_REG(base) ((base)->RXFR3)
ethaderu 3:78f223d34f36 12250
ethaderu 3:78f223d34f36 12251 /*!
ethaderu 3:78f223d34f36 12252 * @}
ethaderu 3:78f223d34f36 12253 */ /* end of group SPI_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 12254
ethaderu 3:78f223d34f36 12255
ethaderu 3:78f223d34f36 12256 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 12257 -- SPI Register Masks
ethaderu 3:78f223d34f36 12258 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 12259
ethaderu 3:78f223d34f36 12260 /*!
ethaderu 3:78f223d34f36 12261 * @addtogroup SPI_Register_Masks SPI Register Masks
ethaderu 3:78f223d34f36 12262 * @{
ethaderu 3:78f223d34f36 12263 */
ethaderu 3:78f223d34f36 12264
ethaderu 3:78f223d34f36 12265 /* MCR Bit Fields */
ethaderu 3:78f223d34f36 12266 #define SPI_MCR_HALT_MASK 0x1u
ethaderu 3:78f223d34f36 12267 #define SPI_MCR_HALT_SHIFT 0
ethaderu 3:78f223d34f36 12268 #define SPI_MCR_SMPL_PT_MASK 0x300u
ethaderu 3:78f223d34f36 12269 #define SPI_MCR_SMPL_PT_SHIFT 8
ethaderu 3:78f223d34f36 12270 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
ethaderu 3:78f223d34f36 12271 #define SPI_MCR_CLR_RXF_MASK 0x400u
ethaderu 3:78f223d34f36 12272 #define SPI_MCR_CLR_RXF_SHIFT 10
ethaderu 3:78f223d34f36 12273 #define SPI_MCR_CLR_TXF_MASK 0x800u
ethaderu 3:78f223d34f36 12274 #define SPI_MCR_CLR_TXF_SHIFT 11
ethaderu 3:78f223d34f36 12275 #define SPI_MCR_DIS_RXF_MASK 0x1000u
ethaderu 3:78f223d34f36 12276 #define SPI_MCR_DIS_RXF_SHIFT 12
ethaderu 3:78f223d34f36 12277 #define SPI_MCR_DIS_TXF_MASK 0x2000u
ethaderu 3:78f223d34f36 12278 #define SPI_MCR_DIS_TXF_SHIFT 13
ethaderu 3:78f223d34f36 12279 #define SPI_MCR_MDIS_MASK 0x4000u
ethaderu 3:78f223d34f36 12280 #define SPI_MCR_MDIS_SHIFT 14
ethaderu 3:78f223d34f36 12281 #define SPI_MCR_DOZE_MASK 0x8000u
ethaderu 3:78f223d34f36 12282 #define SPI_MCR_DOZE_SHIFT 15
ethaderu 3:78f223d34f36 12283 #define SPI_MCR_PCSIS_MASK 0x3F0000u
ethaderu 3:78f223d34f36 12284 #define SPI_MCR_PCSIS_SHIFT 16
ethaderu 3:78f223d34f36 12285 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
ethaderu 3:78f223d34f36 12286 #define SPI_MCR_ROOE_MASK 0x1000000u
ethaderu 3:78f223d34f36 12287 #define SPI_MCR_ROOE_SHIFT 24
ethaderu 3:78f223d34f36 12288 #define SPI_MCR_PCSSE_MASK 0x2000000u
ethaderu 3:78f223d34f36 12289 #define SPI_MCR_PCSSE_SHIFT 25
ethaderu 3:78f223d34f36 12290 #define SPI_MCR_MTFE_MASK 0x4000000u
ethaderu 3:78f223d34f36 12291 #define SPI_MCR_MTFE_SHIFT 26
ethaderu 3:78f223d34f36 12292 #define SPI_MCR_FRZ_MASK 0x8000000u
ethaderu 3:78f223d34f36 12293 #define SPI_MCR_FRZ_SHIFT 27
ethaderu 3:78f223d34f36 12294 #define SPI_MCR_DCONF_MASK 0x30000000u
ethaderu 3:78f223d34f36 12295 #define SPI_MCR_DCONF_SHIFT 28
ethaderu 3:78f223d34f36 12296 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
ethaderu 3:78f223d34f36 12297 #define SPI_MCR_CONT_SCKE_MASK 0x40000000u
ethaderu 3:78f223d34f36 12298 #define SPI_MCR_CONT_SCKE_SHIFT 30
ethaderu 3:78f223d34f36 12299 #define SPI_MCR_MSTR_MASK 0x80000000u
ethaderu 3:78f223d34f36 12300 #define SPI_MCR_MSTR_SHIFT 31
ethaderu 3:78f223d34f36 12301 /* TCR Bit Fields */
ethaderu 3:78f223d34f36 12302 #define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
ethaderu 3:78f223d34f36 12303 #define SPI_TCR_SPI_TCNT_SHIFT 16
ethaderu 3:78f223d34f36 12304 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
ethaderu 3:78f223d34f36 12305 /* CTAR Bit Fields */
ethaderu 3:78f223d34f36 12306 #define SPI_CTAR_BR_MASK 0xFu
ethaderu 3:78f223d34f36 12307 #define SPI_CTAR_BR_SHIFT 0
ethaderu 3:78f223d34f36 12308 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
ethaderu 3:78f223d34f36 12309 #define SPI_CTAR_DT_MASK 0xF0u
ethaderu 3:78f223d34f36 12310 #define SPI_CTAR_DT_SHIFT 4
ethaderu 3:78f223d34f36 12311 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
ethaderu 3:78f223d34f36 12312 #define SPI_CTAR_ASC_MASK 0xF00u
ethaderu 3:78f223d34f36 12313 #define SPI_CTAR_ASC_SHIFT 8
ethaderu 3:78f223d34f36 12314 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
ethaderu 3:78f223d34f36 12315 #define SPI_CTAR_CSSCK_MASK 0xF000u
ethaderu 3:78f223d34f36 12316 #define SPI_CTAR_CSSCK_SHIFT 12
ethaderu 3:78f223d34f36 12317 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
ethaderu 3:78f223d34f36 12318 #define SPI_CTAR_PBR_MASK 0x30000u
ethaderu 3:78f223d34f36 12319 #define SPI_CTAR_PBR_SHIFT 16
ethaderu 3:78f223d34f36 12320 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
ethaderu 3:78f223d34f36 12321 #define SPI_CTAR_PDT_MASK 0xC0000u
ethaderu 3:78f223d34f36 12322 #define SPI_CTAR_PDT_SHIFT 18
ethaderu 3:78f223d34f36 12323 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
ethaderu 3:78f223d34f36 12324 #define SPI_CTAR_PASC_MASK 0x300000u
ethaderu 3:78f223d34f36 12325 #define SPI_CTAR_PASC_SHIFT 20
ethaderu 3:78f223d34f36 12326 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
ethaderu 3:78f223d34f36 12327 #define SPI_CTAR_PCSSCK_MASK 0xC00000u
ethaderu 3:78f223d34f36 12328 #define SPI_CTAR_PCSSCK_SHIFT 22
ethaderu 3:78f223d34f36 12329 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
ethaderu 3:78f223d34f36 12330 #define SPI_CTAR_LSBFE_MASK 0x1000000u
ethaderu 3:78f223d34f36 12331 #define SPI_CTAR_LSBFE_SHIFT 24
ethaderu 3:78f223d34f36 12332 #define SPI_CTAR_CPHA_MASK 0x2000000u
ethaderu 3:78f223d34f36 12333 #define SPI_CTAR_CPHA_SHIFT 25
ethaderu 3:78f223d34f36 12334 #define SPI_CTAR_CPOL_MASK 0x4000000u
ethaderu 3:78f223d34f36 12335 #define SPI_CTAR_CPOL_SHIFT 26
ethaderu 3:78f223d34f36 12336 #define SPI_CTAR_FMSZ_MASK 0x78000000u
ethaderu 3:78f223d34f36 12337 #define SPI_CTAR_FMSZ_SHIFT 27
ethaderu 3:78f223d34f36 12338 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
ethaderu 3:78f223d34f36 12339 #define SPI_CTAR_DBR_MASK 0x80000000u
ethaderu 3:78f223d34f36 12340 #define SPI_CTAR_DBR_SHIFT 31
ethaderu 3:78f223d34f36 12341 /* CTAR_SLAVE Bit Fields */
ethaderu 3:78f223d34f36 12342 #define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
ethaderu 3:78f223d34f36 12343 #define SPI_CTAR_SLAVE_CPHA_SHIFT 25
ethaderu 3:78f223d34f36 12344 #define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
ethaderu 3:78f223d34f36 12345 #define SPI_CTAR_SLAVE_CPOL_SHIFT 26
ethaderu 3:78f223d34f36 12346 #define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
ethaderu 3:78f223d34f36 12347 #define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
ethaderu 3:78f223d34f36 12348 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
ethaderu 3:78f223d34f36 12349 /* SR Bit Fields */
ethaderu 3:78f223d34f36 12350 #define SPI_SR_POPNXTPTR_MASK 0xFu
ethaderu 3:78f223d34f36 12351 #define SPI_SR_POPNXTPTR_SHIFT 0
ethaderu 3:78f223d34f36 12352 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
ethaderu 3:78f223d34f36 12353 #define SPI_SR_RXCTR_MASK 0xF0u
ethaderu 3:78f223d34f36 12354 #define SPI_SR_RXCTR_SHIFT 4
ethaderu 3:78f223d34f36 12355 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
ethaderu 3:78f223d34f36 12356 #define SPI_SR_TXNXTPTR_MASK 0xF00u
ethaderu 3:78f223d34f36 12357 #define SPI_SR_TXNXTPTR_SHIFT 8
ethaderu 3:78f223d34f36 12358 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
ethaderu 3:78f223d34f36 12359 #define SPI_SR_TXCTR_MASK 0xF000u
ethaderu 3:78f223d34f36 12360 #define SPI_SR_TXCTR_SHIFT 12
ethaderu 3:78f223d34f36 12361 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
ethaderu 3:78f223d34f36 12362 #define SPI_SR_RFDF_MASK 0x20000u
ethaderu 3:78f223d34f36 12363 #define SPI_SR_RFDF_SHIFT 17
ethaderu 3:78f223d34f36 12364 #define SPI_SR_RFOF_MASK 0x80000u
ethaderu 3:78f223d34f36 12365 #define SPI_SR_RFOF_SHIFT 19
ethaderu 3:78f223d34f36 12366 #define SPI_SR_TFFF_MASK 0x2000000u
ethaderu 3:78f223d34f36 12367 #define SPI_SR_TFFF_SHIFT 25
ethaderu 3:78f223d34f36 12368 #define SPI_SR_TFUF_MASK 0x8000000u
ethaderu 3:78f223d34f36 12369 #define SPI_SR_TFUF_SHIFT 27
ethaderu 3:78f223d34f36 12370 #define SPI_SR_EOQF_MASK 0x10000000u
ethaderu 3:78f223d34f36 12371 #define SPI_SR_EOQF_SHIFT 28
ethaderu 3:78f223d34f36 12372 #define SPI_SR_TXRXS_MASK 0x40000000u
ethaderu 3:78f223d34f36 12373 #define SPI_SR_TXRXS_SHIFT 30
ethaderu 3:78f223d34f36 12374 #define SPI_SR_TCF_MASK 0x80000000u
ethaderu 3:78f223d34f36 12375 #define SPI_SR_TCF_SHIFT 31
ethaderu 3:78f223d34f36 12376 /* RSER Bit Fields */
ethaderu 3:78f223d34f36 12377 #define SPI_RSER_RFDF_DIRS_MASK 0x10000u
ethaderu 3:78f223d34f36 12378 #define SPI_RSER_RFDF_DIRS_SHIFT 16
ethaderu 3:78f223d34f36 12379 #define SPI_RSER_RFDF_RE_MASK 0x20000u
ethaderu 3:78f223d34f36 12380 #define SPI_RSER_RFDF_RE_SHIFT 17
ethaderu 3:78f223d34f36 12381 #define SPI_RSER_RFOF_RE_MASK 0x80000u
ethaderu 3:78f223d34f36 12382 #define SPI_RSER_RFOF_RE_SHIFT 19
ethaderu 3:78f223d34f36 12383 #define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
ethaderu 3:78f223d34f36 12384 #define SPI_RSER_TFFF_DIRS_SHIFT 24
ethaderu 3:78f223d34f36 12385 #define SPI_RSER_TFFF_RE_MASK 0x2000000u
ethaderu 3:78f223d34f36 12386 #define SPI_RSER_TFFF_RE_SHIFT 25
ethaderu 3:78f223d34f36 12387 #define SPI_RSER_TFUF_RE_MASK 0x8000000u
ethaderu 3:78f223d34f36 12388 #define SPI_RSER_TFUF_RE_SHIFT 27
ethaderu 3:78f223d34f36 12389 #define SPI_RSER_EOQF_RE_MASK 0x10000000u
ethaderu 3:78f223d34f36 12390 #define SPI_RSER_EOQF_RE_SHIFT 28
ethaderu 3:78f223d34f36 12391 #define SPI_RSER_TCF_RE_MASK 0x80000000u
ethaderu 3:78f223d34f36 12392 #define SPI_RSER_TCF_RE_SHIFT 31
ethaderu 3:78f223d34f36 12393 /* PUSHR Bit Fields */
ethaderu 3:78f223d34f36 12394 #define SPI_PUSHR_TXDATA_MASK 0xFFFFu
ethaderu 3:78f223d34f36 12395 #define SPI_PUSHR_TXDATA_SHIFT 0
ethaderu 3:78f223d34f36 12396 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
ethaderu 3:78f223d34f36 12397 #define SPI_PUSHR_PCS_MASK 0x3F0000u
ethaderu 3:78f223d34f36 12398 #define SPI_PUSHR_PCS_SHIFT 16
ethaderu 3:78f223d34f36 12399 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
ethaderu 3:78f223d34f36 12400 #define SPI_PUSHR_CTCNT_MASK 0x4000000u
ethaderu 3:78f223d34f36 12401 #define SPI_PUSHR_CTCNT_SHIFT 26
ethaderu 3:78f223d34f36 12402 #define SPI_PUSHR_EOQ_MASK 0x8000000u
ethaderu 3:78f223d34f36 12403 #define SPI_PUSHR_EOQ_SHIFT 27
ethaderu 3:78f223d34f36 12404 #define SPI_PUSHR_CTAS_MASK 0x70000000u
ethaderu 3:78f223d34f36 12405 #define SPI_PUSHR_CTAS_SHIFT 28
ethaderu 3:78f223d34f36 12406 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
ethaderu 3:78f223d34f36 12407 #define SPI_PUSHR_CONT_MASK 0x80000000u
ethaderu 3:78f223d34f36 12408 #define SPI_PUSHR_CONT_SHIFT 31
ethaderu 3:78f223d34f36 12409 /* PUSHR_SLAVE Bit Fields */
ethaderu 3:78f223d34f36 12410 #define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 12411 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
ethaderu 3:78f223d34f36 12412 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
ethaderu 3:78f223d34f36 12413 /* POPR Bit Fields */
ethaderu 3:78f223d34f36 12414 #define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 12415 #define SPI_POPR_RXDATA_SHIFT 0
ethaderu 3:78f223d34f36 12416 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
ethaderu 3:78f223d34f36 12417 /* TXFR0 Bit Fields */
ethaderu 3:78f223d34f36 12418 #define SPI_TXFR0_TXDATA_MASK 0xFFFFu
ethaderu 3:78f223d34f36 12419 #define SPI_TXFR0_TXDATA_SHIFT 0
ethaderu 3:78f223d34f36 12420 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
ethaderu 3:78f223d34f36 12421 #define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
ethaderu 3:78f223d34f36 12422 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
ethaderu 3:78f223d34f36 12423 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
ethaderu 3:78f223d34f36 12424 /* TXFR1 Bit Fields */
ethaderu 3:78f223d34f36 12425 #define SPI_TXFR1_TXDATA_MASK 0xFFFFu
ethaderu 3:78f223d34f36 12426 #define SPI_TXFR1_TXDATA_SHIFT 0
ethaderu 3:78f223d34f36 12427 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
ethaderu 3:78f223d34f36 12428 #define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
ethaderu 3:78f223d34f36 12429 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
ethaderu 3:78f223d34f36 12430 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
ethaderu 3:78f223d34f36 12431 /* TXFR2 Bit Fields */
ethaderu 3:78f223d34f36 12432 #define SPI_TXFR2_TXDATA_MASK 0xFFFFu
ethaderu 3:78f223d34f36 12433 #define SPI_TXFR2_TXDATA_SHIFT 0
ethaderu 3:78f223d34f36 12434 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
ethaderu 3:78f223d34f36 12435 #define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
ethaderu 3:78f223d34f36 12436 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
ethaderu 3:78f223d34f36 12437 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
ethaderu 3:78f223d34f36 12438 /* TXFR3 Bit Fields */
ethaderu 3:78f223d34f36 12439 #define SPI_TXFR3_TXDATA_MASK 0xFFFFu
ethaderu 3:78f223d34f36 12440 #define SPI_TXFR3_TXDATA_SHIFT 0
ethaderu 3:78f223d34f36 12441 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
ethaderu 3:78f223d34f36 12442 #define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
ethaderu 3:78f223d34f36 12443 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
ethaderu 3:78f223d34f36 12444 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
ethaderu 3:78f223d34f36 12445 /* RXFR0 Bit Fields */
ethaderu 3:78f223d34f36 12446 #define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 12447 #define SPI_RXFR0_RXDATA_SHIFT 0
ethaderu 3:78f223d34f36 12448 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
ethaderu 3:78f223d34f36 12449 /* RXFR1 Bit Fields */
ethaderu 3:78f223d34f36 12450 #define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 12451 #define SPI_RXFR1_RXDATA_SHIFT 0
ethaderu 3:78f223d34f36 12452 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
ethaderu 3:78f223d34f36 12453 /* RXFR2 Bit Fields */
ethaderu 3:78f223d34f36 12454 #define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 12455 #define SPI_RXFR2_RXDATA_SHIFT 0
ethaderu 3:78f223d34f36 12456 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
ethaderu 3:78f223d34f36 12457 /* RXFR3 Bit Fields */
ethaderu 3:78f223d34f36 12458 #define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
ethaderu 3:78f223d34f36 12459 #define SPI_RXFR3_RXDATA_SHIFT 0
ethaderu 3:78f223d34f36 12460 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
ethaderu 3:78f223d34f36 12461
ethaderu 3:78f223d34f36 12462 /*!
ethaderu 3:78f223d34f36 12463 * @}
ethaderu 3:78f223d34f36 12464 */ /* end of group SPI_Register_Masks */
ethaderu 3:78f223d34f36 12465
ethaderu 3:78f223d34f36 12466
ethaderu 3:78f223d34f36 12467 /* SPI - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 12468 /** Peripheral SPI0 base address */
ethaderu 3:78f223d34f36 12469 #define SPI0_BASE (0x4002C000u)
ethaderu 3:78f223d34f36 12470 /** Peripheral SPI0 base pointer */
ethaderu 3:78f223d34f36 12471 #define SPI0 ((SPI_Type *)SPI0_BASE)
ethaderu 3:78f223d34f36 12472 #define SPI0_BASE_PTR (SPI0)
ethaderu 3:78f223d34f36 12473 /** Peripheral SPI1 base address */
ethaderu 3:78f223d34f36 12474 #define SPI1_BASE (0x4002D000u)
ethaderu 3:78f223d34f36 12475 /** Peripheral SPI1 base pointer */
ethaderu 3:78f223d34f36 12476 #define SPI1 ((SPI_Type *)SPI1_BASE)
ethaderu 3:78f223d34f36 12477 #define SPI1_BASE_PTR (SPI1)
ethaderu 3:78f223d34f36 12478 /** Peripheral SPI2 base address */
ethaderu 3:78f223d34f36 12479 #define SPI2_BASE (0x400AC000u)
ethaderu 3:78f223d34f36 12480 /** Peripheral SPI2 base pointer */
ethaderu 3:78f223d34f36 12481 #define SPI2 ((SPI_Type *)SPI2_BASE)
ethaderu 3:78f223d34f36 12482 #define SPI2_BASE_PTR (SPI2)
ethaderu 3:78f223d34f36 12483 /** Array initializer of SPI peripheral base addresses */
ethaderu 3:78f223d34f36 12484 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE }
ethaderu 3:78f223d34f36 12485 /** Array initializer of SPI peripheral base pointers */
ethaderu 3:78f223d34f36 12486 #define SPI_BASE_PTRS { SPI0, SPI1, SPI2 }
ethaderu 3:78f223d34f36 12487 /** Interrupt vectors for the SPI peripheral type */
ethaderu 3:78f223d34f36 12488 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
ethaderu 3:78f223d34f36 12489
ethaderu 3:78f223d34f36 12490 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 12491 -- SPI - Register accessor macros
ethaderu 3:78f223d34f36 12492 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 12493
ethaderu 3:78f223d34f36 12494 /*!
ethaderu 3:78f223d34f36 12495 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
ethaderu 3:78f223d34f36 12496 * @{
ethaderu 3:78f223d34f36 12497 */
ethaderu 3:78f223d34f36 12498
ethaderu 3:78f223d34f36 12499
ethaderu 3:78f223d34f36 12500 /* SPI - Register instance definitions */
ethaderu 3:78f223d34f36 12501 /* SPI0 */
ethaderu 3:78f223d34f36 12502 #define SPI0_MCR SPI_MCR_REG(SPI0)
ethaderu 3:78f223d34f36 12503 #define SPI0_TCR SPI_TCR_REG(SPI0)
ethaderu 3:78f223d34f36 12504 #define SPI0_CTAR0 SPI_CTAR_REG(SPI0,0)
ethaderu 3:78f223d34f36 12505 #define SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0,0)
ethaderu 3:78f223d34f36 12506 #define SPI0_CTAR1 SPI_CTAR_REG(SPI0,1)
ethaderu 3:78f223d34f36 12507 #define SPI0_SR SPI_SR_REG(SPI0)
ethaderu 3:78f223d34f36 12508 #define SPI0_RSER SPI_RSER_REG(SPI0)
ethaderu 3:78f223d34f36 12509 #define SPI0_PUSHR SPI_PUSHR_REG(SPI0)
ethaderu 3:78f223d34f36 12510 #define SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0)
ethaderu 3:78f223d34f36 12511 #define SPI0_POPR SPI_POPR_REG(SPI0)
ethaderu 3:78f223d34f36 12512 #define SPI0_TXFR0 SPI_TXFR0_REG(SPI0)
ethaderu 3:78f223d34f36 12513 #define SPI0_TXFR1 SPI_TXFR1_REG(SPI0)
ethaderu 3:78f223d34f36 12514 #define SPI0_TXFR2 SPI_TXFR2_REG(SPI0)
ethaderu 3:78f223d34f36 12515 #define SPI0_TXFR3 SPI_TXFR3_REG(SPI0)
ethaderu 3:78f223d34f36 12516 #define SPI0_RXFR0 SPI_RXFR0_REG(SPI0)
ethaderu 3:78f223d34f36 12517 #define SPI0_RXFR1 SPI_RXFR1_REG(SPI0)
ethaderu 3:78f223d34f36 12518 #define SPI0_RXFR2 SPI_RXFR2_REG(SPI0)
ethaderu 3:78f223d34f36 12519 #define SPI0_RXFR3 SPI_RXFR3_REG(SPI0)
ethaderu 3:78f223d34f36 12520 /* SPI1 */
ethaderu 3:78f223d34f36 12521 #define SPI1_MCR SPI_MCR_REG(SPI1)
ethaderu 3:78f223d34f36 12522 #define SPI1_TCR SPI_TCR_REG(SPI1)
ethaderu 3:78f223d34f36 12523 #define SPI1_CTAR0 SPI_CTAR_REG(SPI1,0)
ethaderu 3:78f223d34f36 12524 #define SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1,0)
ethaderu 3:78f223d34f36 12525 #define SPI1_CTAR1 SPI_CTAR_REG(SPI1,1)
ethaderu 3:78f223d34f36 12526 #define SPI1_SR SPI_SR_REG(SPI1)
ethaderu 3:78f223d34f36 12527 #define SPI1_RSER SPI_RSER_REG(SPI1)
ethaderu 3:78f223d34f36 12528 #define SPI1_PUSHR SPI_PUSHR_REG(SPI1)
ethaderu 3:78f223d34f36 12529 #define SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1)
ethaderu 3:78f223d34f36 12530 #define SPI1_POPR SPI_POPR_REG(SPI1)
ethaderu 3:78f223d34f36 12531 #define SPI1_TXFR0 SPI_TXFR0_REG(SPI1)
ethaderu 3:78f223d34f36 12532 #define SPI1_TXFR1 SPI_TXFR1_REG(SPI1)
ethaderu 3:78f223d34f36 12533 #define SPI1_TXFR2 SPI_TXFR2_REG(SPI1)
ethaderu 3:78f223d34f36 12534 #define SPI1_TXFR3 SPI_TXFR3_REG(SPI1)
ethaderu 3:78f223d34f36 12535 #define SPI1_RXFR0 SPI_RXFR0_REG(SPI1)
ethaderu 3:78f223d34f36 12536 #define SPI1_RXFR1 SPI_RXFR1_REG(SPI1)
ethaderu 3:78f223d34f36 12537 #define SPI1_RXFR2 SPI_RXFR2_REG(SPI1)
ethaderu 3:78f223d34f36 12538 #define SPI1_RXFR3 SPI_RXFR3_REG(SPI1)
ethaderu 3:78f223d34f36 12539 /* SPI2 */
ethaderu 3:78f223d34f36 12540 #define SPI2_MCR SPI_MCR_REG(SPI2)
ethaderu 3:78f223d34f36 12541 #define SPI2_TCR SPI_TCR_REG(SPI2)
ethaderu 3:78f223d34f36 12542 #define SPI2_CTAR0 SPI_CTAR_REG(SPI2,0)
ethaderu 3:78f223d34f36 12543 #define SPI2_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI2,0)
ethaderu 3:78f223d34f36 12544 #define SPI2_CTAR1 SPI_CTAR_REG(SPI2,1)
ethaderu 3:78f223d34f36 12545 #define SPI2_SR SPI_SR_REG(SPI2)
ethaderu 3:78f223d34f36 12546 #define SPI2_RSER SPI_RSER_REG(SPI2)
ethaderu 3:78f223d34f36 12547 #define SPI2_PUSHR SPI_PUSHR_REG(SPI2)
ethaderu 3:78f223d34f36 12548 #define SPI2_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI2)
ethaderu 3:78f223d34f36 12549 #define SPI2_POPR SPI_POPR_REG(SPI2)
ethaderu 3:78f223d34f36 12550 #define SPI2_TXFR0 SPI_TXFR0_REG(SPI2)
ethaderu 3:78f223d34f36 12551 #define SPI2_TXFR1 SPI_TXFR1_REG(SPI2)
ethaderu 3:78f223d34f36 12552 #define SPI2_TXFR2 SPI_TXFR2_REG(SPI2)
ethaderu 3:78f223d34f36 12553 #define SPI2_TXFR3 SPI_TXFR3_REG(SPI2)
ethaderu 3:78f223d34f36 12554 #define SPI2_RXFR0 SPI_RXFR0_REG(SPI2)
ethaderu 3:78f223d34f36 12555 #define SPI2_RXFR1 SPI_RXFR1_REG(SPI2)
ethaderu 3:78f223d34f36 12556 #define SPI2_RXFR2 SPI_RXFR2_REG(SPI2)
ethaderu 3:78f223d34f36 12557 #define SPI2_RXFR3 SPI_RXFR3_REG(SPI2)
ethaderu 3:78f223d34f36 12558
ethaderu 3:78f223d34f36 12559 /* SPI - Register array accessors */
ethaderu 3:78f223d34f36 12560 #define SPI0_CTAR(index2) SPI_CTAR_REG(SPI0,index2)
ethaderu 3:78f223d34f36 12561 #define SPI1_CTAR(index2) SPI_CTAR_REG(SPI1,index2)
ethaderu 3:78f223d34f36 12562 #define SPI2_CTAR(index2) SPI_CTAR_REG(SPI2,index2)
ethaderu 3:78f223d34f36 12563 #define SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0,index2)
ethaderu 3:78f223d34f36 12564 #define SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1,index2)
ethaderu 3:78f223d34f36 12565 #define SPI2_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI2,index2)
ethaderu 3:78f223d34f36 12566
ethaderu 3:78f223d34f36 12567 /*!
ethaderu 3:78f223d34f36 12568 * @}
ethaderu 3:78f223d34f36 12569 */ /* end of group SPI_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 12570
ethaderu 3:78f223d34f36 12571
ethaderu 3:78f223d34f36 12572 /*!
ethaderu 3:78f223d34f36 12573 * @}
ethaderu 3:78f223d34f36 12574 */ /* end of group SPI_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 12575
ethaderu 3:78f223d34f36 12576
ethaderu 3:78f223d34f36 12577 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 12578 -- UART Peripheral Access Layer
ethaderu 3:78f223d34f36 12579 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 12580
ethaderu 3:78f223d34f36 12581 /*!
ethaderu 3:78f223d34f36 12582 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
ethaderu 3:78f223d34f36 12583 * @{
ethaderu 3:78f223d34f36 12584 */
ethaderu 3:78f223d34f36 12585
ethaderu 3:78f223d34f36 12586 /** UART - Register Layout Typedef */
ethaderu 3:78f223d34f36 12587 typedef struct {
ethaderu 3:78f223d34f36 12588 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
ethaderu 3:78f223d34f36 12589 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
ethaderu 3:78f223d34f36 12590 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
ethaderu 3:78f223d34f36 12591 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
ethaderu 3:78f223d34f36 12592 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
ethaderu 3:78f223d34f36 12593 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
ethaderu 3:78f223d34f36 12594 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
ethaderu 3:78f223d34f36 12595 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
ethaderu 3:78f223d34f36 12596 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
ethaderu 3:78f223d34f36 12597 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
ethaderu 3:78f223d34f36 12598 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
ethaderu 3:78f223d34f36 12599 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
ethaderu 3:78f223d34f36 12600 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
ethaderu 3:78f223d34f36 12601 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
ethaderu 3:78f223d34f36 12602 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
ethaderu 3:78f223d34f36 12603 uint8_t RESERVED_0[1];
ethaderu 3:78f223d34f36 12604 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
ethaderu 3:78f223d34f36 12605 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
ethaderu 3:78f223d34f36 12606 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
ethaderu 3:78f223d34f36 12607 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
ethaderu 3:78f223d34f36 12608 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
ethaderu 3:78f223d34f36 12609 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
ethaderu 3:78f223d34f36 12610 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
ethaderu 3:78f223d34f36 12611 uint8_t RESERVED_1[1];
ethaderu 3:78f223d34f36 12612 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
ethaderu 3:78f223d34f36 12613 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
ethaderu 3:78f223d34f36 12614 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
ethaderu 3:78f223d34f36 12615 union { /* offset: 0x1B */
ethaderu 3:78f223d34f36 12616 __IO uint8_t WP7816T0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
ethaderu 3:78f223d34f36 12617 __IO uint8_t WP7816T1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
ethaderu 3:78f223d34f36 12618 };
ethaderu 3:78f223d34f36 12619 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
ethaderu 3:78f223d34f36 12620 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
ethaderu 3:78f223d34f36 12621 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
ethaderu 3:78f223d34f36 12622 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
ethaderu 3:78f223d34f36 12623 } UART_Type, *UART_MemMapPtr;
ethaderu 3:78f223d34f36 12624
ethaderu 3:78f223d34f36 12625 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 12626 -- UART - Register accessor macros
ethaderu 3:78f223d34f36 12627 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 12628
ethaderu 3:78f223d34f36 12629 /*!
ethaderu 3:78f223d34f36 12630 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
ethaderu 3:78f223d34f36 12631 * @{
ethaderu 3:78f223d34f36 12632 */
ethaderu 3:78f223d34f36 12633
ethaderu 3:78f223d34f36 12634
ethaderu 3:78f223d34f36 12635 /* UART - Register accessors */
ethaderu 3:78f223d34f36 12636 #define UART_BDH_REG(base) ((base)->BDH)
ethaderu 3:78f223d34f36 12637 #define UART_BDL_REG(base) ((base)->BDL)
ethaderu 3:78f223d34f36 12638 #define UART_C1_REG(base) ((base)->C1)
ethaderu 3:78f223d34f36 12639 #define UART_C2_REG(base) ((base)->C2)
ethaderu 3:78f223d34f36 12640 #define UART_S1_REG(base) ((base)->S1)
ethaderu 3:78f223d34f36 12641 #define UART_S2_REG(base) ((base)->S2)
ethaderu 3:78f223d34f36 12642 #define UART_C3_REG(base) ((base)->C3)
ethaderu 3:78f223d34f36 12643 #define UART_D_REG(base) ((base)->D)
ethaderu 3:78f223d34f36 12644 #define UART_MA1_REG(base) ((base)->MA1)
ethaderu 3:78f223d34f36 12645 #define UART_MA2_REG(base) ((base)->MA2)
ethaderu 3:78f223d34f36 12646 #define UART_C4_REG(base) ((base)->C4)
ethaderu 3:78f223d34f36 12647 #define UART_C5_REG(base) ((base)->C5)
ethaderu 3:78f223d34f36 12648 #define UART_ED_REG(base) ((base)->ED)
ethaderu 3:78f223d34f36 12649 #define UART_MODEM_REG(base) ((base)->MODEM)
ethaderu 3:78f223d34f36 12650 #define UART_IR_REG(base) ((base)->IR)
ethaderu 3:78f223d34f36 12651 #define UART_PFIFO_REG(base) ((base)->PFIFO)
ethaderu 3:78f223d34f36 12652 #define UART_CFIFO_REG(base) ((base)->CFIFO)
ethaderu 3:78f223d34f36 12653 #define UART_SFIFO_REG(base) ((base)->SFIFO)
ethaderu 3:78f223d34f36 12654 #define UART_TWFIFO_REG(base) ((base)->TWFIFO)
ethaderu 3:78f223d34f36 12655 #define UART_TCFIFO_REG(base) ((base)->TCFIFO)
ethaderu 3:78f223d34f36 12656 #define UART_RWFIFO_REG(base) ((base)->RWFIFO)
ethaderu 3:78f223d34f36 12657 #define UART_RCFIFO_REG(base) ((base)->RCFIFO)
ethaderu 3:78f223d34f36 12658 #define UART_C7816_REG(base) ((base)->C7816)
ethaderu 3:78f223d34f36 12659 #define UART_IE7816_REG(base) ((base)->IE7816)
ethaderu 3:78f223d34f36 12660 #define UART_IS7816_REG(base) ((base)->IS7816)
ethaderu 3:78f223d34f36 12661 #define UART_WP7816T0_REG(base) ((base)->WP7816T0)
ethaderu 3:78f223d34f36 12662 #define UART_WP7816T1_REG(base) ((base)->WP7816T1)
ethaderu 3:78f223d34f36 12663 #define UART_WN7816_REG(base) ((base)->WN7816)
ethaderu 3:78f223d34f36 12664 #define UART_WF7816_REG(base) ((base)->WF7816)
ethaderu 3:78f223d34f36 12665 #define UART_ET7816_REG(base) ((base)->ET7816)
ethaderu 3:78f223d34f36 12666 #define UART_TL7816_REG(base) ((base)->TL7816)
ethaderu 3:78f223d34f36 12667
ethaderu 3:78f223d34f36 12668 /*!
ethaderu 3:78f223d34f36 12669 * @}
ethaderu 3:78f223d34f36 12670 */ /* end of group UART_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 12671
ethaderu 3:78f223d34f36 12672
ethaderu 3:78f223d34f36 12673 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 12674 -- UART Register Masks
ethaderu 3:78f223d34f36 12675 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 12676
ethaderu 3:78f223d34f36 12677 /*!
ethaderu 3:78f223d34f36 12678 * @addtogroup UART_Register_Masks UART Register Masks
ethaderu 3:78f223d34f36 12679 * @{
ethaderu 3:78f223d34f36 12680 */
ethaderu 3:78f223d34f36 12681
ethaderu 3:78f223d34f36 12682 /* BDH Bit Fields */
ethaderu 3:78f223d34f36 12683 #define UART_BDH_SBR_MASK 0x1Fu
ethaderu 3:78f223d34f36 12684 #define UART_BDH_SBR_SHIFT 0
ethaderu 3:78f223d34f36 12685 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
ethaderu 3:78f223d34f36 12686 #define UART_BDH_SBNS_MASK 0x20u
ethaderu 3:78f223d34f36 12687 #define UART_BDH_SBNS_SHIFT 5
ethaderu 3:78f223d34f36 12688 #define UART_BDH_RXEDGIE_MASK 0x40u
ethaderu 3:78f223d34f36 12689 #define UART_BDH_RXEDGIE_SHIFT 6
ethaderu 3:78f223d34f36 12690 #define UART_BDH_LBKDIE_MASK 0x80u
ethaderu 3:78f223d34f36 12691 #define UART_BDH_LBKDIE_SHIFT 7
ethaderu 3:78f223d34f36 12692 /* BDL Bit Fields */
ethaderu 3:78f223d34f36 12693 #define UART_BDL_SBR_MASK 0xFFu
ethaderu 3:78f223d34f36 12694 #define UART_BDL_SBR_SHIFT 0
ethaderu 3:78f223d34f36 12695 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
ethaderu 3:78f223d34f36 12696 /* C1 Bit Fields */
ethaderu 3:78f223d34f36 12697 #define UART_C1_PT_MASK 0x1u
ethaderu 3:78f223d34f36 12698 #define UART_C1_PT_SHIFT 0
ethaderu 3:78f223d34f36 12699 #define UART_C1_PE_MASK 0x2u
ethaderu 3:78f223d34f36 12700 #define UART_C1_PE_SHIFT 1
ethaderu 3:78f223d34f36 12701 #define UART_C1_ILT_MASK 0x4u
ethaderu 3:78f223d34f36 12702 #define UART_C1_ILT_SHIFT 2
ethaderu 3:78f223d34f36 12703 #define UART_C1_WAKE_MASK 0x8u
ethaderu 3:78f223d34f36 12704 #define UART_C1_WAKE_SHIFT 3
ethaderu 3:78f223d34f36 12705 #define UART_C1_M_MASK 0x10u
ethaderu 3:78f223d34f36 12706 #define UART_C1_M_SHIFT 4
ethaderu 3:78f223d34f36 12707 #define UART_C1_RSRC_MASK 0x20u
ethaderu 3:78f223d34f36 12708 #define UART_C1_RSRC_SHIFT 5
ethaderu 3:78f223d34f36 12709 #define UART_C1_UARTSWAI_MASK 0x40u
ethaderu 3:78f223d34f36 12710 #define UART_C1_UARTSWAI_SHIFT 6
ethaderu 3:78f223d34f36 12711 #define UART_C1_LOOPS_MASK 0x80u
ethaderu 3:78f223d34f36 12712 #define UART_C1_LOOPS_SHIFT 7
ethaderu 3:78f223d34f36 12713 /* C2 Bit Fields */
ethaderu 3:78f223d34f36 12714 #define UART_C2_SBK_MASK 0x1u
ethaderu 3:78f223d34f36 12715 #define UART_C2_SBK_SHIFT 0
ethaderu 3:78f223d34f36 12716 #define UART_C2_RWU_MASK 0x2u
ethaderu 3:78f223d34f36 12717 #define UART_C2_RWU_SHIFT 1
ethaderu 3:78f223d34f36 12718 #define UART_C2_RE_MASK 0x4u
ethaderu 3:78f223d34f36 12719 #define UART_C2_RE_SHIFT 2
ethaderu 3:78f223d34f36 12720 #define UART_C2_TE_MASK 0x8u
ethaderu 3:78f223d34f36 12721 #define UART_C2_TE_SHIFT 3
ethaderu 3:78f223d34f36 12722 #define UART_C2_ILIE_MASK 0x10u
ethaderu 3:78f223d34f36 12723 #define UART_C2_ILIE_SHIFT 4
ethaderu 3:78f223d34f36 12724 #define UART_C2_RIE_MASK 0x20u
ethaderu 3:78f223d34f36 12725 #define UART_C2_RIE_SHIFT 5
ethaderu 3:78f223d34f36 12726 #define UART_C2_TCIE_MASK 0x40u
ethaderu 3:78f223d34f36 12727 #define UART_C2_TCIE_SHIFT 6
ethaderu 3:78f223d34f36 12728 #define UART_C2_TIE_MASK 0x80u
ethaderu 3:78f223d34f36 12729 #define UART_C2_TIE_SHIFT 7
ethaderu 3:78f223d34f36 12730 /* S1 Bit Fields */
ethaderu 3:78f223d34f36 12731 #define UART_S1_PF_MASK 0x1u
ethaderu 3:78f223d34f36 12732 #define UART_S1_PF_SHIFT 0
ethaderu 3:78f223d34f36 12733 #define UART_S1_FE_MASK 0x2u
ethaderu 3:78f223d34f36 12734 #define UART_S1_FE_SHIFT 1
ethaderu 3:78f223d34f36 12735 #define UART_S1_NF_MASK 0x4u
ethaderu 3:78f223d34f36 12736 #define UART_S1_NF_SHIFT 2
ethaderu 3:78f223d34f36 12737 #define UART_S1_OR_MASK 0x8u
ethaderu 3:78f223d34f36 12738 #define UART_S1_OR_SHIFT 3
ethaderu 3:78f223d34f36 12739 #define UART_S1_IDLE_MASK 0x10u
ethaderu 3:78f223d34f36 12740 #define UART_S1_IDLE_SHIFT 4
ethaderu 3:78f223d34f36 12741 #define UART_S1_RDRF_MASK 0x20u
ethaderu 3:78f223d34f36 12742 #define UART_S1_RDRF_SHIFT 5
ethaderu 3:78f223d34f36 12743 #define UART_S1_TC_MASK 0x40u
ethaderu 3:78f223d34f36 12744 #define UART_S1_TC_SHIFT 6
ethaderu 3:78f223d34f36 12745 #define UART_S1_TDRE_MASK 0x80u
ethaderu 3:78f223d34f36 12746 #define UART_S1_TDRE_SHIFT 7
ethaderu 3:78f223d34f36 12747 /* S2 Bit Fields */
ethaderu 3:78f223d34f36 12748 #define UART_S2_RAF_MASK 0x1u
ethaderu 3:78f223d34f36 12749 #define UART_S2_RAF_SHIFT 0
ethaderu 3:78f223d34f36 12750 #define UART_S2_LBKDE_MASK 0x2u
ethaderu 3:78f223d34f36 12751 #define UART_S2_LBKDE_SHIFT 1
ethaderu 3:78f223d34f36 12752 #define UART_S2_BRK13_MASK 0x4u
ethaderu 3:78f223d34f36 12753 #define UART_S2_BRK13_SHIFT 2
ethaderu 3:78f223d34f36 12754 #define UART_S2_RWUID_MASK 0x8u
ethaderu 3:78f223d34f36 12755 #define UART_S2_RWUID_SHIFT 3
ethaderu 3:78f223d34f36 12756 #define UART_S2_RXINV_MASK 0x10u
ethaderu 3:78f223d34f36 12757 #define UART_S2_RXINV_SHIFT 4
ethaderu 3:78f223d34f36 12758 #define UART_S2_MSBF_MASK 0x20u
ethaderu 3:78f223d34f36 12759 #define UART_S2_MSBF_SHIFT 5
ethaderu 3:78f223d34f36 12760 #define UART_S2_RXEDGIF_MASK 0x40u
ethaderu 3:78f223d34f36 12761 #define UART_S2_RXEDGIF_SHIFT 6
ethaderu 3:78f223d34f36 12762 #define UART_S2_LBKDIF_MASK 0x80u
ethaderu 3:78f223d34f36 12763 #define UART_S2_LBKDIF_SHIFT 7
ethaderu 3:78f223d34f36 12764 /* C3 Bit Fields */
ethaderu 3:78f223d34f36 12765 #define UART_C3_PEIE_MASK 0x1u
ethaderu 3:78f223d34f36 12766 #define UART_C3_PEIE_SHIFT 0
ethaderu 3:78f223d34f36 12767 #define UART_C3_FEIE_MASK 0x2u
ethaderu 3:78f223d34f36 12768 #define UART_C3_FEIE_SHIFT 1
ethaderu 3:78f223d34f36 12769 #define UART_C3_NEIE_MASK 0x4u
ethaderu 3:78f223d34f36 12770 #define UART_C3_NEIE_SHIFT 2
ethaderu 3:78f223d34f36 12771 #define UART_C3_ORIE_MASK 0x8u
ethaderu 3:78f223d34f36 12772 #define UART_C3_ORIE_SHIFT 3
ethaderu 3:78f223d34f36 12773 #define UART_C3_TXINV_MASK 0x10u
ethaderu 3:78f223d34f36 12774 #define UART_C3_TXINV_SHIFT 4
ethaderu 3:78f223d34f36 12775 #define UART_C3_TXDIR_MASK 0x20u
ethaderu 3:78f223d34f36 12776 #define UART_C3_TXDIR_SHIFT 5
ethaderu 3:78f223d34f36 12777 #define UART_C3_T8_MASK 0x40u
ethaderu 3:78f223d34f36 12778 #define UART_C3_T8_SHIFT 6
ethaderu 3:78f223d34f36 12779 #define UART_C3_R8_MASK 0x80u
ethaderu 3:78f223d34f36 12780 #define UART_C3_R8_SHIFT 7
ethaderu 3:78f223d34f36 12781 /* D Bit Fields */
ethaderu 3:78f223d34f36 12782 #define UART_D_RT_MASK 0xFFu
ethaderu 3:78f223d34f36 12783 #define UART_D_RT_SHIFT 0
ethaderu 3:78f223d34f36 12784 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
ethaderu 3:78f223d34f36 12785 /* MA1 Bit Fields */
ethaderu 3:78f223d34f36 12786 #define UART_MA1_MA_MASK 0xFFu
ethaderu 3:78f223d34f36 12787 #define UART_MA1_MA_SHIFT 0
ethaderu 3:78f223d34f36 12788 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
ethaderu 3:78f223d34f36 12789 /* MA2 Bit Fields */
ethaderu 3:78f223d34f36 12790 #define UART_MA2_MA_MASK 0xFFu
ethaderu 3:78f223d34f36 12791 #define UART_MA2_MA_SHIFT 0
ethaderu 3:78f223d34f36 12792 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
ethaderu 3:78f223d34f36 12793 /* C4 Bit Fields */
ethaderu 3:78f223d34f36 12794 #define UART_C4_BRFA_MASK 0x1Fu
ethaderu 3:78f223d34f36 12795 #define UART_C4_BRFA_SHIFT 0
ethaderu 3:78f223d34f36 12796 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
ethaderu 3:78f223d34f36 12797 #define UART_C4_M10_MASK 0x20u
ethaderu 3:78f223d34f36 12798 #define UART_C4_M10_SHIFT 5
ethaderu 3:78f223d34f36 12799 #define UART_C4_MAEN2_MASK 0x40u
ethaderu 3:78f223d34f36 12800 #define UART_C4_MAEN2_SHIFT 6
ethaderu 3:78f223d34f36 12801 #define UART_C4_MAEN1_MASK 0x80u
ethaderu 3:78f223d34f36 12802 #define UART_C4_MAEN1_SHIFT 7
ethaderu 3:78f223d34f36 12803 /* C5 Bit Fields */
ethaderu 3:78f223d34f36 12804 #define UART_C5_LBKDDMAS_MASK 0x8u
ethaderu 3:78f223d34f36 12805 #define UART_C5_LBKDDMAS_SHIFT 3
ethaderu 3:78f223d34f36 12806 #define UART_C5_ILDMAS_MASK 0x10u
ethaderu 3:78f223d34f36 12807 #define UART_C5_ILDMAS_SHIFT 4
ethaderu 3:78f223d34f36 12808 #define UART_C5_RDMAS_MASK 0x20u
ethaderu 3:78f223d34f36 12809 #define UART_C5_RDMAS_SHIFT 5
ethaderu 3:78f223d34f36 12810 #define UART_C5_TCDMAS_MASK 0x40u
ethaderu 3:78f223d34f36 12811 #define UART_C5_TCDMAS_SHIFT 6
ethaderu 3:78f223d34f36 12812 #define UART_C5_TDMAS_MASK 0x80u
ethaderu 3:78f223d34f36 12813 #define UART_C5_TDMAS_SHIFT 7
ethaderu 3:78f223d34f36 12814 /* ED Bit Fields */
ethaderu 3:78f223d34f36 12815 #define UART_ED_PARITYE_MASK 0x40u
ethaderu 3:78f223d34f36 12816 #define UART_ED_PARITYE_SHIFT 6
ethaderu 3:78f223d34f36 12817 #define UART_ED_NOISY_MASK 0x80u
ethaderu 3:78f223d34f36 12818 #define UART_ED_NOISY_SHIFT 7
ethaderu 3:78f223d34f36 12819 /* MODEM Bit Fields */
ethaderu 3:78f223d34f36 12820 #define UART_MODEM_TXCTSE_MASK 0x1u
ethaderu 3:78f223d34f36 12821 #define UART_MODEM_TXCTSE_SHIFT 0
ethaderu 3:78f223d34f36 12822 #define UART_MODEM_TXRTSE_MASK 0x2u
ethaderu 3:78f223d34f36 12823 #define UART_MODEM_TXRTSE_SHIFT 1
ethaderu 3:78f223d34f36 12824 #define UART_MODEM_TXRTSPOL_MASK 0x4u
ethaderu 3:78f223d34f36 12825 #define UART_MODEM_TXRTSPOL_SHIFT 2
ethaderu 3:78f223d34f36 12826 #define UART_MODEM_RXRTSE_MASK 0x8u
ethaderu 3:78f223d34f36 12827 #define UART_MODEM_RXRTSE_SHIFT 3
ethaderu 3:78f223d34f36 12828 /* IR Bit Fields */
ethaderu 3:78f223d34f36 12829 #define UART_IR_TNP_MASK 0x3u
ethaderu 3:78f223d34f36 12830 #define UART_IR_TNP_SHIFT 0
ethaderu 3:78f223d34f36 12831 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
ethaderu 3:78f223d34f36 12832 #define UART_IR_IREN_MASK 0x4u
ethaderu 3:78f223d34f36 12833 #define UART_IR_IREN_SHIFT 2
ethaderu 3:78f223d34f36 12834 /* PFIFO Bit Fields */
ethaderu 3:78f223d34f36 12835 #define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
ethaderu 3:78f223d34f36 12836 #define UART_PFIFO_RXFIFOSIZE_SHIFT 0
ethaderu 3:78f223d34f36 12837 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
ethaderu 3:78f223d34f36 12838 #define UART_PFIFO_RXFE_MASK 0x8u
ethaderu 3:78f223d34f36 12839 #define UART_PFIFO_RXFE_SHIFT 3
ethaderu 3:78f223d34f36 12840 #define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
ethaderu 3:78f223d34f36 12841 #define UART_PFIFO_TXFIFOSIZE_SHIFT 4
ethaderu 3:78f223d34f36 12842 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
ethaderu 3:78f223d34f36 12843 #define UART_PFIFO_TXFE_MASK 0x80u
ethaderu 3:78f223d34f36 12844 #define UART_PFIFO_TXFE_SHIFT 7
ethaderu 3:78f223d34f36 12845 /* CFIFO Bit Fields */
ethaderu 3:78f223d34f36 12846 #define UART_CFIFO_RXUFE_MASK 0x1u
ethaderu 3:78f223d34f36 12847 #define UART_CFIFO_RXUFE_SHIFT 0
ethaderu 3:78f223d34f36 12848 #define UART_CFIFO_TXOFE_MASK 0x2u
ethaderu 3:78f223d34f36 12849 #define UART_CFIFO_TXOFE_SHIFT 1
ethaderu 3:78f223d34f36 12850 #define UART_CFIFO_RXOFE_MASK 0x4u
ethaderu 3:78f223d34f36 12851 #define UART_CFIFO_RXOFE_SHIFT 2
ethaderu 3:78f223d34f36 12852 #define UART_CFIFO_RXFLUSH_MASK 0x40u
ethaderu 3:78f223d34f36 12853 #define UART_CFIFO_RXFLUSH_SHIFT 6
ethaderu 3:78f223d34f36 12854 #define UART_CFIFO_TXFLUSH_MASK 0x80u
ethaderu 3:78f223d34f36 12855 #define UART_CFIFO_TXFLUSH_SHIFT 7
ethaderu 3:78f223d34f36 12856 /* SFIFO Bit Fields */
ethaderu 3:78f223d34f36 12857 #define UART_SFIFO_RXUF_MASK 0x1u
ethaderu 3:78f223d34f36 12858 #define UART_SFIFO_RXUF_SHIFT 0
ethaderu 3:78f223d34f36 12859 #define UART_SFIFO_TXOF_MASK 0x2u
ethaderu 3:78f223d34f36 12860 #define UART_SFIFO_TXOF_SHIFT 1
ethaderu 3:78f223d34f36 12861 #define UART_SFIFO_RXOF_MASK 0x4u
ethaderu 3:78f223d34f36 12862 #define UART_SFIFO_RXOF_SHIFT 2
ethaderu 3:78f223d34f36 12863 #define UART_SFIFO_RXEMPT_MASK 0x40u
ethaderu 3:78f223d34f36 12864 #define UART_SFIFO_RXEMPT_SHIFT 6
ethaderu 3:78f223d34f36 12865 #define UART_SFIFO_TXEMPT_MASK 0x80u
ethaderu 3:78f223d34f36 12866 #define UART_SFIFO_TXEMPT_SHIFT 7
ethaderu 3:78f223d34f36 12867 /* TWFIFO Bit Fields */
ethaderu 3:78f223d34f36 12868 #define UART_TWFIFO_TXWATER_MASK 0xFFu
ethaderu 3:78f223d34f36 12869 #define UART_TWFIFO_TXWATER_SHIFT 0
ethaderu 3:78f223d34f36 12870 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
ethaderu 3:78f223d34f36 12871 /* TCFIFO Bit Fields */
ethaderu 3:78f223d34f36 12872 #define UART_TCFIFO_TXCOUNT_MASK 0xFFu
ethaderu 3:78f223d34f36 12873 #define UART_TCFIFO_TXCOUNT_SHIFT 0
ethaderu 3:78f223d34f36 12874 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
ethaderu 3:78f223d34f36 12875 /* RWFIFO Bit Fields */
ethaderu 3:78f223d34f36 12876 #define UART_RWFIFO_RXWATER_MASK 0xFFu
ethaderu 3:78f223d34f36 12877 #define UART_RWFIFO_RXWATER_SHIFT 0
ethaderu 3:78f223d34f36 12878 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
ethaderu 3:78f223d34f36 12879 /* RCFIFO Bit Fields */
ethaderu 3:78f223d34f36 12880 #define UART_RCFIFO_RXCOUNT_MASK 0xFFu
ethaderu 3:78f223d34f36 12881 #define UART_RCFIFO_RXCOUNT_SHIFT 0
ethaderu 3:78f223d34f36 12882 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
ethaderu 3:78f223d34f36 12883 /* C7816 Bit Fields */
ethaderu 3:78f223d34f36 12884 #define UART_C7816_ISO_7816E_MASK 0x1u
ethaderu 3:78f223d34f36 12885 #define UART_C7816_ISO_7816E_SHIFT 0
ethaderu 3:78f223d34f36 12886 #define UART_C7816_TTYPE_MASK 0x2u
ethaderu 3:78f223d34f36 12887 #define UART_C7816_TTYPE_SHIFT 1
ethaderu 3:78f223d34f36 12888 #define UART_C7816_INIT_MASK 0x4u
ethaderu 3:78f223d34f36 12889 #define UART_C7816_INIT_SHIFT 2
ethaderu 3:78f223d34f36 12890 #define UART_C7816_ANACK_MASK 0x8u
ethaderu 3:78f223d34f36 12891 #define UART_C7816_ANACK_SHIFT 3
ethaderu 3:78f223d34f36 12892 #define UART_C7816_ONACK_MASK 0x10u
ethaderu 3:78f223d34f36 12893 #define UART_C7816_ONACK_SHIFT 4
ethaderu 3:78f223d34f36 12894 /* IE7816 Bit Fields */
ethaderu 3:78f223d34f36 12895 #define UART_IE7816_RXTE_MASK 0x1u
ethaderu 3:78f223d34f36 12896 #define UART_IE7816_RXTE_SHIFT 0
ethaderu 3:78f223d34f36 12897 #define UART_IE7816_TXTE_MASK 0x2u
ethaderu 3:78f223d34f36 12898 #define UART_IE7816_TXTE_SHIFT 1
ethaderu 3:78f223d34f36 12899 #define UART_IE7816_GTVE_MASK 0x4u
ethaderu 3:78f223d34f36 12900 #define UART_IE7816_GTVE_SHIFT 2
ethaderu 3:78f223d34f36 12901 #define UART_IE7816_INITDE_MASK 0x10u
ethaderu 3:78f223d34f36 12902 #define UART_IE7816_INITDE_SHIFT 4
ethaderu 3:78f223d34f36 12903 #define UART_IE7816_BWTE_MASK 0x20u
ethaderu 3:78f223d34f36 12904 #define UART_IE7816_BWTE_SHIFT 5
ethaderu 3:78f223d34f36 12905 #define UART_IE7816_CWTE_MASK 0x40u
ethaderu 3:78f223d34f36 12906 #define UART_IE7816_CWTE_SHIFT 6
ethaderu 3:78f223d34f36 12907 #define UART_IE7816_WTE_MASK 0x80u
ethaderu 3:78f223d34f36 12908 #define UART_IE7816_WTE_SHIFT 7
ethaderu 3:78f223d34f36 12909 /* IS7816 Bit Fields */
ethaderu 3:78f223d34f36 12910 #define UART_IS7816_RXT_MASK 0x1u
ethaderu 3:78f223d34f36 12911 #define UART_IS7816_RXT_SHIFT 0
ethaderu 3:78f223d34f36 12912 #define UART_IS7816_TXT_MASK 0x2u
ethaderu 3:78f223d34f36 12913 #define UART_IS7816_TXT_SHIFT 1
ethaderu 3:78f223d34f36 12914 #define UART_IS7816_GTV_MASK 0x4u
ethaderu 3:78f223d34f36 12915 #define UART_IS7816_GTV_SHIFT 2
ethaderu 3:78f223d34f36 12916 #define UART_IS7816_INITD_MASK 0x10u
ethaderu 3:78f223d34f36 12917 #define UART_IS7816_INITD_SHIFT 4
ethaderu 3:78f223d34f36 12918 #define UART_IS7816_BWT_MASK 0x20u
ethaderu 3:78f223d34f36 12919 #define UART_IS7816_BWT_SHIFT 5
ethaderu 3:78f223d34f36 12920 #define UART_IS7816_CWT_MASK 0x40u
ethaderu 3:78f223d34f36 12921 #define UART_IS7816_CWT_SHIFT 6
ethaderu 3:78f223d34f36 12922 #define UART_IS7816_WT_MASK 0x80u
ethaderu 3:78f223d34f36 12923 #define UART_IS7816_WT_SHIFT 7
ethaderu 3:78f223d34f36 12924 /* WP7816T0 Bit Fields */
ethaderu 3:78f223d34f36 12925 #define UART_WP7816T0_WI_MASK 0xFFu
ethaderu 3:78f223d34f36 12926 #define UART_WP7816T0_WI_SHIFT 0
ethaderu 3:78f223d34f36 12927 #define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T0_WI_SHIFT))&UART_WP7816T0_WI_MASK)
ethaderu 3:78f223d34f36 12928 /* WP7816T1 Bit Fields */
ethaderu 3:78f223d34f36 12929 #define UART_WP7816T1_BWI_MASK 0xFu
ethaderu 3:78f223d34f36 12930 #define UART_WP7816T1_BWI_SHIFT 0
ethaderu 3:78f223d34f36 12931 #define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_BWI_SHIFT))&UART_WP7816T1_BWI_MASK)
ethaderu 3:78f223d34f36 12932 #define UART_WP7816T1_CWI_MASK 0xF0u
ethaderu 3:78f223d34f36 12933 #define UART_WP7816T1_CWI_SHIFT 4
ethaderu 3:78f223d34f36 12934 #define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_CWI_SHIFT))&UART_WP7816T1_CWI_MASK)
ethaderu 3:78f223d34f36 12935 /* WN7816 Bit Fields */
ethaderu 3:78f223d34f36 12936 #define UART_WN7816_GTN_MASK 0xFFu
ethaderu 3:78f223d34f36 12937 #define UART_WN7816_GTN_SHIFT 0
ethaderu 3:78f223d34f36 12938 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
ethaderu 3:78f223d34f36 12939 /* WF7816 Bit Fields */
ethaderu 3:78f223d34f36 12940 #define UART_WF7816_GTFD_MASK 0xFFu
ethaderu 3:78f223d34f36 12941 #define UART_WF7816_GTFD_SHIFT 0
ethaderu 3:78f223d34f36 12942 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
ethaderu 3:78f223d34f36 12943 /* ET7816 Bit Fields */
ethaderu 3:78f223d34f36 12944 #define UART_ET7816_RXTHRESHOLD_MASK 0xFu
ethaderu 3:78f223d34f36 12945 #define UART_ET7816_RXTHRESHOLD_SHIFT 0
ethaderu 3:78f223d34f36 12946 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
ethaderu 3:78f223d34f36 12947 #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
ethaderu 3:78f223d34f36 12948 #define UART_ET7816_TXTHRESHOLD_SHIFT 4
ethaderu 3:78f223d34f36 12949 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
ethaderu 3:78f223d34f36 12950 /* TL7816 Bit Fields */
ethaderu 3:78f223d34f36 12951 #define UART_TL7816_TLEN_MASK 0xFFu
ethaderu 3:78f223d34f36 12952 #define UART_TL7816_TLEN_SHIFT 0
ethaderu 3:78f223d34f36 12953 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
ethaderu 3:78f223d34f36 12954
ethaderu 3:78f223d34f36 12955 /*!
ethaderu 3:78f223d34f36 12956 * @}
ethaderu 3:78f223d34f36 12957 */ /* end of group UART_Register_Masks */
ethaderu 3:78f223d34f36 12958
ethaderu 3:78f223d34f36 12959
ethaderu 3:78f223d34f36 12960 /* UART - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 12961 /** Peripheral UART0 base address */
ethaderu 3:78f223d34f36 12962 #define UART0_BASE (0x4006A000u)
ethaderu 3:78f223d34f36 12963 /** Peripheral UART0 base pointer */
ethaderu 3:78f223d34f36 12964 #define UART0 ((UART_Type *)UART0_BASE)
ethaderu 3:78f223d34f36 12965 #define UART0_BASE_PTR (UART0)
ethaderu 3:78f223d34f36 12966 /** Peripheral UART1 base address */
ethaderu 3:78f223d34f36 12967 #define UART1_BASE (0x4006B000u)
ethaderu 3:78f223d34f36 12968 /** Peripheral UART1 base pointer */
ethaderu 3:78f223d34f36 12969 #define UART1 ((UART_Type *)UART1_BASE)
ethaderu 3:78f223d34f36 12970 #define UART1_BASE_PTR (UART1)
ethaderu 3:78f223d34f36 12971 /** Peripheral UART2 base address */
ethaderu 3:78f223d34f36 12972 #define UART2_BASE (0x4006C000u)
ethaderu 3:78f223d34f36 12973 /** Peripheral UART2 base pointer */
ethaderu 3:78f223d34f36 12974 #define UART2 ((UART_Type *)UART2_BASE)
ethaderu 3:78f223d34f36 12975 #define UART2_BASE_PTR (UART2)
ethaderu 3:78f223d34f36 12976 /** Peripheral UART3 base address */
ethaderu 3:78f223d34f36 12977 #define UART3_BASE (0x4006D000u)
ethaderu 3:78f223d34f36 12978 /** Peripheral UART3 base pointer */
ethaderu 3:78f223d34f36 12979 #define UART3 ((UART_Type *)UART3_BASE)
ethaderu 3:78f223d34f36 12980 #define UART3_BASE_PTR (UART3)
ethaderu 3:78f223d34f36 12981 /** Peripheral UART4 base address */
ethaderu 3:78f223d34f36 12982 #define UART4_BASE (0x400EA000u)
ethaderu 3:78f223d34f36 12983 /** Peripheral UART4 base pointer */
ethaderu 3:78f223d34f36 12984 #define UART4 ((UART_Type *)UART4_BASE)
ethaderu 3:78f223d34f36 12985 #define UART4_BASE_PTR (UART4)
ethaderu 3:78f223d34f36 12986 /** Peripheral UART5 base address */
ethaderu 3:78f223d34f36 12987 #define UART5_BASE (0x400EB000u)
ethaderu 3:78f223d34f36 12988 /** Peripheral UART5 base pointer */
ethaderu 3:78f223d34f36 12989 #define UART5 ((UART_Type *)UART5_BASE)
ethaderu 3:78f223d34f36 12990 #define UART5_BASE_PTR (UART5)
ethaderu 3:78f223d34f36 12991 /** Array initializer of UART peripheral base addresses */
ethaderu 3:78f223d34f36 12992 #define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
ethaderu 3:78f223d34f36 12993 /** Array initializer of UART peripheral base pointers */
ethaderu 3:78f223d34f36 12994 #define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4, UART5 }
ethaderu 3:78f223d34f36 12995 /** Interrupt vectors for the UART peripheral type */
ethaderu 3:78f223d34f36 12996 #define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn }
ethaderu 3:78f223d34f36 12997 #define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn }
ethaderu 3:78f223d34f36 12998 #define UART_LON_IRQS { UART0_LON_IRQn, 0, 0, 0, 0, 0 }
ethaderu 3:78f223d34f36 12999
ethaderu 3:78f223d34f36 13000 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 13001 -- UART - Register accessor macros
ethaderu 3:78f223d34f36 13002 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 13003
ethaderu 3:78f223d34f36 13004 /*!
ethaderu 3:78f223d34f36 13005 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
ethaderu 3:78f223d34f36 13006 * @{
ethaderu 3:78f223d34f36 13007 */
ethaderu 3:78f223d34f36 13008
ethaderu 3:78f223d34f36 13009
ethaderu 3:78f223d34f36 13010 /* UART - Register instance definitions */
ethaderu 3:78f223d34f36 13011 /* UART0 */
ethaderu 3:78f223d34f36 13012 #define UART0_BDH UART_BDH_REG(UART0)
ethaderu 3:78f223d34f36 13013 #define UART0_BDL UART_BDL_REG(UART0)
ethaderu 3:78f223d34f36 13014 #define UART0_C1 UART_C1_REG(UART0)
ethaderu 3:78f223d34f36 13015 #define UART0_C2 UART_C2_REG(UART0)
ethaderu 3:78f223d34f36 13016 #define UART0_S1 UART_S1_REG(UART0)
ethaderu 3:78f223d34f36 13017 #define UART0_S2 UART_S2_REG(UART0)
ethaderu 3:78f223d34f36 13018 #define UART0_C3 UART_C3_REG(UART0)
ethaderu 3:78f223d34f36 13019 #define UART0_D UART_D_REG(UART0)
ethaderu 3:78f223d34f36 13020 #define UART0_MA1 UART_MA1_REG(UART0)
ethaderu 3:78f223d34f36 13021 #define UART0_MA2 UART_MA2_REG(UART0)
ethaderu 3:78f223d34f36 13022 #define UART0_C4 UART_C4_REG(UART0)
ethaderu 3:78f223d34f36 13023 #define UART0_C5 UART_C5_REG(UART0)
ethaderu 3:78f223d34f36 13024 #define UART0_ED UART_ED_REG(UART0)
ethaderu 3:78f223d34f36 13025 #define UART0_MODEM UART_MODEM_REG(UART0)
ethaderu 3:78f223d34f36 13026 #define UART0_IR UART_IR_REG(UART0)
ethaderu 3:78f223d34f36 13027 #define UART0_PFIFO UART_PFIFO_REG(UART0)
ethaderu 3:78f223d34f36 13028 #define UART0_CFIFO UART_CFIFO_REG(UART0)
ethaderu 3:78f223d34f36 13029 #define UART0_SFIFO UART_SFIFO_REG(UART0)
ethaderu 3:78f223d34f36 13030 #define UART0_TWFIFO UART_TWFIFO_REG(UART0)
ethaderu 3:78f223d34f36 13031 #define UART0_TCFIFO UART_TCFIFO_REG(UART0)
ethaderu 3:78f223d34f36 13032 #define UART0_RWFIFO UART_RWFIFO_REG(UART0)
ethaderu 3:78f223d34f36 13033 #define UART0_RCFIFO UART_RCFIFO_REG(UART0)
ethaderu 3:78f223d34f36 13034 #define UART0_C7816 UART_C7816_REG(UART0)
ethaderu 3:78f223d34f36 13035 #define UART0_IE7816 UART_IE7816_REG(UART0)
ethaderu 3:78f223d34f36 13036 #define UART0_IS7816 UART_IS7816_REG(UART0)
ethaderu 3:78f223d34f36 13037 #define UART0_WP7816T0 UART_WP7816T0_REG(UART0)
ethaderu 3:78f223d34f36 13038 #define UART0_WP7816T1 UART_WP7816T1_REG(UART0)
ethaderu 3:78f223d34f36 13039 #define UART0_WN7816 UART_WN7816_REG(UART0)
ethaderu 3:78f223d34f36 13040 #define UART0_WF7816 UART_WF7816_REG(UART0)
ethaderu 3:78f223d34f36 13041 #define UART0_ET7816 UART_ET7816_REG(UART0)
ethaderu 3:78f223d34f36 13042 #define UART0_TL7816 UART_TL7816_REG(UART0)
ethaderu 3:78f223d34f36 13043 /* UART1 */
ethaderu 3:78f223d34f36 13044 #define UART1_BDH UART_BDH_REG(UART1)
ethaderu 3:78f223d34f36 13045 #define UART1_BDL UART_BDL_REG(UART1)
ethaderu 3:78f223d34f36 13046 #define UART1_C1 UART_C1_REG(UART1)
ethaderu 3:78f223d34f36 13047 #define UART1_C2 UART_C2_REG(UART1)
ethaderu 3:78f223d34f36 13048 #define UART1_S1 UART_S1_REG(UART1)
ethaderu 3:78f223d34f36 13049 #define UART1_S2 UART_S2_REG(UART1)
ethaderu 3:78f223d34f36 13050 #define UART1_C3 UART_C3_REG(UART1)
ethaderu 3:78f223d34f36 13051 #define UART1_D UART_D_REG(UART1)
ethaderu 3:78f223d34f36 13052 #define UART1_MA1 UART_MA1_REG(UART1)
ethaderu 3:78f223d34f36 13053 #define UART1_MA2 UART_MA2_REG(UART1)
ethaderu 3:78f223d34f36 13054 #define UART1_C4 UART_C4_REG(UART1)
ethaderu 3:78f223d34f36 13055 #define UART1_C5 UART_C5_REG(UART1)
ethaderu 3:78f223d34f36 13056 #define UART1_ED UART_ED_REG(UART1)
ethaderu 3:78f223d34f36 13057 #define UART1_MODEM UART_MODEM_REG(UART1)
ethaderu 3:78f223d34f36 13058 #define UART1_IR UART_IR_REG(UART1)
ethaderu 3:78f223d34f36 13059 #define UART1_PFIFO UART_PFIFO_REG(UART1)
ethaderu 3:78f223d34f36 13060 #define UART1_CFIFO UART_CFIFO_REG(UART1)
ethaderu 3:78f223d34f36 13061 #define UART1_SFIFO UART_SFIFO_REG(UART1)
ethaderu 3:78f223d34f36 13062 #define UART1_TWFIFO UART_TWFIFO_REG(UART1)
ethaderu 3:78f223d34f36 13063 #define UART1_TCFIFO UART_TCFIFO_REG(UART1)
ethaderu 3:78f223d34f36 13064 #define UART1_RWFIFO UART_RWFIFO_REG(UART1)
ethaderu 3:78f223d34f36 13065 #define UART1_RCFIFO UART_RCFIFO_REG(UART1)
ethaderu 3:78f223d34f36 13066 /* UART2 */
ethaderu 3:78f223d34f36 13067 #define UART2_BDH UART_BDH_REG(UART2)
ethaderu 3:78f223d34f36 13068 #define UART2_BDL UART_BDL_REG(UART2)
ethaderu 3:78f223d34f36 13069 #define UART2_C1 UART_C1_REG(UART2)
ethaderu 3:78f223d34f36 13070 #define UART2_C2 UART_C2_REG(UART2)
ethaderu 3:78f223d34f36 13071 #define UART2_S1 UART_S1_REG(UART2)
ethaderu 3:78f223d34f36 13072 #define UART2_S2 UART_S2_REG(UART2)
ethaderu 3:78f223d34f36 13073 #define UART2_C3 UART_C3_REG(UART2)
ethaderu 3:78f223d34f36 13074 #define UART2_D UART_D_REG(UART2)
ethaderu 3:78f223d34f36 13075 #define UART2_MA1 UART_MA1_REG(UART2)
ethaderu 3:78f223d34f36 13076 #define UART2_MA2 UART_MA2_REG(UART2)
ethaderu 3:78f223d34f36 13077 #define UART2_C4 UART_C4_REG(UART2)
ethaderu 3:78f223d34f36 13078 #define UART2_C5 UART_C5_REG(UART2)
ethaderu 3:78f223d34f36 13079 #define UART2_ED UART_ED_REG(UART2)
ethaderu 3:78f223d34f36 13080 #define UART2_MODEM UART_MODEM_REG(UART2)
ethaderu 3:78f223d34f36 13081 #define UART2_IR UART_IR_REG(UART2)
ethaderu 3:78f223d34f36 13082 #define UART2_PFIFO UART_PFIFO_REG(UART2)
ethaderu 3:78f223d34f36 13083 #define UART2_CFIFO UART_CFIFO_REG(UART2)
ethaderu 3:78f223d34f36 13084 #define UART2_SFIFO UART_SFIFO_REG(UART2)
ethaderu 3:78f223d34f36 13085 #define UART2_TWFIFO UART_TWFIFO_REG(UART2)
ethaderu 3:78f223d34f36 13086 #define UART2_TCFIFO UART_TCFIFO_REG(UART2)
ethaderu 3:78f223d34f36 13087 #define UART2_RWFIFO UART_RWFIFO_REG(UART2)
ethaderu 3:78f223d34f36 13088 #define UART2_RCFIFO UART_RCFIFO_REG(UART2)
ethaderu 3:78f223d34f36 13089 /* UART3 */
ethaderu 3:78f223d34f36 13090 #define UART3_BDH UART_BDH_REG(UART3)
ethaderu 3:78f223d34f36 13091 #define UART3_BDL UART_BDL_REG(UART3)
ethaderu 3:78f223d34f36 13092 #define UART3_C1 UART_C1_REG(UART3)
ethaderu 3:78f223d34f36 13093 #define UART3_C2 UART_C2_REG(UART3)
ethaderu 3:78f223d34f36 13094 #define UART3_S1 UART_S1_REG(UART3)
ethaderu 3:78f223d34f36 13095 #define UART3_S2 UART_S2_REG(UART3)
ethaderu 3:78f223d34f36 13096 #define UART3_C3 UART_C3_REG(UART3)
ethaderu 3:78f223d34f36 13097 #define UART3_D UART_D_REG(UART3)
ethaderu 3:78f223d34f36 13098 #define UART3_MA1 UART_MA1_REG(UART3)
ethaderu 3:78f223d34f36 13099 #define UART3_MA2 UART_MA2_REG(UART3)
ethaderu 3:78f223d34f36 13100 #define UART3_C4 UART_C4_REG(UART3)
ethaderu 3:78f223d34f36 13101 #define UART3_C5 UART_C5_REG(UART3)
ethaderu 3:78f223d34f36 13102 #define UART3_ED UART_ED_REG(UART3)
ethaderu 3:78f223d34f36 13103 #define UART3_MODEM UART_MODEM_REG(UART3)
ethaderu 3:78f223d34f36 13104 #define UART3_IR UART_IR_REG(UART3)
ethaderu 3:78f223d34f36 13105 #define UART3_PFIFO UART_PFIFO_REG(UART3)
ethaderu 3:78f223d34f36 13106 #define UART3_CFIFO UART_CFIFO_REG(UART3)
ethaderu 3:78f223d34f36 13107 #define UART3_SFIFO UART_SFIFO_REG(UART3)
ethaderu 3:78f223d34f36 13108 #define UART3_TWFIFO UART_TWFIFO_REG(UART3)
ethaderu 3:78f223d34f36 13109 #define UART3_TCFIFO UART_TCFIFO_REG(UART3)
ethaderu 3:78f223d34f36 13110 #define UART3_RWFIFO UART_RWFIFO_REG(UART3)
ethaderu 3:78f223d34f36 13111 #define UART3_RCFIFO UART_RCFIFO_REG(UART3)
ethaderu 3:78f223d34f36 13112 /* UART4 */
ethaderu 3:78f223d34f36 13113 #define UART4_BDH UART_BDH_REG(UART4)
ethaderu 3:78f223d34f36 13114 #define UART4_BDL UART_BDL_REG(UART4)
ethaderu 3:78f223d34f36 13115 #define UART4_C1 UART_C1_REG(UART4)
ethaderu 3:78f223d34f36 13116 #define UART4_C2 UART_C2_REG(UART4)
ethaderu 3:78f223d34f36 13117 #define UART4_S1 UART_S1_REG(UART4)
ethaderu 3:78f223d34f36 13118 #define UART4_S2 UART_S2_REG(UART4)
ethaderu 3:78f223d34f36 13119 #define UART4_C3 UART_C3_REG(UART4)
ethaderu 3:78f223d34f36 13120 #define UART4_D UART_D_REG(UART4)
ethaderu 3:78f223d34f36 13121 #define UART4_MA1 UART_MA1_REG(UART4)
ethaderu 3:78f223d34f36 13122 #define UART4_MA2 UART_MA2_REG(UART4)
ethaderu 3:78f223d34f36 13123 #define UART4_C4 UART_C4_REG(UART4)
ethaderu 3:78f223d34f36 13124 #define UART4_C5 UART_C5_REG(UART4)
ethaderu 3:78f223d34f36 13125 #define UART4_ED UART_ED_REG(UART4)
ethaderu 3:78f223d34f36 13126 #define UART4_MODEM UART_MODEM_REG(UART4)
ethaderu 3:78f223d34f36 13127 #define UART4_IR UART_IR_REG(UART4)
ethaderu 3:78f223d34f36 13128 #define UART4_PFIFO UART_PFIFO_REG(UART4)
ethaderu 3:78f223d34f36 13129 #define UART4_CFIFO UART_CFIFO_REG(UART4)
ethaderu 3:78f223d34f36 13130 #define UART4_SFIFO UART_SFIFO_REG(UART4)
ethaderu 3:78f223d34f36 13131 #define UART4_TWFIFO UART_TWFIFO_REG(UART4)
ethaderu 3:78f223d34f36 13132 #define UART4_TCFIFO UART_TCFIFO_REG(UART4)
ethaderu 3:78f223d34f36 13133 #define UART4_RWFIFO UART_RWFIFO_REG(UART4)
ethaderu 3:78f223d34f36 13134 #define UART4_RCFIFO UART_RCFIFO_REG(UART4)
ethaderu 3:78f223d34f36 13135 /* UART5 */
ethaderu 3:78f223d34f36 13136 #define UART5_BDH UART_BDH_REG(UART5)
ethaderu 3:78f223d34f36 13137 #define UART5_BDL UART_BDL_REG(UART5)
ethaderu 3:78f223d34f36 13138 #define UART5_C1 UART_C1_REG(UART5)
ethaderu 3:78f223d34f36 13139 #define UART5_C2 UART_C2_REG(UART5)
ethaderu 3:78f223d34f36 13140 #define UART5_S1 UART_S1_REG(UART5)
ethaderu 3:78f223d34f36 13141 #define UART5_S2 UART_S2_REG(UART5)
ethaderu 3:78f223d34f36 13142 #define UART5_C3 UART_C3_REG(UART5)
ethaderu 3:78f223d34f36 13143 #define UART5_D UART_D_REG(UART5)
ethaderu 3:78f223d34f36 13144 #define UART5_MA1 UART_MA1_REG(UART5)
ethaderu 3:78f223d34f36 13145 #define UART5_MA2 UART_MA2_REG(UART5)
ethaderu 3:78f223d34f36 13146 #define UART5_C4 UART_C4_REG(UART5)
ethaderu 3:78f223d34f36 13147 #define UART5_C5 UART_C5_REG(UART5)
ethaderu 3:78f223d34f36 13148 #define UART5_ED UART_ED_REG(UART5)
ethaderu 3:78f223d34f36 13149 #define UART5_MODEM UART_MODEM_REG(UART5)
ethaderu 3:78f223d34f36 13150 #define UART5_IR UART_IR_REG(UART5)
ethaderu 3:78f223d34f36 13151 #define UART5_PFIFO UART_PFIFO_REG(UART5)
ethaderu 3:78f223d34f36 13152 #define UART5_CFIFO UART_CFIFO_REG(UART5)
ethaderu 3:78f223d34f36 13153 #define UART5_SFIFO UART_SFIFO_REG(UART5)
ethaderu 3:78f223d34f36 13154 #define UART5_TWFIFO UART_TWFIFO_REG(UART5)
ethaderu 3:78f223d34f36 13155 #define UART5_TCFIFO UART_TCFIFO_REG(UART5)
ethaderu 3:78f223d34f36 13156 #define UART5_RWFIFO UART_RWFIFO_REG(UART5)
ethaderu 3:78f223d34f36 13157 #define UART5_RCFIFO UART_RCFIFO_REG(UART5)
ethaderu 3:78f223d34f36 13158
ethaderu 3:78f223d34f36 13159 /*!
ethaderu 3:78f223d34f36 13160 * @}
ethaderu 3:78f223d34f36 13161 */ /* end of group UART_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 13162
ethaderu 3:78f223d34f36 13163
ethaderu 3:78f223d34f36 13164 /*!
ethaderu 3:78f223d34f36 13165 * @}
ethaderu 3:78f223d34f36 13166 */ /* end of group UART_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 13167
ethaderu 3:78f223d34f36 13168
ethaderu 3:78f223d34f36 13169 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 13170 -- USB Peripheral Access Layer
ethaderu 3:78f223d34f36 13171 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 13172
ethaderu 3:78f223d34f36 13173 /*!
ethaderu 3:78f223d34f36 13174 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
ethaderu 3:78f223d34f36 13175 * @{
ethaderu 3:78f223d34f36 13176 */
ethaderu 3:78f223d34f36 13177
ethaderu 3:78f223d34f36 13178 /** USB - Register Layout Typedef */
ethaderu 3:78f223d34f36 13179 typedef struct {
ethaderu 3:78f223d34f36 13180 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
ethaderu 3:78f223d34f36 13181 uint8_t RESERVED_0[3];
ethaderu 3:78f223d34f36 13182 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
ethaderu 3:78f223d34f36 13183 uint8_t RESERVED_1[3];
ethaderu 3:78f223d34f36 13184 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
ethaderu 3:78f223d34f36 13185 uint8_t RESERVED_2[3];
ethaderu 3:78f223d34f36 13186 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
ethaderu 3:78f223d34f36 13187 uint8_t RESERVED_3[3];
ethaderu 3:78f223d34f36 13188 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
ethaderu 3:78f223d34f36 13189 uint8_t RESERVED_4[3];
ethaderu 3:78f223d34f36 13190 __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
ethaderu 3:78f223d34f36 13191 uint8_t RESERVED_5[3];
ethaderu 3:78f223d34f36 13192 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
ethaderu 3:78f223d34f36 13193 uint8_t RESERVED_6[3];
ethaderu 3:78f223d34f36 13194 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
ethaderu 3:78f223d34f36 13195 uint8_t RESERVED_7[99];
ethaderu 3:78f223d34f36 13196 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
ethaderu 3:78f223d34f36 13197 uint8_t RESERVED_8[3];
ethaderu 3:78f223d34f36 13198 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
ethaderu 3:78f223d34f36 13199 uint8_t RESERVED_9[3];
ethaderu 3:78f223d34f36 13200 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
ethaderu 3:78f223d34f36 13201 uint8_t RESERVED_10[3];
ethaderu 3:78f223d34f36 13202 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
ethaderu 3:78f223d34f36 13203 uint8_t RESERVED_11[3];
ethaderu 3:78f223d34f36 13204 __I uint8_t STAT; /**< Status register, offset: 0x90 */
ethaderu 3:78f223d34f36 13205 uint8_t RESERVED_12[3];
ethaderu 3:78f223d34f36 13206 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
ethaderu 3:78f223d34f36 13207 uint8_t RESERVED_13[3];
ethaderu 3:78f223d34f36 13208 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
ethaderu 3:78f223d34f36 13209 uint8_t RESERVED_14[3];
ethaderu 3:78f223d34f36 13210 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
ethaderu 3:78f223d34f36 13211 uint8_t RESERVED_15[3];
ethaderu 3:78f223d34f36 13212 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
ethaderu 3:78f223d34f36 13213 uint8_t RESERVED_16[3];
ethaderu 3:78f223d34f36 13214 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
ethaderu 3:78f223d34f36 13215 uint8_t RESERVED_17[3];
ethaderu 3:78f223d34f36 13216 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
ethaderu 3:78f223d34f36 13217 uint8_t RESERVED_18[3];
ethaderu 3:78f223d34f36 13218 __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
ethaderu 3:78f223d34f36 13219 uint8_t RESERVED_19[3];
ethaderu 3:78f223d34f36 13220 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
ethaderu 3:78f223d34f36 13221 uint8_t RESERVED_20[3];
ethaderu 3:78f223d34f36 13222 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
ethaderu 3:78f223d34f36 13223 uint8_t RESERVED_21[11];
ethaderu 3:78f223d34f36 13224 struct { /* offset: 0xC0, array step: 0x4 */
ethaderu 3:78f223d34f36 13225 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
ethaderu 3:78f223d34f36 13226 uint8_t RESERVED_0[3];
ethaderu 3:78f223d34f36 13227 } ENDPOINT[16];
ethaderu 3:78f223d34f36 13228 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
ethaderu 3:78f223d34f36 13229 uint8_t RESERVED_22[3];
ethaderu 3:78f223d34f36 13230 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
ethaderu 3:78f223d34f36 13231 uint8_t RESERVED_23[3];
ethaderu 3:78f223d34f36 13232 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
ethaderu 3:78f223d34f36 13233 uint8_t RESERVED_24[3];
ethaderu 3:78f223d34f36 13234 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
ethaderu 3:78f223d34f36 13235 uint8_t RESERVED_25[7];
ethaderu 3:78f223d34f36 13236 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
ethaderu 3:78f223d34f36 13237 uint8_t RESERVED_26[43];
ethaderu 3:78f223d34f36 13238 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
ethaderu 3:78f223d34f36 13239 uint8_t RESERVED_27[3];
ethaderu 3:78f223d34f36 13240 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
ethaderu 3:78f223d34f36 13241 uint8_t RESERVED_28[23];
ethaderu 3:78f223d34f36 13242 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
ethaderu 3:78f223d34f36 13243 } USB_Type, *USB_MemMapPtr;
ethaderu 3:78f223d34f36 13244
ethaderu 3:78f223d34f36 13245 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 13246 -- USB - Register accessor macros
ethaderu 3:78f223d34f36 13247 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 13248
ethaderu 3:78f223d34f36 13249 /*!
ethaderu 3:78f223d34f36 13250 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
ethaderu 3:78f223d34f36 13251 * @{
ethaderu 3:78f223d34f36 13252 */
ethaderu 3:78f223d34f36 13253
ethaderu 3:78f223d34f36 13254
ethaderu 3:78f223d34f36 13255 /* USB - Register accessors */
ethaderu 3:78f223d34f36 13256 #define USB_PERID_REG(base) ((base)->PERID)
ethaderu 3:78f223d34f36 13257 #define USB_IDCOMP_REG(base) ((base)->IDCOMP)
ethaderu 3:78f223d34f36 13258 #define USB_REV_REG(base) ((base)->REV)
ethaderu 3:78f223d34f36 13259 #define USB_ADDINFO_REG(base) ((base)->ADDINFO)
ethaderu 3:78f223d34f36 13260 #define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
ethaderu 3:78f223d34f36 13261 #define USB_OTGICR_REG(base) ((base)->OTGICR)
ethaderu 3:78f223d34f36 13262 #define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
ethaderu 3:78f223d34f36 13263 #define USB_OTGCTL_REG(base) ((base)->OTGCTL)
ethaderu 3:78f223d34f36 13264 #define USB_ISTAT_REG(base) ((base)->ISTAT)
ethaderu 3:78f223d34f36 13265 #define USB_INTEN_REG(base) ((base)->INTEN)
ethaderu 3:78f223d34f36 13266 #define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
ethaderu 3:78f223d34f36 13267 #define USB_ERREN_REG(base) ((base)->ERREN)
ethaderu 3:78f223d34f36 13268 #define USB_STAT_REG(base) ((base)->STAT)
ethaderu 3:78f223d34f36 13269 #define USB_CTL_REG(base) ((base)->CTL)
ethaderu 3:78f223d34f36 13270 #define USB_ADDR_REG(base) ((base)->ADDR)
ethaderu 3:78f223d34f36 13271 #define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
ethaderu 3:78f223d34f36 13272 #define USB_FRMNUML_REG(base) ((base)->FRMNUML)
ethaderu 3:78f223d34f36 13273 #define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
ethaderu 3:78f223d34f36 13274 #define USB_TOKEN_REG(base) ((base)->TOKEN)
ethaderu 3:78f223d34f36 13275 #define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
ethaderu 3:78f223d34f36 13276 #define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
ethaderu 3:78f223d34f36 13277 #define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
ethaderu 3:78f223d34f36 13278 #define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
ethaderu 3:78f223d34f36 13279 #define USB_USBCTRL_REG(base) ((base)->USBCTRL)
ethaderu 3:78f223d34f36 13280 #define USB_OBSERVE_REG(base) ((base)->OBSERVE)
ethaderu 3:78f223d34f36 13281 #define USB_CONTROL_REG(base) ((base)->CONTROL)
ethaderu 3:78f223d34f36 13282 #define USB_USBTRC0_REG(base) ((base)->USBTRC0)
ethaderu 3:78f223d34f36 13283 #define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
ethaderu 3:78f223d34f36 13284 #define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
ethaderu 3:78f223d34f36 13285 #define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
ethaderu 3:78f223d34f36 13286 #define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
ethaderu 3:78f223d34f36 13287
ethaderu 3:78f223d34f36 13288 /*!
ethaderu 3:78f223d34f36 13289 * @}
ethaderu 3:78f223d34f36 13290 */ /* end of group USB_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 13291
ethaderu 3:78f223d34f36 13292
ethaderu 3:78f223d34f36 13293 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 13294 -- USB Register Masks
ethaderu 3:78f223d34f36 13295 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 13296
ethaderu 3:78f223d34f36 13297 /*!
ethaderu 3:78f223d34f36 13298 * @addtogroup USB_Register_Masks USB Register Masks
ethaderu 3:78f223d34f36 13299 * @{
ethaderu 3:78f223d34f36 13300 */
ethaderu 3:78f223d34f36 13301
ethaderu 3:78f223d34f36 13302 /* PERID Bit Fields */
ethaderu 3:78f223d34f36 13303 #define USB_PERID_ID_MASK 0x3Fu
ethaderu 3:78f223d34f36 13304 #define USB_PERID_ID_SHIFT 0
ethaderu 3:78f223d34f36 13305 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
ethaderu 3:78f223d34f36 13306 /* IDCOMP Bit Fields */
ethaderu 3:78f223d34f36 13307 #define USB_IDCOMP_NID_MASK 0x3Fu
ethaderu 3:78f223d34f36 13308 #define USB_IDCOMP_NID_SHIFT 0
ethaderu 3:78f223d34f36 13309 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
ethaderu 3:78f223d34f36 13310 /* REV Bit Fields */
ethaderu 3:78f223d34f36 13311 #define USB_REV_REV_MASK 0xFFu
ethaderu 3:78f223d34f36 13312 #define USB_REV_REV_SHIFT 0
ethaderu 3:78f223d34f36 13313 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
ethaderu 3:78f223d34f36 13314 /* ADDINFO Bit Fields */
ethaderu 3:78f223d34f36 13315 #define USB_ADDINFO_IEHOST_MASK 0x1u
ethaderu 3:78f223d34f36 13316 #define USB_ADDINFO_IEHOST_SHIFT 0
ethaderu 3:78f223d34f36 13317 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
ethaderu 3:78f223d34f36 13318 #define USB_ADDINFO_IRQNUM_SHIFT 3
ethaderu 3:78f223d34f36 13319 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
ethaderu 3:78f223d34f36 13320 /* OTGISTAT Bit Fields */
ethaderu 3:78f223d34f36 13321 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
ethaderu 3:78f223d34f36 13322 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
ethaderu 3:78f223d34f36 13323 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
ethaderu 3:78f223d34f36 13324 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
ethaderu 3:78f223d34f36 13325 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
ethaderu 3:78f223d34f36 13326 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
ethaderu 3:78f223d34f36 13327 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
ethaderu 3:78f223d34f36 13328 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
ethaderu 3:78f223d34f36 13329 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
ethaderu 3:78f223d34f36 13330 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
ethaderu 3:78f223d34f36 13331 #define USB_OTGISTAT_IDCHG_MASK 0x80u
ethaderu 3:78f223d34f36 13332 #define USB_OTGISTAT_IDCHG_SHIFT 7
ethaderu 3:78f223d34f36 13333 /* OTGICR Bit Fields */
ethaderu 3:78f223d34f36 13334 #define USB_OTGICR_AVBUSEN_MASK 0x1u
ethaderu 3:78f223d34f36 13335 #define USB_OTGICR_AVBUSEN_SHIFT 0
ethaderu 3:78f223d34f36 13336 #define USB_OTGICR_BSESSEN_MASK 0x4u
ethaderu 3:78f223d34f36 13337 #define USB_OTGICR_BSESSEN_SHIFT 2
ethaderu 3:78f223d34f36 13338 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
ethaderu 3:78f223d34f36 13339 #define USB_OTGICR_SESSVLDEN_SHIFT 3
ethaderu 3:78f223d34f36 13340 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
ethaderu 3:78f223d34f36 13341 #define USB_OTGICR_LINESTATEEN_SHIFT 5
ethaderu 3:78f223d34f36 13342 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
ethaderu 3:78f223d34f36 13343 #define USB_OTGICR_ONEMSECEN_SHIFT 6
ethaderu 3:78f223d34f36 13344 #define USB_OTGICR_IDEN_MASK 0x80u
ethaderu 3:78f223d34f36 13345 #define USB_OTGICR_IDEN_SHIFT 7
ethaderu 3:78f223d34f36 13346 /* OTGSTAT Bit Fields */
ethaderu 3:78f223d34f36 13347 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
ethaderu 3:78f223d34f36 13348 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
ethaderu 3:78f223d34f36 13349 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
ethaderu 3:78f223d34f36 13350 #define USB_OTGSTAT_BSESSEND_SHIFT 2
ethaderu 3:78f223d34f36 13351 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
ethaderu 3:78f223d34f36 13352 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
ethaderu 3:78f223d34f36 13353 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
ethaderu 3:78f223d34f36 13354 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
ethaderu 3:78f223d34f36 13355 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
ethaderu 3:78f223d34f36 13356 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
ethaderu 3:78f223d34f36 13357 #define USB_OTGSTAT_ID_MASK 0x80u
ethaderu 3:78f223d34f36 13358 #define USB_OTGSTAT_ID_SHIFT 7
ethaderu 3:78f223d34f36 13359 /* OTGCTL Bit Fields */
ethaderu 3:78f223d34f36 13360 #define USB_OTGCTL_OTGEN_MASK 0x4u
ethaderu 3:78f223d34f36 13361 #define USB_OTGCTL_OTGEN_SHIFT 2
ethaderu 3:78f223d34f36 13362 #define USB_OTGCTL_DMLOW_MASK 0x10u
ethaderu 3:78f223d34f36 13363 #define USB_OTGCTL_DMLOW_SHIFT 4
ethaderu 3:78f223d34f36 13364 #define USB_OTGCTL_DPLOW_MASK 0x20u
ethaderu 3:78f223d34f36 13365 #define USB_OTGCTL_DPLOW_SHIFT 5
ethaderu 3:78f223d34f36 13366 #define USB_OTGCTL_DPHIGH_MASK 0x80u
ethaderu 3:78f223d34f36 13367 #define USB_OTGCTL_DPHIGH_SHIFT 7
ethaderu 3:78f223d34f36 13368 /* ISTAT Bit Fields */
ethaderu 3:78f223d34f36 13369 #define USB_ISTAT_USBRST_MASK 0x1u
ethaderu 3:78f223d34f36 13370 #define USB_ISTAT_USBRST_SHIFT 0
ethaderu 3:78f223d34f36 13371 #define USB_ISTAT_ERROR_MASK 0x2u
ethaderu 3:78f223d34f36 13372 #define USB_ISTAT_ERROR_SHIFT 1
ethaderu 3:78f223d34f36 13373 #define USB_ISTAT_SOFTOK_MASK 0x4u
ethaderu 3:78f223d34f36 13374 #define USB_ISTAT_SOFTOK_SHIFT 2
ethaderu 3:78f223d34f36 13375 #define USB_ISTAT_TOKDNE_MASK 0x8u
ethaderu 3:78f223d34f36 13376 #define USB_ISTAT_TOKDNE_SHIFT 3
ethaderu 3:78f223d34f36 13377 #define USB_ISTAT_SLEEP_MASK 0x10u
ethaderu 3:78f223d34f36 13378 #define USB_ISTAT_SLEEP_SHIFT 4
ethaderu 3:78f223d34f36 13379 #define USB_ISTAT_RESUME_MASK 0x20u
ethaderu 3:78f223d34f36 13380 #define USB_ISTAT_RESUME_SHIFT 5
ethaderu 3:78f223d34f36 13381 #define USB_ISTAT_ATTACH_MASK 0x40u
ethaderu 3:78f223d34f36 13382 #define USB_ISTAT_ATTACH_SHIFT 6
ethaderu 3:78f223d34f36 13383 #define USB_ISTAT_STALL_MASK 0x80u
ethaderu 3:78f223d34f36 13384 #define USB_ISTAT_STALL_SHIFT 7
ethaderu 3:78f223d34f36 13385 /* INTEN Bit Fields */
ethaderu 3:78f223d34f36 13386 #define USB_INTEN_USBRSTEN_MASK 0x1u
ethaderu 3:78f223d34f36 13387 #define USB_INTEN_USBRSTEN_SHIFT 0
ethaderu 3:78f223d34f36 13388 #define USB_INTEN_ERROREN_MASK 0x2u
ethaderu 3:78f223d34f36 13389 #define USB_INTEN_ERROREN_SHIFT 1
ethaderu 3:78f223d34f36 13390 #define USB_INTEN_SOFTOKEN_MASK 0x4u
ethaderu 3:78f223d34f36 13391 #define USB_INTEN_SOFTOKEN_SHIFT 2
ethaderu 3:78f223d34f36 13392 #define USB_INTEN_TOKDNEEN_MASK 0x8u
ethaderu 3:78f223d34f36 13393 #define USB_INTEN_TOKDNEEN_SHIFT 3
ethaderu 3:78f223d34f36 13394 #define USB_INTEN_SLEEPEN_MASK 0x10u
ethaderu 3:78f223d34f36 13395 #define USB_INTEN_SLEEPEN_SHIFT 4
ethaderu 3:78f223d34f36 13396 #define USB_INTEN_RESUMEEN_MASK 0x20u
ethaderu 3:78f223d34f36 13397 #define USB_INTEN_RESUMEEN_SHIFT 5
ethaderu 3:78f223d34f36 13398 #define USB_INTEN_ATTACHEN_MASK 0x40u
ethaderu 3:78f223d34f36 13399 #define USB_INTEN_ATTACHEN_SHIFT 6
ethaderu 3:78f223d34f36 13400 #define USB_INTEN_STALLEN_MASK 0x80u
ethaderu 3:78f223d34f36 13401 #define USB_INTEN_STALLEN_SHIFT 7
ethaderu 3:78f223d34f36 13402 /* ERRSTAT Bit Fields */
ethaderu 3:78f223d34f36 13403 #define USB_ERRSTAT_PIDERR_MASK 0x1u
ethaderu 3:78f223d34f36 13404 #define USB_ERRSTAT_PIDERR_SHIFT 0
ethaderu 3:78f223d34f36 13405 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
ethaderu 3:78f223d34f36 13406 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
ethaderu 3:78f223d34f36 13407 #define USB_ERRSTAT_CRC16_MASK 0x4u
ethaderu 3:78f223d34f36 13408 #define USB_ERRSTAT_CRC16_SHIFT 2
ethaderu 3:78f223d34f36 13409 #define USB_ERRSTAT_DFN8_MASK 0x8u
ethaderu 3:78f223d34f36 13410 #define USB_ERRSTAT_DFN8_SHIFT 3
ethaderu 3:78f223d34f36 13411 #define USB_ERRSTAT_BTOERR_MASK 0x10u
ethaderu 3:78f223d34f36 13412 #define USB_ERRSTAT_BTOERR_SHIFT 4
ethaderu 3:78f223d34f36 13413 #define USB_ERRSTAT_DMAERR_MASK 0x20u
ethaderu 3:78f223d34f36 13414 #define USB_ERRSTAT_DMAERR_SHIFT 5
ethaderu 3:78f223d34f36 13415 #define USB_ERRSTAT_BTSERR_MASK 0x80u
ethaderu 3:78f223d34f36 13416 #define USB_ERRSTAT_BTSERR_SHIFT 7
ethaderu 3:78f223d34f36 13417 /* ERREN Bit Fields */
ethaderu 3:78f223d34f36 13418 #define USB_ERREN_PIDERREN_MASK 0x1u
ethaderu 3:78f223d34f36 13419 #define USB_ERREN_PIDERREN_SHIFT 0
ethaderu 3:78f223d34f36 13420 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
ethaderu 3:78f223d34f36 13421 #define USB_ERREN_CRC5EOFEN_SHIFT 1
ethaderu 3:78f223d34f36 13422 #define USB_ERREN_CRC16EN_MASK 0x4u
ethaderu 3:78f223d34f36 13423 #define USB_ERREN_CRC16EN_SHIFT 2
ethaderu 3:78f223d34f36 13424 #define USB_ERREN_DFN8EN_MASK 0x8u
ethaderu 3:78f223d34f36 13425 #define USB_ERREN_DFN8EN_SHIFT 3
ethaderu 3:78f223d34f36 13426 #define USB_ERREN_BTOERREN_MASK 0x10u
ethaderu 3:78f223d34f36 13427 #define USB_ERREN_BTOERREN_SHIFT 4
ethaderu 3:78f223d34f36 13428 #define USB_ERREN_DMAERREN_MASK 0x20u
ethaderu 3:78f223d34f36 13429 #define USB_ERREN_DMAERREN_SHIFT 5
ethaderu 3:78f223d34f36 13430 #define USB_ERREN_BTSERREN_MASK 0x80u
ethaderu 3:78f223d34f36 13431 #define USB_ERREN_BTSERREN_SHIFT 7
ethaderu 3:78f223d34f36 13432 /* STAT Bit Fields */
ethaderu 3:78f223d34f36 13433 #define USB_STAT_ODD_MASK 0x4u
ethaderu 3:78f223d34f36 13434 #define USB_STAT_ODD_SHIFT 2
ethaderu 3:78f223d34f36 13435 #define USB_STAT_TX_MASK 0x8u
ethaderu 3:78f223d34f36 13436 #define USB_STAT_TX_SHIFT 3
ethaderu 3:78f223d34f36 13437 #define USB_STAT_ENDP_MASK 0xF0u
ethaderu 3:78f223d34f36 13438 #define USB_STAT_ENDP_SHIFT 4
ethaderu 3:78f223d34f36 13439 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
ethaderu 3:78f223d34f36 13440 /* CTL Bit Fields */
ethaderu 3:78f223d34f36 13441 #define USB_CTL_USBENSOFEN_MASK 0x1u
ethaderu 3:78f223d34f36 13442 #define USB_CTL_USBENSOFEN_SHIFT 0
ethaderu 3:78f223d34f36 13443 #define USB_CTL_ODDRST_MASK 0x2u
ethaderu 3:78f223d34f36 13444 #define USB_CTL_ODDRST_SHIFT 1
ethaderu 3:78f223d34f36 13445 #define USB_CTL_RESUME_MASK 0x4u
ethaderu 3:78f223d34f36 13446 #define USB_CTL_RESUME_SHIFT 2
ethaderu 3:78f223d34f36 13447 #define USB_CTL_HOSTMODEEN_MASK 0x8u
ethaderu 3:78f223d34f36 13448 #define USB_CTL_HOSTMODEEN_SHIFT 3
ethaderu 3:78f223d34f36 13449 #define USB_CTL_RESET_MASK 0x10u
ethaderu 3:78f223d34f36 13450 #define USB_CTL_RESET_SHIFT 4
ethaderu 3:78f223d34f36 13451 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
ethaderu 3:78f223d34f36 13452 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
ethaderu 3:78f223d34f36 13453 #define USB_CTL_SE0_MASK 0x40u
ethaderu 3:78f223d34f36 13454 #define USB_CTL_SE0_SHIFT 6
ethaderu 3:78f223d34f36 13455 #define USB_CTL_JSTATE_MASK 0x80u
ethaderu 3:78f223d34f36 13456 #define USB_CTL_JSTATE_SHIFT 7
ethaderu 3:78f223d34f36 13457 /* ADDR Bit Fields */
ethaderu 3:78f223d34f36 13458 #define USB_ADDR_ADDR_MASK 0x7Fu
ethaderu 3:78f223d34f36 13459 #define USB_ADDR_ADDR_SHIFT 0
ethaderu 3:78f223d34f36 13460 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
ethaderu 3:78f223d34f36 13461 #define USB_ADDR_LSEN_MASK 0x80u
ethaderu 3:78f223d34f36 13462 #define USB_ADDR_LSEN_SHIFT 7
ethaderu 3:78f223d34f36 13463 /* BDTPAGE1 Bit Fields */
ethaderu 3:78f223d34f36 13464 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
ethaderu 3:78f223d34f36 13465 #define USB_BDTPAGE1_BDTBA_SHIFT 1
ethaderu 3:78f223d34f36 13466 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
ethaderu 3:78f223d34f36 13467 /* FRMNUML Bit Fields */
ethaderu 3:78f223d34f36 13468 #define USB_FRMNUML_FRM_MASK 0xFFu
ethaderu 3:78f223d34f36 13469 #define USB_FRMNUML_FRM_SHIFT 0
ethaderu 3:78f223d34f36 13470 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
ethaderu 3:78f223d34f36 13471 /* FRMNUMH Bit Fields */
ethaderu 3:78f223d34f36 13472 #define USB_FRMNUMH_FRM_MASK 0x7u
ethaderu 3:78f223d34f36 13473 #define USB_FRMNUMH_FRM_SHIFT 0
ethaderu 3:78f223d34f36 13474 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
ethaderu 3:78f223d34f36 13475 /* TOKEN Bit Fields */
ethaderu 3:78f223d34f36 13476 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
ethaderu 3:78f223d34f36 13477 #define USB_TOKEN_TOKENENDPT_SHIFT 0
ethaderu 3:78f223d34f36 13478 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
ethaderu 3:78f223d34f36 13479 #define USB_TOKEN_TOKENPID_MASK 0xF0u
ethaderu 3:78f223d34f36 13480 #define USB_TOKEN_TOKENPID_SHIFT 4
ethaderu 3:78f223d34f36 13481 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
ethaderu 3:78f223d34f36 13482 /* SOFTHLD Bit Fields */
ethaderu 3:78f223d34f36 13483 #define USB_SOFTHLD_CNT_MASK 0xFFu
ethaderu 3:78f223d34f36 13484 #define USB_SOFTHLD_CNT_SHIFT 0
ethaderu 3:78f223d34f36 13485 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
ethaderu 3:78f223d34f36 13486 /* BDTPAGE2 Bit Fields */
ethaderu 3:78f223d34f36 13487 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
ethaderu 3:78f223d34f36 13488 #define USB_BDTPAGE2_BDTBA_SHIFT 0
ethaderu 3:78f223d34f36 13489 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
ethaderu 3:78f223d34f36 13490 /* BDTPAGE3 Bit Fields */
ethaderu 3:78f223d34f36 13491 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
ethaderu 3:78f223d34f36 13492 #define USB_BDTPAGE3_BDTBA_SHIFT 0
ethaderu 3:78f223d34f36 13493 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
ethaderu 3:78f223d34f36 13494 /* ENDPT Bit Fields */
ethaderu 3:78f223d34f36 13495 #define USB_ENDPT_EPHSHK_MASK 0x1u
ethaderu 3:78f223d34f36 13496 #define USB_ENDPT_EPHSHK_SHIFT 0
ethaderu 3:78f223d34f36 13497 #define USB_ENDPT_EPSTALL_MASK 0x2u
ethaderu 3:78f223d34f36 13498 #define USB_ENDPT_EPSTALL_SHIFT 1
ethaderu 3:78f223d34f36 13499 #define USB_ENDPT_EPTXEN_MASK 0x4u
ethaderu 3:78f223d34f36 13500 #define USB_ENDPT_EPTXEN_SHIFT 2
ethaderu 3:78f223d34f36 13501 #define USB_ENDPT_EPRXEN_MASK 0x8u
ethaderu 3:78f223d34f36 13502 #define USB_ENDPT_EPRXEN_SHIFT 3
ethaderu 3:78f223d34f36 13503 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
ethaderu 3:78f223d34f36 13504 #define USB_ENDPT_EPCTLDIS_SHIFT 4
ethaderu 3:78f223d34f36 13505 #define USB_ENDPT_RETRYDIS_MASK 0x40u
ethaderu 3:78f223d34f36 13506 #define USB_ENDPT_RETRYDIS_SHIFT 6
ethaderu 3:78f223d34f36 13507 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
ethaderu 3:78f223d34f36 13508 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
ethaderu 3:78f223d34f36 13509 /* USBCTRL Bit Fields */
ethaderu 3:78f223d34f36 13510 #define USB_USBCTRL_PDE_MASK 0x40u
ethaderu 3:78f223d34f36 13511 #define USB_USBCTRL_PDE_SHIFT 6
ethaderu 3:78f223d34f36 13512 #define USB_USBCTRL_SUSP_MASK 0x80u
ethaderu 3:78f223d34f36 13513 #define USB_USBCTRL_SUSP_SHIFT 7
ethaderu 3:78f223d34f36 13514 /* OBSERVE Bit Fields */
ethaderu 3:78f223d34f36 13515 #define USB_OBSERVE_DMPD_MASK 0x10u
ethaderu 3:78f223d34f36 13516 #define USB_OBSERVE_DMPD_SHIFT 4
ethaderu 3:78f223d34f36 13517 #define USB_OBSERVE_DPPD_MASK 0x40u
ethaderu 3:78f223d34f36 13518 #define USB_OBSERVE_DPPD_SHIFT 6
ethaderu 3:78f223d34f36 13519 #define USB_OBSERVE_DPPU_MASK 0x80u
ethaderu 3:78f223d34f36 13520 #define USB_OBSERVE_DPPU_SHIFT 7
ethaderu 3:78f223d34f36 13521 /* CONTROL Bit Fields */
ethaderu 3:78f223d34f36 13522 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
ethaderu 3:78f223d34f36 13523 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
ethaderu 3:78f223d34f36 13524 /* USBTRC0 Bit Fields */
ethaderu 3:78f223d34f36 13525 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
ethaderu 3:78f223d34f36 13526 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
ethaderu 3:78f223d34f36 13527 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
ethaderu 3:78f223d34f36 13528 #define USB_USBTRC0_SYNC_DET_SHIFT 1
ethaderu 3:78f223d34f36 13529 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
ethaderu 3:78f223d34f36 13530 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
ethaderu 3:78f223d34f36 13531 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
ethaderu 3:78f223d34f36 13532 #define USB_USBTRC0_USBRESMEN_SHIFT 5
ethaderu 3:78f223d34f36 13533 #define USB_USBTRC0_USBRESET_MASK 0x80u
ethaderu 3:78f223d34f36 13534 #define USB_USBTRC0_USBRESET_SHIFT 7
ethaderu 3:78f223d34f36 13535 /* USBFRMADJUST Bit Fields */
ethaderu 3:78f223d34f36 13536 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
ethaderu 3:78f223d34f36 13537 #define USB_USBFRMADJUST_ADJ_SHIFT 0
ethaderu 3:78f223d34f36 13538 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
ethaderu 3:78f223d34f36 13539 /* CLK_RECOVER_CTRL Bit Fields */
ethaderu 3:78f223d34f36 13540 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
ethaderu 3:78f223d34f36 13541 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
ethaderu 3:78f223d34f36 13542 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
ethaderu 3:78f223d34f36 13543 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
ethaderu 3:78f223d34f36 13544 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
ethaderu 3:78f223d34f36 13545 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
ethaderu 3:78f223d34f36 13546 /* CLK_RECOVER_IRC_EN Bit Fields */
ethaderu 3:78f223d34f36 13547 #define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK 0x1u
ethaderu 3:78f223d34f36 13548 #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT 0
ethaderu 3:78f223d34f36 13549 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
ethaderu 3:78f223d34f36 13550 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
ethaderu 3:78f223d34f36 13551 /* CLK_RECOVER_INT_STATUS Bit Fields */
ethaderu 3:78f223d34f36 13552 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
ethaderu 3:78f223d34f36 13553 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
ethaderu 3:78f223d34f36 13554
ethaderu 3:78f223d34f36 13555 /*!
ethaderu 3:78f223d34f36 13556 * @}
ethaderu 3:78f223d34f36 13557 */ /* end of group USB_Register_Masks */
ethaderu 3:78f223d34f36 13558
ethaderu 3:78f223d34f36 13559
ethaderu 3:78f223d34f36 13560 /* USB - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 13561 /** Peripheral USB0 base address */
ethaderu 3:78f223d34f36 13562 #define USB0_BASE (0x40072000u)
ethaderu 3:78f223d34f36 13563 /** Peripheral USB0 base pointer */
ethaderu 3:78f223d34f36 13564 #define USB0 ((USB_Type *)USB0_BASE)
ethaderu 3:78f223d34f36 13565 #define USB0_BASE_PTR (USB0)
ethaderu 3:78f223d34f36 13566 /** Array initializer of USB peripheral base addresses */
ethaderu 3:78f223d34f36 13567 #define USB_BASE_ADDRS { USB0_BASE }
ethaderu 3:78f223d34f36 13568 /** Array initializer of USB peripheral base pointers */
ethaderu 3:78f223d34f36 13569 #define USB_BASE_PTRS { USB0 }
ethaderu 3:78f223d34f36 13570 /** Interrupt vectors for the USB peripheral type */
ethaderu 3:78f223d34f36 13571 #define USB_IRQS { USB0_IRQn }
ethaderu 3:78f223d34f36 13572
ethaderu 3:78f223d34f36 13573 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 13574 -- USB - Register accessor macros
ethaderu 3:78f223d34f36 13575 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 13576
ethaderu 3:78f223d34f36 13577 /*!
ethaderu 3:78f223d34f36 13578 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
ethaderu 3:78f223d34f36 13579 * @{
ethaderu 3:78f223d34f36 13580 */
ethaderu 3:78f223d34f36 13581
ethaderu 3:78f223d34f36 13582
ethaderu 3:78f223d34f36 13583 /* USB - Register instance definitions */
ethaderu 3:78f223d34f36 13584 /* USB0 */
ethaderu 3:78f223d34f36 13585 #define USB0_PERID USB_PERID_REG(USB0)
ethaderu 3:78f223d34f36 13586 #define USB0_IDCOMP USB_IDCOMP_REG(USB0)
ethaderu 3:78f223d34f36 13587 #define USB0_REV USB_REV_REG(USB0)
ethaderu 3:78f223d34f36 13588 #define USB0_ADDINFO USB_ADDINFO_REG(USB0)
ethaderu 3:78f223d34f36 13589 #define USB0_OTGISTAT USB_OTGISTAT_REG(USB0)
ethaderu 3:78f223d34f36 13590 #define USB0_OTGICR USB_OTGICR_REG(USB0)
ethaderu 3:78f223d34f36 13591 #define USB0_OTGSTAT USB_OTGSTAT_REG(USB0)
ethaderu 3:78f223d34f36 13592 #define USB0_OTGCTL USB_OTGCTL_REG(USB0)
ethaderu 3:78f223d34f36 13593 #define USB0_ISTAT USB_ISTAT_REG(USB0)
ethaderu 3:78f223d34f36 13594 #define USB0_INTEN USB_INTEN_REG(USB0)
ethaderu 3:78f223d34f36 13595 #define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
ethaderu 3:78f223d34f36 13596 #define USB0_ERREN USB_ERREN_REG(USB0)
ethaderu 3:78f223d34f36 13597 #define USB0_STAT USB_STAT_REG(USB0)
ethaderu 3:78f223d34f36 13598 #define USB0_CTL USB_CTL_REG(USB0)
ethaderu 3:78f223d34f36 13599 #define USB0_ADDR USB_ADDR_REG(USB0)
ethaderu 3:78f223d34f36 13600 #define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
ethaderu 3:78f223d34f36 13601 #define USB0_FRMNUML USB_FRMNUML_REG(USB0)
ethaderu 3:78f223d34f36 13602 #define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
ethaderu 3:78f223d34f36 13603 #define USB0_TOKEN USB_TOKEN_REG(USB0)
ethaderu 3:78f223d34f36 13604 #define USB0_SOFTHLD USB_SOFTHLD_REG(USB0)
ethaderu 3:78f223d34f36 13605 #define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
ethaderu 3:78f223d34f36 13606 #define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
ethaderu 3:78f223d34f36 13607 #define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
ethaderu 3:78f223d34f36 13608 #define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
ethaderu 3:78f223d34f36 13609 #define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
ethaderu 3:78f223d34f36 13610 #define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
ethaderu 3:78f223d34f36 13611 #define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
ethaderu 3:78f223d34f36 13612 #define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
ethaderu 3:78f223d34f36 13613 #define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
ethaderu 3:78f223d34f36 13614 #define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
ethaderu 3:78f223d34f36 13615 #define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
ethaderu 3:78f223d34f36 13616 #define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
ethaderu 3:78f223d34f36 13617 #define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
ethaderu 3:78f223d34f36 13618 #define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
ethaderu 3:78f223d34f36 13619 #define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
ethaderu 3:78f223d34f36 13620 #define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
ethaderu 3:78f223d34f36 13621 #define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
ethaderu 3:78f223d34f36 13622 #define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
ethaderu 3:78f223d34f36 13623 #define USB0_USBCTRL USB_USBCTRL_REG(USB0)
ethaderu 3:78f223d34f36 13624 #define USB0_OBSERVE USB_OBSERVE_REG(USB0)
ethaderu 3:78f223d34f36 13625 #define USB0_CONTROL USB_CONTROL_REG(USB0)
ethaderu 3:78f223d34f36 13626 #define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
ethaderu 3:78f223d34f36 13627 #define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
ethaderu 3:78f223d34f36 13628 #define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
ethaderu 3:78f223d34f36 13629 #define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
ethaderu 3:78f223d34f36 13630 #define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
ethaderu 3:78f223d34f36 13631
ethaderu 3:78f223d34f36 13632 /* USB - Register array accessors */
ethaderu 3:78f223d34f36 13633 #define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
ethaderu 3:78f223d34f36 13634
ethaderu 3:78f223d34f36 13635 /*!
ethaderu 3:78f223d34f36 13636 * @}
ethaderu 3:78f223d34f36 13637 */ /* end of group USB_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 13638
ethaderu 3:78f223d34f36 13639
ethaderu 3:78f223d34f36 13640 /*!
ethaderu 3:78f223d34f36 13641 * @}
ethaderu 3:78f223d34f36 13642 */ /* end of group USB_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 13643
ethaderu 3:78f223d34f36 13644
ethaderu 3:78f223d34f36 13645 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 13646 -- USBDCD Peripheral Access Layer
ethaderu 3:78f223d34f36 13647 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 13648
ethaderu 3:78f223d34f36 13649 /*!
ethaderu 3:78f223d34f36 13650 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
ethaderu 3:78f223d34f36 13651 * @{
ethaderu 3:78f223d34f36 13652 */
ethaderu 3:78f223d34f36 13653
ethaderu 3:78f223d34f36 13654 /** USBDCD - Register Layout Typedef */
ethaderu 3:78f223d34f36 13655 typedef struct {
ethaderu 3:78f223d34f36 13656 __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
ethaderu 3:78f223d34f36 13657 __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
ethaderu 3:78f223d34f36 13658 __I uint32_t STATUS; /**< Status register, offset: 0x8 */
ethaderu 3:78f223d34f36 13659 uint8_t RESERVED_0[4];
ethaderu 3:78f223d34f36 13660 __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
ethaderu 3:78f223d34f36 13661 __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
ethaderu 3:78f223d34f36 13662 union { /* offset: 0x18 */
ethaderu 3:78f223d34f36 13663 __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
ethaderu 3:78f223d34f36 13664 __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
ethaderu 3:78f223d34f36 13665 };
ethaderu 3:78f223d34f36 13666 } USBDCD_Type, *USBDCD_MemMapPtr;
ethaderu 3:78f223d34f36 13667
ethaderu 3:78f223d34f36 13668 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 13669 -- USBDCD - Register accessor macros
ethaderu 3:78f223d34f36 13670 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 13671
ethaderu 3:78f223d34f36 13672 /*!
ethaderu 3:78f223d34f36 13673 * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
ethaderu 3:78f223d34f36 13674 * @{
ethaderu 3:78f223d34f36 13675 */
ethaderu 3:78f223d34f36 13676
ethaderu 3:78f223d34f36 13677
ethaderu 3:78f223d34f36 13678 /* USBDCD - Register accessors */
ethaderu 3:78f223d34f36 13679 #define USBDCD_CONTROL_REG(base) ((base)->CONTROL)
ethaderu 3:78f223d34f36 13680 #define USBDCD_CLOCK_REG(base) ((base)->CLOCK)
ethaderu 3:78f223d34f36 13681 #define USBDCD_STATUS_REG(base) ((base)->STATUS)
ethaderu 3:78f223d34f36 13682 #define USBDCD_TIMER0_REG(base) ((base)->TIMER0)
ethaderu 3:78f223d34f36 13683 #define USBDCD_TIMER1_REG(base) ((base)->TIMER1)
ethaderu 3:78f223d34f36 13684 #define USBDCD_TIMER2_BC11_REG(base) ((base)->TIMER2_BC11)
ethaderu 3:78f223d34f36 13685 #define USBDCD_TIMER2_BC12_REG(base) ((base)->TIMER2_BC12)
ethaderu 3:78f223d34f36 13686
ethaderu 3:78f223d34f36 13687 /*!
ethaderu 3:78f223d34f36 13688 * @}
ethaderu 3:78f223d34f36 13689 */ /* end of group USBDCD_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 13690
ethaderu 3:78f223d34f36 13691
ethaderu 3:78f223d34f36 13692 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 13693 -- USBDCD Register Masks
ethaderu 3:78f223d34f36 13694 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 13695
ethaderu 3:78f223d34f36 13696 /*!
ethaderu 3:78f223d34f36 13697 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
ethaderu 3:78f223d34f36 13698 * @{
ethaderu 3:78f223d34f36 13699 */
ethaderu 3:78f223d34f36 13700
ethaderu 3:78f223d34f36 13701 /* CONTROL Bit Fields */
ethaderu 3:78f223d34f36 13702 #define USBDCD_CONTROL_IACK_MASK 0x1u
ethaderu 3:78f223d34f36 13703 #define USBDCD_CONTROL_IACK_SHIFT 0
ethaderu 3:78f223d34f36 13704 #define USBDCD_CONTROL_IF_MASK 0x100u
ethaderu 3:78f223d34f36 13705 #define USBDCD_CONTROL_IF_SHIFT 8
ethaderu 3:78f223d34f36 13706 #define USBDCD_CONTROL_IE_MASK 0x10000u
ethaderu 3:78f223d34f36 13707 #define USBDCD_CONTROL_IE_SHIFT 16
ethaderu 3:78f223d34f36 13708 #define USBDCD_CONTROL_BC12_MASK 0x20000u
ethaderu 3:78f223d34f36 13709 #define USBDCD_CONTROL_BC12_SHIFT 17
ethaderu 3:78f223d34f36 13710 #define USBDCD_CONTROL_START_MASK 0x1000000u
ethaderu 3:78f223d34f36 13711 #define USBDCD_CONTROL_START_SHIFT 24
ethaderu 3:78f223d34f36 13712 #define USBDCD_CONTROL_SR_MASK 0x2000000u
ethaderu 3:78f223d34f36 13713 #define USBDCD_CONTROL_SR_SHIFT 25
ethaderu 3:78f223d34f36 13714 /* CLOCK Bit Fields */
ethaderu 3:78f223d34f36 13715 #define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
ethaderu 3:78f223d34f36 13716 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
ethaderu 3:78f223d34f36 13717 #define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
ethaderu 3:78f223d34f36 13718 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
ethaderu 3:78f223d34f36 13719 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
ethaderu 3:78f223d34f36 13720 /* STATUS Bit Fields */
ethaderu 3:78f223d34f36 13721 #define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
ethaderu 3:78f223d34f36 13722 #define USBDCD_STATUS_SEQ_RES_SHIFT 16
ethaderu 3:78f223d34f36 13723 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
ethaderu 3:78f223d34f36 13724 #define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
ethaderu 3:78f223d34f36 13725 #define USBDCD_STATUS_SEQ_STAT_SHIFT 18
ethaderu 3:78f223d34f36 13726 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
ethaderu 3:78f223d34f36 13727 #define USBDCD_STATUS_ERR_MASK 0x100000u
ethaderu 3:78f223d34f36 13728 #define USBDCD_STATUS_ERR_SHIFT 20
ethaderu 3:78f223d34f36 13729 #define USBDCD_STATUS_TO_MASK 0x200000u
ethaderu 3:78f223d34f36 13730 #define USBDCD_STATUS_TO_SHIFT 21
ethaderu 3:78f223d34f36 13731 #define USBDCD_STATUS_ACTIVE_MASK 0x400000u
ethaderu 3:78f223d34f36 13732 #define USBDCD_STATUS_ACTIVE_SHIFT 22
ethaderu 3:78f223d34f36 13733 /* TIMER0 Bit Fields */
ethaderu 3:78f223d34f36 13734 #define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
ethaderu 3:78f223d34f36 13735 #define USBDCD_TIMER0_TUNITCON_SHIFT 0
ethaderu 3:78f223d34f36 13736 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
ethaderu 3:78f223d34f36 13737 #define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
ethaderu 3:78f223d34f36 13738 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
ethaderu 3:78f223d34f36 13739 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
ethaderu 3:78f223d34f36 13740 /* TIMER1 Bit Fields */
ethaderu 3:78f223d34f36 13741 #define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
ethaderu 3:78f223d34f36 13742 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
ethaderu 3:78f223d34f36 13743 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
ethaderu 3:78f223d34f36 13744 #define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
ethaderu 3:78f223d34f36 13745 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
ethaderu 3:78f223d34f36 13746 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
ethaderu 3:78f223d34f36 13747 /* TIMER2_BC11 Bit Fields */
ethaderu 3:78f223d34f36 13748 #define USBDCD_TIMER2_BC11_CHECK_DM_MASK 0xFu
ethaderu 3:78f223d34f36 13749 #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT 0
ethaderu 3:78f223d34f36 13750 #define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_CHECK_DM_SHIFT))&USBDCD_TIMER2_BC11_CHECK_DM_MASK)
ethaderu 3:78f223d34f36 13751 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK 0x3FF0000u
ethaderu 3:78f223d34f36 13752 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT 16
ethaderu 3:78f223d34f36 13753 #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
ethaderu 3:78f223d34f36 13754 /* TIMER2_BC12 Bit Fields */
ethaderu 3:78f223d34f36 13755 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK 0x3FFu
ethaderu 3:78f223d34f36 13756 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT 0
ethaderu 3:78f223d34f36 13757 #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT))&USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
ethaderu 3:78f223d34f36 13758 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK 0x3FF0000u
ethaderu 3:78f223d34f36 13759 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT 16
ethaderu 3:78f223d34f36 13760 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT))&USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
ethaderu 3:78f223d34f36 13761
ethaderu 3:78f223d34f36 13762 /*!
ethaderu 3:78f223d34f36 13763 * @}
ethaderu 3:78f223d34f36 13764 */ /* end of group USBDCD_Register_Masks */
ethaderu 3:78f223d34f36 13765
ethaderu 3:78f223d34f36 13766
ethaderu 3:78f223d34f36 13767 /* USBDCD - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 13768 /** Peripheral USBDCD base address */
ethaderu 3:78f223d34f36 13769 #define USBDCD_BASE (0x40035000u)
ethaderu 3:78f223d34f36 13770 /** Peripheral USBDCD base pointer */
ethaderu 3:78f223d34f36 13771 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
ethaderu 3:78f223d34f36 13772 #define USBDCD_BASE_PTR (USBDCD)
ethaderu 3:78f223d34f36 13773 /** Array initializer of USBDCD peripheral base addresses */
ethaderu 3:78f223d34f36 13774 #define USBDCD_BASE_ADDRS { USBDCD_BASE }
ethaderu 3:78f223d34f36 13775 /** Array initializer of USBDCD peripheral base pointers */
ethaderu 3:78f223d34f36 13776 #define USBDCD_BASE_PTRS { USBDCD }
ethaderu 3:78f223d34f36 13777 /** Interrupt vectors for the USBDCD peripheral type */
ethaderu 3:78f223d34f36 13778 #define USBDCD_IRQS { USBDCD_IRQn }
ethaderu 3:78f223d34f36 13779
ethaderu 3:78f223d34f36 13780 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 13781 -- USBDCD - Register accessor macros
ethaderu 3:78f223d34f36 13782 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 13783
ethaderu 3:78f223d34f36 13784 /*!
ethaderu 3:78f223d34f36 13785 * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
ethaderu 3:78f223d34f36 13786 * @{
ethaderu 3:78f223d34f36 13787 */
ethaderu 3:78f223d34f36 13788
ethaderu 3:78f223d34f36 13789
ethaderu 3:78f223d34f36 13790 /* USBDCD - Register instance definitions */
ethaderu 3:78f223d34f36 13791 /* USBDCD */
ethaderu 3:78f223d34f36 13792 #define USBDCD_CONTROL USBDCD_CONTROL_REG(USBDCD)
ethaderu 3:78f223d34f36 13793 #define USBDCD_CLOCK USBDCD_CLOCK_REG(USBDCD)
ethaderu 3:78f223d34f36 13794 #define USBDCD_STATUS USBDCD_STATUS_REG(USBDCD)
ethaderu 3:78f223d34f36 13795 #define USBDCD_TIMER0 USBDCD_TIMER0_REG(USBDCD)
ethaderu 3:78f223d34f36 13796 #define USBDCD_TIMER1 USBDCD_TIMER1_REG(USBDCD)
ethaderu 3:78f223d34f36 13797 #define USBDCD_TIMER2_BC11 USBDCD_TIMER2_BC11_REG(USBDCD)
ethaderu 3:78f223d34f36 13798 #define USBDCD_TIMER2_BC12 USBDCD_TIMER2_BC12_REG(USBDCD)
ethaderu 3:78f223d34f36 13799
ethaderu 3:78f223d34f36 13800 /*!
ethaderu 3:78f223d34f36 13801 * @}
ethaderu 3:78f223d34f36 13802 */ /* end of group USBDCD_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 13803
ethaderu 3:78f223d34f36 13804
ethaderu 3:78f223d34f36 13805 /*!
ethaderu 3:78f223d34f36 13806 * @}
ethaderu 3:78f223d34f36 13807 */ /* end of group USBDCD_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 13808
ethaderu 3:78f223d34f36 13809
ethaderu 3:78f223d34f36 13810 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 13811 -- VREF Peripheral Access Layer
ethaderu 3:78f223d34f36 13812 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 13813
ethaderu 3:78f223d34f36 13814 /*!
ethaderu 3:78f223d34f36 13815 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
ethaderu 3:78f223d34f36 13816 * @{
ethaderu 3:78f223d34f36 13817 */
ethaderu 3:78f223d34f36 13818
ethaderu 3:78f223d34f36 13819 /** VREF - Register Layout Typedef */
ethaderu 3:78f223d34f36 13820 typedef struct {
ethaderu 3:78f223d34f36 13821 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
ethaderu 3:78f223d34f36 13822 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
ethaderu 3:78f223d34f36 13823 } VREF_Type, *VREF_MemMapPtr;
ethaderu 3:78f223d34f36 13824
ethaderu 3:78f223d34f36 13825 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 13826 -- VREF - Register accessor macros
ethaderu 3:78f223d34f36 13827 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 13828
ethaderu 3:78f223d34f36 13829 /*!
ethaderu 3:78f223d34f36 13830 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
ethaderu 3:78f223d34f36 13831 * @{
ethaderu 3:78f223d34f36 13832 */
ethaderu 3:78f223d34f36 13833
ethaderu 3:78f223d34f36 13834
ethaderu 3:78f223d34f36 13835 /* VREF - Register accessors */
ethaderu 3:78f223d34f36 13836 #define VREF_TRM_REG(base) ((base)->TRM)
ethaderu 3:78f223d34f36 13837 #define VREF_SC_REG(base) ((base)->SC)
ethaderu 3:78f223d34f36 13838
ethaderu 3:78f223d34f36 13839 /*!
ethaderu 3:78f223d34f36 13840 * @}
ethaderu 3:78f223d34f36 13841 */ /* end of group VREF_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 13842
ethaderu 3:78f223d34f36 13843
ethaderu 3:78f223d34f36 13844 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 13845 -- VREF Register Masks
ethaderu 3:78f223d34f36 13846 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 13847
ethaderu 3:78f223d34f36 13848 /*!
ethaderu 3:78f223d34f36 13849 * @addtogroup VREF_Register_Masks VREF Register Masks
ethaderu 3:78f223d34f36 13850 * @{
ethaderu 3:78f223d34f36 13851 */
ethaderu 3:78f223d34f36 13852
ethaderu 3:78f223d34f36 13853 /* TRM Bit Fields */
ethaderu 3:78f223d34f36 13854 #define VREF_TRM_TRIM_MASK 0x3Fu
ethaderu 3:78f223d34f36 13855 #define VREF_TRM_TRIM_SHIFT 0
ethaderu 3:78f223d34f36 13856 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
ethaderu 3:78f223d34f36 13857 #define VREF_TRM_CHOPEN_MASK 0x40u
ethaderu 3:78f223d34f36 13858 #define VREF_TRM_CHOPEN_SHIFT 6
ethaderu 3:78f223d34f36 13859 /* SC Bit Fields */
ethaderu 3:78f223d34f36 13860 #define VREF_SC_MODE_LV_MASK 0x3u
ethaderu 3:78f223d34f36 13861 #define VREF_SC_MODE_LV_SHIFT 0
ethaderu 3:78f223d34f36 13862 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
ethaderu 3:78f223d34f36 13863 #define VREF_SC_VREFST_MASK 0x4u
ethaderu 3:78f223d34f36 13864 #define VREF_SC_VREFST_SHIFT 2
ethaderu 3:78f223d34f36 13865 #define VREF_SC_ICOMPEN_MASK 0x20u
ethaderu 3:78f223d34f36 13866 #define VREF_SC_ICOMPEN_SHIFT 5
ethaderu 3:78f223d34f36 13867 #define VREF_SC_REGEN_MASK 0x40u
ethaderu 3:78f223d34f36 13868 #define VREF_SC_REGEN_SHIFT 6
ethaderu 3:78f223d34f36 13869 #define VREF_SC_VREFEN_MASK 0x80u
ethaderu 3:78f223d34f36 13870 #define VREF_SC_VREFEN_SHIFT 7
ethaderu 3:78f223d34f36 13871
ethaderu 3:78f223d34f36 13872 /*!
ethaderu 3:78f223d34f36 13873 * @}
ethaderu 3:78f223d34f36 13874 */ /* end of group VREF_Register_Masks */
ethaderu 3:78f223d34f36 13875
ethaderu 3:78f223d34f36 13876
ethaderu 3:78f223d34f36 13877 /* VREF - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 13878 /** Peripheral VREF base address */
ethaderu 3:78f223d34f36 13879 #define VREF_BASE (0x40074000u)
ethaderu 3:78f223d34f36 13880 /** Peripheral VREF base pointer */
ethaderu 3:78f223d34f36 13881 #define VREF ((VREF_Type *)VREF_BASE)
ethaderu 3:78f223d34f36 13882 #define VREF_BASE_PTR (VREF)
ethaderu 3:78f223d34f36 13883 /** Array initializer of VREF peripheral base addresses */
ethaderu 3:78f223d34f36 13884 #define VREF_BASE_ADDRS { VREF_BASE }
ethaderu 3:78f223d34f36 13885 /** Array initializer of VREF peripheral base pointers */
ethaderu 3:78f223d34f36 13886 #define VREF_BASE_PTRS { VREF }
ethaderu 3:78f223d34f36 13887
ethaderu 3:78f223d34f36 13888 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 13889 -- VREF - Register accessor macros
ethaderu 3:78f223d34f36 13890 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 13891
ethaderu 3:78f223d34f36 13892 /*!
ethaderu 3:78f223d34f36 13893 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
ethaderu 3:78f223d34f36 13894 * @{
ethaderu 3:78f223d34f36 13895 */
ethaderu 3:78f223d34f36 13896
ethaderu 3:78f223d34f36 13897
ethaderu 3:78f223d34f36 13898 /* VREF - Register instance definitions */
ethaderu 3:78f223d34f36 13899 /* VREF */
ethaderu 3:78f223d34f36 13900 #define VREF_TRM VREF_TRM_REG(VREF)
ethaderu 3:78f223d34f36 13901 #define VREF_SC VREF_SC_REG(VREF)
ethaderu 3:78f223d34f36 13902
ethaderu 3:78f223d34f36 13903 /*!
ethaderu 3:78f223d34f36 13904 * @}
ethaderu 3:78f223d34f36 13905 */ /* end of group VREF_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 13906
ethaderu 3:78f223d34f36 13907
ethaderu 3:78f223d34f36 13908 /*!
ethaderu 3:78f223d34f36 13909 * @}
ethaderu 3:78f223d34f36 13910 */ /* end of group VREF_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 13911
ethaderu 3:78f223d34f36 13912
ethaderu 3:78f223d34f36 13913 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 13914 -- WDOG Peripheral Access Layer
ethaderu 3:78f223d34f36 13915 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 13916
ethaderu 3:78f223d34f36 13917 /*!
ethaderu 3:78f223d34f36 13918 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
ethaderu 3:78f223d34f36 13919 * @{
ethaderu 3:78f223d34f36 13920 */
ethaderu 3:78f223d34f36 13921
ethaderu 3:78f223d34f36 13922 /** WDOG - Register Layout Typedef */
ethaderu 3:78f223d34f36 13923 typedef struct {
ethaderu 3:78f223d34f36 13924 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
ethaderu 3:78f223d34f36 13925 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
ethaderu 3:78f223d34f36 13926 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
ethaderu 3:78f223d34f36 13927 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
ethaderu 3:78f223d34f36 13928 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
ethaderu 3:78f223d34f36 13929 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
ethaderu 3:78f223d34f36 13930 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
ethaderu 3:78f223d34f36 13931 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
ethaderu 3:78f223d34f36 13932 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
ethaderu 3:78f223d34f36 13933 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
ethaderu 3:78f223d34f36 13934 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
ethaderu 3:78f223d34f36 13935 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
ethaderu 3:78f223d34f36 13936 } WDOG_Type, *WDOG_MemMapPtr;
ethaderu 3:78f223d34f36 13937
ethaderu 3:78f223d34f36 13938 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 13939 -- WDOG - Register accessor macros
ethaderu 3:78f223d34f36 13940 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 13941
ethaderu 3:78f223d34f36 13942 /*!
ethaderu 3:78f223d34f36 13943 * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
ethaderu 3:78f223d34f36 13944 * @{
ethaderu 3:78f223d34f36 13945 */
ethaderu 3:78f223d34f36 13946
ethaderu 3:78f223d34f36 13947
ethaderu 3:78f223d34f36 13948 /* WDOG - Register accessors */
ethaderu 3:78f223d34f36 13949 #define WDOG_STCTRLH_REG(base) ((base)->STCTRLH)
ethaderu 3:78f223d34f36 13950 #define WDOG_STCTRLL_REG(base) ((base)->STCTRLL)
ethaderu 3:78f223d34f36 13951 #define WDOG_TOVALH_REG(base) ((base)->TOVALH)
ethaderu 3:78f223d34f36 13952 #define WDOG_TOVALL_REG(base) ((base)->TOVALL)
ethaderu 3:78f223d34f36 13953 #define WDOG_WINH_REG(base) ((base)->WINH)
ethaderu 3:78f223d34f36 13954 #define WDOG_WINL_REG(base) ((base)->WINL)
ethaderu 3:78f223d34f36 13955 #define WDOG_REFRESH_REG(base) ((base)->REFRESH)
ethaderu 3:78f223d34f36 13956 #define WDOG_UNLOCK_REG(base) ((base)->UNLOCK)
ethaderu 3:78f223d34f36 13957 #define WDOG_TMROUTH_REG(base) ((base)->TMROUTH)
ethaderu 3:78f223d34f36 13958 #define WDOG_TMROUTL_REG(base) ((base)->TMROUTL)
ethaderu 3:78f223d34f36 13959 #define WDOG_RSTCNT_REG(base) ((base)->RSTCNT)
ethaderu 3:78f223d34f36 13960 #define WDOG_PRESC_REG(base) ((base)->PRESC)
ethaderu 3:78f223d34f36 13961
ethaderu 3:78f223d34f36 13962 /*!
ethaderu 3:78f223d34f36 13963 * @}
ethaderu 3:78f223d34f36 13964 */ /* end of group WDOG_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 13965
ethaderu 3:78f223d34f36 13966
ethaderu 3:78f223d34f36 13967 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 13968 -- WDOG Register Masks
ethaderu 3:78f223d34f36 13969 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 13970
ethaderu 3:78f223d34f36 13971 /*!
ethaderu 3:78f223d34f36 13972 * @addtogroup WDOG_Register_Masks WDOG Register Masks
ethaderu 3:78f223d34f36 13973 * @{
ethaderu 3:78f223d34f36 13974 */
ethaderu 3:78f223d34f36 13975
ethaderu 3:78f223d34f36 13976 /* STCTRLH Bit Fields */
ethaderu 3:78f223d34f36 13977 #define WDOG_STCTRLH_WDOGEN_MASK 0x1u
ethaderu 3:78f223d34f36 13978 #define WDOG_STCTRLH_WDOGEN_SHIFT 0
ethaderu 3:78f223d34f36 13979 #define WDOG_STCTRLH_CLKSRC_MASK 0x2u
ethaderu 3:78f223d34f36 13980 #define WDOG_STCTRLH_CLKSRC_SHIFT 1
ethaderu 3:78f223d34f36 13981 #define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
ethaderu 3:78f223d34f36 13982 #define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
ethaderu 3:78f223d34f36 13983 #define WDOG_STCTRLH_WINEN_MASK 0x8u
ethaderu 3:78f223d34f36 13984 #define WDOG_STCTRLH_WINEN_SHIFT 3
ethaderu 3:78f223d34f36 13985 #define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
ethaderu 3:78f223d34f36 13986 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
ethaderu 3:78f223d34f36 13987 #define WDOG_STCTRLH_DBGEN_MASK 0x20u
ethaderu 3:78f223d34f36 13988 #define WDOG_STCTRLH_DBGEN_SHIFT 5
ethaderu 3:78f223d34f36 13989 #define WDOG_STCTRLH_STOPEN_MASK 0x40u
ethaderu 3:78f223d34f36 13990 #define WDOG_STCTRLH_STOPEN_SHIFT 6
ethaderu 3:78f223d34f36 13991 #define WDOG_STCTRLH_WAITEN_MASK 0x80u
ethaderu 3:78f223d34f36 13992 #define WDOG_STCTRLH_WAITEN_SHIFT 7
ethaderu 3:78f223d34f36 13993 #define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
ethaderu 3:78f223d34f36 13994 #define WDOG_STCTRLH_TESTWDOG_SHIFT 10
ethaderu 3:78f223d34f36 13995 #define WDOG_STCTRLH_TESTSEL_MASK 0x800u
ethaderu 3:78f223d34f36 13996 #define WDOG_STCTRLH_TESTSEL_SHIFT 11
ethaderu 3:78f223d34f36 13997 #define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
ethaderu 3:78f223d34f36 13998 #define WDOG_STCTRLH_BYTESEL_SHIFT 12
ethaderu 3:78f223d34f36 13999 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
ethaderu 3:78f223d34f36 14000 #define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
ethaderu 3:78f223d34f36 14001 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
ethaderu 3:78f223d34f36 14002 /* STCTRLL Bit Fields */
ethaderu 3:78f223d34f36 14003 #define WDOG_STCTRLL_INTFLG_MASK 0x8000u
ethaderu 3:78f223d34f36 14004 #define WDOG_STCTRLL_INTFLG_SHIFT 15
ethaderu 3:78f223d34f36 14005 /* TOVALH Bit Fields */
ethaderu 3:78f223d34f36 14006 #define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
ethaderu 3:78f223d34f36 14007 #define WDOG_TOVALH_TOVALHIGH_SHIFT 0
ethaderu 3:78f223d34f36 14008 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
ethaderu 3:78f223d34f36 14009 /* TOVALL Bit Fields */
ethaderu 3:78f223d34f36 14010 #define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
ethaderu 3:78f223d34f36 14011 #define WDOG_TOVALL_TOVALLOW_SHIFT 0
ethaderu 3:78f223d34f36 14012 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
ethaderu 3:78f223d34f36 14013 /* WINH Bit Fields */
ethaderu 3:78f223d34f36 14014 #define WDOG_WINH_WINHIGH_MASK 0xFFFFu
ethaderu 3:78f223d34f36 14015 #define WDOG_WINH_WINHIGH_SHIFT 0
ethaderu 3:78f223d34f36 14016 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
ethaderu 3:78f223d34f36 14017 /* WINL Bit Fields */
ethaderu 3:78f223d34f36 14018 #define WDOG_WINL_WINLOW_MASK 0xFFFFu
ethaderu 3:78f223d34f36 14019 #define WDOG_WINL_WINLOW_SHIFT 0
ethaderu 3:78f223d34f36 14020 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
ethaderu 3:78f223d34f36 14021 /* REFRESH Bit Fields */
ethaderu 3:78f223d34f36 14022 #define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
ethaderu 3:78f223d34f36 14023 #define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
ethaderu 3:78f223d34f36 14024 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
ethaderu 3:78f223d34f36 14025 /* UNLOCK Bit Fields */
ethaderu 3:78f223d34f36 14026 #define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
ethaderu 3:78f223d34f36 14027 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
ethaderu 3:78f223d34f36 14028 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
ethaderu 3:78f223d34f36 14029 /* TMROUTH Bit Fields */
ethaderu 3:78f223d34f36 14030 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
ethaderu 3:78f223d34f36 14031 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
ethaderu 3:78f223d34f36 14032 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
ethaderu 3:78f223d34f36 14033 /* TMROUTL Bit Fields */
ethaderu 3:78f223d34f36 14034 #define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
ethaderu 3:78f223d34f36 14035 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
ethaderu 3:78f223d34f36 14036 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
ethaderu 3:78f223d34f36 14037 /* RSTCNT Bit Fields */
ethaderu 3:78f223d34f36 14038 #define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
ethaderu 3:78f223d34f36 14039 #define WDOG_RSTCNT_RSTCNT_SHIFT 0
ethaderu 3:78f223d34f36 14040 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
ethaderu 3:78f223d34f36 14041 /* PRESC Bit Fields */
ethaderu 3:78f223d34f36 14042 #define WDOG_PRESC_PRESCVAL_MASK 0x700u
ethaderu 3:78f223d34f36 14043 #define WDOG_PRESC_PRESCVAL_SHIFT 8
ethaderu 3:78f223d34f36 14044 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
ethaderu 3:78f223d34f36 14045
ethaderu 3:78f223d34f36 14046 /*!
ethaderu 3:78f223d34f36 14047 * @}
ethaderu 3:78f223d34f36 14048 */ /* end of group WDOG_Register_Masks */
ethaderu 3:78f223d34f36 14049
ethaderu 3:78f223d34f36 14050
ethaderu 3:78f223d34f36 14051 /* WDOG - Peripheral instance base addresses */
ethaderu 3:78f223d34f36 14052 /** Peripheral WDOG base address */
ethaderu 3:78f223d34f36 14053 #define WDOG_BASE (0x40052000u)
ethaderu 3:78f223d34f36 14054 /** Peripheral WDOG base pointer */
ethaderu 3:78f223d34f36 14055 #define WDOG ((WDOG_Type *)WDOG_BASE)
ethaderu 3:78f223d34f36 14056 #define WDOG_BASE_PTR (WDOG)
ethaderu 3:78f223d34f36 14057 /** Array initializer of WDOG peripheral base addresses */
ethaderu 3:78f223d34f36 14058 #define WDOG_BASE_ADDRS { WDOG_BASE }
ethaderu 3:78f223d34f36 14059 /** Array initializer of WDOG peripheral base pointers */
ethaderu 3:78f223d34f36 14060 #define WDOG_BASE_PTRS { WDOG }
ethaderu 3:78f223d34f36 14061 /** Interrupt vectors for the WDOG peripheral type */
ethaderu 3:78f223d34f36 14062 #define WDOG_IRQS { Watchdog_IRQn }
ethaderu 3:78f223d34f36 14063
ethaderu 3:78f223d34f36 14064 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 14065 -- WDOG - Register accessor macros
ethaderu 3:78f223d34f36 14066 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 14067
ethaderu 3:78f223d34f36 14068 /*!
ethaderu 3:78f223d34f36 14069 * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
ethaderu 3:78f223d34f36 14070 * @{
ethaderu 3:78f223d34f36 14071 */
ethaderu 3:78f223d34f36 14072
ethaderu 3:78f223d34f36 14073
ethaderu 3:78f223d34f36 14074 /* WDOG - Register instance definitions */
ethaderu 3:78f223d34f36 14075 /* WDOG */
ethaderu 3:78f223d34f36 14076 #define WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG)
ethaderu 3:78f223d34f36 14077 #define WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG)
ethaderu 3:78f223d34f36 14078 #define WDOG_TOVALH WDOG_TOVALH_REG(WDOG)
ethaderu 3:78f223d34f36 14079 #define WDOG_TOVALL WDOG_TOVALL_REG(WDOG)
ethaderu 3:78f223d34f36 14080 #define WDOG_WINH WDOG_WINH_REG(WDOG)
ethaderu 3:78f223d34f36 14081 #define WDOG_WINL WDOG_WINL_REG(WDOG)
ethaderu 3:78f223d34f36 14082 #define WDOG_REFRESH WDOG_REFRESH_REG(WDOG)
ethaderu 3:78f223d34f36 14083 #define WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG)
ethaderu 3:78f223d34f36 14084 #define WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG)
ethaderu 3:78f223d34f36 14085 #define WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG)
ethaderu 3:78f223d34f36 14086 #define WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG)
ethaderu 3:78f223d34f36 14087 #define WDOG_PRESC WDOG_PRESC_REG(WDOG)
ethaderu 3:78f223d34f36 14088
ethaderu 3:78f223d34f36 14089 /*!
ethaderu 3:78f223d34f36 14090 * @}
ethaderu 3:78f223d34f36 14091 */ /* end of group WDOG_Register_Accessor_Macros */
ethaderu 3:78f223d34f36 14092
ethaderu 3:78f223d34f36 14093
ethaderu 3:78f223d34f36 14094 /*!
ethaderu 3:78f223d34f36 14095 * @}
ethaderu 3:78f223d34f36 14096 */ /* end of group WDOG_Peripheral_Access_Layer */
ethaderu 3:78f223d34f36 14097
ethaderu 3:78f223d34f36 14098
ethaderu 3:78f223d34f36 14099 /*
ethaderu 3:78f223d34f36 14100 ** End of section using anonymous unions
ethaderu 3:78f223d34f36 14101 */
ethaderu 3:78f223d34f36 14102
ethaderu 3:78f223d34f36 14103 #if defined(__ARMCC_VERSION)
ethaderu 3:78f223d34f36 14104 #pragma pop
ethaderu 3:78f223d34f36 14105 #elif defined(__CWCC__)
ethaderu 3:78f223d34f36 14106 #pragma pop
ethaderu 3:78f223d34f36 14107 #elif defined(__GNUC__)
ethaderu 3:78f223d34f36 14108 /* leave anonymous unions enabled */
ethaderu 3:78f223d34f36 14109 #elif defined(__IAR_SYSTEMS_ICC__)
ethaderu 3:78f223d34f36 14110 #pragma language=default
ethaderu 3:78f223d34f36 14111 #else
ethaderu 3:78f223d34f36 14112 #error Not supported compiler type
ethaderu 3:78f223d34f36 14113 #endif
ethaderu 3:78f223d34f36 14114
ethaderu 3:78f223d34f36 14115 /*!
ethaderu 3:78f223d34f36 14116 * @}
ethaderu 3:78f223d34f36 14117 */ /* end of group Peripheral_access_layer */
ethaderu 3:78f223d34f36 14118
ethaderu 3:78f223d34f36 14119
ethaderu 3:78f223d34f36 14120 /* ----------------------------------------------------------------------------
ethaderu 3:78f223d34f36 14121 -- Backward Compatibility
ethaderu 3:78f223d34f36 14122 ---------------------------------------------------------------------------- */
ethaderu 3:78f223d34f36 14123
ethaderu 3:78f223d34f36 14124 /*!
ethaderu 3:78f223d34f36 14125 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
ethaderu 3:78f223d34f36 14126 * @{
ethaderu 3:78f223d34f36 14127 */
ethaderu 3:78f223d34f36 14128
ethaderu 3:78f223d34f36 14129 #define DMA_EARS_REG(base) This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14130 #define DMA_EARS This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14131 #define DMA_EARS_EDREQ_0_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14132 #define DMA_EARS_EDREQ_0_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14133 #define DMA_EARS_EDREQ_1_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14134 #define DMA_EARS_EDREQ_1_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14135 #define DMA_EARS_EDREQ_2_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14136 #define DMA_EARS_EDREQ_2_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14137 #define DMA_EARS_EDREQ_3_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14138 #define DMA_EARS_EDREQ_3_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14139 #define DMA_EARS_EDREQ_4_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14140 #define DMA_EARS_EDREQ_4_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14141 #define DMA_EARS_EDREQ_5_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14142 #define DMA_EARS_EDREQ_5_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14143 #define DMA_EARS_EDREQ_6_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14144 #define DMA_EARS_EDREQ_6_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14145 #define DMA_EARS_EDREQ_7_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14146 #define DMA_EARS_EDREQ_7_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14147 #define DMA_EARS_EDREQ_8_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14148 #define DMA_EARS_EDREQ_8_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14149 #define DMA_EARS_EDREQ_9_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14150 #define DMA_EARS_EDREQ_9_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14151 #define DMA_EARS_EDREQ_10_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14152 #define DMA_EARS_EDREQ_10_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14153 #define DMA_EARS_EDREQ_11_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14154 #define DMA_EARS_EDREQ_11_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14155 #define DMA_EARS_EDREQ_12_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14156 #define DMA_EARS_EDREQ_12_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14157 #define DMA_EARS_EDREQ_13_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14158 #define DMA_EARS_EDREQ_13_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14159 #define DMA_EARS_EDREQ_14_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14160 #define DMA_EARS_EDREQ_14_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14161 #define DMA_EARS_EDREQ_15_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14162 #define DMA_EARS_EDREQ_15_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14163 #define ENET_RMON_T_DROP_REG(base) This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14164 #define ENET_IEEE_T_DROP_REG(base) This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14165 #define ENET_IEEE_T_SQE_REG(base) This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14166 #define ENET_RMON_R_RESVD_0_REG(base) This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14167 #define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
ethaderu 3:78f223d34f36 14168 #define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
ethaderu 3:78f223d34f36 14169 #define ENET_RMON_T_DROP This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14170 #define ENET_IEEE_T_DROP This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14171 #define ENET_IEEE_T_SQE This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14172 #define ENET_RMON_R_RESVD_0 This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14173 #define MCG_C9_REG(base) This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14174 #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
ethaderu 3:78f223d34f36 14175 #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
ethaderu 3:78f223d34f36 14176 #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
ethaderu 3:78f223d34f36 14177 #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
ethaderu 3:78f223d34f36 14178 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
ethaderu 3:78f223d34f36 14179 #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
ethaderu 3:78f223d34f36 14180 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
ethaderu 3:78f223d34f36 14181 #define MCG_C9 This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14182 #define MCM_PLACR_REG(base) This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14183 #define MCM_PLACR_ARB_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14184 #define MCM_PLACR_ARB_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14185 #define MCM_PLACR This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14186 #define ADC_BASES ADC_BASE_PTRS
ethaderu 3:78f223d34f36 14187 #define AIPS_BASES AIPS_BASE_PTRS
ethaderu 3:78f223d34f36 14188 #define AXBS_BASES AXBS_BASE_PTRS
ethaderu 3:78f223d34f36 14189 #define CAN_BASES CAN_BASE_PTRS
ethaderu 3:78f223d34f36 14190 #define CAU_BASES CAU_BASE_PTRS
ethaderu 3:78f223d34f36 14191 #define CMP_BASES CMP_BASE_PTRS
ethaderu 3:78f223d34f36 14192 #define CMT_BASES CMT_BASE_PTRS
ethaderu 3:78f223d34f36 14193 #define CRC_BASES CRC_BASE_PTRS
ethaderu 3:78f223d34f36 14194 #define DAC_BASES DAC_BASE_PTRS
ethaderu 3:78f223d34f36 14195 #define DMA_BASES DMA_BASE_PTRS
ethaderu 3:78f223d34f36 14196 #define DMAMUX_BASES DMAMUX_BASE_PTRS
ethaderu 3:78f223d34f36 14197 #define ENET_BASES ENET_BASE_PTRS
ethaderu 3:78f223d34f36 14198 #define EWM_BASES EWM_BASE_PTRS
ethaderu 3:78f223d34f36 14199 #define FB_BASES FB_BASE_PTRS
ethaderu 3:78f223d34f36 14200 #define FMC_BASES FMC_BASE_PTRS
ethaderu 3:78f223d34f36 14201 #define FTFE_BASES FTFE_BASE_PTRS
ethaderu 3:78f223d34f36 14202 #define FTM_BASES FTM_BASE_PTRS
ethaderu 3:78f223d34f36 14203 #define GPIO_BASES GPIO_BASE_PTRS
ethaderu 3:78f223d34f36 14204 #define I2C_BASES I2C_BASE_PTRS
ethaderu 3:78f223d34f36 14205 #define I2S_BASES I2S_BASE_PTRS
ethaderu 3:78f223d34f36 14206 #define LLWU_BASES LLWU_BASE_PTRS
ethaderu 3:78f223d34f36 14207 #define LPTMR_BASES LPTMR_BASE_PTRS
ethaderu 3:78f223d34f36 14208 #define MCG_BASES MCG_BASE_PTRS
ethaderu 3:78f223d34f36 14209 #define MCM_ISR_REG(base) MCM_ISCR_REG(base)
ethaderu 3:78f223d34f36 14210 #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
ethaderu 3:78f223d34f36 14211 #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
ethaderu 3:78f223d34f36 14212 #define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
ethaderu 3:78f223d34f36 14213 #define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
ethaderu 3:78f223d34f36 14214 #define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
ethaderu 3:78f223d34f36 14215 #define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
ethaderu 3:78f223d34f36 14216 #define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
ethaderu 3:78f223d34f36 14217 #define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
ethaderu 3:78f223d34f36 14218 #define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
ethaderu 3:78f223d34f36 14219 #define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
ethaderu 3:78f223d34f36 14220 #define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
ethaderu 3:78f223d34f36 14221 #define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
ethaderu 3:78f223d34f36 14222 #define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
ethaderu 3:78f223d34f36 14223 #define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
ethaderu 3:78f223d34f36 14224 #define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
ethaderu 3:78f223d34f36 14225 #define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
ethaderu 3:78f223d34f36 14226 #define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
ethaderu 3:78f223d34f36 14227 #define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
ethaderu 3:78f223d34f36 14228 #define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
ethaderu 3:78f223d34f36 14229 #define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
ethaderu 3:78f223d34f36 14230 #define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
ethaderu 3:78f223d34f36 14231 #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
ethaderu 3:78f223d34f36 14232 #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
ethaderu 3:78f223d34f36 14233 #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
ethaderu 3:78f223d34f36 14234 #define MCM_BASES MCM_BASE_PTRS
ethaderu 3:78f223d34f36 14235 #define MPU_BASES MPU_BASE_PTRS
ethaderu 3:78f223d34f36 14236 #define NV_BASES NV_BASE_PTRS
ethaderu 3:78f223d34f36 14237 #define OSC_BASES OSC_BASE_PTRS
ethaderu 3:78f223d34f36 14238 #define PDB_BASES PDB_BASE_PTRS
ethaderu 3:78f223d34f36 14239 #define PIT_BASES PIT_BASE_PTRS
ethaderu 3:78f223d34f36 14240 #define PMC_BASES PMC_BASE_PTRS
ethaderu 3:78f223d34f36 14241 #define PORT_BASES PORT_BASE_PTRS
ethaderu 3:78f223d34f36 14242 #define RCM_BASES RCM_BASE_PTRS
ethaderu 3:78f223d34f36 14243 #define RFSYS_BASES RFSYS_BASE_PTRS
ethaderu 3:78f223d34f36 14244 #define RFVBAT_BASES RFVBAT_BASE_PTRS
ethaderu 3:78f223d34f36 14245 #define RNG_BASES RNG_BASE_PTRS
ethaderu 3:78f223d34f36 14246 #define RTC_BASES RTC_BASE_PTRS
ethaderu 3:78f223d34f36 14247 #define SDHC_BASES SDHC_BASE_PTRS
ethaderu 3:78f223d34f36 14248 #define SIM_BASES SIM_BASE_PTRS
ethaderu 3:78f223d34f36 14249 #define SMC_BASES SMC_BASE_PTRS
ethaderu 3:78f223d34f36 14250 #define SPI_BASES SPI_BASE_PTRS
ethaderu 3:78f223d34f36 14251 #define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
ethaderu 3:78f223d34f36 14252 #define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
ethaderu 3:78f223d34f36 14253 #define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK
ethaderu 3:78f223d34f36 14254 #define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
ethaderu 3:78f223d34f36 14255 #define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x)
ethaderu 3:78f223d34f36 14256 #define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
ethaderu 3:78f223d34f36 14257 #define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
ethaderu 3:78f223d34f36 14258 #define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x)
ethaderu 3:78f223d34f36 14259 #define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
ethaderu 3:78f223d34f36 14260 #define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
ethaderu 3:78f223d34f36 14261 #define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x)
ethaderu 3:78f223d34f36 14262 #define UART_BASES UART_BASE_PTRS
ethaderu 3:78f223d34f36 14263 #define USB_BASES USB_BASE_PTRS
ethaderu 3:78f223d34f36 14264 #define USBDCD_BASES USBDCD_BASE_PTRS
ethaderu 3:78f223d34f36 14265 #define VREF_BASES VREF_BASE_PTRS
ethaderu 3:78f223d34f36 14266 #define WDOG_BASES WDOG_BASE_PTRS
ethaderu 3:78f223d34f36 14267 #define DMA_EARS_REG(base) This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14268 #define DMA_EARS This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14269 #define DMA_EARS_EDREQ_0_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14270 #define DMA_EARS_EDREQ_0_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14271 #define DMA_EARS_EDREQ_1_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14272 #define DMA_EARS_EDREQ_1_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14273 #define DMA_EARS_EDREQ_2_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14274 #define DMA_EARS_EDREQ_2_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14275 #define DMA_EARS_EDREQ_3_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14276 #define DMA_EARS_EDREQ_3_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14277 #define DMA_EARS_EDREQ_4_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14278 #define DMA_EARS_EDREQ_4_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14279 #define DMA_EARS_EDREQ_5_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14280 #define DMA_EARS_EDREQ_5_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14281 #define DMA_EARS_EDREQ_6_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14282 #define DMA_EARS_EDREQ_6_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14283 #define DMA_EARS_EDREQ_7_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14284 #define DMA_EARS_EDREQ_7_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14285 #define DMA_EARS_EDREQ_8_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14286 #define DMA_EARS_EDREQ_8_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14287 #define DMA_EARS_EDREQ_9_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14288 #define DMA_EARS_EDREQ_9_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14289 #define DMA_EARS_EDREQ_10_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14290 #define DMA_EARS_EDREQ_10_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14291 #define DMA_EARS_EDREQ_11_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14292 #define DMA_EARS_EDREQ_11_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14293 #define DMA_EARS_EDREQ_12_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14294 #define DMA_EARS_EDREQ_12_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14295 #define DMA_EARS_EDREQ_13_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14296 #define DMA_EARS_EDREQ_13_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14297 #define DMA_EARS_EDREQ_14_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14298 #define DMA_EARS_EDREQ_14_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14299 #define DMA_EARS_EDREQ_15_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14300 #define DMA_EARS_EDREQ_15_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14301 #define ENET_RMON_T_DROP_REG(base) This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14302 #define ENET_IEEE_T_DROP_REG(base) This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14303 #define ENET_IEEE_T_SQE_REG(base) This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14304 #define ENET_RMON_R_RESVD_0_REG(base) This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14305 #define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
ethaderu 3:78f223d34f36 14306 #define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
ethaderu 3:78f223d34f36 14307 #define ENET_RMON_T_DROP This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14308 #define ENET_IEEE_T_DROP This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14309 #define ENET_IEEE_T_SQE This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14310 #define ENET_RMON_R_RESVD_0 This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14311 #define MCG_C9_REG(base) This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14312 #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
ethaderu 3:78f223d34f36 14313 #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
ethaderu 3:78f223d34f36 14314 #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
ethaderu 3:78f223d34f36 14315 #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
ethaderu 3:78f223d34f36 14316 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
ethaderu 3:78f223d34f36 14317 #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
ethaderu 3:78f223d34f36 14318 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
ethaderu 3:78f223d34f36 14319 #define MCG_C9 This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14320 #define MCM_PLACR_REG(base) This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14321 #define MCM_PLACR_ARB_MASK This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14322 #define MCM_PLACR_ARB_SHIFT This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14323 #define MCM_PLACR This_symbol_has_been_deprecated
ethaderu 3:78f223d34f36 14324 #define ADC_BASES ADC_BASE_PTRS
ethaderu 3:78f223d34f36 14325 #define AIPS_BASES AIPS_BASE_PTRS
ethaderu 3:78f223d34f36 14326 #define AXBS_BASES AXBS_BASE_PTRS
ethaderu 3:78f223d34f36 14327 #define CAN_BASES CAN_BASE_PTRS
ethaderu 3:78f223d34f36 14328 #define CAU_BASES CAU_BASE_PTRS
ethaderu 3:78f223d34f36 14329 #define CMP_BASES CMP_BASE_PTRS
ethaderu 3:78f223d34f36 14330 #define CMT_BASES CMT_BASE_PTRS
ethaderu 3:78f223d34f36 14331 #define CRC_BASES CRC_BASE_PTRS
ethaderu 3:78f223d34f36 14332 #define DAC_BASES DAC_BASE_PTRS
ethaderu 3:78f223d34f36 14333 #define DMA_BASES DMA_BASE_PTRS
ethaderu 3:78f223d34f36 14334 #define DMAMUX_BASES DMAMUX_BASE_PTRS
ethaderu 3:78f223d34f36 14335 #define ENET_BASES ENET_BASE_PTRS
ethaderu 3:78f223d34f36 14336 #define EWM_BASES EWM_BASE_PTRS
ethaderu 3:78f223d34f36 14337 #define FB_BASES FB_BASE_PTRS
ethaderu 3:78f223d34f36 14338 #define FMC_BASES FMC_BASE_PTRS
ethaderu 3:78f223d34f36 14339 #define FTFE_BASES FTFE_BASE_PTRS
ethaderu 3:78f223d34f36 14340 #define FTM_BASES FTM_BASE_PTRS
ethaderu 3:78f223d34f36 14341 #define GPIO_BASES GPIO_BASE_PTRS
ethaderu 3:78f223d34f36 14342 #define I2C_BASES I2C_BASE_PTRS
ethaderu 3:78f223d34f36 14343 #define I2S_BASES I2S_BASE_PTRS
ethaderu 3:78f223d34f36 14344 #define LLWU_BASES LLWU_BASE_PTRS
ethaderu 3:78f223d34f36 14345 #define LPTMR_BASES LPTMR_BASE_PTRS
ethaderu 3:78f223d34f36 14346 #define MCG_BASES MCG_BASE_PTRS
ethaderu 3:78f223d34f36 14347 #define MCM_ISR_REG(base) MCM_ISCR_REG(base)
ethaderu 3:78f223d34f36 14348 #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
ethaderu 3:78f223d34f36 14349 #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
ethaderu 3:78f223d34f36 14350 #define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
ethaderu 3:78f223d34f36 14351 #define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
ethaderu 3:78f223d34f36 14352 #define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
ethaderu 3:78f223d34f36 14353 #define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
ethaderu 3:78f223d34f36 14354 #define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
ethaderu 3:78f223d34f36 14355 #define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
ethaderu 3:78f223d34f36 14356 #define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
ethaderu 3:78f223d34f36 14357 #define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
ethaderu 3:78f223d34f36 14358 #define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
ethaderu 3:78f223d34f36 14359 #define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
ethaderu 3:78f223d34f36 14360 #define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
ethaderu 3:78f223d34f36 14361 #define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
ethaderu 3:78f223d34f36 14362 #define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
ethaderu 3:78f223d34f36 14363 #define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
ethaderu 3:78f223d34f36 14364 #define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
ethaderu 3:78f223d34f36 14365 #define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
ethaderu 3:78f223d34f36 14366 #define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
ethaderu 3:78f223d34f36 14367 #define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
ethaderu 3:78f223d34f36 14368 #define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
ethaderu 3:78f223d34f36 14369 #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
ethaderu 3:78f223d34f36 14370 #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
ethaderu 3:78f223d34f36 14371 #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
ethaderu 3:78f223d34f36 14372 #define MCM_BASES MCM_BASE_PTRS
ethaderu 3:78f223d34f36 14373 #define MPU_BASES MPU_BASE_PTRS
ethaderu 3:78f223d34f36 14374 #define NV_BASES NV_BASE_PTRS
ethaderu 3:78f223d34f36 14375 #define OSC_BASES OSC_BASE_PTRS
ethaderu 3:78f223d34f36 14376 #define PDB_BASES PDB_BASE_PTRS
ethaderu 3:78f223d34f36 14377 #define PIT_BASES PIT_BASE_PTRS
ethaderu 3:78f223d34f36 14378 #define PMC_BASES PMC_BASE_PTRS
ethaderu 3:78f223d34f36 14379 #define PORT_BASES PORT_BASE_PTRS
ethaderu 3:78f223d34f36 14380 #define RCM_BASES RCM_BASE_PTRS
ethaderu 3:78f223d34f36 14381 #define RFSYS_BASES RFSYS_BASE_PTRS
ethaderu 3:78f223d34f36 14382 #define RFVBAT_BASES RFVBAT_BASE_PTRS
ethaderu 3:78f223d34f36 14383 #define RNG_BASES RNG_BASE_PTRS
ethaderu 3:78f223d34f36 14384 #define RTC_BASES RTC_BASE_PTRS
ethaderu 3:78f223d34f36 14385 #define SDHC_BASES SDHC_BASE_PTRS
ethaderu 3:78f223d34f36 14386 #define SIM_BASES SIM_BASE_PTRS
ethaderu 3:78f223d34f36 14387 #define SMC_BASES SMC_BASE_PTRS
ethaderu 3:78f223d34f36 14388 #define SPI_BASES SPI_BASE_PTRS
ethaderu 3:78f223d34f36 14389 #define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
ethaderu 3:78f223d34f36 14390 #define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
ethaderu 3:78f223d34f36 14391 #define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK
ethaderu 3:78f223d34f36 14392 #define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
ethaderu 3:78f223d34f36 14393 #define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x)
ethaderu 3:78f223d34f36 14394 #define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
ethaderu 3:78f223d34f36 14395 #define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
ethaderu 3:78f223d34f36 14396 #define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x)
ethaderu 3:78f223d34f36 14397 #define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
ethaderu 3:78f223d34f36 14398 #define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
ethaderu 3:78f223d34f36 14399 #define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x)
ethaderu 3:78f223d34f36 14400 #define UART_BASES UART_BASE_PTRS
ethaderu 3:78f223d34f36 14401 #define USB_BASES USB_BASE_PTRS
ethaderu 3:78f223d34f36 14402 #define USBDCD_BASES USBDCD_BASE_PTRS
ethaderu 3:78f223d34f36 14403 #define VREF_BASES VREF_BASE_PTRS
ethaderu 3:78f223d34f36 14404 #define WDOG_BASES WDOG_BASE_PTRS
ethaderu 3:78f223d34f36 14405
ethaderu 3:78f223d34f36 14406 /*!
ethaderu 3:78f223d34f36 14407 * @}
ethaderu 3:78f223d34f36 14408 */ /* end of group Backward_Compatibility_Symbols */
ethaderu 3:78f223d34f36 14409
ethaderu 3:78f223d34f36 14410
ethaderu 3:78f223d34f36 14411 #else /* #if !defined(MK64F12_H_) */
ethaderu 3:78f223d34f36 14412 /* There is already included the same memory map. Check if it is compatible (has the same major version) */
ethaderu 3:78f223d34f36 14413 #if (MCU_MEM_MAP_VERSION != 0x0200u)
ethaderu 3:78f223d34f36 14414 #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
ethaderu 3:78f223d34f36 14415 #warning There are included two not compatible versions of memory maps. Please check possible differences.
ethaderu 3:78f223d34f36 14416 #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
ethaderu 3:78f223d34f36 14417 #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
ethaderu 3:78f223d34f36 14418 #endif /* #if !defined(MK64F12_H_) */
ethaderu 3:78f223d34f36 14419
ethaderu 3:78f223d34f36 14420 /* MK64F12.h, eof. */