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Dependencies:   PWM_Tone_Library DHT

mbed/spi_api.h@5:569a4894abc1, 2019-03-08 (annotated)

Committer:
aziz111
Date:
Fri Mar 08 17:15:02 2019 +0000
Revision:
5:569a4894abc1
Parent:
3:78f223d34f36 
Final

Who changed what in which revision?

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ethaderu 3:78f223d34f36 1 /* mbed Microcontroller Library
ethaderu 3:78f223d34f36 2 * Copyright (c) 2006-2013 ARM Limited
ethaderu 3:78f223d34f36 3 *
ethaderu 3:78f223d34f36 4 * Licensed under the Apache License, Version 2.0 (the "License");
ethaderu 3:78f223d34f36 5 * you may not use this file except in compliance with the License.
ethaderu 3:78f223d34f36 6 * You may obtain a copy of the License at
ethaderu 3:78f223d34f36 7 *
ethaderu 3:78f223d34f36 8 * http://www.apache.org/licenses/LICENSE-2.0
ethaderu 3:78f223d34f36 9 *
ethaderu 3:78f223d34f36 10 * Unless required by applicable law or agreed to in writing, software
ethaderu 3:78f223d34f36 11 * distributed under the License is distributed on an "AS IS" BASIS,
ethaderu 3:78f223d34f36 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ethaderu 3:78f223d34f36 13 * See the License for the specific language governing permissions and
ethaderu 3:78f223d34f36 14 * limitations under the License.
ethaderu 3:78f223d34f36 15 */
ethaderu 3:78f223d34f36 16 #ifndef MBED_SPI_API_H
ethaderu 3:78f223d34f36 17 #define MBED_SPI_API_H
ethaderu 3:78f223d34f36 18
ethaderu 3:78f223d34f36 19 #include "device.h"
ethaderu 3:78f223d34f36 20 #include "dma_api.h"
ethaderu 3:78f223d34f36 21 #include "buffer.h"
ethaderu 3:78f223d34f36 22
ethaderu 3:78f223d34f36 23 #if DEVICE_SPI
ethaderu 3:78f223d34f36 24
ethaderu 3:78f223d34f36 25 #define SPI_EVENT_ERROR (1 << 1)
ethaderu 3:78f223d34f36 26 #define SPI_EVENT_COMPLETE (1 << 2)
ethaderu 3:78f223d34f36 27 #define SPI_EVENT_RX_OVERFLOW (1 << 3)
ethaderu 3:78f223d34f36 28 #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
ethaderu 3:78f223d34f36 29
ethaderu 3:78f223d34f36 30 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // internal flag to report an event occurred
ethaderu 3:78f223d34f36 31
ethaderu 3:78f223d34f36 32 #define SPI_FILL_WORD (0xFFFF)
ethaderu 3:78f223d34f36 33
ethaderu 3:78f223d34f36 34 #if DEVICE_SPI_ASYNCH
ethaderu 3:78f223d34f36 35 /** Asynch spi hal structure
ethaderu 3:78f223d34f36 36 */
ethaderu 3:78f223d34f36 37 typedef struct {
ethaderu 3:78f223d34f36 38 struct spi_s spi; /**< Target specific spi structure */
ethaderu 3:78f223d34f36 39 struct buffer_s tx_buff; /**< Tx buffer */
ethaderu 3:78f223d34f36 40 struct buffer_s rx_buff; /**< Rx buffer */
ethaderu 3:78f223d34f36 41 } spi_t;
ethaderu 3:78f223d34f36 42
ethaderu 3:78f223d34f36 43 #else
ethaderu 3:78f223d34f36 44 /** Non-asynch spi hal structure
ethaderu 3:78f223d34f36 45 */
ethaderu 3:78f223d34f36 46 typedef struct spi_s spi_t;
ethaderu 3:78f223d34f36 47
ethaderu 3:78f223d34f36 48 #endif
ethaderu 3:78f223d34f36 49
ethaderu 3:78f223d34f36 50 #ifdef __cplusplus
ethaderu 3:78f223d34f36 51 extern "C" {
ethaderu 3:78f223d34f36 52 #endif
ethaderu 3:78f223d34f36 53
ethaderu 3:78f223d34f36 54 /**
ethaderu 3:78f223d34f36 55 * \defgroup GeneralSPI SPI Configuration Functions
ethaderu 3:78f223d34f36 56 * @{
ethaderu 3:78f223d34f36 57 */
ethaderu 3:78f223d34f36 58
ethaderu 3:78f223d34f36 59 /** Initialize the SPI peripheral
ethaderu 3:78f223d34f36 60 *
ethaderu 3:78f223d34f36 61 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
ethaderu 3:78f223d34f36 62 * @param[out] obj The SPI object to initialize
ethaderu 3:78f223d34f36 63 * @param[in] mosi The pin to use for MOSI
ethaderu 3:78f223d34f36 64 * @param[in] miso The pin to use for MISO
ethaderu 3:78f223d34f36 65 * @param[in] sclk The pin to use for SCLK
ethaderu 3:78f223d34f36 66 * @param[in] ssel The pin to use for SSEL
ethaderu 3:78f223d34f36 67 */
ethaderu 3:78f223d34f36 68 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
ethaderu 3:78f223d34f36 69
ethaderu 3:78f223d34f36 70 /** Release a SPI object
ethaderu 3:78f223d34f36 71 *
ethaderu 3:78f223d34f36 72 * TODO: spi_free is currently unimplemented
ethaderu 3:78f223d34f36 73 * This will require reference counting at the C++ level to be safe
ethaderu 3:78f223d34f36 74 *
ethaderu 3:78f223d34f36 75 * Return the pins owned by the SPI object to their reset state
ethaderu 3:78f223d34f36 76 * Disable the SPI peripheral
ethaderu 3:78f223d34f36 77 * Disable the SPI clock
ethaderu 3:78f223d34f36 78 * @param[in] obj The SPI object to deinitialize
ethaderu 3:78f223d34f36 79 */
ethaderu 3:78f223d34f36 80 void spi_free(spi_t *obj);
ethaderu 3:78f223d34f36 81
ethaderu 3:78f223d34f36 82 /** Configure the SPI format
ethaderu 3:78f223d34f36 83 *
ethaderu 3:78f223d34f36 84 * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode
ethaderu 3:78f223d34f36 85 * @param[in,out] obj The SPI object to configure
ethaderu 3:78f223d34f36 86 * @param[in] bits The number of bits per frame
ethaderu 3:78f223d34f36 87 * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
ethaderu 3:78f223d34f36 88 * @param[in] slave Zero for master mode or non-zero for slave mode
ethaderu 3:78f223d34f36 89 */
ethaderu 3:78f223d34f36 90 void spi_format(spi_t *obj, int bits, int mode, int slave);
ethaderu 3:78f223d34f36 91
ethaderu 3:78f223d34f36 92 /** Set the SPI baud rate
ethaderu 3:78f223d34f36 93 *
ethaderu 3:78f223d34f36 94 * Actual frequency may differ from the desired frequency due to available dividers and bus clock
ethaderu 3:78f223d34f36 95 * Configures the SPI peripheral's baud rate
ethaderu 3:78f223d34f36 96 * @param[in,out] obj The SPI object to configure
ethaderu 3:78f223d34f36 97 * @param[in] hz The baud rate in Hz
ethaderu 3:78f223d34f36 98 */
ethaderu 3:78f223d34f36 99 void spi_frequency(spi_t *obj, int hz);
ethaderu 3:78f223d34f36 100
ethaderu 3:78f223d34f36 101 /**@}*/
ethaderu 3:78f223d34f36 102 /**
ethaderu 3:78f223d34f36 103 * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
ethaderu 3:78f223d34f36 104 * @{
ethaderu 3:78f223d34f36 105 */
ethaderu 3:78f223d34f36 106
ethaderu 3:78f223d34f36 107 /** Write a byte out in master mode and receive a value
ethaderu 3:78f223d34f36 108 *
ethaderu 3:78f223d34f36 109 * @param[in] obj The SPI peripheral to use for sending
ethaderu 3:78f223d34f36 110 * @param[in] value The value to send
ethaderu 3:78f223d34f36 111 * @return Returns the value received during send
ethaderu 3:78f223d34f36 112 */
ethaderu 3:78f223d34f36 113 int spi_master_write(spi_t *obj, int value);
ethaderu 3:78f223d34f36 114
ethaderu 3:78f223d34f36 115 /** Check if a value is available to read
ethaderu 3:78f223d34f36 116 *
ethaderu 3:78f223d34f36 117 * @param[in] obj The SPI peripheral to check
ethaderu 3:78f223d34f36 118 * @return non-zero if a value is available
ethaderu 3:78f223d34f36 119 */
ethaderu 3:78f223d34f36 120 int spi_slave_receive(spi_t *obj);
ethaderu 3:78f223d34f36 121
ethaderu 3:78f223d34f36 122 /** Get a received value out of the SPI receive buffer in slave mode
ethaderu 3:78f223d34f36 123 *
ethaderu 3:78f223d34f36 124 * Blocks until a value is available
ethaderu 3:78f223d34f36 125 * @param[in] obj The SPI peripheral to read
ethaderu 3:78f223d34f36 126 * @return The value received
ethaderu 3:78f223d34f36 127 */
ethaderu 3:78f223d34f36 128 int spi_slave_read(spi_t *obj);
ethaderu 3:78f223d34f36 129
ethaderu 3:78f223d34f36 130 /** Write a value to the SPI peripheral in slave mode
ethaderu 3:78f223d34f36 131 *
ethaderu 3:78f223d34f36 132 * Blocks until the SPI peripheral can be written to
ethaderu 3:78f223d34f36 133 * @param[in] obj The SPI peripheral to write
ethaderu 3:78f223d34f36 134 * @param[in] value The value to write
ethaderu 3:78f223d34f36 135 */
ethaderu 3:78f223d34f36 136 void spi_slave_write(spi_t *obj, int value);
ethaderu 3:78f223d34f36 137
ethaderu 3:78f223d34f36 138 /** Checks if the specified SPI peripheral is in use
ethaderu 3:78f223d34f36 139 *
ethaderu 3:78f223d34f36 140 * @param[in] obj The SPI peripheral to check
ethaderu 3:78f223d34f36 141 * @return non-zero if the peripheral is currently transmitting
ethaderu 3:78f223d34f36 142 */
ethaderu 3:78f223d34f36 143 int spi_busy(spi_t *obj);
ethaderu 3:78f223d34f36 144
ethaderu 3:78f223d34f36 145 /** Get the module number
ethaderu 3:78f223d34f36 146 *
ethaderu 3:78f223d34f36 147 * @param[in] obj The SPI peripheral to check
ethaderu 3:78f223d34f36 148 * @return The module number
ethaderu 3:78f223d34f36 149 */
ethaderu 3:78f223d34f36 150 uint8_t spi_get_module(spi_t *obj);
ethaderu 3:78f223d34f36 151
ethaderu 3:78f223d34f36 152 /**@}*/
ethaderu 3:78f223d34f36 153
ethaderu 3:78f223d34f36 154 #if DEVICE_SPI_ASYNCH
ethaderu 3:78f223d34f36 155 /**
ethaderu 3:78f223d34f36 156 * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
ethaderu 3:78f223d34f36 157 * @{
ethaderu 3:78f223d34f36 158 */
ethaderu 3:78f223d34f36 159
ethaderu 3:78f223d34f36 160 /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
ethaderu 3:78f223d34f36 161 *
ethaderu 3:78f223d34f36 162 * @param[in] obj The SPI object which holds the transfer information
ethaderu 3:78f223d34f36 163 * @param[in] tx The buffer to send
ethaderu 3:78f223d34f36 164 * @param[in] tx_length The number of words to transmit
ethaderu 3:78f223d34f36 165 * @param[in] rx The buffer to receive
ethaderu 3:78f223d34f36 166 * @param[in] rx_length The number of words to receive
ethaderu 3:78f223d34f36 167 * @param[in] bit_width The bit width of buffer words
ethaderu 3:78f223d34f36 168 * @param[in] event The logical OR of events to be registered
ethaderu 3:78f223d34f36 169 * @param[in] handler SPI interrupt handler
ethaderu 3:78f223d34f36 170 * @param[in] hint A suggestion for how to use DMA with this transfer
ethaderu 3:78f223d34f36 171 */
ethaderu 3:78f223d34f36 172 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
ethaderu 3:78f223d34f36 173
ethaderu 3:78f223d34f36 174 /** The asynchronous IRQ handler
ethaderu 3:78f223d34f36 175 *
ethaderu 3:78f223d34f36 176 * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
ethaderu 3:78f223d34f36 177 * conditions, such as buffer overflows or transfer complete.
ethaderu 3:78f223d34f36 178 * @param[in] obj The SPI object which holds the transfer information
ethaderu 3:78f223d34f36 179 * @return event flags if a transfer termination condition was met or 0 otherwise.
ethaderu 3:78f223d34f36 180 */
ethaderu 3:78f223d34f36 181 uint32_t spi_irq_handler_asynch(spi_t *obj);
ethaderu 3:78f223d34f36 182
ethaderu 3:78f223d34f36 183 /** Attempts to determine if the SPI peripheral is already in use.
ethaderu 3:78f223d34f36 184 *
ethaderu 3:78f223d34f36 185 * If a temporary DMA channel has been allocated, peripheral is in use.
ethaderu 3:78f223d34f36 186 * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
ethaderu 3:78f223d34f36 187 * channel were allocated.
ethaderu 3:78f223d34f36 188 * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
ethaderu 3:78f223d34f36 189 * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
ethaderu 3:78f223d34f36 190 * there are any bytes in the FIFOs.
ethaderu 3:78f223d34f36 191 * @param[in] obj The SPI object to check for activity
ethaderu 3:78f223d34f36 192 * @return non-zero if the SPI port is active or zero if it is not.
ethaderu 3:78f223d34f36 193 */
ethaderu 3:78f223d34f36 194 uint8_t spi_active(spi_t *obj);
ethaderu 3:78f223d34f36 195
ethaderu 3:78f223d34f36 196 /** Abort an SPI transfer
ethaderu 3:78f223d34f36 197 *
ethaderu 3:78f223d34f36 198 * @param obj The SPI peripheral to stop
ethaderu 3:78f223d34f36 199 */
ethaderu 3:78f223d34f36 200 void spi_abort_asynch(spi_t *obj);
ethaderu 3:78f223d34f36 201
ethaderu 3:78f223d34f36 202
ethaderu 3:78f223d34f36 203 #endif
ethaderu 3:78f223d34f36 204
ethaderu 3:78f223d34f36 205 /**@}*/
ethaderu 3:78f223d34f36 206
ethaderu 3:78f223d34f36 207 #ifdef __cplusplus
ethaderu 3:78f223d34f36 208 }
ethaderu 3:78f223d34f36 209 #endif // __cplusplus
ethaderu 3:78f223d34f36 210
ethaderu 3:78f223d34f36 211 #endif // SPI_DEVICE
ethaderu 3:78f223d34f36 212
ethaderu 3:78f223d34f36 213 #endif // MBED_SPI_API_H