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mbed/TARGET_K64F/system_MK64F12.h@5:569a4894abc1, 2019-03-08 (annotated)

Committer:
aziz111
Date:
Fri Mar 08 17:15:02 2019 +0000
Revision:
5:569a4894abc1
Parent:
3:78f223d34f36 
Final

Who changed what in which revision?

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ethaderu 3:78f223d34f36 1 /*
ethaderu 3:78f223d34f36 2 ** ###################################################################
ethaderu 3:78f223d34f36 3 ** Processor: MK64FN1M0VMD12
ethaderu 3:78f223d34f36 4 ** Compilers: Keil ARM C/C++ Compiler
ethaderu 3:78f223d34f36 5 ** Freescale C/C++ for Embedded ARM
ethaderu 3:78f223d34f36 6 ** GNU C Compiler
ethaderu 3:78f223d34f36 7 ** GNU C Compiler - CodeSourcery Sourcery G++
ethaderu 3:78f223d34f36 8 ** IAR ANSI C/C++ Compiler for ARM
ethaderu 3:78f223d34f36 9 **
ethaderu 3:78f223d34f36 10 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
ethaderu 3:78f223d34f36 11 ** Version: rev. 2.5, 2014-02-10
ethaderu 3:78f223d34f36 12 ** Build: b140611
ethaderu 3:78f223d34f36 13 **
ethaderu 3:78f223d34f36 14 ** Abstract:
ethaderu 3:78f223d34f36 15 ** Provides a system configuration function and a global variable that
ethaderu 3:78f223d34f36 16 ** contains the system frequency. It configures the device and initializes
ethaderu 3:78f223d34f36 17 ** the oscillator (PLL) that is part of the microcontroller device.
ethaderu 3:78f223d34f36 18 **
ethaderu 3:78f223d34f36 19 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
ethaderu 3:78f223d34f36 20 ** All rights reserved.
ethaderu 3:78f223d34f36 21 **
ethaderu 3:78f223d34f36 22 ** Redistribution and use in source and binary forms, with or without modification,
ethaderu 3:78f223d34f36 23 ** are permitted provided that the following conditions are met:
ethaderu 3:78f223d34f36 24 **
ethaderu 3:78f223d34f36 25 ** o Redistributions of source code must retain the above copyright notice, this list
ethaderu 3:78f223d34f36 26 ** of conditions and the following disclaimer.
ethaderu 3:78f223d34f36 27 **
ethaderu 3:78f223d34f36 28 ** o Redistributions in binary form must reproduce the above copyright notice, this
ethaderu 3:78f223d34f36 29 ** list of conditions and the following disclaimer in the documentation and/or
ethaderu 3:78f223d34f36 30 ** other materials provided with the distribution.
ethaderu 3:78f223d34f36 31 **
ethaderu 3:78f223d34f36 32 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
ethaderu 3:78f223d34f36 33 ** contributors may be used to endorse or promote products derived from this
ethaderu 3:78f223d34f36 34 ** software without specific prior written permission.
ethaderu 3:78f223d34f36 35 **
ethaderu 3:78f223d34f36 36 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ethaderu 3:78f223d34f36 37 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
ethaderu 3:78f223d34f36 38 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ethaderu 3:78f223d34f36 39 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ethaderu 3:78f223d34f36 40 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
ethaderu 3:78f223d34f36 41 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
ethaderu 3:78f223d34f36 42 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ethaderu 3:78f223d34f36 43 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
ethaderu 3:78f223d34f36 44 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
ethaderu 3:78f223d34f36 45 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ethaderu 3:78f223d34f36 46 **
ethaderu 3:78f223d34f36 47 ** http: www.freescale.com
ethaderu 3:78f223d34f36 48 ** mail: support@freescale.com
ethaderu 3:78f223d34f36 49 **
ethaderu 3:78f223d34f36 50 ** Revisions:
ethaderu 3:78f223d34f36 51 ** - rev. 1.0 (2013-08-12)
ethaderu 3:78f223d34f36 52 ** Initial version.
ethaderu 3:78f223d34f36 53 ** - rev. 2.0 (2013-10-29)
ethaderu 3:78f223d34f36 54 ** Register accessor macros added to the memory map.
ethaderu 3:78f223d34f36 55 ** Symbols for Processor Expert memory map compatibility added to the memory map.
ethaderu 3:78f223d34f36 56 ** Startup file for gcc has been updated according to CMSIS 3.2.
ethaderu 3:78f223d34f36 57 ** System initialization updated.
ethaderu 3:78f223d34f36 58 ** MCG - registers updated.
ethaderu 3:78f223d34f36 59 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
ethaderu 3:78f223d34f36 60 ** - rev. 2.1 (2013-10-30)
ethaderu 3:78f223d34f36 61 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
ethaderu 3:78f223d34f36 62 ** - rev. 2.2 (2013-12-09)
ethaderu 3:78f223d34f36 63 ** DMA - EARS register removed.
ethaderu 3:78f223d34f36 64 ** AIPS0, AIPS1 - MPRA register updated.
ethaderu 3:78f223d34f36 65 ** - rev. 2.3 (2014-01-24)
ethaderu 3:78f223d34f36 66 ** Update according to reference manual rev. 2
ethaderu 3:78f223d34f36 67 ** ENET, MCG, MCM, SIM, USB - registers updated
ethaderu 3:78f223d34f36 68 ** - rev. 2.4 (2014-02-10)
ethaderu 3:78f223d34f36 69 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
ethaderu 3:78f223d34f36 70 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
ethaderu 3:78f223d34f36 71 ** - rev. 2.5 (2014-02-10)
ethaderu 3:78f223d34f36 72 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
ethaderu 3:78f223d34f36 73 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
ethaderu 3:78f223d34f36 74 ** Module access macro module_BASES replaced by module_BASE_PTRS.
ethaderu 3:78f223d34f36 75 **
ethaderu 3:78f223d34f36 76 ** ###################################################################
ethaderu 3:78f223d34f36 77 */
ethaderu 3:78f223d34f36 78
ethaderu 3:78f223d34f36 79 /*!
ethaderu 3:78f223d34f36 80 * @file MK64F12
ethaderu 3:78f223d34f36 81 * @version 2.5
ethaderu 3:78f223d34f36 82 * @date 2014-02-10
ethaderu 3:78f223d34f36 83 * @brief Device specific configuration file for MK64F12 (header file)
ethaderu 3:78f223d34f36 84 *
ethaderu 3:78f223d34f36 85 * Provides a system configuration function and a global variable that contains
ethaderu 3:78f223d34f36 86 * the system frequency. It configures the device and initializes the oscillator
ethaderu 3:78f223d34f36 87 * (PLL) that is part of the microcontroller device.
ethaderu 3:78f223d34f36 88 */
ethaderu 3:78f223d34f36 89
ethaderu 3:78f223d34f36 90 #ifndef SYSTEM_MK64F12_H_
ethaderu 3:78f223d34f36 91 #define SYSTEM_MK64F12_H_ /**< Symbol preventing repeated inclusion */
ethaderu 3:78f223d34f36 92
ethaderu 3:78f223d34f36 93 #ifdef __cplusplus
ethaderu 3:78f223d34f36 94 extern "C" {
ethaderu 3:78f223d34f36 95 #endif
ethaderu 3:78f223d34f36 96
ethaderu 3:78f223d34f36 97 #include <stdint.h>
ethaderu 3:78f223d34f36 98
ethaderu 3:78f223d34f36 99
ethaderu 3:78f223d34f36 100 #define DISABLE_WDOG 1
ethaderu 3:78f223d34f36 101
ethaderu 3:78f223d34f36 102 #ifndef CLOCK_SETUP
ethaderu 3:78f223d34f36 103 #define CLOCK_SETUP 4
ethaderu 3:78f223d34f36 104 #endif
ethaderu 3:78f223d34f36 105
ethaderu 3:78f223d34f36 106 /* MCG mode constants */
ethaderu 3:78f223d34f36 107
ethaderu 3:78f223d34f36 108 #define MCG_MODE_FEI 0U
ethaderu 3:78f223d34f36 109 #define MCG_MODE_FBI 1U
ethaderu 3:78f223d34f36 110 #define MCG_MODE_BLPI 2U
ethaderu 3:78f223d34f36 111 #define MCG_MODE_FEE 3U
ethaderu 3:78f223d34f36 112 #define MCG_MODE_FBE 4U
ethaderu 3:78f223d34f36 113 #define MCG_MODE_BLPE 5U
ethaderu 3:78f223d34f36 114 #define MCG_MODE_PBE 6U
ethaderu 3:78f223d34f36 115 #define MCG_MODE_PEE 7U
ethaderu 3:78f223d34f36 116
ethaderu 3:78f223d34f36 117 /* Predefined clock setups
ethaderu 3:78f223d34f36 118 0 ... Default part configuration
ethaderu 3:78f223d34f36 119 Multipurpose Clock Generator (MCG) in FEI mode.
ethaderu 3:78f223d34f36 120 Reference clock source for MCG module: Slow internal reference clock
ethaderu 3:78f223d34f36 121 Core clock = 20.97152MHz
ethaderu 3:78f223d34f36 122 Bus clock = 20.97152MHz
ethaderu 3:78f223d34f36 123 1 ... Maximum achievable clock frequency configuration
ethaderu 3:78f223d34f36 124 Multipurpose Clock Generator (MCG) in PEE mode.
ethaderu 3:78f223d34f36 125 Reference clock source for MCG module: System oscillator 0 reference clock
ethaderu 3:78f223d34f36 126 Core clock = 120MHz
ethaderu 3:78f223d34f36 127 Bus clock = 60MHz
ethaderu 3:78f223d34f36 128 2 ... Chip internaly clocked, ready for Very Low Power Run mode.
ethaderu 3:78f223d34f36 129 Multipurpose Clock Generator (MCG) in BLPI mode.
ethaderu 3:78f223d34f36 130 Reference clock source for MCG module: Fast internal reference clock
ethaderu 3:78f223d34f36 131 Core clock = 4MHz
ethaderu 3:78f223d34f36 132 Bus clock = 4MHz
ethaderu 3:78f223d34f36 133 3 ... Chip externally clocked, ready for Very Low Power Run mode.
ethaderu 3:78f223d34f36 134 Multipurpose Clock Generator (MCG) in BLPE mode.
ethaderu 3:78f223d34f36 135 Reference clock source for MCG module: RTC oscillator reference clock
ethaderu 3:78f223d34f36 136 Core clock = 0.032768MHz
ethaderu 3:78f223d34f36 137 Bus clock = 0.032768MHz
ethaderu 3:78f223d34f36 138 4 ... USB clock setup
ethaderu 3:78f223d34f36 139 Multipurpose Clock Generator (MCG) in PEE mode.
ethaderu 3:78f223d34f36 140 Reference clock source for MCG module: System oscillator 0 reference clock
ethaderu 3:78f223d34f36 141 Core clock = 120MHz
ethaderu 3:78f223d34f36 142 Bus clock = 60MHz
ethaderu 3:78f223d34f36 143 */
ethaderu 3:78f223d34f36 144
ethaderu 3:78f223d34f36 145 /* Define clock source values */
ethaderu 3:78f223d34f36 146
ethaderu 3:78f223d34f36 147 #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
ethaderu 3:78f223d34f36 148 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
ethaderu 3:78f223d34f36 149 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
ethaderu 3:78f223d34f36 150 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
ethaderu 3:78f223d34f36 151 #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
ethaderu 3:78f223d34f36 152
ethaderu 3:78f223d34f36 153 /* RTC oscillator setting */
ethaderu 3:78f223d34f36 154 /* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
ethaderu 3:78f223d34f36 155 #define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
ethaderu 3:78f223d34f36 156
ethaderu 3:78f223d34f36 157 /* Low power mode enable */
ethaderu 3:78f223d34f36 158 /* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */
ethaderu 3:78f223d34f36 159 #define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */
ethaderu 3:78f223d34f36 160
ethaderu 3:78f223d34f36 161 /* Internal reference clock trim */
ethaderu 3:78f223d34f36 162 /* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
ethaderu 3:78f223d34f36 163 /* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
ethaderu 3:78f223d34f36 164 /* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
ethaderu 3:78f223d34f36 165 /* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
ethaderu 3:78f223d34f36 166
ethaderu 3:78f223d34f36 167 #if (CLOCK_SETUP == 0)
ethaderu 3:78f223d34f36 168 #define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
ethaderu 3:78f223d34f36 169 #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
ethaderu 3:78f223d34f36 170 /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
ethaderu 3:78f223d34f36 171 #define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
ethaderu 3:78f223d34f36 172 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
ethaderu 3:78f223d34f36 173 #define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
ethaderu 3:78f223d34f36 174 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
ethaderu 3:78f223d34f36 175 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
ethaderu 3:78f223d34f36 176 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
ethaderu 3:78f223d34f36 177 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
ethaderu 3:78f223d34f36 178 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
ethaderu 3:78f223d34f36 179 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
ethaderu 3:78f223d34f36 180 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
ethaderu 3:78f223d34f36 181 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
ethaderu 3:78f223d34f36 182 /* MCG_C7: OSCSEL=0 */
ethaderu 3:78f223d34f36 183 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
ethaderu 3:78f223d34f36 184 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
ethaderu 3:78f223d34f36 185 #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
ethaderu 3:78f223d34f36 186 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
ethaderu 3:78f223d34f36 187 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
ethaderu 3:78f223d34f36 188 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
ethaderu 3:78f223d34f36 189 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */
ethaderu 3:78f223d34f36 190 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
ethaderu 3:78f223d34f36 191 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
ethaderu 3:78f223d34f36 192 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
ethaderu 3:78f223d34f36 193 #define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
ethaderu 3:78f223d34f36 194 #elif (CLOCK_SETUP == 1)
ethaderu 3:78f223d34f36 195 #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
ethaderu 3:78f223d34f36 196 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
ethaderu 3:78f223d34f36 197 /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
ethaderu 3:78f223d34f36 198 #define SYSTEM_MCG_C1_VALUE 0x3AU /* MCG_C1 */
ethaderu 3:78f223d34f36 199 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
ethaderu 3:78f223d34f36 200 #define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
ethaderu 3:78f223d34f36 201 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
ethaderu 3:78f223d34f36 202 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
ethaderu 3:78f223d34f36 203 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
ethaderu 3:78f223d34f36 204 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
ethaderu 3:78f223d34f36 205 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
ethaderu 3:78f223d34f36 206 #define SYSTEM_MCG_C5_VALUE 0x13U /* MCG_C5 */
ethaderu 3:78f223d34f36 207 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
ethaderu 3:78f223d34f36 208 #define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */
ethaderu 3:78f223d34f36 209 /* MCG_C7: OSCSEL=0 */
ethaderu 3:78f223d34f36 210 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
ethaderu 3:78f223d34f36 211 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
ethaderu 3:78f223d34f36 212 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
ethaderu 3:78f223d34f36 213 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
ethaderu 3:78f223d34f36 214 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
ethaderu 3:78f223d34f36 215 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
ethaderu 3:78f223d34f36 216 #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
ethaderu 3:78f223d34f36 217 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
ethaderu 3:78f223d34f36 218 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
ethaderu 3:78f223d34f36 219 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
ethaderu 3:78f223d34f36 220 #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
ethaderu 3:78f223d34f36 221 #elif (CLOCK_SETUP == 2)
ethaderu 3:78f223d34f36 222 #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
ethaderu 3:78f223d34f36 223 #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
ethaderu 3:78f223d34f36 224 /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
ethaderu 3:78f223d34f36 225 #define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
ethaderu 3:78f223d34f36 226 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
ethaderu 3:78f223d34f36 227 #define SYSTEM_MCG_C2_VALUE 0x23U /* MCG_C2 */
ethaderu 3:78f223d34f36 228 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
ethaderu 3:78f223d34f36 229 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
ethaderu 3:78f223d34f36 230 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
ethaderu 3:78f223d34f36 231 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
ethaderu 3:78f223d34f36 232 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
ethaderu 3:78f223d34f36 233 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
ethaderu 3:78f223d34f36 234 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
ethaderu 3:78f223d34f36 235 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
ethaderu 3:78f223d34f36 236 /* MCG_C7: OSCSEL=0 */
ethaderu 3:78f223d34f36 237 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
ethaderu 3:78f223d34f36 238 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
ethaderu 3:78f223d34f36 239 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
ethaderu 3:78f223d34f36 240 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
ethaderu 3:78f223d34f36 241 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
ethaderu 3:78f223d34f36 242 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
ethaderu 3:78f223d34f36 243 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
ethaderu 3:78f223d34f36 244 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
ethaderu 3:78f223d34f36 245 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
ethaderu 3:78f223d34f36 246 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
ethaderu 3:78f223d34f36 247 #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
ethaderu 3:78f223d34f36 248 #elif (CLOCK_SETUP == 3)
ethaderu 3:78f223d34f36 249 #define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
ethaderu 3:78f223d34f36 250 #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
ethaderu 3:78f223d34f36 251 /* MCG_C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
ethaderu 3:78f223d34f36 252 #define SYSTEM_MCG_C1_VALUE 0x82U /* MCG_C1 */
ethaderu 3:78f223d34f36 253 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
ethaderu 3:78f223d34f36 254 #define SYSTEM_MCG_C2_VALUE 0x23U /* MCG_C2 */
ethaderu 3:78f223d34f36 255 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
ethaderu 3:78f223d34f36 256 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
ethaderu 3:78f223d34f36 257 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
ethaderu 3:78f223d34f36 258 #define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
ethaderu 3:78f223d34f36 259 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
ethaderu 3:78f223d34f36 260 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
ethaderu 3:78f223d34f36 261 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
ethaderu 3:78f223d34f36 262 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
ethaderu 3:78f223d34f36 263 /* MCG_C7: OSCSEL=1 */
ethaderu 3:78f223d34f36 264 #define SYSTEM_MCG_C7_VALUE 0x01U /* MCG_C7 */
ethaderu 3:78f223d34f36 265 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
ethaderu 3:78f223d34f36 266 #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
ethaderu 3:78f223d34f36 267 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
ethaderu 3:78f223d34f36 268 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
ethaderu 3:78f223d34f36 269 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0 */
ethaderu 3:78f223d34f36 270 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00U /* SIM_CLKDIV1 */
ethaderu 3:78f223d34f36 271 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
ethaderu 3:78f223d34f36 272 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
ethaderu 3:78f223d34f36 273 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
ethaderu 3:78f223d34f36 274 #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
ethaderu 3:78f223d34f36 275 #elif (CLOCK_SETUP == 4)
ethaderu 3:78f223d34f36 276 #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
ethaderu 3:78f223d34f36 277 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
ethaderu 3:78f223d34f36 278 /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
ethaderu 3:78f223d34f36 279 #define SYSTEM_MCG_C1_VALUE 0x3AU /* MCG_C1 */
ethaderu 3:78f223d34f36 280 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
ethaderu 3:78f223d34f36 281 #define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
ethaderu 3:78f223d34f36 282 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
ethaderu 3:78f223d34f36 283 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
ethaderu 3:78f223d34f36 284 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
ethaderu 3:78f223d34f36 285 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
ethaderu 3:78f223d34f36 286 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
ethaderu 3:78f223d34f36 287 #define SYSTEM_MCG_C5_VALUE 0x13U /* MCG_C5 */
ethaderu 3:78f223d34f36 288 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
ethaderu 3:78f223d34f36 289 #define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */
ethaderu 3:78f223d34f36 290 /* MCG_C7: OSCSEL=0 */
ethaderu 3:78f223d34f36 291 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
ethaderu 3:78f223d34f36 292 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
ethaderu 3:78f223d34f36 293 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
ethaderu 3:78f223d34f36 294 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
ethaderu 3:78f223d34f36 295 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
ethaderu 3:78f223d34f36 296 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
ethaderu 3:78f223d34f36 297 #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
ethaderu 3:78f223d34f36 298 /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
ethaderu 3:78f223d34f36 299 #define SYSTEM_SIM_CLKDIV2_VALUE 0x09U /* SIM_CLKDIV2 */
ethaderu 3:78f223d34f36 300 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
ethaderu 3:78f223d34f36 301 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
ethaderu 3:78f223d34f36 302 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
ethaderu 3:78f223d34f36 303 #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
ethaderu 3:78f223d34f36 304 #endif
ethaderu 3:78f223d34f36 305
ethaderu 3:78f223d34f36 306 /**
ethaderu 3:78f223d34f36 307 * @brief System clock frequency (core clock)
ethaderu 3:78f223d34f36 308 *
ethaderu 3:78f223d34f36 309 * The system clock frequency supplied to the SysTick timer and the processor
ethaderu 3:78f223d34f36 310 * core clock. This variable can be used by the user application to setup the
ethaderu 3:78f223d34f36 311 * SysTick timer or configure other parameters. It may also be used by debugger to
ethaderu 3:78f223d34f36 312 * query the frequency of the debug timer or configure the trace clock speed
ethaderu 3:78f223d34f36 313 * SystemCoreClock is initialized with a correct predefined value.
ethaderu 3:78f223d34f36 314 */
ethaderu 3:78f223d34f36 315 extern uint32_t SystemCoreClock;
ethaderu 3:78f223d34f36 316
ethaderu 3:78f223d34f36 317 /**
ethaderu 3:78f223d34f36 318 * @brief Setup the microcontroller system.
ethaderu 3:78f223d34f36 319 *
ethaderu 3:78f223d34f36 320 * Typically this function configures the oscillator (PLL) that is part of the
ethaderu 3:78f223d34f36 321 * microcontroller device. For systems with variable clock speed it also updates
ethaderu 3:78f223d34f36 322 * the variable SystemCoreClock. SystemInit is called from startup_device file.
ethaderu 3:78f223d34f36 323 */
ethaderu 3:78f223d34f36 324 void SystemInit (void);
ethaderu 3:78f223d34f36 325
ethaderu 3:78f223d34f36 326 /**
ethaderu 3:78f223d34f36 327 * @brief Updates the SystemCoreClock variable.
ethaderu 3:78f223d34f36 328 *
ethaderu 3:78f223d34f36 329 * It must be called whenever the core clock is changed during program
ethaderu 3:78f223d34f36 330 * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
ethaderu 3:78f223d34f36 331 * the current core clock.
ethaderu 3:78f223d34f36 332 */
ethaderu 3:78f223d34f36 333 void SystemCoreClockUpdate (void);
ethaderu 3:78f223d34f36 334
ethaderu 3:78f223d34f36 335 #ifdef __cplusplus
ethaderu 3:78f223d34f36 336 }
ethaderu 3:78f223d34f36 337 #endif
ethaderu 3:78f223d34f36 338
ethaderu 3:78f223d34f36 339 #endif /* #if !defined(SYSTEM_MK64F12_H_) */