Austin Brown
/
MikeEtekController
Mike Etek Controller
Inverter/Inverter.cpp@0:9edd6ec0f56a, 2017-05-20 (annotated)
- Committer:
- austinbrown124
- Date:
- Sat May 20 21:42:20 2017 +0000
- Revision:
- 0:9edd6ec0f56a
- Child:
- 1:94193b31f0ee
First Commit
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
austinbrown124 | 0:9edd6ec0f56a | 1 | |
austinbrown124 | 0:9edd6ec0f56a | 2 | #include "mbed.h" |
austinbrown124 | 0:9edd6ec0f56a | 3 | #include "hw_pins.h" |
austinbrown124 | 0:9edd6ec0f56a | 4 | //#include "hw_config.h" |
austinbrown124 | 0:9edd6ec0f56a | 5 | #include "structs.h" |
austinbrown124 | 0:9edd6ec0f56a | 6 | #include "FastPWM.h" |
austinbrown124 | 0:9edd6ec0f56a | 7 | |
austinbrown124 | 0:9edd6ec0f56a | 8 | void Init_PWM(GPIOStruct *gpio){ |
austinbrown124 | 0:9edd6ec0f56a | 9 | |
austinbrown124 | 0:9edd6ec0f56a | 10 | printf("\nStarting Hardware Function\n\r"); |
austinbrown124 | 0:9edd6ec0f56a | 11 | |
austinbrown124 | 0:9edd6ec0f56a | 12 | RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; // enable the clock to GPIOC |
austinbrown124 | 0:9edd6ec0f56a | 13 | RCC->APB1ENR |= 0x00000001; // enable TIM2 clock |
austinbrown124 | 0:9edd6ec0f56a | 14 | RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; // enable TIM1 clock |
austinbrown124 | 0:9edd6ec0f56a | 15 | |
austinbrown124 | 0:9edd6ec0f56a | 16 | GPIOC->MODER |= (1 << 10); // set pin 5 to be general purpose output for LED |
austinbrown124 | 0:9edd6ec0f56a | 17 | |
austinbrown124 | 0:9edd6ec0f56a | 18 | //gpio->enable = new DigitalOut(ENABLE_PIN); |
austinbrown124 | 0:9edd6ec0f56a | 19 | gpio->pwm_ul = new FastPWM(PIN_AL); |
austinbrown124 | 0:9edd6ec0f56a | 20 | gpio->pwm_vl = new FastPWM(PIN_BL); |
austinbrown124 | 0:9edd6ec0f56a | 21 | gpio->pwm_wl = new FastPWM(PIN_CL); |
austinbrown124 | 0:9edd6ec0f56a | 22 | gpio->pwm_uh = new FastPWM(PIN_AH); |
austinbrown124 | 0:9edd6ec0f56a | 23 | gpio->pwm_vh = new FastPWM(PIN_BH); |
austinbrown124 | 0:9edd6ec0f56a | 24 | gpio->pwm_wh = new FastPWM(PIN_CH); |
austinbrown124 | 0:9edd6ec0f56a | 25 | |
austinbrown124 | 0:9edd6ec0f56a | 26 | gpio->phasing = 1; |
austinbrown124 | 0:9edd6ec0f56a | 27 | |
austinbrown124 | 0:9edd6ec0f56a | 28 | |
austinbrown124 | 0:9edd6ec0f56a | 29 | //ISR Setup |
austinbrown124 | 0:9edd6ec0f56a | 30 | |
austinbrown124 | 0:9edd6ec0f56a | 31 | NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn); //Enable TIM1 IRQ |
austinbrown124 | 0:9edd6ec0f56a | 32 | |
austinbrown124 | 0:9edd6ec0f56a | 33 | TIM1->DIER |= TIM_DIER_UIE; // enable update interrupt |
austinbrown124 | 0:9edd6ec0f56a | 34 | TIM1->CR1 = 0x40; // CMS = 10, interrupt only when counting up |
austinbrown124 | 0:9edd6ec0f56a | 35 | TIM1->CR1 |= TIM_CR1_UDIS; |
austinbrown124 | 0:9edd6ec0f56a | 36 | TIM1->CR1 |= TIM_CR1_ARPE; // autoreload on, |
austinbrown124 | 0:9edd6ec0f56a | 37 | TIM1->RCR |= 0x001; // update event once per up/down count of tim1 |
austinbrown124 | 0:9edd6ec0f56a | 38 | TIM1->EGR |= TIM_EGR_UG; |
austinbrown124 | 0:9edd6ec0f56a | 39 | |
austinbrown124 | 0:9edd6ec0f56a | 40 | |
austinbrown124 | 0:9edd6ec0f56a | 41 | //PWM Setup |
austinbrown124 | 0:9edd6ec0f56a | 42 | TIM1->DIER |= TIM_DIER_UIE; // enable update interrupt |
austinbrown124 | 0:9edd6ec0f56a | 43 | TIM1->CR1 = 0x40;//CMS = 10, interrupt only when counting up |
austinbrown124 | 0:9edd6ec0f56a | 44 | |
austinbrown124 | 0:9edd6ec0f56a | 45 | TIM1->CR1 |= TIM_CR1_ARPE; // autoreload on, |
austinbrown124 | 0:9edd6ec0f56a | 46 | TIM1->RCR |= 0x001; // update event once per up/down count of tim1 |
austinbrown124 | 0:9edd6ec0f56a | 47 | TIM1->EGR |= TIM_EGR_UG; |
austinbrown124 | 0:9edd6ec0f56a | 48 | |
austinbrown124 | 0:9edd6ec0f56a | 49 | |
austinbrown124 | 0:9edd6ec0f56a | 50 | //PWM Setup |
austinbrown124 | 0:9edd6ec0f56a | 51 | TIM1->PSC = 0x0; // no prescaler, timer counts up in sync with the peripheral clock |
austinbrown124 | 0:9edd6ec0f56a | 52 | TIM1->ARR = 0x1194; // 20 Khz |
austinbrown124 | 0:9edd6ec0f56a | 53 | //TIM1->BDTR |= TIM_BDTR_MOE; |
austinbrown124 | 0:9edd6ec0f56a | 54 | //TIM1->BDTR |= TIM_BDTR_OSSI; |
austinbrown124 | 0:9edd6ec0f56a | 55 | //TIM1->BDTR |= TIM_BDTR_OSSR; |
austinbrown124 | 0:9edd6ec0f56a | 56 | TIM1->BDTR |= 0xBF; |
austinbrown124 | 0:9edd6ec0f56a | 57 | TIM1->CCER |= TIM_CCER_CC1E | TIM_CCER_CC1NE | TIM_CCER_CC2E | TIM_CCER_CC2NE | TIM_CCER_CC3E | TIM_CCER_CC3NE; |
austinbrown124 | 0:9edd6ec0f56a | 58 | //TIM1->CCER |= ~TIM_CCER_CC1NP; //Interupt when low side is on. |
austinbrown124 | 0:9edd6ec0f56a | 59 | //TIM1->CCER |= TIM_CCER_CC1NP; |
austinbrown124 | 0:9edd6ec0f56a | 60 | TIM1->CR1 |= TIM_CR1_CEN; |
austinbrown124 | 0:9edd6ec0f56a | 61 | |
austinbrown124 | 0:9edd6ec0f56a | 62 | |
austinbrown124 | 0:9edd6ec0f56a | 63 | } |
austinbrown124 | 0:9edd6ec0f56a | 64 | |
austinbrown124 | 0:9edd6ec0f56a | 65 | void Init_ADC(void){ |
austinbrown124 | 0:9edd6ec0f56a | 66 | // ADC Setup |
austinbrown124 | 0:9edd6ec0f56a | 67 | RCC->APB2ENR |= RCC_APB2ENR_ADC2EN; // clock for ADC2 |
austinbrown124 | 0:9edd6ec0f56a | 68 | RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; // clock for ADC1 |
austinbrown124 | 0:9edd6ec0f56a | 69 | RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; // Enable clock for GPIOC |
austinbrown124 | 0:9edd6ec0f56a | 70 | |
austinbrown124 | 0:9edd6ec0f56a | 71 | ADC->CCR = 0x00000006; // Regular simultaneous mode only |
austinbrown124 | 0:9edd6ec0f56a | 72 | ADC1->CR2 |= ADC_CR2_ADON;//0x00000001; // ADC1 ON |
austinbrown124 | 0:9edd6ec0f56a | 73 | ADC1->SQR3 = 0x000000A; // use PC_0 as input this is the V phase |
austinbrown124 | 0:9edd6ec0f56a | 74 | ADC2->CR2 |= ADC_CR2_ADON;//0x00000001; // ADC1 ON |
austinbrown124 | 0:9edd6ec0f56a | 75 | ADC2->SQR3 = 0x0000000B; // use PC_1 as input. This is the U phase |
austinbrown124 | 0:9edd6ec0f56a | 76 | GPIOC->MODER |= 0x0000000f; // Alternate function, PC_0, PC_1 are analog inputs |
austinbrown124 | 0:9edd6ec0f56a | 77 | |
austinbrown124 | 0:9edd6ec0f56a | 78 | } |
austinbrown124 | 0:9edd6ec0f56a | 79 | |
austinbrown124 | 0:9edd6ec0f56a | 80 | void Init_DAC(void){ |
austinbrown124 | 0:9edd6ec0f56a | 81 | RCC->APB1ENR |= 0x20000000; // Enable clock for DAC |
austinbrown124 | 0:9edd6ec0f56a | 82 | DAC->CR |= 0x00000001; // DAC control reg, both channels ON |
austinbrown124 | 0:9edd6ec0f56a | 83 | GPIOA->MODER |= 0x00000300; // PA04 as analog output |
austinbrown124 | 0:9edd6ec0f56a | 84 | } |
austinbrown124 | 0:9edd6ec0f56a | 85 | |
austinbrown124 | 0:9edd6ec0f56a | 86 | void Init_All_HW(GPIOStruct *gpio){ |
austinbrown124 | 0:9edd6ec0f56a | 87 | wait_ms(100); |
austinbrown124 | 0:9edd6ec0f56a | 88 | Init_ADC(); |
austinbrown124 | 0:9edd6ec0f56a | 89 | wait(0.1); |
austinbrown124 | 0:9edd6ec0f56a | 90 | |
austinbrown124 | 0:9edd6ec0f56a | 91 | //Init_DAC(); |
austinbrown124 | 0:9edd6ec0f56a | 92 | wait(0.1); |
austinbrown124 | 0:9edd6ec0f56a | 93 | |
austinbrown124 | 0:9edd6ec0f56a | 94 | Init_PWM(gpio); |
austinbrown124 | 0:9edd6ec0f56a | 95 | |
austinbrown124 | 0:9edd6ec0f56a | 96 | } |