Austin Brown / Mbed 2 deprecated MikeEtekController

Mike Etek Controller

Dependencies:   mbed

Inverter/Inverter.cpp@1:94193b31f0ee, 2019-04-06 (annotated)

Committer:
austinbrown124
Date:
Sat Apr 06 02:16:12 2019 +0000
Revision:
1:94193b31f0ee
Parent:
0:9edd6ec0f56a 
first commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
austinbrown124 1:94193b31f0ee 1 #include "Inverter.h"
austinbrown124 0:9edd6ec0f56a 2
austinbrown124 1:94193b31f0ee 3
austinbrown124 1:94193b31f0ee 4
austinbrown124 1:94193b31f0ee 5 //Condensing all hardware related variables into just this file.
austinbrown124 1:94193b31f0ee 6 //This includes all the register diddling, assigning duty cycles, etc.
austinbrown124 1:94193b31f0ee 7 //should probably have a class called "inverter" but thats a lot of effort
austinbrown124 1:94193b31f0ee 8
austinbrown124 1:94193b31f0ee 9 Inverter::Inverter(){
austinbrown124 0:9edd6ec0f56a 10
austinbrown124 0:9edd6ec0f56a 11
austinbrown124 1:94193b31f0ee 12 }
austinbrown124 1:94193b31f0ee 13
austinbrown124 1:94193b31f0ee 14 void Inverter::Init_PWM(void){
austinbrown124 0:9edd6ec0f56a 15
austinbrown124 1:94193b31f0ee 16 printf("\nStarting Hardware PWM\n\r");
austinbrown124 0:9edd6ec0f56a 17
austinbrown124 1:94193b31f0ee 18 RCC->AHBENR |= RCC_AHBENR_GPIOAEN; // enable the clock to GPIOA
austinbrown124 1:94193b31f0ee 19 RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; // enable TIM1 clock
austinbrown124 0:9edd6ec0f56a 20
austinbrown124 0:9edd6ec0f56a 21
austinbrown124 1:94193b31f0ee 22 //PWM Setup
austinbrown124 1:94193b31f0ee 23 TIM1->CCMR1 |= 0x0070; // Enable output compare 1 PWM mode 2 (inverted for low side shunts)
austinbrown124 1:94193b31f0ee 24 TIM1->CCER |= TIM_CCER_CC1E; // enable outputs 1
austinbrown124 1:94193b31f0ee 25 //no dead time needed!
austinbrown124 1:94193b31f0ee 26 TIM1->BDTR |= TIM_BDTR_MOE; //main output enable = 1
austinbrown124 1:94193b31f0ee 27 TIM1->PSC = 0x0; // no prescaler
austinbrown124 1:94193b31f0ee 28 TIM1->ARR = PWM_ARR; // set auto reload, 20 khz
austinbrown124 1:94193b31f0ee 29 TIM1->CR1 |= TIM_CR1_ARPE; // autoreload on,
austinbrown124 1:94193b31f0ee 30 RCC->CFGR3 |= RCC_CFGR3_TIM1SW; // bump tim1 up to 144MHz
austinbrown124 0:9edd6ec0f56a 31
austinbrown124 1:94193b31f0ee 32 //hardware pin setup
austinbrown124 1:94193b31f0ee 33 GPIOA->MODER |= GPIO_MODER_MODER8_1 ;
austinbrown124 1:94193b31f0ee 34 GPIOA->AFR[1] |= 0x00000006; // PA8 to alternate function 6
austinbrown124 1:94193b31f0ee 35
austinbrown124 1:94193b31f0ee 36 //interrupt generation
austinbrown124 1:94193b31f0ee 37 NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn); //Enable TIM1 IRQ //dafuq is this TIM16 BS?
austinbrown124 1:94193b31f0ee 38 TIM1->DIER |= TIM_DIER_UIE; // enable update interrupt
austinbrown124 1:94193b31f0ee 39 TIM1->CR1 |= 0x40; //CMS = 10, interrupt only when counting up
austinbrown124 1:94193b31f0ee 40 TIM1->RCR |= 0x001; // update event once per up/down count of tim1
austinbrown124 0:9edd6ec0f56a 41 TIM1->EGR |= TIM_EGR_UG;
austinbrown124 0:9edd6ec0f56a 42
austinbrown124 1:94193b31f0ee 43 TIM1->CR1 |= TIM_CR1_CEN; //go!
austinbrown124 0:9edd6ec0f56a 44
austinbrown124 0:9edd6ec0f56a 45 }
austinbrown124 0:9edd6ec0f56a 46
austinbrown124 1:94193b31f0ee 47 void Inverter::Init_ADC(void){
austinbrown124 0:9edd6ec0f56a 48 // ADC Setup
austinbrown124 1:94193b31f0ee 49 RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
austinbrown124 1:94193b31f0ee 50 RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
austinbrown124 1:94193b31f0ee 51 RCC->AHBENR |= RCC_AHBENR_ADC12EN; // clock for ADC1 and 2 enable
austinbrown124 1:94193b31f0ee 52 //RCC->AHBENR |= RCC_AHBENR_GPIOAEN; //page 149 on the ref manual
austinbrown124 1:94193b31f0ee 53
austinbrown124 1:94193b31f0ee 54 ADC12_COMMON->CCR |= 0x20001; // Regular simultaneous mode plus injected conversions
austinbrown124 1:94193b31f0ee 55
austinbrown124 1:94193b31f0ee 56
austinbrown124 1:94193b31f0ee 57 //for board 3
austinbrown124 1:94193b31f0ee 58 ADC1->SQR1 = 0x40; // use PA_0 as input, ADC1 in1
austinbrown124 1:94193b31f0ee 59 ADC2->SQR1 = 0x40; // use PA_4 as input, ADC2 in1
austinbrown124 1:94193b31f0ee 60 GPIOA->MODER |= 0x00000303; // Alternate function, PA_0, PA_4 are analog inputs
austinbrown124 0:9edd6ec0f56a 61
austinbrown124 1:94193b31f0ee 62 ADC1->SMPR1 = 32; //19.5 adc cock cycles for sample
austinbrown124 1:94193b31f0ee 63 ADC2->SMPR1 = 32; //19.5 adc cock cycles for sample.
austinbrown124 1:94193b31f0ee 64
austinbrown124 1:94193b31f0ee 65 ADC2->CR |= ADC_CR_ADEN;
austinbrown124 1:94193b31f0ee 66 ADC1->CR |= ADC_CR_ADEN;
austinbrown124 1:94193b31f0ee 67
austinbrown124 1:94193b31f0ee 68 wait_ms(10);
austinbrown124 0:9edd6ec0f56a 69
austinbrown124 1:94193b31f0ee 70 }
austinbrown124 1:94193b31f0ee 71
austinbrown124 0:9edd6ec0f56a 72
austinbrown124 1:94193b31f0ee 73
austinbrown124 1:94193b31f0ee 74
austinbrown124 1:94193b31f0ee 75 void Inverter::Init(){
austinbrown124 0:9edd6ec0f56a 76 wait_ms(100);
austinbrown124 0:9edd6ec0f56a 77 Init_ADC();
austinbrown124 0:9edd6ec0f56a 78 wait(0.1);
austinbrown124 1:94193b31f0ee 79 Init_PWM();
austinbrown124 0:9edd6ec0f56a 80
austinbrown124 1:94193b31f0ee 81 }
austinbrown124 0:9edd6ec0f56a 82
austinbrown124 1:94193b31f0ee 83 void Inverter::zero_current(){
austinbrown124 1:94193b31f0ee 84 int adc1_offset_s = 0;
austinbrown124 1:94193b31f0ee 85 int adc2_offset_s = 0;
austinbrown124 1:94193b31f0ee 86 int n = 1024;
austinbrown124 1:94193b31f0ee 87 for (int i = 0; i<n; i++){
austinbrown124 1:94193b31f0ee 88 ADC1->CR |= ADC_CR_ADSTART;
austinbrown124 1:94193b31f0ee 89 //wait_us(5);
austinbrown124 1:94193b31f0ee 90 for (volatile int t = 0; t < 16; t++) {}
austinbrown124 1:94193b31f0ee 91 adc2_offset_s += ADC2->DR;
austinbrown124 1:94193b31f0ee 92 adc1_offset_s += ADC1->DR;
austinbrown124 1:94193b31f0ee 93 }
austinbrown124 1:94193b31f0ee 94 adc1_offset = adc1_offset_s/n;
austinbrown124 1:94193b31f0ee 95 adc2_offset = adc2_offset_s/n;
austinbrown124 1:94193b31f0ee 96
austinbrown124 1:94193b31f0ee 97 }
austinbrown124 0:9edd6ec0f56a 98
austinbrown124 1:94193b31f0ee 99 void Inverter::ADCsync() {
austinbrown124 1:94193b31f0ee 100 //EXTEN[1:0] = 01
austinbrown124 1:94193b31f0ee 101 //EXTSEL[3:0] = 1010
austinbrown124 1:94193b31f0ee 102
austinbrown124 1:94193b31f0ee 103 //this code works to slave to center of TIM1 update
austinbrown124 1:94193b31f0ee 104 ADC1->CFGR |= ADC_CFGR_EXTEN_0 | ADC_CFGR_EXTEN_1;
austinbrown124 1:94193b31f0ee 105 ADC1->CFGR |= ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1;
austinbrown124 1:94193b31f0ee 106 TIM1->CR2 |= TIM_CR2_MMS2_1;
austinbrown124 1:94193b31f0ee 107 ADC1->CR |= ADC_CR_ADSTART;
austinbrown124 1:94193b31f0ee 108 }
austinbrown124 1:94193b31f0ee 109
austinbrown124 1:94193b31f0ee 110
austinbrown124 1:94193b31f0ee 111