Alejandro Ungria Hirte / GA-Test_copy

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Dependencies:   mbed-dev

decadriver/deca_device.c@0:a3b83d366423, 2017-12-06 (annotated)

Committer:
aungriah
Date:
Wed Dec 06 21:35:45 2017 +0000
Revision:
0:a3b83d366423
test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aungriah 0:a3b83d366423 1 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2 * @file deca_device.c
aungriah 0:a3b83d366423 3 * @brief Decawave device configuration and control functions
aungriah 0:a3b83d366423 4 *
aungriah 0:a3b83d366423 5 * @attention
aungriah 0:a3b83d366423 6 *
aungriah 0:a3b83d366423 7 * Copyright 2013 (c) Decawave Ltd, Dublin, Ireland.
aungriah 0:a3b83d366423 8 *
aungriah 0:a3b83d366423 9 * All rights reserved.
aungriah 0:a3b83d366423 10 *
aungriah 0:a3b83d366423 11 */
aungriah 0:a3b83d366423 12
aungriah 0:a3b83d366423 13 #include <assert.h>
aungriah 0:a3b83d366423 14
aungriah 0:a3b83d366423 15 #include "deca_types.h"
aungriah 0:a3b83d366423 16 #include "deca_param_types.h"
aungriah 0:a3b83d366423 17 #include "deca_regs.h"
aungriah 0:a3b83d366423 18 #include "deca_device_api.h"
aungriah 0:a3b83d366423 19
aungriah 0:a3b83d366423 20 // Defines for enable_clocks function
aungriah 0:a3b83d366423 21 #define FORCE_SYS_XTI 0
aungriah 0:a3b83d366423 22 #define ENABLE_ALL_SEQ 1
aungriah 0:a3b83d366423 23 #define FORCE_SYS_PLL 2
aungriah 0:a3b83d366423 24 #define READ_ACC_ON 7
aungriah 0:a3b83d366423 25 #define READ_ACC_OFF 8
aungriah 0:a3b83d366423 26 #define FORCE_OTP_ON 11
aungriah 0:a3b83d366423 27 #define FORCE_OTP_OFF 12
aungriah 0:a3b83d366423 28 #define FORCE_TX_PLL 13
aungriah 0:a3b83d366423 29 #define FORCE_LDE 14
aungriah 0:a3b83d366423 30
aungriah 0:a3b83d366423 31 // Defines for ACK request bitmask in DATA and MAC COMMAND frame control (first byte) - Used to detect AAT bit wrongly set.
aungriah 0:a3b83d366423 32 #define FCTRL_ACK_REQ_MASK 0x20
aungriah 0:a3b83d366423 33 // Frame control maximum length in bytes.
aungriah 0:a3b83d366423 34 #define FCTRL_LEN_MAX 2
aungriah 0:a3b83d366423 35
aungriah 0:a3b83d366423 36 // #define DWT_API_ERROR_CHECK // define so API checks config input parameters
aungriah 0:a3b83d366423 37
aungriah 0:a3b83d366423 38 // -------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 39 //
aungriah 0:a3b83d366423 40 // Internal functions for controlling and configuring the device
aungriah 0:a3b83d366423 41 //
aungriah 0:a3b83d366423 42 // -------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 43
aungriah 0:a3b83d366423 44 // Enable and Configure specified clocks
aungriah 0:a3b83d366423 45 void _dwt_enableclocks(int clocks) ;
aungriah 0:a3b83d366423 46 // Configure the ucode (FP algorithm) parameters
aungriah 0:a3b83d366423 47 void _dwt_configlde(int prf);
aungriah 0:a3b83d366423 48 // Load ucode from OTP/ROM
aungriah 0:a3b83d366423 49 void _dwt_loaducodefromrom(void);
aungriah 0:a3b83d366423 50 // Read non-volatile memory
aungriah 0:a3b83d366423 51 uint32 _dwt_otpread(uint32 address);
aungriah 0:a3b83d366423 52 // Program the non-volatile memory
aungriah 0:a3b83d366423 53 uint32 _dwt_otpprogword32(uint32 data, uint16 address);
aungriah 0:a3b83d366423 54 // Upload the device configuration into always on memory
aungriah 0:a3b83d366423 55 void _dwt_aonarrayupload(void);
aungriah 0:a3b83d366423 56 // -------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 57
aungriah 0:a3b83d366423 58 /*!
aungriah 0:a3b83d366423 59 * Static data for DW1000 DecaWave Transceiver control
aungriah 0:a3b83d366423 60 */
aungriah 0:a3b83d366423 61
aungriah 0:a3b83d366423 62 // -------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 63 // Structure to hold device data
aungriah 0:a3b83d366423 64 typedef struct
aungriah 0:a3b83d366423 65 {
aungriah 0:a3b83d366423 66 uint32 partID ; // IC Part ID - read during initialisation
aungriah 0:a3b83d366423 67 uint32 lotID ; // IC Lot ID - read during initialisation
aungriah 0:a3b83d366423 68 uint8 longFrames ; // Flag in non-standard long frame mode
aungriah 0:a3b83d366423 69 uint8 otprev ; // OTP revision number (read during initialisation)
aungriah 0:a3b83d366423 70 uint32 txFCTRL ; // Keep TX_FCTRL register config
aungriah 0:a3b83d366423 71 uint8 init_xtrim; // initial XTAL trim value read from OTP (or defaulted to mid-range if OTP not programmed)
aungriah 0:a3b83d366423 72 uint8 dblbuffon; // Double RX buffer mode flag
aungriah 0:a3b83d366423 73 uint32 sysCFGreg ; // Local copy of system config register
aungriah 0:a3b83d366423 74 uint16 sleep_mode; // Used for automatic reloading of LDO tune and microcode at wake-up
aungriah 0:a3b83d366423 75 uint8 wait4resp ; // wait4response was set with last TX start command
aungriah 0:a3b83d366423 76 dwt_cb_data_t cbData; // Callback data structure
aungriah 0:a3b83d366423 77 dwt_cb_t cbTxDone; // Callback for TX confirmation event
aungriah 0:a3b83d366423 78 dwt_cb_t cbRxOk; // Callback for RX good frame event
aungriah 0:a3b83d366423 79 dwt_cb_t cbRxTo; // Callback for RX timeout events
aungriah 0:a3b83d366423 80 dwt_cb_t cbRxErr; // Callback for RX error events
aungriah 0:a3b83d366423 81 } dwt_local_data_t ;
aungriah 0:a3b83d366423 82
aungriah 0:a3b83d366423 83 static dwt_local_data_t dw1000local ; // Static local device data
aungriah 0:a3b83d366423 84
aungriah 0:a3b83d366423 85 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 86 * @fn dwt_initialise()
aungriah 0:a3b83d366423 87 *
aungriah 0:a3b83d366423 88 * @brief This function initiates communications with the DW1000 transceiver
aungriah 0:a3b83d366423 89 * and reads its DEV_ID register (address 0x00) to verify the IC is one supported
aungriah 0:a3b83d366423 90 * by this software (e.g. DW1000 32-bit device ID value is 0xDECA0130). Then it
aungriah 0:a3b83d366423 91 * does any initial once only device configurations needed for use and initialises
aungriah 0:a3b83d366423 92 * as necessary any static data items belonging to this low-level driver.
aungriah 0:a3b83d366423 93 *
aungriah 0:a3b83d366423 94 * NOTES:
aungriah 0:a3b83d366423 95 * 1.this function needs to be run before dwt_configuresleep, also the SPI frequency has to be < 3MHz
aungriah 0:a3b83d366423 96 * 2.it also reads and applies LDO tune and crystal trim values from OTP memory
aungriah 0:a3b83d366423 97 *
aungriah 0:a3b83d366423 98 * input parameters
aungriah 0:a3b83d366423 99 * @param config - specifies what configuration to load
aungriah 0:a3b83d366423 100 * DWT_LOADUCODE 0x1 - load the LDE microcode from ROM - enabled accurate RX timestamp
aungriah 0:a3b83d366423 101 * DWT_LOADNONE 0x0 - do not load any values from OTP memory
aungriah 0:a3b83d366423 102 *
aungriah 0:a3b83d366423 103 * output parameters
aungriah 0:a3b83d366423 104 *
aungriah 0:a3b83d366423 105 * returns DWT_SUCCESS for success, or DWT_ERROR for error
aungriah 0:a3b83d366423 106 */
aungriah 0:a3b83d366423 107 // OTP addresses definitions
aungriah 0:a3b83d366423 108 #define LDOTUNE_ADDRESS (0x04)
aungriah 0:a3b83d366423 109 #define PARTID_ADDRESS (0x06)
aungriah 0:a3b83d366423 110 #define LOTID_ADDRESS (0x07)
aungriah 0:a3b83d366423 111 #define VBAT_ADDRESS (0x08)
aungriah 0:a3b83d366423 112 #define VTEMP_ADDRESS (0x09)
aungriah 0:a3b83d366423 113 #define XTRIM_ADDRESS (0x1E)
aungriah 0:a3b83d366423 114
aungriah 0:a3b83d366423 115 int dwt_initialise(uint16 config)
aungriah 0:a3b83d366423 116 {
aungriah 0:a3b83d366423 117 uint16 otp_addr = 0;
aungriah 0:a3b83d366423 118 uint32 ldo_tune = 0;
aungriah 0:a3b83d366423 119
aungriah 0:a3b83d366423 120 dw1000local.dblbuffon = 0; // Double buffer mode off by default
aungriah 0:a3b83d366423 121 dw1000local.wait4resp = 0;
aungriah 0:a3b83d366423 122 dw1000local.sleep_mode = 0;
aungriah 0:a3b83d366423 123
aungriah 0:a3b83d366423 124 dw1000local.cbTxDone = NULL;
aungriah 0:a3b83d366423 125 dw1000local.cbRxOk = NULL;
aungriah 0:a3b83d366423 126 dw1000local.cbRxTo = NULL;
aungriah 0:a3b83d366423 127 dw1000local.cbRxErr = NULL;
aungriah 0:a3b83d366423 128
aungriah 0:a3b83d366423 129 // Read and validate device ID return -1 if not recognised
aungriah 0:a3b83d366423 130 if (DWT_DEVICE_ID != dwt_readdevid()) // MP IC ONLY (i.e. DW1000) FOR THIS CODE
aungriah 0:a3b83d366423 131 {
aungriah 0:a3b83d366423 132 return DWT_ERROR ;
aungriah 0:a3b83d366423 133 }
aungriah 0:a3b83d366423 134
aungriah 0:a3b83d366423 135 // Make sure the device is completely reset before starting initialisation
aungriah 0:a3b83d366423 136 dwt_softreset();
aungriah 0:a3b83d366423 137
aungriah 0:a3b83d366423 138 _dwt_enableclocks(FORCE_SYS_XTI); // NOTE: set system clock to XTI - this is necessary to make sure the values read by _dwt_otpread are reliable
aungriah 0:a3b83d366423 139
aungriah 0:a3b83d366423 140 // Configure the CPLL lock detect
aungriah 0:a3b83d366423 141 dwt_write8bitoffsetreg(EXT_SYNC_ID, EC_CTRL_OFFSET, EC_CTRL_PLLLCK);
aungriah 0:a3b83d366423 142
aungriah 0:a3b83d366423 143 // Read OTP revision number
aungriah 0:a3b83d366423 144 otp_addr = _dwt_otpread(XTRIM_ADDRESS) & 0xffff; // Read 32 bit value, XTAL trim val is in low octet-0 (5 bits)
aungriah 0:a3b83d366423 145 dw1000local.otprev = (otp_addr >> 8) & 0xff; // OTP revision is next byte
aungriah 0:a3b83d366423 146
aungriah 0:a3b83d366423 147 // Load LDO tune from OTP and kick it if there is a value actually programmed.
aungriah 0:a3b83d366423 148 ldo_tune = _dwt_otpread(LDOTUNE_ADDRESS);
aungriah 0:a3b83d366423 149 if((ldo_tune & 0xFF) != 0)
aungriah 0:a3b83d366423 150 {
aungriah 0:a3b83d366423 151 // Kick LDO tune
aungriah 0:a3b83d366423 152 dwt_write8bitoffsetreg(OTP_IF_ID, OTP_SF, OTP_SF_LDO_KICK); // Set load LDE kick bit
aungriah 0:a3b83d366423 153 dw1000local.sleep_mode |= AON_WCFG_ONW_LLDO; // LDO tune must be kicked at wake-up
aungriah 0:a3b83d366423 154 }
aungriah 0:a3b83d366423 155
aungriah 0:a3b83d366423 156 // Load Part and Lot ID from OTP
aungriah 0:a3b83d366423 157 dw1000local.partID = _dwt_otpread(PARTID_ADDRESS);
aungriah 0:a3b83d366423 158 dw1000local.lotID = _dwt_otpread(LOTID_ADDRESS);
aungriah 0:a3b83d366423 159
aungriah 0:a3b83d366423 160 // XTAL trim value is set in OTP for DW1000 module and EVK/TREK boards but that might not be the case in a custom design
aungriah 0:a3b83d366423 161 dw1000local.init_xtrim = otp_addr & 0x1F;
aungriah 0:a3b83d366423 162 if (!dw1000local.init_xtrim) // A value of 0 means that the crystal has not been trimmed
aungriah 0:a3b83d366423 163 {
aungriah 0:a3b83d366423 164 dw1000local.init_xtrim = FS_XTALT_MIDRANGE ; // Set to mid-range if no calibration value inside
aungriah 0:a3b83d366423 165 }
aungriah 0:a3b83d366423 166 // Configure XTAL trim
aungriah 0:a3b83d366423 167 dwt_setxtaltrim(dw1000local.init_xtrim);
aungriah 0:a3b83d366423 168
aungriah 0:a3b83d366423 169 // Load leading edge detect code
aungriah 0:a3b83d366423 170 if(config & DWT_LOADUCODE)
aungriah 0:a3b83d366423 171 {
aungriah 0:a3b83d366423 172 _dwt_loaducodefromrom();
aungriah 0:a3b83d366423 173 dw1000local.sleep_mode |= AON_WCFG_ONW_LLDE; // microcode must be loaded at wake-up
aungriah 0:a3b83d366423 174 }
aungriah 0:a3b83d366423 175 else // Should disable the LDERUN enable bit in 0x36, 0x4
aungriah 0:a3b83d366423 176 {
aungriah 0:a3b83d366423 177 uint16 rega = dwt_read16bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET+1) ;
aungriah 0:a3b83d366423 178 rega &= 0xFDFF ; // Clear LDERUN bit
aungriah 0:a3b83d366423 179 dwt_write16bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET+1, rega) ;
aungriah 0:a3b83d366423 180 }
aungriah 0:a3b83d366423 181
aungriah 0:a3b83d366423 182 _dwt_enableclocks(ENABLE_ALL_SEQ); // Enable clocks for sequencing
aungriah 0:a3b83d366423 183
aungriah 0:a3b83d366423 184 // The 3 bits in AON CFG1 register must be cleared to ensure proper operation of the DW1000 in DEEPSLEEP mode.
aungriah 0:a3b83d366423 185 dwt_write8bitoffsetreg(AON_ID, AON_CFG1_OFFSET, 0x00);
aungriah 0:a3b83d366423 186
aungriah 0:a3b83d366423 187 // Read system register / store local copy
aungriah 0:a3b83d366423 188 dw1000local.sysCFGreg = dwt_read32bitreg(SYS_CFG_ID) ; // Read sysconfig register
aungriah 0:a3b83d366423 189
aungriah 0:a3b83d366423 190 return DWT_SUCCESS ;
aungriah 0:a3b83d366423 191
aungriah 0:a3b83d366423 192 } // end dwt_initialise()
aungriah 0:a3b83d366423 193
aungriah 0:a3b83d366423 194 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 195 * @fn dwt_otprevision()
aungriah 0:a3b83d366423 196 *
aungriah 0:a3b83d366423 197 * @brief This is used to return the read OTP revision
aungriah 0:a3b83d366423 198 *
aungriah 0:a3b83d366423 199 * NOTE: dwt_initialise() must be called prior to this function so that it can return a relevant value.
aungriah 0:a3b83d366423 200 *
aungriah 0:a3b83d366423 201 * input parameters
aungriah 0:a3b83d366423 202 *
aungriah 0:a3b83d366423 203 * output parameters
aungriah 0:a3b83d366423 204 *
aungriah 0:a3b83d366423 205 * returns the read OTP revision value
aungriah 0:a3b83d366423 206 */
aungriah 0:a3b83d366423 207 uint8 dwt_otprevision(void)
aungriah 0:a3b83d366423 208 {
aungriah 0:a3b83d366423 209 return dw1000local.otprev ;
aungriah 0:a3b83d366423 210 }
aungriah 0:a3b83d366423 211
aungriah 0:a3b83d366423 212 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 213 * @fn dwt_setfinegraintxseq()
aungriah 0:a3b83d366423 214 *
aungriah 0:a3b83d366423 215 * @brief This function enables/disables the fine grain TX sequencing (enabled by default).
aungriah 0:a3b83d366423 216 *
aungriah 0:a3b83d366423 217 * input parameters
aungriah 0:a3b83d366423 218 * @param enable - 1 to enable fine grain TX sequencing, 0 to disable it.
aungriah 0:a3b83d366423 219 *
aungriah 0:a3b83d366423 220 * output parameters none
aungriah 0:a3b83d366423 221 *
aungriah 0:a3b83d366423 222 * no return value
aungriah 0:a3b83d366423 223 */
aungriah 0:a3b83d366423 224 void dwt_setfinegraintxseq(int enable)
aungriah 0:a3b83d366423 225 {
aungriah 0:a3b83d366423 226 if (enable)
aungriah 0:a3b83d366423 227 {
aungriah 0:a3b83d366423 228 dwt_write16bitoffsetreg(PMSC_ID, PMSC_TXFINESEQ_OFFSET, PMSC_TXFINESEQ_ENABLE);
aungriah 0:a3b83d366423 229 }
aungriah 0:a3b83d366423 230 else
aungriah 0:a3b83d366423 231 {
aungriah 0:a3b83d366423 232 dwt_write16bitoffsetreg(PMSC_ID, PMSC_TXFINESEQ_OFFSET, PMSC_TXFINESEQ_DISABLE);
aungriah 0:a3b83d366423 233 }
aungriah 0:a3b83d366423 234 }
aungriah 0:a3b83d366423 235
aungriah 0:a3b83d366423 236 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 237 * @fn dwt_setlnapamode()
aungriah 0:a3b83d366423 238 *
aungriah 0:a3b83d366423 239 * @brief This is used to enable GPIO for external LNA or PA functionality - HW dependent, consult the DW1000 User Manual.
aungriah 0:a3b83d366423 240 * This can also be used for debug as enabling TX and RX GPIOs is quite handy to monitor DW1000's activity.
aungriah 0:a3b83d366423 241 *
aungriah 0:a3b83d366423 242 * NOTE: Enabling PA functionality requires that fine grain TX sequencing is deactivated. This can be done using
aungriah 0:a3b83d366423 243 * dwt_setfinegraintxseq().
aungriah 0:a3b83d366423 244 *
aungriah 0:a3b83d366423 245 * input parameters
aungriah 0:a3b83d366423 246 * @param lna - 1 to enable LNA functionality, 0 to disable it
aungriah 0:a3b83d366423 247 * @param pa - 1 to enable PA functionality, 0 to disable it
aungriah 0:a3b83d366423 248 *
aungriah 0:a3b83d366423 249 * output parameters
aungriah 0:a3b83d366423 250 *
aungriah 0:a3b83d366423 251 * no return value
aungriah 0:a3b83d366423 252 */
aungriah 0:a3b83d366423 253 void dwt_setlnapamode(int lna, int pa)
aungriah 0:a3b83d366423 254 {
aungriah 0:a3b83d366423 255 uint32 gpio_mode = dwt_read32bitoffsetreg(GPIO_CTRL_ID, GPIO_MODE_OFFSET);
aungriah 0:a3b83d366423 256 gpio_mode &= ~(GPIO_MSGP4_MASK | GPIO_MSGP5_MASK | GPIO_MSGP6_MASK);
aungriah 0:a3b83d366423 257 if (lna)
aungriah 0:a3b83d366423 258 {
aungriah 0:a3b83d366423 259 gpio_mode |= GPIO_PIN6_EXTRXE;
aungriah 0:a3b83d366423 260 }
aungriah 0:a3b83d366423 261 if (pa)
aungriah 0:a3b83d366423 262 {
aungriah 0:a3b83d366423 263 gpio_mode |= (GPIO_PIN5_EXTTXE | GPIO_PIN4_EXTPA);
aungriah 0:a3b83d366423 264 }
aungriah 0:a3b83d366423 265 dwt_write32bitoffsetreg(GPIO_CTRL_ID, GPIO_MODE_OFFSET, gpio_mode);
aungriah 0:a3b83d366423 266 }
aungriah 0:a3b83d366423 267
aungriah 0:a3b83d366423 268 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 269 * @fn dwt_setgpiodirection()
aungriah 0:a3b83d366423 270 *
aungriah 0:a3b83d366423 271 * @brief This is used to set GPIO direction as an input (1) or output (0)
aungriah 0:a3b83d366423 272 *
aungriah 0:a3b83d366423 273 * input parameters
aungriah 0:a3b83d366423 274 * @param gpioNum - this is the GPIO to configure - see GxM0... GxM8 in the deca_regs.h file
aungriah 0:a3b83d366423 275 * @param direction - this sets the GPIO direction - see GxP0... GxP8 in the deca_regs.h file
aungriah 0:a3b83d366423 276 *
aungriah 0:a3b83d366423 277 * output parameters
aungriah 0:a3b83d366423 278 *
aungriah 0:a3b83d366423 279 * no return value
aungriah 0:a3b83d366423 280 */
aungriah 0:a3b83d366423 281 void dwt_setgpiodirection(uint32 gpioNum, uint32 direction)
aungriah 0:a3b83d366423 282 {
aungriah 0:a3b83d366423 283 uint8 buf[GPIO_DIR_LEN];
aungriah 0:a3b83d366423 284 uint32 command = direction | gpioNum;
aungriah 0:a3b83d366423 285
aungriah 0:a3b83d366423 286 buf[0] = command & 0xff;
aungriah 0:a3b83d366423 287 buf[1] = (command >> 8) & 0xff;
aungriah 0:a3b83d366423 288 buf[2] = (command >> 16) & 0xff;
aungriah 0:a3b83d366423 289
aungriah 0:a3b83d366423 290 dwt_writetodevice(GPIO_CTRL_ID, GPIO_DIR_OFFSET, GPIO_DIR_LEN, buf);
aungriah 0:a3b83d366423 291 }
aungriah 0:a3b83d366423 292
aungriah 0:a3b83d366423 293 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 294 * @fn dwt_setgpiovalue()
aungriah 0:a3b83d366423 295 *
aungriah 0:a3b83d366423 296 * @brief This is used to set GPIO value as (1) or (0) only applies if the GPIO is configured as output
aungriah 0:a3b83d366423 297 *
aungriah 0:a3b83d366423 298 * input parameters
aungriah 0:a3b83d366423 299 * @param gpioNum - this is the GPIO to configure - see GxM0... GxM8 in the deca_regs.h file
aungriah 0:a3b83d366423 300 * @param value - this sets the GPIO value - see GDP0... GDP8 in the deca_regs.h file
aungriah 0:a3b83d366423 301 *
aungriah 0:a3b83d366423 302 * output parameters
aungriah 0:a3b83d366423 303 *
aungriah 0:a3b83d366423 304 * no return value
aungriah 0:a3b83d366423 305 */
aungriah 0:a3b83d366423 306 void dwt_setgpiovalue(uint32 gpioNum, uint32 value)
aungriah 0:a3b83d366423 307 {
aungriah 0:a3b83d366423 308 uint8 buf[GPIO_DOUT_LEN];
aungriah 0:a3b83d366423 309 uint32 command = value | gpioNum;
aungriah 0:a3b83d366423 310
aungriah 0:a3b83d366423 311 buf[0] = command & 0xff;
aungriah 0:a3b83d366423 312 buf[1] = (command >> 8) & 0xff;
aungriah 0:a3b83d366423 313 buf[2] = (command >> 16) & 0xff;
aungriah 0:a3b83d366423 314
aungriah 0:a3b83d366423 315 dwt_writetodevice(GPIO_CTRL_ID, GPIO_DOUT_OFFSET, GPIO_DOUT_LEN, buf);
aungriah 0:a3b83d366423 316 }
aungriah 0:a3b83d366423 317
aungriah 0:a3b83d366423 318 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 319 * @fn dwt_getpartid()
aungriah 0:a3b83d366423 320 *
aungriah 0:a3b83d366423 321 * @brief This is used to return the read part ID of the device
aungriah 0:a3b83d366423 322 *
aungriah 0:a3b83d366423 323 * NOTE: dwt_initialise() must be called prior to this function so that it can return a relevant value.
aungriah 0:a3b83d366423 324 *
aungriah 0:a3b83d366423 325 * input parameters
aungriah 0:a3b83d366423 326 *
aungriah 0:a3b83d366423 327 * output parameters
aungriah 0:a3b83d366423 328 *
aungriah 0:a3b83d366423 329 * returns the 32 bit part ID value as programmed in the factory
aungriah 0:a3b83d366423 330 */
aungriah 0:a3b83d366423 331 uint32 dwt_getpartid(void)
aungriah 0:a3b83d366423 332 {
aungriah 0:a3b83d366423 333 return dw1000local.partID;
aungriah 0:a3b83d366423 334 }
aungriah 0:a3b83d366423 335
aungriah 0:a3b83d366423 336 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 337 * @fn dwt_getlotid()
aungriah 0:a3b83d366423 338 *
aungriah 0:a3b83d366423 339 * @brief This is used to return the read lot ID of the device
aungriah 0:a3b83d366423 340 *
aungriah 0:a3b83d366423 341 * NOTE: dwt_initialise() must be called prior to this function so that it can return a relevant value.
aungriah 0:a3b83d366423 342 *
aungriah 0:a3b83d366423 343 * input parameters
aungriah 0:a3b83d366423 344 *
aungriah 0:a3b83d366423 345 * output parameters
aungriah 0:a3b83d366423 346 *
aungriah 0:a3b83d366423 347 * returns the 32 bit lot ID value as programmed in the factory
aungriah 0:a3b83d366423 348 */
aungriah 0:a3b83d366423 349 uint32 dwt_getlotid(void)
aungriah 0:a3b83d366423 350 {
aungriah 0:a3b83d366423 351 return dw1000local.lotID;
aungriah 0:a3b83d366423 352 }
aungriah 0:a3b83d366423 353
aungriah 0:a3b83d366423 354 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 355 * @fn dwt_readdevid()
aungriah 0:a3b83d366423 356 *
aungriah 0:a3b83d366423 357 * @brief This is used to return the read device type and revision information of the DW1000 device (MP part is 0xDECA0130)
aungriah 0:a3b83d366423 358 *
aungriah 0:a3b83d366423 359 * input parameters
aungriah 0:a3b83d366423 360 *
aungriah 0:a3b83d366423 361 * output parameters
aungriah 0:a3b83d366423 362 *
aungriah 0:a3b83d366423 363 * returns the read value which for DW1000 is 0xDECA0130
aungriah 0:a3b83d366423 364 */
aungriah 0:a3b83d366423 365 uint32 dwt_readdevid(void)
aungriah 0:a3b83d366423 366 {
aungriah 0:a3b83d366423 367 return dwt_read32bitoffsetreg(DEV_ID_ID,0);
aungriah 0:a3b83d366423 368 }
aungriah 0:a3b83d366423 369
aungriah 0:a3b83d366423 370 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 371 * @fn dwt_configuretxrf()
aungriah 0:a3b83d366423 372 *
aungriah 0:a3b83d366423 373 * @brief This function provides the API for the configuration of the TX spectrum
aungriah 0:a3b83d366423 374 * including the power and pulse generator delay. The input is a pointer to the data structure
aungriah 0:a3b83d366423 375 * of type dwt_txconfig_t that holds all the configurable items.
aungriah 0:a3b83d366423 376 *
aungriah 0:a3b83d366423 377 * input parameters
aungriah 0:a3b83d366423 378 * @param config - pointer to the txrf configuration structure, which contains the tx rf config data
aungriah 0:a3b83d366423 379 *
aungriah 0:a3b83d366423 380 * output parameters
aungriah 0:a3b83d366423 381 *
aungriah 0:a3b83d366423 382 * no return value
aungriah 0:a3b83d366423 383 */
aungriah 0:a3b83d366423 384 void dwt_configuretxrf(dwt_txconfig_t *config)
aungriah 0:a3b83d366423 385 {
aungriah 0:a3b83d366423 386
aungriah 0:a3b83d366423 387 // Configure RF TX PG_DELAY
aungriah 0:a3b83d366423 388 dwt_write8bitoffsetreg(TX_CAL_ID, TC_PGDELAY_OFFSET, config->PGdly);
aungriah 0:a3b83d366423 389
aungriah 0:a3b83d366423 390 // Configure TX power
aungriah 0:a3b83d366423 391 dwt_write32bitreg(TX_POWER_ID, config->power);
aungriah 0:a3b83d366423 392
aungriah 0:a3b83d366423 393 }
aungriah 0:a3b83d366423 394
aungriah 0:a3b83d366423 395 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 396 * @fn dwt_configure()
aungriah 0:a3b83d366423 397 *
aungriah 0:a3b83d366423 398 * @brief This function provides the main API for the configuration of the
aungriah 0:a3b83d366423 399 * DW1000 and this low-level driver. The input is a pointer to the data structure
aungriah 0:a3b83d366423 400 * of type dwt_config_t that holds all the configurable items.
aungriah 0:a3b83d366423 401 * The dwt_config_t structure shows which ones are supported
aungriah 0:a3b83d366423 402 *
aungriah 0:a3b83d366423 403 * input parameters
aungriah 0:a3b83d366423 404 * @param config - pointer to the configuration structure, which contains the device configuration data.
aungriah 0:a3b83d366423 405 *
aungriah 0:a3b83d366423 406 * output parameters
aungriah 0:a3b83d366423 407 *
aungriah 0:a3b83d366423 408 * no return value
aungriah 0:a3b83d366423 409 */
aungriah 0:a3b83d366423 410 void dwt_configure(dwt_config_t *config)
aungriah 0:a3b83d366423 411 {
aungriah 0:a3b83d366423 412 uint8 chan = config->chan ;
aungriah 0:a3b83d366423 413 uint32 regval ;
aungriah 0:a3b83d366423 414 uint16 reg16 = lde_replicaCoeff[config->rxCode];
aungriah 0:a3b83d366423 415 uint8 prfIndex = config->prf - DWT_PRF_16M;
aungriah 0:a3b83d366423 416 uint8 bw = ((chan == 4) || (chan == 7)) ? 1 : 0 ; // Select wide or narrow band
aungriah 0:a3b83d366423 417
aungriah 0:a3b83d366423 418 #ifdef DWT_API_ERROR_CHECK
aungriah 0:a3b83d366423 419 assert(config->dataRate <= DWT_BR_6M8);
aungriah 0:a3b83d366423 420 assert(config->rxPAC <= DWT_PAC64);
aungriah 0:a3b83d366423 421 assert((chan >= 1) && (chan <= 7) && (chan != 6));
aungriah 0:a3b83d366423 422 assert(((config->prf == DWT_PRF_64M) && (config->txCode >= 9) && (config->txCode <= 24))
aungriah 0:a3b83d366423 423 || ((config->prf == DWT_PRF_16M) && (config->txCode >= 1) && (config->txCode <= 8)));
aungriah 0:a3b83d366423 424 assert(((config->prf == DWT_PRF_64M) && (config->rxCode >= 9) && (config->rxCode <= 24))
aungriah 0:a3b83d366423 425 || ((config->prf == DWT_PRF_16M) && (config->rxCode >= 1) && (config->rxCode <= 8)));
aungriah 0:a3b83d366423 426 assert((config->txPreambLength == DWT_PLEN_64) || (config->txPreambLength == DWT_PLEN_128) || (config->txPreambLength == DWT_PLEN_256)
aungriah 0:a3b83d366423 427 || (config->txPreambLength == DWT_PLEN_512) || (config->txPreambLength == DWT_PLEN_1024) || (config->txPreambLength == DWT_PLEN_1536)
aungriah 0:a3b83d366423 428 || (config->txPreambLength == DWT_PLEN_2048) || (config->txPreambLength == DWT_PLEN_4096));
aungriah 0:a3b83d366423 429 assert((config->phrMode == DWT_PHRMODE_STD) || (config->phrMode == DWT_PHRMODE_EXT));
aungriah 0:a3b83d366423 430 #endif
aungriah 0:a3b83d366423 431
aungriah 0:a3b83d366423 432 // For 110 kbps we need a special setup
aungriah 0:a3b83d366423 433 if(DWT_BR_110K == config->dataRate)
aungriah 0:a3b83d366423 434 {
aungriah 0:a3b83d366423 435 dw1000local.sysCFGreg |= SYS_CFG_RXM110K ;
aungriah 0:a3b83d366423 436 reg16 >>= 3; // lde_replicaCoeff must be divided by 8
aungriah 0:a3b83d366423 437 }
aungriah 0:a3b83d366423 438 else
aungriah 0:a3b83d366423 439 {
aungriah 0:a3b83d366423 440 dw1000local.sysCFGreg &= (~SYS_CFG_RXM110K) ;
aungriah 0:a3b83d366423 441 }
aungriah 0:a3b83d366423 442
aungriah 0:a3b83d366423 443 dw1000local.longFrames = config->phrMode ;
aungriah 0:a3b83d366423 444
aungriah 0:a3b83d366423 445 dw1000local.sysCFGreg &= ~SYS_CFG_PHR_MODE_11;
aungriah 0:a3b83d366423 446 dw1000local.sysCFGreg |= (SYS_CFG_PHR_MODE_11 & (config->phrMode << SYS_CFG_PHR_MODE_SHFT));
aungriah 0:a3b83d366423 447
aungriah 0:a3b83d366423 448 dwt_write32bitreg(SYS_CFG_ID,dw1000local.sysCFGreg) ;
aungriah 0:a3b83d366423 449 // Set the lde_replicaCoeff
aungriah 0:a3b83d366423 450 dwt_write16bitoffsetreg(LDE_IF_ID, LDE_REPC_OFFSET, reg16) ;
aungriah 0:a3b83d366423 451
aungriah 0:a3b83d366423 452 _dwt_configlde(prfIndex);
aungriah 0:a3b83d366423 453
aungriah 0:a3b83d366423 454 // Configure PLL2/RF PLL block CFG/TUNE (for a given channel)
aungriah 0:a3b83d366423 455 dwt_write32bitoffsetreg(FS_CTRL_ID, FS_PLLCFG_OFFSET, fs_pll_cfg[chan_idx[chan]]);
aungriah 0:a3b83d366423 456 dwt_write8bitoffsetreg(FS_CTRL_ID, FS_PLLTUNE_OFFSET, fs_pll_tune[chan_idx[chan]]);
aungriah 0:a3b83d366423 457
aungriah 0:a3b83d366423 458 // Configure RF RX blocks (for specified channel/bandwidth)
aungriah 0:a3b83d366423 459 dwt_write8bitoffsetreg(RF_CONF_ID, RF_RXCTRLH_OFFSET, rx_config[bw]);
aungriah 0:a3b83d366423 460
aungriah 0:a3b83d366423 461 // Configure RF TX blocks (for specified channel and PRF)
aungriah 0:a3b83d366423 462 // Configure RF TX control
aungriah 0:a3b83d366423 463 dwt_write32bitoffsetreg(RF_CONF_ID, RF_TXCTRL_OFFSET, tx_config[chan_idx[chan]]);
aungriah 0:a3b83d366423 464
aungriah 0:a3b83d366423 465 // Configure the baseband parameters (for specified PRF, bit rate, PAC, and SFD settings)
aungriah 0:a3b83d366423 466 // DTUNE0
aungriah 0:a3b83d366423 467 dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_TUNE0b_OFFSET, sftsh[config->dataRate][config->nsSFD]);
aungriah 0:a3b83d366423 468
aungriah 0:a3b83d366423 469 // DTUNE1
aungriah 0:a3b83d366423 470 dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_TUNE1a_OFFSET, dtune1[prfIndex]);
aungriah 0:a3b83d366423 471
aungriah 0:a3b83d366423 472 if(config->dataRate == DWT_BR_110K)
aungriah 0:a3b83d366423 473 {
aungriah 0:a3b83d366423 474 dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_TUNE1b_OFFSET, DRX_TUNE1b_110K);
aungriah 0:a3b83d366423 475 }
aungriah 0:a3b83d366423 476 else
aungriah 0:a3b83d366423 477 {
aungriah 0:a3b83d366423 478 if(config->txPreambLength == DWT_PLEN_64)
aungriah 0:a3b83d366423 479 {
aungriah 0:a3b83d366423 480 dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_TUNE1b_OFFSET, DRX_TUNE1b_6M8_PRE64);
aungriah 0:a3b83d366423 481 dwt_write8bitoffsetreg(DRX_CONF_ID, DRX_TUNE4H_OFFSET, DRX_TUNE4H_PRE64);
aungriah 0:a3b83d366423 482 }
aungriah 0:a3b83d366423 483 else
aungriah 0:a3b83d366423 484 {
aungriah 0:a3b83d366423 485 dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_TUNE1b_OFFSET, DRX_TUNE1b_850K_6M8);
aungriah 0:a3b83d366423 486 dwt_write8bitoffsetreg(DRX_CONF_ID, DRX_TUNE4H_OFFSET, DRX_TUNE4H_PRE128PLUS);
aungriah 0:a3b83d366423 487 }
aungriah 0:a3b83d366423 488 }
aungriah 0:a3b83d366423 489
aungriah 0:a3b83d366423 490 // DTUNE2
aungriah 0:a3b83d366423 491 dwt_write32bitoffsetreg(DRX_CONF_ID, DRX_TUNE2_OFFSET, digital_bb_config[prfIndex][config->rxPAC]);
aungriah 0:a3b83d366423 492
aungriah 0:a3b83d366423 493 // DTUNE3 (SFD timeout)
aungriah 0:a3b83d366423 494 // Don't allow 0 - SFD timeout will always be enabled
aungriah 0:a3b83d366423 495 if(config->sfdTO == 0)
aungriah 0:a3b83d366423 496 {
aungriah 0:a3b83d366423 497 config->sfdTO = DWT_SFDTOC_DEF;
aungriah 0:a3b83d366423 498 }
aungriah 0:a3b83d366423 499 dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_SFDTOC_OFFSET, config->sfdTO);
aungriah 0:a3b83d366423 500
aungriah 0:a3b83d366423 501 // Configure AGC parameters
aungriah 0:a3b83d366423 502 dwt_write32bitoffsetreg( AGC_CFG_STS_ID, 0xC, agc_config.lo32);
aungriah 0:a3b83d366423 503 dwt_write16bitoffsetreg( AGC_CFG_STS_ID, 0x4, agc_config.target[prfIndex]);
aungriah 0:a3b83d366423 504
aungriah 0:a3b83d366423 505 // Set (non-standard) user SFD for improved performance,
aungriah 0:a3b83d366423 506 if(config->nsSFD)
aungriah 0:a3b83d366423 507 {
aungriah 0:a3b83d366423 508 // Write non standard (DW) SFD length
aungriah 0:a3b83d366423 509 dwt_write8bitoffsetreg(USR_SFD_ID, 0x00, dwnsSFDlen[config->dataRate]);
aungriah 0:a3b83d366423 510 }
aungriah 0:a3b83d366423 511 regval = (CHAN_CTRL_TX_CHAN_MASK & (chan << CHAN_CTRL_TX_CHAN_SHIFT)) | // Transmit Channel
aungriah 0:a3b83d366423 512 (CHAN_CTRL_RX_CHAN_MASK & (chan << CHAN_CTRL_RX_CHAN_SHIFT)) | // Receive Channel
aungriah 0:a3b83d366423 513 (CHAN_CTRL_RXFPRF_MASK & (config->prf << CHAN_CTRL_RXFPRF_SHIFT)) | // RX PRF
aungriah 0:a3b83d366423 514 (CHAN_CTRL_DWSFD & (config->nsSFD << CHAN_CTRL_DWSFD_SHIFT)) | // Use DW nsSFD
aungriah 0:a3b83d366423 515 (CHAN_CTRL_TX_PCOD_MASK & (config->txCode << CHAN_CTRL_TX_PCOD_SHIFT)) | // TX Preamble Code
aungriah 0:a3b83d366423 516 (CHAN_CTRL_RX_PCOD_MASK & (config->rxCode << CHAN_CTRL_RX_PCOD_SHIFT)) ; // RX Preamble Code
aungriah 0:a3b83d366423 517
aungriah 0:a3b83d366423 518 dwt_write32bitreg(CHAN_CTRL_ID,regval) ;
aungriah 0:a3b83d366423 519
aungriah 0:a3b83d366423 520 // Set up TX Preamble Size, PRF and Data Rate
aungriah 0:a3b83d366423 521 dw1000local.txFCTRL = ((config->txPreambLength | config->prf) << TX_FCTRL_TXPRF_SHFT) | (config->dataRate << TX_FCTRL_TXBR_SHFT);
aungriah 0:a3b83d366423 522 dwt_write32bitreg(TX_FCTRL_ID, dw1000local.txFCTRL);
aungriah 0:a3b83d366423 523
aungriah 0:a3b83d366423 524 // The SFD transmit pattern is initialised by the DW1000 upon a user TX request, but (due to an IC issue) it is not done for an auto-ACK TX. The
aungriah 0:a3b83d366423 525 // SYS_CTRL write below works around this issue, by simultaneously initiating and aborting a transmission, which correctly initialises the SFD
aungriah 0:a3b83d366423 526 // after its configuration or reconfiguration.
aungriah 0:a3b83d366423 527 // This issue is not documented at the time of writing this code. It should be in next release of DW1000 User Manual (v2.09, from July 2016).
aungriah 0:a3b83d366423 528 dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, SYS_CTRL_TXSTRT | SYS_CTRL_TRXOFF); // Request TX start and TRX off at the same time
aungriah 0:a3b83d366423 529 } // end dwt_configure()
aungriah 0:a3b83d366423 530
aungriah 0:a3b83d366423 531 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 532 * @fn dwt_setrxantennadelay()
aungriah 0:a3b83d366423 533 *
aungriah 0:a3b83d366423 534 * @brief This API function writes the antenna delay (in time units) to RX registers
aungriah 0:a3b83d366423 535 *
aungriah 0:a3b83d366423 536 * input parameters:
aungriah 0:a3b83d366423 537 * @param rxDelay - this is the total (RX) antenna delay value, which
aungriah 0:a3b83d366423 538 * will be programmed into the RX register
aungriah 0:a3b83d366423 539 *
aungriah 0:a3b83d366423 540 * output parameters
aungriah 0:a3b83d366423 541 *
aungriah 0:a3b83d366423 542 * no return value
aungriah 0:a3b83d366423 543 */
aungriah 0:a3b83d366423 544 void dwt_setrxantennadelay(uint16 rxDelay)
aungriah 0:a3b83d366423 545 {
aungriah 0:a3b83d366423 546 // Set the RX antenna delay for auto TX timestamp adjustment
aungriah 0:a3b83d366423 547 dwt_write16bitoffsetreg(LDE_IF_ID, LDE_RXANTD_OFFSET, rxDelay);
aungriah 0:a3b83d366423 548 }
aungriah 0:a3b83d366423 549
aungriah 0:a3b83d366423 550 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 551 * @fn dwt_settxantennadelay()
aungriah 0:a3b83d366423 552 *
aungriah 0:a3b83d366423 553 * @brief This API function writes the antenna delay (in time units) to TX registers
aungriah 0:a3b83d366423 554 *
aungriah 0:a3b83d366423 555 * input parameters:
aungriah 0:a3b83d366423 556 * @param txDelay - this is the total (TX) antenna delay value, which
aungriah 0:a3b83d366423 557 * will be programmed into the TX delay register
aungriah 0:a3b83d366423 558 *
aungriah 0:a3b83d366423 559 * output parameters
aungriah 0:a3b83d366423 560 *
aungriah 0:a3b83d366423 561 * no return value
aungriah 0:a3b83d366423 562 */
aungriah 0:a3b83d366423 563 void dwt_settxantennadelay(uint16 txDelay)
aungriah 0:a3b83d366423 564 {
aungriah 0:a3b83d366423 565 // Set the TX antenna delay for auto TX timestamp adjustment
aungriah 0:a3b83d366423 566 dwt_write16bitoffsetreg(TX_ANTD_ID, TX_ANTD_OFFSET, txDelay);
aungriah 0:a3b83d366423 567 }
aungriah 0:a3b83d366423 568
aungriah 0:a3b83d366423 569 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 570 * @fn dwt_writetxdata()
aungriah 0:a3b83d366423 571 *
aungriah 0:a3b83d366423 572 * @brief This API function writes the supplied TX data into the DW1000's
aungriah 0:a3b83d366423 573 * TX buffer. The input parameters are the data length in bytes and a pointer
aungriah 0:a3b83d366423 574 * to those data bytes.
aungriah 0:a3b83d366423 575 *
aungriah 0:a3b83d366423 576 * input parameters
aungriah 0:a3b83d366423 577 * @param txFrameLength - This is the total frame length, including the two byte CRC.
aungriah 0:a3b83d366423 578 * Note: this is the length of TX message (including the 2 byte CRC) - max is 1023
aungriah 0:a3b83d366423 579 * standard PHR mode allows up to 127 bytes
aungriah 0:a3b83d366423 580 * if > 127 is programmed, DWT_PHRMODE_EXT needs to be set in the phrMode configuration
aungriah 0:a3b83d366423 581 * see dwt_configure function
aungriah 0:a3b83d366423 582 * @param txFrameBytes - Pointer to the user’s buffer containing the data to send.
aungriah 0:a3b83d366423 583 * @param txBufferOffset - This specifies an offset in the DW1000’s TX Buffer at which to start writing data.
aungriah 0:a3b83d366423 584 *
aungriah 0:a3b83d366423 585 * output parameters
aungriah 0:a3b83d366423 586 *
aungriah 0:a3b83d366423 587 * returns DWT_SUCCESS for success, or DWT_ERROR for error
aungriah 0:a3b83d366423 588 */
aungriah 0:a3b83d366423 589 int dwt_writetxdata(uint16 txFrameLength, uint8 *txFrameBytes, uint16 txBufferOffset)
aungriah 0:a3b83d366423 590 {
aungriah 0:a3b83d366423 591 #ifdef DWT_API_ERROR_CHECK
aungriah 0:a3b83d366423 592 assert(txFrameLength >= 2);
aungriah 0:a3b83d366423 593 assert((dw1000local.longFrames && (txFrameLength <= 1023)) || (txFrameLength <= 127));
aungriah 0:a3b83d366423 594 assert((txBufferOffset + txFrameLength) <= 1024);
aungriah 0:a3b83d366423 595 #endif
aungriah 0:a3b83d366423 596
aungriah 0:a3b83d366423 597 if ((txBufferOffset + txFrameLength) <= 1024)
aungriah 0:a3b83d366423 598 {
aungriah 0:a3b83d366423 599 // Write the data to the IC TX buffer, (-2 bytes for auto generated CRC)
aungriah 0:a3b83d366423 600 dwt_writetodevice( TX_BUFFER_ID, txBufferOffset, txFrameLength-2, txFrameBytes);
aungriah 0:a3b83d366423 601 return DWT_SUCCESS;
aungriah 0:a3b83d366423 602 }
aungriah 0:a3b83d366423 603 else
aungriah 0:a3b83d366423 604 {
aungriah 0:a3b83d366423 605 return DWT_ERROR;
aungriah 0:a3b83d366423 606 }
aungriah 0:a3b83d366423 607 } // end dwt_writetxdata()
aungriah 0:a3b83d366423 608
aungriah 0:a3b83d366423 609 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 610 * @fn dwt_writetxfctrl()
aungriah 0:a3b83d366423 611 *
aungriah 0:a3b83d366423 612 * @brief This API function configures the TX frame control register before the transmission of a frame
aungriah 0:a3b83d366423 613 *
aungriah 0:a3b83d366423 614 * input parameters:
aungriah 0:a3b83d366423 615 * @param txFrameLength - this is the length of TX message (including the 2 byte CRC) - max is 1023
aungriah 0:a3b83d366423 616 * NOTE: standard PHR mode allows up to 127 bytes
aungriah 0:a3b83d366423 617 * if > 127 is programmed, DWT_PHRMODE_EXT needs to be set in the phrMode configuration
aungriah 0:a3b83d366423 618 * see dwt_configure function
aungriah 0:a3b83d366423 619 * @param txBufferOffset - the offset in the tx buffer to start writing the data
aungriah 0:a3b83d366423 620 * @param ranging - 1 if this is a ranging frame, else 0
aungriah 0:a3b83d366423 621 *
aungriah 0:a3b83d366423 622 * output parameters
aungriah 0:a3b83d366423 623 *
aungriah 0:a3b83d366423 624 * no return value
aungriah 0:a3b83d366423 625 */
aungriah 0:a3b83d366423 626 void dwt_writetxfctrl(uint16 txFrameLength, uint16 txBufferOffset, int ranging)
aungriah 0:a3b83d366423 627 {
aungriah 0:a3b83d366423 628
aungriah 0:a3b83d366423 629 #ifdef DWT_API_ERROR_CHECK
aungriah 0:a3b83d366423 630 assert((dw1000local.longFrames && (txFrameLength <= 1023)) || (txFrameLength <= 127));
aungriah 0:a3b83d366423 631 #endif
aungriah 0:a3b83d366423 632
aungriah 0:a3b83d366423 633 // Write the frame length to the TX frame control register
aungriah 0:a3b83d366423 634 // dw1000local.txFCTRL has kept configured bit rate information
aungriah 0:a3b83d366423 635 uint32 reg32 = dw1000local.txFCTRL | txFrameLength | (txBufferOffset << TX_FCTRL_TXBOFFS_SHFT) | (ranging << TX_FCTRL_TR_SHFT);
aungriah 0:a3b83d366423 636 dwt_write32bitreg(TX_FCTRL_ID, reg32);
aungriah 0:a3b83d366423 637 } // end dwt_writetxfctrl()
aungriah 0:a3b83d366423 638
aungriah 0:a3b83d366423 639
aungriah 0:a3b83d366423 640 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 641 * @fn dwt_readrxdata()
aungriah 0:a3b83d366423 642 *
aungriah 0:a3b83d366423 643 * @brief This is used to read the data from the RX buffer, from an offset location give by offset parameter
aungriah 0:a3b83d366423 644 *
aungriah 0:a3b83d366423 645 * input parameters
aungriah 0:a3b83d366423 646 * @param buffer - the buffer into which the data will be read
aungriah 0:a3b83d366423 647 * @param length - the length of data to read (in bytes)
aungriah 0:a3b83d366423 648 * @param rxBufferOffset - the offset in the rx buffer from which to read the data
aungriah 0:a3b83d366423 649 *
aungriah 0:a3b83d366423 650 * output parameters
aungriah 0:a3b83d366423 651 *
aungriah 0:a3b83d366423 652 * no return value
aungriah 0:a3b83d366423 653 */
aungriah 0:a3b83d366423 654 void dwt_readrxdata(uint8 *buffer, uint16 length, uint16 rxBufferOffset)
aungriah 0:a3b83d366423 655 {
aungriah 0:a3b83d366423 656 dwt_readfromdevice(RX_BUFFER_ID,rxBufferOffset,length,buffer) ;
aungriah 0:a3b83d366423 657 }
aungriah 0:a3b83d366423 658
aungriah 0:a3b83d366423 659 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 660 * @fn dwt_readaccdata()
aungriah 0:a3b83d366423 661 *
aungriah 0:a3b83d366423 662 * @brief This is used to read the data from the Accumulator buffer, from an offset location give by offset parameter
aungriah 0:a3b83d366423 663 *
aungriah 0:a3b83d366423 664 * NOTE: Because of an internal memory access delay when reading the accumulator the first octet output is a dummy octet
aungriah 0:a3b83d366423 665 * that should be discarded. This is true no matter what sub-index the read begins at.
aungriah 0:a3b83d366423 666 *
aungriah 0:a3b83d366423 667 * input parameters
aungriah 0:a3b83d366423 668 * @param buffer - the buffer into which the data will be read
aungriah 0:a3b83d366423 669 * @param length - the length of data to read (in bytes)
aungriah 0:a3b83d366423 670 * @param accOffset - the offset in the acc buffer from which to read the data
aungriah 0:a3b83d366423 671 *
aungriah 0:a3b83d366423 672 * output parameters
aungriah 0:a3b83d366423 673 *
aungriah 0:a3b83d366423 674 * no return value
aungriah 0:a3b83d366423 675 */
aungriah 0:a3b83d366423 676 void dwt_readaccdata(uint8 *buffer, uint16 len, uint16 accOffset)
aungriah 0:a3b83d366423 677 {
aungriah 0:a3b83d366423 678 // Force on the ACC clocks if we are sequenced
aungriah 0:a3b83d366423 679 _dwt_enableclocks(READ_ACC_ON);
aungriah 0:a3b83d366423 680
aungriah 0:a3b83d366423 681 dwt_readfromdevice(ACC_MEM_ID,accOffset,len,buffer) ;
aungriah 0:a3b83d366423 682
aungriah 0:a3b83d366423 683 _dwt_enableclocks(READ_ACC_OFF); // Revert clocks back
aungriah 0:a3b83d366423 684 }
aungriah 0:a3b83d366423 685
aungriah 0:a3b83d366423 686 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 687 * @fn dwt_readdiagnostics()
aungriah 0:a3b83d366423 688 *
aungriah 0:a3b83d366423 689 * @brief this function reads the RX signal quality diagnostic data
aungriah 0:a3b83d366423 690 *
aungriah 0:a3b83d366423 691 * input parameters
aungriah 0:a3b83d366423 692 * @param diagnostics - diagnostic structure pointer, this will contain the diagnostic data read from the DW1000
aungriah 0:a3b83d366423 693 *
aungriah 0:a3b83d366423 694 * output parameters
aungriah 0:a3b83d366423 695 *
aungriah 0:a3b83d366423 696 * no return value
aungriah 0:a3b83d366423 697 */
aungriah 0:a3b83d366423 698 void dwt_readdiagnostics(dwt_rxdiag_t *diagnostics)
aungriah 0:a3b83d366423 699 {
aungriah 0:a3b83d366423 700 // Read the HW FP index
aungriah 0:a3b83d366423 701 diagnostics->firstPath = dwt_read16bitoffsetreg(RX_TIME_ID, RX_TIME_FP_INDEX_OFFSET);
aungriah 0:a3b83d366423 702
aungriah 0:a3b83d366423 703 // LDE diagnostic data
aungriah 0:a3b83d366423 704 diagnostics->maxNoise = dwt_read16bitoffsetreg(LDE_IF_ID, LDE_THRESH_OFFSET);
aungriah 0:a3b83d366423 705
aungriah 0:a3b83d366423 706 // Read all 8 bytes in one SPI transaction
aungriah 0:a3b83d366423 707 dwt_readfromdevice(RX_FQUAL_ID, 0x0, 8, (uint8*)&diagnostics->stdNoise);
aungriah 0:a3b83d366423 708
aungriah 0:a3b83d366423 709 diagnostics->firstPathAmp1 = dwt_read16bitoffsetreg(RX_TIME_ID, RX_TIME_FP_AMPL1_OFFSET);
aungriah 0:a3b83d366423 710
aungriah 0:a3b83d366423 711 diagnostics->rxPreamCount = (dwt_read32bitreg(RX_FINFO_ID) & RX_FINFO_RXPACC_MASK) >> RX_FINFO_RXPACC_SHIFT ;
aungriah 0:a3b83d366423 712 }
aungriah 0:a3b83d366423 713
aungriah 0:a3b83d366423 714 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 715 * @fn dwt_readtxtimestamp()
aungriah 0:a3b83d366423 716 *
aungriah 0:a3b83d366423 717 * @brief This is used to read the TX timestamp (adjusted with the programmed antenna delay)
aungriah 0:a3b83d366423 718 *
aungriah 0:a3b83d366423 719 * input parameters
aungriah 0:a3b83d366423 720 * @param timestamp - a pointer to a 5-byte buffer which will store the read TX timestamp time
aungriah 0:a3b83d366423 721 *
aungriah 0:a3b83d366423 722 * output parameters - the timestamp buffer will contain the value after the function call
aungriah 0:a3b83d366423 723 *
aungriah 0:a3b83d366423 724 * no return value
aungriah 0:a3b83d366423 725 */
aungriah 0:a3b83d366423 726 void dwt_readtxtimestamp(uint8 * timestamp)
aungriah 0:a3b83d366423 727 {
aungriah 0:a3b83d366423 728 dwt_readfromdevice(TX_TIME_ID, TX_TIME_TX_STAMP_OFFSET, TX_TIME_TX_STAMP_LEN, timestamp) ; // Read bytes directly into buffer
aungriah 0:a3b83d366423 729 }
aungriah 0:a3b83d366423 730
aungriah 0:a3b83d366423 731 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 732 * @fn dwt_readtxtimestamphi32()
aungriah 0:a3b83d366423 733 *
aungriah 0:a3b83d366423 734 * @brief This is used to read the high 32-bits of the TX timestamp (adjusted with the programmed antenna delay)
aungriah 0:a3b83d366423 735 *
aungriah 0:a3b83d366423 736 * input parameters
aungriah 0:a3b83d366423 737 *
aungriah 0:a3b83d366423 738 * output parameters
aungriah 0:a3b83d366423 739 *
aungriah 0:a3b83d366423 740 * returns high 32-bits of TX timestamp
aungriah 0:a3b83d366423 741 */
aungriah 0:a3b83d366423 742 uint32 dwt_readtxtimestamphi32(void)
aungriah 0:a3b83d366423 743 {
aungriah 0:a3b83d366423 744 return dwt_read32bitoffsetreg(TX_TIME_ID, 1); // Offset is 1 to get the 4 upper bytes out of 5
aungriah 0:a3b83d366423 745 }
aungriah 0:a3b83d366423 746
aungriah 0:a3b83d366423 747 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 748 * @fn dwt_readtxtimestamplo32()
aungriah 0:a3b83d366423 749 *
aungriah 0:a3b83d366423 750 * @brief This is used to read the low 32-bits of the TX timestamp (adjusted with the programmed antenna delay)
aungriah 0:a3b83d366423 751 *
aungriah 0:a3b83d366423 752 * input parameters
aungriah 0:a3b83d366423 753 *
aungriah 0:a3b83d366423 754 * output parameters
aungriah 0:a3b83d366423 755 *
aungriah 0:a3b83d366423 756 * returns low 32-bits of TX timestamp
aungriah 0:a3b83d366423 757 */
aungriah 0:a3b83d366423 758 uint32 dwt_readtxtimestamplo32(void)
aungriah 0:a3b83d366423 759 {
aungriah 0:a3b83d366423 760 return dwt_read32bitreg(TX_TIME_ID); // Read TX TIME as a 32-bit register to get the 4 lower bytes out of 5
aungriah 0:a3b83d366423 761 }
aungriah 0:a3b83d366423 762
aungriah 0:a3b83d366423 763 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 764 * @fn dwt_readrxtimestamp()
aungriah 0:a3b83d366423 765 *
aungriah 0:a3b83d366423 766 * @brief This is used to read the RX timestamp (adjusted time of arrival)
aungriah 0:a3b83d366423 767 *
aungriah 0:a3b83d366423 768 * input parameters
aungriah 0:a3b83d366423 769 * @param timestamp - a pointer to a 5-byte buffer which will store the read RX timestamp time
aungriah 0:a3b83d366423 770 *
aungriah 0:a3b83d366423 771 * output parameters - the timestamp buffer will contain the value after the function call
aungriah 0:a3b83d366423 772 *
aungriah 0:a3b83d366423 773 * no return value
aungriah 0:a3b83d366423 774 */
aungriah 0:a3b83d366423 775 void dwt_readrxtimestamp(uint8 * timestamp)
aungriah 0:a3b83d366423 776 {
aungriah 0:a3b83d366423 777 dwt_readfromdevice(RX_TIME_ID, RX_TIME_RX_STAMP_OFFSET, RX_TIME_RX_STAMP_LEN, timestamp) ; // Get the adjusted time of arrival
aungriah 0:a3b83d366423 778 }
aungriah 0:a3b83d366423 779
aungriah 0:a3b83d366423 780 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 781 * @fn dwt_readrxtimestamphi32()
aungriah 0:a3b83d366423 782 *
aungriah 0:a3b83d366423 783 * @brief This is used to read the high 32-bits of the RX timestamp (adjusted with the programmed antenna delay)
aungriah 0:a3b83d366423 784 *
aungriah 0:a3b83d366423 785 * input parameters
aungriah 0:a3b83d366423 786 *
aungriah 0:a3b83d366423 787 * output parameters
aungriah 0:a3b83d366423 788 *
aungriah 0:a3b83d366423 789 * returns high 32-bits of RX timestamp
aungriah 0:a3b83d366423 790 */
aungriah 0:a3b83d366423 791 uint32 dwt_readrxtimestamphi32(void)
aungriah 0:a3b83d366423 792 {
aungriah 0:a3b83d366423 793 return dwt_read32bitoffsetreg(RX_TIME_ID, 1); // Offset is 1 to get the 4 upper bytes out of 5
aungriah 0:a3b83d366423 794 }
aungriah 0:a3b83d366423 795
aungriah 0:a3b83d366423 796 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 797 * @fn dwt_readrxtimestamplo32()
aungriah 0:a3b83d366423 798 *
aungriah 0:a3b83d366423 799 * @brief This is used to read the low 32-bits of the RX timestamp (adjusted with the programmed antenna delay)
aungriah 0:a3b83d366423 800 *
aungriah 0:a3b83d366423 801 * input parameters
aungriah 0:a3b83d366423 802 *
aungriah 0:a3b83d366423 803 * output parameters
aungriah 0:a3b83d366423 804 *
aungriah 0:a3b83d366423 805 * returns low 32-bits of RX timestamp
aungriah 0:a3b83d366423 806 */
aungriah 0:a3b83d366423 807 uint32 dwt_readrxtimestamplo32(void)
aungriah 0:a3b83d366423 808 {
aungriah 0:a3b83d366423 809 return dwt_read32bitreg(RX_TIME_ID); // Read RX TIME as a 32-bit register to get the 4 lower bytes out of 5
aungriah 0:a3b83d366423 810 }
aungriah 0:a3b83d366423 811
aungriah 0:a3b83d366423 812 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 813 * @fn dwt_readsystimestamphi32()
aungriah 0:a3b83d366423 814 *
aungriah 0:a3b83d366423 815 * @brief This is used to read the high 32-bits of the system time
aungriah 0:a3b83d366423 816 *
aungriah 0:a3b83d366423 817 * input parameters
aungriah 0:a3b83d366423 818 *
aungriah 0:a3b83d366423 819 * output parameters
aungriah 0:a3b83d366423 820 *
aungriah 0:a3b83d366423 821 * returns high 32-bits of system time timestamp
aungriah 0:a3b83d366423 822 */
aungriah 0:a3b83d366423 823 uint32 dwt_readsystimestamphi32(void)
aungriah 0:a3b83d366423 824 {
aungriah 0:a3b83d366423 825 return dwt_read32bitoffsetreg(SYS_TIME_ID, 1); // Offset is 1 to get the 4 upper bytes out of 5
aungriah 0:a3b83d366423 826 }
aungriah 0:a3b83d366423 827
aungriah 0:a3b83d366423 828 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 829 * @fn dwt_readsystime()
aungriah 0:a3b83d366423 830 *
aungriah 0:a3b83d366423 831 * @brief This is used to read the system time
aungriah 0:a3b83d366423 832 *
aungriah 0:a3b83d366423 833 * input parameters
aungriah 0:a3b83d366423 834 * @param timestamp - a pointer to a 5-byte buffer which will store the read system time
aungriah 0:a3b83d366423 835 *
aungriah 0:a3b83d366423 836 * output parameters
aungriah 0:a3b83d366423 837 * @param timestamp - the timestamp buffer will contain the value after the function call
aungriah 0:a3b83d366423 838 *
aungriah 0:a3b83d366423 839 * no return value
aungriah 0:a3b83d366423 840 */
aungriah 0:a3b83d366423 841 void dwt_readsystime(uint8 * timestamp)
aungriah 0:a3b83d366423 842 {
aungriah 0:a3b83d366423 843 dwt_readfromdevice(SYS_TIME_ID, SYS_TIME_OFFSET, SYS_TIME_LEN, timestamp) ;
aungriah 0:a3b83d366423 844 }
aungriah 0:a3b83d366423 845
aungriah 0:a3b83d366423 846 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 847 * @fn dwt_writetodevice()
aungriah 0:a3b83d366423 848 *
aungriah 0:a3b83d366423 849 * @brief this function is used to write to the DW1000 device registers
aungriah 0:a3b83d366423 850 * Notes:
aungriah 0:a3b83d366423 851 * 1. Firstly we create a header (the first byte is a header byte)
aungriah 0:a3b83d366423 852 * a. check if sub index is used, if subindexing is used - set bit-6 to 1 to signify that the sub-index address follows the register index byte
aungriah 0:a3b83d366423 853 * b. set bit-7 (or with 0x80) for write operation
aungriah 0:a3b83d366423 854 * c. if extended sub address index is used (i.e. if index > 127) set bit-7 of the first sub-index byte following the first header byte
aungriah 0:a3b83d366423 855 *
aungriah 0:a3b83d366423 856 * 2. Write the header followed by the data bytes to the DW1000 device
aungriah 0:a3b83d366423 857 *
aungriah 0:a3b83d366423 858 *
aungriah 0:a3b83d366423 859 * input parameters:
aungriah 0:a3b83d366423 860 * @param recordNumber - ID of register file or buffer being accessed
aungriah 0:a3b83d366423 861 * @param index - byte index into register file or buffer being accessed
aungriah 0:a3b83d366423 862 * @param length - number of bytes being written
aungriah 0:a3b83d366423 863 * @param buffer - pointer to buffer containing the 'length' bytes to be written
aungriah 0:a3b83d366423 864 *
aungriah 0:a3b83d366423 865 * output parameters
aungriah 0:a3b83d366423 866 *
aungriah 0:a3b83d366423 867 * no return value
aungriah 0:a3b83d366423 868 */
aungriah 0:a3b83d366423 869 void dwt_writetodevice
aungriah 0:a3b83d366423 870 (
aungriah 0:a3b83d366423 871 uint16 recordNumber,
aungriah 0:a3b83d366423 872 uint16 index,
aungriah 0:a3b83d366423 873 uint32 length,
aungriah 0:a3b83d366423 874 const uint8 *buffer
aungriah 0:a3b83d366423 875 )
aungriah 0:a3b83d366423 876 {
aungriah 0:a3b83d366423 877 uint8 header[3] ; // Buffer to compose header in
aungriah 0:a3b83d366423 878 int cnt = 0; // Counter for length of header
aungriah 0:a3b83d366423 879 #ifdef DWT_API_ERROR_CHECK
aungriah 0:a3b83d366423 880 assert(recordNumber <= 0x3F); // Record number is limited to 6-bits.
aungriah 0:a3b83d366423 881 #endif
aungriah 0:a3b83d366423 882
aungriah 0:a3b83d366423 883 // Write message header selecting WRITE operation and addresses as appropriate (this is one to three bytes long)
aungriah 0:a3b83d366423 884 if (index == 0) // For index of 0, no sub-index is required
aungriah 0:a3b83d366423 885 {
aungriah 0:a3b83d366423 886 header[cnt++] = 0x80 | recordNumber ; // Bit-7 is WRITE operation, bit-6 zero=NO sub-addressing, bits 5-0 is reg file id
aungriah 0:a3b83d366423 887 }
aungriah 0:a3b83d366423 888 else
aungriah 0:a3b83d366423 889 {
aungriah 0:a3b83d366423 890 #ifdef DWT_API_ERROR_CHECK
aungriah 0:a3b83d366423 891 assert((index <= 0x7FFF) && ((index + length) <= 0x7FFF)); // Index and sub-addressable area are limited to 15-bits.
aungriah 0:a3b83d366423 892 #endif
aungriah 0:a3b83d366423 893 header[cnt++] = 0xC0 | recordNumber ; // Bit-7 is WRITE operation, bit-6 one=sub-address follows, bits 5-0 is reg file id
aungriah 0:a3b83d366423 894
aungriah 0:a3b83d366423 895 if (index <= 127) // For non-zero index < 127, just a single sub-index byte is required
aungriah 0:a3b83d366423 896 {
aungriah 0:a3b83d366423 897 header[cnt++] = (uint8)index ; // Bit-7 zero means no extension, bits 6-0 is index.
aungriah 0:a3b83d366423 898 }
aungriah 0:a3b83d366423 899 else
aungriah 0:a3b83d366423 900 {
aungriah 0:a3b83d366423 901 header[cnt++] = 0x80 | (uint8)(index) ; // Bit-7 one means extended index, bits 6-0 is low seven bits of index.
aungriah 0:a3b83d366423 902 header[cnt++] = (uint8) (index >> 7) ; // 8-bit value = high eight bits of index.
aungriah 0:a3b83d366423 903 }
aungriah 0:a3b83d366423 904 }
aungriah 0:a3b83d366423 905
aungriah 0:a3b83d366423 906 // Write it to the SPI
aungriah 0:a3b83d366423 907 writetospi(cnt,header,length,buffer);
aungriah 0:a3b83d366423 908 } // end dwt_writetodevice()
aungriah 0:a3b83d366423 909
aungriah 0:a3b83d366423 910 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 911 * @fn dwt_readfromdevice()
aungriah 0:a3b83d366423 912 *
aungriah 0:a3b83d366423 913 * @brief this function is used to read from the DW1000 device registers
aungriah 0:a3b83d366423 914 * Notes:
aungriah 0:a3b83d366423 915 * 1. Firstly we create a header (the first byte is a header byte)
aungriah 0:a3b83d366423 916 * a. check if sub index is used, if subindexing is used - set bit-6 to 1 to signify that the sub-index address follows the register index byte
aungriah 0:a3b83d366423 917 * b. set bit-7 (or with 0x80) for write operation
aungriah 0:a3b83d366423 918 * c. if extended sub address index is used (i.e. if index > 127) set bit-7 of the first sub-index byte following the first header byte
aungriah 0:a3b83d366423 919 *
aungriah 0:a3b83d366423 920 * 2. Write the header followed by the data bytes to the DW1000 device
aungriah 0:a3b83d366423 921 * 3. Store the read data in the input buffer
aungriah 0:a3b83d366423 922 *
aungriah 0:a3b83d366423 923 * input parameters:
aungriah 0:a3b83d366423 924 * @param recordNumber - ID of register file or buffer being accessed
aungriah 0:a3b83d366423 925 * @param index - byte index into register file or buffer being accessed
aungriah 0:a3b83d366423 926 * @param length - number of bytes being read
aungriah 0:a3b83d366423 927 * @param buffer - pointer to buffer in which to return the read data.
aungriah 0:a3b83d366423 928 *
aungriah 0:a3b83d366423 929 * output parameters
aungriah 0:a3b83d366423 930 *
aungriah 0:a3b83d366423 931 * no return value
aungriah 0:a3b83d366423 932 */
aungriah 0:a3b83d366423 933 void dwt_readfromdevice
aungriah 0:a3b83d366423 934 (
aungriah 0:a3b83d366423 935 uint16 recordNumber,
aungriah 0:a3b83d366423 936 uint16 index,
aungriah 0:a3b83d366423 937 uint32 length,
aungriah 0:a3b83d366423 938 uint8 *buffer
aungriah 0:a3b83d366423 939 )
aungriah 0:a3b83d366423 940 {
aungriah 0:a3b83d366423 941 uint8 header[3] ; // Buffer to compose header in
aungriah 0:a3b83d366423 942 int cnt = 0; // Counter for length of header
aungriah 0:a3b83d366423 943 #ifdef DWT_API_ERROR_CHECK
aungriah 0:a3b83d366423 944 assert(recordNumber <= 0x3F); // Record number is limited to 6-bits.
aungriah 0:a3b83d366423 945 #endif
aungriah 0:a3b83d366423 946
aungriah 0:a3b83d366423 947 // Write message header selecting READ operation and addresses as appropriate (this is one to three bytes long)
aungriah 0:a3b83d366423 948 if (index == 0) // For index of 0, no sub-index is required
aungriah 0:a3b83d366423 949 {
aungriah 0:a3b83d366423 950 header[cnt++] = (uint8) recordNumber ; // Bit-7 zero is READ operation, bit-6 zero=NO sub-addressing, bits 5-0 is reg file id
aungriah 0:a3b83d366423 951 }
aungriah 0:a3b83d366423 952 else
aungriah 0:a3b83d366423 953 {
aungriah 0:a3b83d366423 954 #ifdef DWT_API_ERROR_CHECK
aungriah 0:a3b83d366423 955 assert((index <= 0x7FFF) && ((index + length) <= 0x7FFF)); // Index and sub-addressable area are limited to 15-bits.
aungriah 0:a3b83d366423 956 #endif
aungriah 0:a3b83d366423 957 header[cnt++] = (uint8)(0x40 | recordNumber) ; // Bit-7 zero is READ operation, bit-6 one=sub-address follows, bits 5-0 is reg file id
aungriah 0:a3b83d366423 958
aungriah 0:a3b83d366423 959 if (index <= 127) // For non-zero index < 127, just a single sub-index byte is required
aungriah 0:a3b83d366423 960 {
aungriah 0:a3b83d366423 961 header[cnt++] = (uint8) index ; // Bit-7 zero means no extension, bits 6-0 is index.
aungriah 0:a3b83d366423 962 }
aungriah 0:a3b83d366423 963 else
aungriah 0:a3b83d366423 964 {
aungriah 0:a3b83d366423 965 header[cnt++] = 0x80 | (uint8)(index) ; // Bit-7 one means extended index, bits 6-0 is low seven bits of index.
aungriah 0:a3b83d366423 966 header[cnt++] = (uint8) (index >> 7) ; // 8-bit value = high eight bits of index.
aungriah 0:a3b83d366423 967 }
aungriah 0:a3b83d366423 968 }
aungriah 0:a3b83d366423 969
aungriah 0:a3b83d366423 970 // Do the read from the SPI
aungriah 0:a3b83d366423 971 readfromspi(cnt, header, length, buffer); // result is stored in the buffer
aungriah 0:a3b83d366423 972 } // end dwt_readfromdevice()
aungriah 0:a3b83d366423 973
aungriah 0:a3b83d366423 974
aungriah 0:a3b83d366423 975
aungriah 0:a3b83d366423 976 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 977 * @fn dwt_read32bitoffsetreg()
aungriah 0:a3b83d366423 978 *
aungriah 0:a3b83d366423 979 * @brief this function is used to read 32-bit value from the DW1000 device registers
aungriah 0:a3b83d366423 980 *
aungriah 0:a3b83d366423 981 * input parameters:
aungriah 0:a3b83d366423 982 * @param regFileID - ID of register file or buffer being accessed
aungriah 0:a3b83d366423 983 * @param regOffset - the index into register file or buffer being accessed
aungriah 0:a3b83d366423 984 *
aungriah 0:a3b83d366423 985 * output parameters
aungriah 0:a3b83d366423 986 *
aungriah 0:a3b83d366423 987 * returns 32 bit register value
aungriah 0:a3b83d366423 988 */
aungriah 0:a3b83d366423 989 uint32 dwt_read32bitoffsetreg(int regFileID,int regOffset)
aungriah 0:a3b83d366423 990 {
aungriah 0:a3b83d366423 991 uint32 regval = 0 ;
aungriah 0:a3b83d366423 992 int j ;
aungriah 0:a3b83d366423 993 uint8 buffer[4] ;
aungriah 0:a3b83d366423 994
aungriah 0:a3b83d366423 995 dwt_readfromdevice(regFileID,regOffset,4,buffer); // Read 4 bytes (32-bits) register into buffer
aungriah 0:a3b83d366423 996
aungriah 0:a3b83d366423 997 for (j = 3 ; j >= 0 ; j --)
aungriah 0:a3b83d366423 998 {
aungriah 0:a3b83d366423 999 regval = (regval << 8) + buffer[j] ;
aungriah 0:a3b83d366423 1000 }
aungriah 0:a3b83d366423 1001 return regval ;
aungriah 0:a3b83d366423 1002
aungriah 0:a3b83d366423 1003 } // end dwt_read32bitoffsetreg()
aungriah 0:a3b83d366423 1004
aungriah 0:a3b83d366423 1005 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1006 * @fn dwt_read16bitoffsetreg()
aungriah 0:a3b83d366423 1007 *
aungriah 0:a3b83d366423 1008 * @brief this function is used to read 16-bit value from the DW1000 device registers
aungriah 0:a3b83d366423 1009 *
aungriah 0:a3b83d366423 1010 * input parameters:
aungriah 0:a3b83d366423 1011 * @param regFileID - ID of register file or buffer being accessed
aungriah 0:a3b83d366423 1012 * @param regOffset - the index into register file or buffer being accessed
aungriah 0:a3b83d366423 1013 *
aungriah 0:a3b83d366423 1014 * output parameters
aungriah 0:a3b83d366423 1015 *
aungriah 0:a3b83d366423 1016 * returns 16 bit register value
aungriah 0:a3b83d366423 1017 */
aungriah 0:a3b83d366423 1018 uint16 dwt_read16bitoffsetreg(int regFileID,int regOffset)
aungriah 0:a3b83d366423 1019 {
aungriah 0:a3b83d366423 1020 uint16 regval = 0 ;
aungriah 0:a3b83d366423 1021 uint8 buffer[2] ;
aungriah 0:a3b83d366423 1022
aungriah 0:a3b83d366423 1023 dwt_readfromdevice(regFileID,regOffset,2,buffer); // Read 2 bytes (16-bits) register into buffer
aungriah 0:a3b83d366423 1024
aungriah 0:a3b83d366423 1025 regval = (buffer[1] << 8) + buffer[0] ;
aungriah 0:a3b83d366423 1026 return regval ;
aungriah 0:a3b83d366423 1027
aungriah 0:a3b83d366423 1028 } // end dwt_read16bitoffsetreg()
aungriah 0:a3b83d366423 1029
aungriah 0:a3b83d366423 1030 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1031 * @fn dwt_read8bitoffsetreg()
aungriah 0:a3b83d366423 1032 *
aungriah 0:a3b83d366423 1033 * @brief this function is used to read an 8-bit value from the DW1000 device registers
aungriah 0:a3b83d366423 1034 *
aungriah 0:a3b83d366423 1035 * input parameters:
aungriah 0:a3b83d366423 1036 * @param regFileID - ID of register file or buffer being accessed
aungriah 0:a3b83d366423 1037 * @param regOffset - the index into register file or buffer being accessed
aungriah 0:a3b83d366423 1038 *
aungriah 0:a3b83d366423 1039 * output parameters
aungriah 0:a3b83d366423 1040 *
aungriah 0:a3b83d366423 1041 * returns 8-bit register value
aungriah 0:a3b83d366423 1042 */
aungriah 0:a3b83d366423 1043 uint8 dwt_read8bitoffsetreg(int regFileID, int regOffset)
aungriah 0:a3b83d366423 1044 {
aungriah 0:a3b83d366423 1045 uint8 regval;
aungriah 0:a3b83d366423 1046
aungriah 0:a3b83d366423 1047 dwt_readfromdevice(regFileID, regOffset, 1, &regval);
aungriah 0:a3b83d366423 1048
aungriah 0:a3b83d366423 1049 return regval ;
aungriah 0:a3b83d366423 1050 }
aungriah 0:a3b83d366423 1051
aungriah 0:a3b83d366423 1052 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1053 * @fn dwt_write8bitoffsetreg()
aungriah 0:a3b83d366423 1054 *
aungriah 0:a3b83d366423 1055 * @brief this function is used to write an 8-bit value to the DW1000 device registers
aungriah 0:a3b83d366423 1056 *
aungriah 0:a3b83d366423 1057 * input parameters:
aungriah 0:a3b83d366423 1058 * @param regFileID - ID of register file or buffer being accessed
aungriah 0:a3b83d366423 1059 * @param regOffset - the index into register file or buffer being accessed
aungriah 0:a3b83d366423 1060 * @param regval - the value to write
aungriah 0:a3b83d366423 1061 *
aungriah 0:a3b83d366423 1062 * output parameters
aungriah 0:a3b83d366423 1063 *
aungriah 0:a3b83d366423 1064 * no return value
aungriah 0:a3b83d366423 1065 */
aungriah 0:a3b83d366423 1066 void dwt_write8bitoffsetreg(int regFileID, int regOffset, uint8 regval)
aungriah 0:a3b83d366423 1067 {
aungriah 0:a3b83d366423 1068 dwt_writetodevice(regFileID, regOffset, 1, &regval);
aungriah 0:a3b83d366423 1069 }
aungriah 0:a3b83d366423 1070
aungriah 0:a3b83d366423 1071 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1072 * @fn dwt_write16bitoffsetreg()
aungriah 0:a3b83d366423 1073 *
aungriah 0:a3b83d366423 1074 * @brief this function is used to write 16-bit value to the DW1000 device registers
aungriah 0:a3b83d366423 1075 *
aungriah 0:a3b83d366423 1076 * input parameters:
aungriah 0:a3b83d366423 1077 * @param regFileID - ID of register file or buffer being accessed
aungriah 0:a3b83d366423 1078 * @param regOffset - the index into register file or buffer being accessed
aungriah 0:a3b83d366423 1079 * @param regval - the value to write
aungriah 0:a3b83d366423 1080 *
aungriah 0:a3b83d366423 1081 * output parameters
aungriah 0:a3b83d366423 1082 *
aungriah 0:a3b83d366423 1083 * no return value
aungriah 0:a3b83d366423 1084 */
aungriah 0:a3b83d366423 1085 void dwt_write16bitoffsetreg(int regFileID,int regOffset,uint16 regval)
aungriah 0:a3b83d366423 1086 {
aungriah 0:a3b83d366423 1087 uint8 buffer[2] ;
aungriah 0:a3b83d366423 1088
aungriah 0:a3b83d366423 1089 buffer[0] = regval & 0xFF;
aungriah 0:a3b83d366423 1090 buffer[1] = regval >> 8 ;
aungriah 0:a3b83d366423 1091
aungriah 0:a3b83d366423 1092 dwt_writetodevice(regFileID,regOffset,2,buffer);
aungriah 0:a3b83d366423 1093 } // end dwt_write16bitoffsetreg()
aungriah 0:a3b83d366423 1094
aungriah 0:a3b83d366423 1095 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1096 * @fn dwt_write32bitoffsetreg()
aungriah 0:a3b83d366423 1097 *
aungriah 0:a3b83d366423 1098 * @brief this function is used to write 32-bit value to the DW1000 device registers
aungriah 0:a3b83d366423 1099 *
aungriah 0:a3b83d366423 1100 * input parameters:
aungriah 0:a3b83d366423 1101 * @param regFileID - ID of register file or buffer being accessed
aungriah 0:a3b83d366423 1102 * @param regOffset - the index into register file or buffer being accessed
aungriah 0:a3b83d366423 1103 * @param regval - the value to write
aungriah 0:a3b83d366423 1104 *
aungriah 0:a3b83d366423 1105 * output parameters
aungriah 0:a3b83d366423 1106 *
aungriah 0:a3b83d366423 1107 * no return value
aungriah 0:a3b83d366423 1108 */
aungriah 0:a3b83d366423 1109 void dwt_write32bitoffsetreg(int regFileID,int regOffset,uint32 regval)
aungriah 0:a3b83d366423 1110 {
aungriah 0:a3b83d366423 1111 int j ;
aungriah 0:a3b83d366423 1112 uint8 buffer[4] ;
aungriah 0:a3b83d366423 1113
aungriah 0:a3b83d366423 1114 for ( j = 0 ; j < 4 ; j++ )
aungriah 0:a3b83d366423 1115 {
aungriah 0:a3b83d366423 1116 buffer[j] = regval & 0xff ;
aungriah 0:a3b83d366423 1117 regval >>= 8 ;
aungriah 0:a3b83d366423 1118 }
aungriah 0:a3b83d366423 1119
aungriah 0:a3b83d366423 1120 dwt_writetodevice(regFileID,regOffset,4,buffer);
aungriah 0:a3b83d366423 1121 } // end dwt_write32bitoffsetreg()
aungriah 0:a3b83d366423 1122
aungriah 0:a3b83d366423 1123 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1124 * @fn dwt_enableframefilter()
aungriah 0:a3b83d366423 1125 *
aungriah 0:a3b83d366423 1126 * @brief This is used to enable the frame filtering - (the default option is to
aungriah 0:a3b83d366423 1127 * accept any data and ACK frames with correct destination address
aungriah 0:a3b83d366423 1128 *
aungriah 0:a3b83d366423 1129 * input parameters
aungriah 0:a3b83d366423 1130 * @param - bitmask - enables/disables the frame filtering options according to
aungriah 0:a3b83d366423 1131 * DWT_FF_NOTYPE_EN 0x000 no frame types allowed
aungriah 0:a3b83d366423 1132 * DWT_FF_COORD_EN 0x002 behave as coordinator (can receive frames with no destination address (PAN ID has to match))
aungriah 0:a3b83d366423 1133 * DWT_FF_BEACON_EN 0x004 beacon frames allowed
aungriah 0:a3b83d366423 1134 * DWT_FF_DATA_EN 0x008 data frames allowed
aungriah 0:a3b83d366423 1135 * DWT_FF_ACK_EN 0x010 ack frames allowed
aungriah 0:a3b83d366423 1136 * DWT_FF_MAC_EN 0x020 mac control frames allowed
aungriah 0:a3b83d366423 1137 * DWT_FF_RSVD_EN 0x040 reserved frame types allowed
aungriah 0:a3b83d366423 1138 *
aungriah 0:a3b83d366423 1139 * output parameters
aungriah 0:a3b83d366423 1140 *
aungriah 0:a3b83d366423 1141 * no return value
aungriah 0:a3b83d366423 1142 */
aungriah 0:a3b83d366423 1143 void dwt_enableframefilter(uint16 enable)
aungriah 0:a3b83d366423 1144 {
aungriah 0:a3b83d366423 1145 uint32 sysconfig = SYS_CFG_MASK & dwt_read32bitreg(SYS_CFG_ID) ; // Read sysconfig register
aungriah 0:a3b83d366423 1146
aungriah 0:a3b83d366423 1147 if(enable)
aungriah 0:a3b83d366423 1148 {
aungriah 0:a3b83d366423 1149 // Enable frame filtering and configure frame types
aungriah 0:a3b83d366423 1150 sysconfig &= ~(SYS_CFG_FF_ALL_EN); // Clear all
aungriah 0:a3b83d366423 1151 sysconfig |= (enable & SYS_CFG_FF_ALL_EN) | SYS_CFG_FFE;
aungriah 0:a3b83d366423 1152 }
aungriah 0:a3b83d366423 1153 else
aungriah 0:a3b83d366423 1154 {
aungriah 0:a3b83d366423 1155 sysconfig &= ~(SYS_CFG_FFE);
aungriah 0:a3b83d366423 1156 }
aungriah 0:a3b83d366423 1157
aungriah 0:a3b83d366423 1158 dw1000local.sysCFGreg = sysconfig ;
aungriah 0:a3b83d366423 1159 dwt_write32bitreg(SYS_CFG_ID,sysconfig) ;
aungriah 0:a3b83d366423 1160 }
aungriah 0:a3b83d366423 1161
aungriah 0:a3b83d366423 1162 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1163 * @fn dwt_setpanid()
aungriah 0:a3b83d366423 1164 *
aungriah 0:a3b83d366423 1165 * @brief This is used to set the PAN ID
aungriah 0:a3b83d366423 1166 *
aungriah 0:a3b83d366423 1167 * input parameters
aungriah 0:a3b83d366423 1168 * @param panID - this is the PAN ID
aungriah 0:a3b83d366423 1169 *
aungriah 0:a3b83d366423 1170 * output parameters
aungriah 0:a3b83d366423 1171 *
aungriah 0:a3b83d366423 1172 * no return value
aungriah 0:a3b83d366423 1173 */
aungriah 0:a3b83d366423 1174 void dwt_setpanid(uint16 panID)
aungriah 0:a3b83d366423 1175 {
aungriah 0:a3b83d366423 1176 // PAN ID is high 16 bits of register
aungriah 0:a3b83d366423 1177 dwt_write16bitoffsetreg(PANADR_ID, PANADR_PAN_ID_OFFSET, panID);
aungriah 0:a3b83d366423 1178 }
aungriah 0:a3b83d366423 1179
aungriah 0:a3b83d366423 1180 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1181 * @fn dwt_setaddress16()
aungriah 0:a3b83d366423 1182 *
aungriah 0:a3b83d366423 1183 * @brief This is used to set 16-bit (short) address
aungriah 0:a3b83d366423 1184 *
aungriah 0:a3b83d366423 1185 * input parameters
aungriah 0:a3b83d366423 1186 * @param shortAddress - this sets the 16 bit short address
aungriah 0:a3b83d366423 1187 *
aungriah 0:a3b83d366423 1188 * output parameters
aungriah 0:a3b83d366423 1189 *
aungriah 0:a3b83d366423 1190 * no return value
aungriah 0:a3b83d366423 1191 */
aungriah 0:a3b83d366423 1192 void dwt_setaddress16(uint16 shortAddress)
aungriah 0:a3b83d366423 1193 {
aungriah 0:a3b83d366423 1194 // Short address into low 16 bits
aungriah 0:a3b83d366423 1195 dwt_write16bitoffsetreg(PANADR_ID, PANADR_SHORT_ADDR_OFFSET, shortAddress);
aungriah 0:a3b83d366423 1196 }
aungriah 0:a3b83d366423 1197
aungriah 0:a3b83d366423 1198 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1199 * @fn dwt_seteui()
aungriah 0:a3b83d366423 1200 *
aungriah 0:a3b83d366423 1201 * @brief This is used to set the EUI 64-bit (long) address
aungriah 0:a3b83d366423 1202 *
aungriah 0:a3b83d366423 1203 * input parameters
aungriah 0:a3b83d366423 1204 * @param eui64 - this is the pointer to a buffer that contains the 64bit address
aungriah 0:a3b83d366423 1205 *
aungriah 0:a3b83d366423 1206 * output parameters
aungriah 0:a3b83d366423 1207 *
aungriah 0:a3b83d366423 1208 * no return value
aungriah 0:a3b83d366423 1209 */
aungriah 0:a3b83d366423 1210 void dwt_seteui(uint8 *eui64)
aungriah 0:a3b83d366423 1211 {
aungriah 0:a3b83d366423 1212 dwt_writetodevice(EUI_64_ID, EUI_64_OFFSET, EUI_64_LEN, eui64);
aungriah 0:a3b83d366423 1213 }
aungriah 0:a3b83d366423 1214
aungriah 0:a3b83d366423 1215 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1216 * @fn dwt_geteui()
aungriah 0:a3b83d366423 1217 *
aungriah 0:a3b83d366423 1218 * @brief This is used to get the EUI 64-bit from the DW1000
aungriah 0:a3b83d366423 1219 *
aungriah 0:a3b83d366423 1220 * input parameters
aungriah 0:a3b83d366423 1221 * @param eui64 - this is the pointer to a buffer that will contain the read 64-bit EUI value
aungriah 0:a3b83d366423 1222 *
aungriah 0:a3b83d366423 1223 * output parameters
aungriah 0:a3b83d366423 1224 *
aungriah 0:a3b83d366423 1225 * no return value
aungriah 0:a3b83d366423 1226 */
aungriah 0:a3b83d366423 1227 void dwt_geteui(uint8 *eui64)
aungriah 0:a3b83d366423 1228 {
aungriah 0:a3b83d366423 1229 dwt_readfromdevice(EUI_64_ID, EUI_64_OFFSET, EUI_64_LEN, eui64);
aungriah 0:a3b83d366423 1230 }
aungriah 0:a3b83d366423 1231
aungriah 0:a3b83d366423 1232 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1233 * @fn dwt_otpread()
aungriah 0:a3b83d366423 1234 *
aungriah 0:a3b83d366423 1235 * @brief This is used to read the OTP data from given address into provided array
aungriah 0:a3b83d366423 1236 *
aungriah 0:a3b83d366423 1237 * input parameters
aungriah 0:a3b83d366423 1238 * @param address - this is the OTP address to read from
aungriah 0:a3b83d366423 1239 * @param array - this is the pointer to the array into which to read the data
aungriah 0:a3b83d366423 1240 * @param length - this is the number of 32 bit words to read (array needs to be at least this length)
aungriah 0:a3b83d366423 1241 *
aungriah 0:a3b83d366423 1242 * output parameters
aungriah 0:a3b83d366423 1243 *
aungriah 0:a3b83d366423 1244 * no return value
aungriah 0:a3b83d366423 1245 */
aungriah 0:a3b83d366423 1246 void dwt_otpread(uint32 address, uint32 *array, uint8 length)
aungriah 0:a3b83d366423 1247 {
aungriah 0:a3b83d366423 1248 int i;
aungriah 0:a3b83d366423 1249
aungriah 0:a3b83d366423 1250 _dwt_enableclocks(FORCE_SYS_XTI); // NOTE: Set system clock to XTAL - this is necessary to make sure the values read by _dwt_otpread are reliable
aungriah 0:a3b83d366423 1251
aungriah 0:a3b83d366423 1252 for(i=0; i<length; i++)
aungriah 0:a3b83d366423 1253 {
aungriah 0:a3b83d366423 1254 array[i] = _dwt_otpread(address + i) ;
aungriah 0:a3b83d366423 1255 }
aungriah 0:a3b83d366423 1256
aungriah 0:a3b83d366423 1257 _dwt_enableclocks(ENABLE_ALL_SEQ); // Restore system clock to PLL
aungriah 0:a3b83d366423 1258
aungriah 0:a3b83d366423 1259 return ;
aungriah 0:a3b83d366423 1260 }
aungriah 0:a3b83d366423 1261
aungriah 0:a3b83d366423 1262 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1263 * @fn _dwt_otpread()
aungriah 0:a3b83d366423 1264 *
aungriah 0:a3b83d366423 1265 * @brief function to read the OTP memory. Ensure that MR,MRa,MRb are reset to 0.
aungriah 0:a3b83d366423 1266 *
aungriah 0:a3b83d366423 1267 * input parameters
aungriah 0:a3b83d366423 1268 * @param address - address to read at
aungriah 0:a3b83d366423 1269 *
aungriah 0:a3b83d366423 1270 * output parameters
aungriah 0:a3b83d366423 1271 *
aungriah 0:a3b83d366423 1272 * returns the 32bit of read data
aungriah 0:a3b83d366423 1273 */
aungriah 0:a3b83d366423 1274 uint32 _dwt_otpread(uint32 address)
aungriah 0:a3b83d366423 1275 {
aungriah 0:a3b83d366423 1276 uint32 ret_data;
aungriah 0:a3b83d366423 1277
aungriah 0:a3b83d366423 1278 // Write the address
aungriah 0:a3b83d366423 1279 dwt_write16bitoffsetreg(OTP_IF_ID, OTP_ADDR, address);
aungriah 0:a3b83d366423 1280
aungriah 0:a3b83d366423 1281 // Perform OTP Read - Manual read mode has to be set
aungriah 0:a3b83d366423 1282 dwt_write8bitoffsetreg(OTP_IF_ID, OTP_CTRL, OTP_CTRL_OTPREAD | OTP_CTRL_OTPRDEN);
aungriah 0:a3b83d366423 1283 dwt_write8bitoffsetreg(OTP_IF_ID, OTP_CTRL, 0x00); // OTPREAD is self clearing but OTPRDEN is not
aungriah 0:a3b83d366423 1284
aungriah 0:a3b83d366423 1285 // Read read data, available 40ns after rising edge of OTP_READ
aungriah 0:a3b83d366423 1286 ret_data = dwt_read32bitoffsetreg(OTP_IF_ID, OTP_RDAT);
aungriah 0:a3b83d366423 1287
aungriah 0:a3b83d366423 1288 // Return the 32bit of read data
aungriah 0:a3b83d366423 1289 return ret_data;
aungriah 0:a3b83d366423 1290 }
aungriah 0:a3b83d366423 1291
aungriah 0:a3b83d366423 1292 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1293 * @fn _dwt_otpsetmrregs()
aungriah 0:a3b83d366423 1294 *
aungriah 0:a3b83d366423 1295 * @brief Configure the MR registers for initial programming (enable charge pump).
aungriah 0:a3b83d366423 1296 * Read margin is used to stress the read back from the
aungriah 0:a3b83d366423 1297 * programmed bit. In normal operation this is relaxed.
aungriah 0:a3b83d366423 1298 *
aungriah 0:a3b83d366423 1299 * input parameters
aungriah 0:a3b83d366423 1300 * @param mode - "0" : Reset all to 0x0: MRA=0x0000, MRB=0x0000, MR=0x0000
aungriah 0:a3b83d366423 1301 * "1" : Set for inital programming: MRA=0x9220, MRB=0x000E, MR=0x1024
aungriah 0:a3b83d366423 1302 * "2" : Set for soak programming: MRA=0x9220, MRB=0x0003, MR=0x1824
aungriah 0:a3b83d366423 1303 * "3" : High Vpp: MRA=0x9220, MRB=0x004E, MR=0x1824
aungriah 0:a3b83d366423 1304 * "4" : Low Read Margin: MRA=0x0000, MRB=0x0003, MR=0x0000
aungriah 0:a3b83d366423 1305 * "5" : Array Clean: MRA=0x0049, MRB=0x0003, MR=0x0024
aungriah 0:a3b83d366423 1306 * "4" : Very Low Read Margin: MRA=0x0000, MRB=0x0003, MR=0x0000
aungriah 0:a3b83d366423 1307 *
aungriah 0:a3b83d366423 1308 * output parameters
aungriah 0:a3b83d366423 1309 *
aungriah 0:a3b83d366423 1310 * returns DWT_SUCCESS for success, or DWT_ERROR for error
aungriah 0:a3b83d366423 1311 */
aungriah 0:a3b83d366423 1312 uint32 _dwt_otpsetmrregs(int mode)
aungriah 0:a3b83d366423 1313 {
aungriah 0:a3b83d366423 1314 uint8 rd_buf[4];
aungriah 0:a3b83d366423 1315 uint8 wr_buf[4];
aungriah 0:a3b83d366423 1316 uint32 mra=0,mrb=0,mr=0;
aungriah 0:a3b83d366423 1317
aungriah 0:a3b83d366423 1318 // PROGRAMME MRA
aungriah 0:a3b83d366423 1319 // Set MRA, MODE_SEL
aungriah 0:a3b83d366423 1320 wr_buf[0] = 0x03;
aungriah 0:a3b83d366423 1321 dwt_writetodevice(OTP_IF_ID, OTP_CTRL+1,1,wr_buf);
aungriah 0:a3b83d366423 1322
aungriah 0:a3b83d366423 1323 // Load data
aungriah 0:a3b83d366423 1324 switch(mode&0x0f) {
aungriah 0:a3b83d366423 1325 case 0x0 :
aungriah 0:a3b83d366423 1326 mr =0x0000;
aungriah 0:a3b83d366423 1327 mra=0x0000;
aungriah 0:a3b83d366423 1328 mrb=0x0000;
aungriah 0:a3b83d366423 1329 break;
aungriah 0:a3b83d366423 1330 case 0x1 :
aungriah 0:a3b83d366423 1331 mr =0x1024;
aungriah 0:a3b83d366423 1332 mra=0x9220; // Enable CPP mon
aungriah 0:a3b83d366423 1333 mrb=0x000e;
aungriah 0:a3b83d366423 1334 break;
aungriah 0:a3b83d366423 1335 case 0x2 :
aungriah 0:a3b83d366423 1336 mr =0x1824;
aungriah 0:a3b83d366423 1337 mra=0x9220;
aungriah 0:a3b83d366423 1338 mrb=0x0003;
aungriah 0:a3b83d366423 1339 break;
aungriah 0:a3b83d366423 1340 case 0x3 :
aungriah 0:a3b83d366423 1341 mr =0x1824;
aungriah 0:a3b83d366423 1342 mra=0x9220;
aungriah 0:a3b83d366423 1343 mrb=0x004e;
aungriah 0:a3b83d366423 1344 break;
aungriah 0:a3b83d366423 1345 case 0x4 :
aungriah 0:a3b83d366423 1346 mr =0x0000;
aungriah 0:a3b83d366423 1347 mra=0x0000;
aungriah 0:a3b83d366423 1348 mrb=0x0003;
aungriah 0:a3b83d366423 1349 break;
aungriah 0:a3b83d366423 1350 case 0x5 :
aungriah 0:a3b83d366423 1351 mr =0x0024;
aungriah 0:a3b83d366423 1352 mra=0x0000;
aungriah 0:a3b83d366423 1353 mrb=0x0003;
aungriah 0:a3b83d366423 1354 break;
aungriah 0:a3b83d366423 1355 default :
aungriah 0:a3b83d366423 1356 return DWT_ERROR;
aungriah 0:a3b83d366423 1357 }
aungriah 0:a3b83d366423 1358
aungriah 0:a3b83d366423 1359 wr_buf[0] = mra & 0x00ff;
aungriah 0:a3b83d366423 1360 wr_buf[1] = (mra & 0xff00)>>8;
aungriah 0:a3b83d366423 1361 dwt_writetodevice(OTP_IF_ID, OTP_WDAT,2,wr_buf);
aungriah 0:a3b83d366423 1362
aungriah 0:a3b83d366423 1363
aungriah 0:a3b83d366423 1364 // Set WRITE_MR
aungriah 0:a3b83d366423 1365 wr_buf[0] = 0x08;
aungriah 0:a3b83d366423 1366 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:a3b83d366423 1367
aungriah 0:a3b83d366423 1368 // Wait?
aungriah 0:a3b83d366423 1369
aungriah 0:a3b83d366423 1370 // Set Clear Mode sel
aungriah 0:a3b83d366423 1371 wr_buf[0] = 0x02;
aungriah 0:a3b83d366423 1372 dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
aungriah 0:a3b83d366423 1373
aungriah 0:a3b83d366423 1374 // Set AUX update, write MR
aungriah 0:a3b83d366423 1375 wr_buf[0] = 0x88;
aungriah 0:a3b83d366423 1376 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:a3b83d366423 1377 // Clear write MR
aungriah 0:a3b83d366423 1378 wr_buf[0] = 0x80;
aungriah 0:a3b83d366423 1379 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:a3b83d366423 1380 // Clear AUX update
aungriah 0:a3b83d366423 1381 wr_buf[0] = 0x00;
aungriah 0:a3b83d366423 1382 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:a3b83d366423 1383
aungriah 0:a3b83d366423 1384 ///////////////////////////////////////////
aungriah 0:a3b83d366423 1385 // PROGRAM MRB
aungriah 0:a3b83d366423 1386 // Set SLOW, MRB, MODE_SEL
aungriah 0:a3b83d366423 1387 wr_buf[0] = 0x05;
aungriah 0:a3b83d366423 1388 dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
aungriah 0:a3b83d366423 1389
aungriah 0:a3b83d366423 1390 wr_buf[0] = mrb & 0x00ff;
aungriah 0:a3b83d366423 1391 wr_buf[1] = (mrb & 0xff00)>>8;
aungriah 0:a3b83d366423 1392 dwt_writetodevice(OTP_IF_ID, OTP_WDAT,2,wr_buf);
aungriah 0:a3b83d366423 1393
aungriah 0:a3b83d366423 1394 // Set WRITE_MR
aungriah 0:a3b83d366423 1395 wr_buf[0] = 0x08;
aungriah 0:a3b83d366423 1396 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:a3b83d366423 1397
aungriah 0:a3b83d366423 1398 // Wait?
aungriah 0:a3b83d366423 1399
aungriah 0:a3b83d366423 1400 // Set Clear Mode sel
aungriah 0:a3b83d366423 1401 wr_buf[0] = 0x04;
aungriah 0:a3b83d366423 1402 dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
aungriah 0:a3b83d366423 1403
aungriah 0:a3b83d366423 1404 // Set AUX update, write MR
aungriah 0:a3b83d366423 1405 wr_buf[0] = 0x88;
aungriah 0:a3b83d366423 1406 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:a3b83d366423 1407 // Clear write MR
aungriah 0:a3b83d366423 1408 wr_buf[0] = 0x80;
aungriah 0:a3b83d366423 1409 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:a3b83d366423 1410 // Clear AUX update
aungriah 0:a3b83d366423 1411 wr_buf[0] = 0x00;
aungriah 0:a3b83d366423 1412 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:a3b83d366423 1413
aungriah 0:a3b83d366423 1414 ///////////////////////////////////////////
aungriah 0:a3b83d366423 1415 // PROGRAM MR
aungriah 0:a3b83d366423 1416 // Set SLOW, MODE_SEL
aungriah 0:a3b83d366423 1417 wr_buf[0] = 0x01;
aungriah 0:a3b83d366423 1418 dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
aungriah 0:a3b83d366423 1419 // Load data
aungriah 0:a3b83d366423 1420
aungriah 0:a3b83d366423 1421 wr_buf[0] = mr & 0x00ff;
aungriah 0:a3b83d366423 1422 wr_buf[1] = (mr & 0xff00)>>8;
aungriah 0:a3b83d366423 1423 dwt_writetodevice(OTP_IF_ID, OTP_WDAT,2,wr_buf);
aungriah 0:a3b83d366423 1424
aungriah 0:a3b83d366423 1425 // Set WRITE_MR
aungriah 0:a3b83d366423 1426 wr_buf[0] = 0x08;
aungriah 0:a3b83d366423 1427 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:a3b83d366423 1428
aungriah 0:a3b83d366423 1429 // Wait?
aungriah 0:a3b83d366423 1430 deca_sleep(10);
aungriah 0:a3b83d366423 1431 // Set Clear Mode sel
aungriah 0:a3b83d366423 1432 wr_buf[0] = 0x00;
aungriah 0:a3b83d366423 1433 dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
aungriah 0:a3b83d366423 1434
aungriah 0:a3b83d366423 1435 // Read confirm mode writes.
aungriah 0:a3b83d366423 1436 // Set man override, MRA_SEL
aungriah 0:a3b83d366423 1437 wr_buf[0] = OTP_CTRL_OTPRDEN;
aungriah 0:a3b83d366423 1438 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:a3b83d366423 1439 wr_buf[0] = 0x02;
aungriah 0:a3b83d366423 1440 dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
aungriah 0:a3b83d366423 1441 // MRB_SEL
aungriah 0:a3b83d366423 1442 wr_buf[0] = 0x04;
aungriah 0:a3b83d366423 1443 dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
aungriah 0:a3b83d366423 1444 deca_sleep(100);
aungriah 0:a3b83d366423 1445
aungriah 0:a3b83d366423 1446 // Clear mode sel
aungriah 0:a3b83d366423 1447 wr_buf[0] = 0x00;
aungriah 0:a3b83d366423 1448 dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
aungriah 0:a3b83d366423 1449 // Clear MAN_OVERRIDE
aungriah 0:a3b83d366423 1450 wr_buf[0] = 0x00;
aungriah 0:a3b83d366423 1451 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:a3b83d366423 1452
aungriah 0:a3b83d366423 1453 deca_sleep(10);
aungriah 0:a3b83d366423 1454
aungriah 0:a3b83d366423 1455 if (((mode&0x0f) == 0x1)||((mode&0x0f) == 0x2))
aungriah 0:a3b83d366423 1456 {
aungriah 0:a3b83d366423 1457 // Read status register
aungriah 0:a3b83d366423 1458 dwt_readfromdevice(OTP_IF_ID, OTP_STAT,1,rd_buf);
aungriah 0:a3b83d366423 1459 }
aungriah 0:a3b83d366423 1460
aungriah 0:a3b83d366423 1461 return DWT_SUCCESS;
aungriah 0:a3b83d366423 1462 }
aungriah 0:a3b83d366423 1463
aungriah 0:a3b83d366423 1464 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1465 * @fn _dwt_otpprogword32()
aungriah 0:a3b83d366423 1466 *
aungriah 0:a3b83d366423 1467 * @brief function to program the OTP memory. Ensure that MR,MRa,MRb are reset to 0.
aungriah 0:a3b83d366423 1468 * VNM Charge pump needs to be enabled (see _dwt_otpsetmrregs)
aungriah 0:a3b83d366423 1469 * Note the address is only 11 bits long.
aungriah 0:a3b83d366423 1470 *
aungriah 0:a3b83d366423 1471 * input parameters
aungriah 0:a3b83d366423 1472 * @param address - address to read at
aungriah 0:a3b83d366423 1473 *
aungriah 0:a3b83d366423 1474 * output parameters
aungriah 0:a3b83d366423 1475 *
aungriah 0:a3b83d366423 1476 * returns DWT_SUCCESS for success, or DWT_ERROR for error
aungriah 0:a3b83d366423 1477 */
aungriah 0:a3b83d366423 1478 uint32 _dwt_otpprogword32(uint32 data, uint16 address)
aungriah 0:a3b83d366423 1479 {
aungriah 0:a3b83d366423 1480 uint8 rd_buf[1];
aungriah 0:a3b83d366423 1481 uint8 wr_buf[4];
aungriah 0:a3b83d366423 1482 uint8 otp_done;
aungriah 0:a3b83d366423 1483
aungriah 0:a3b83d366423 1484 // Read status register
aungriah 0:a3b83d366423 1485 dwt_readfromdevice(OTP_IF_ID, OTP_STAT, 1, rd_buf);
aungriah 0:a3b83d366423 1486
aungriah 0:a3b83d366423 1487 if((rd_buf[0] & 0x02) != 0x02)
aungriah 0:a3b83d366423 1488 {
aungriah 0:a3b83d366423 1489 return DWT_ERROR;
aungriah 0:a3b83d366423 1490 }
aungriah 0:a3b83d366423 1491
aungriah 0:a3b83d366423 1492 // Write the data
aungriah 0:a3b83d366423 1493 wr_buf[3] = (data>>24) & 0xff;
aungriah 0:a3b83d366423 1494 wr_buf[2] = (data>>16) & 0xff;
aungriah 0:a3b83d366423 1495 wr_buf[1] = (data>>8) & 0xff;
aungriah 0:a3b83d366423 1496 wr_buf[0] = data & 0xff;
aungriah 0:a3b83d366423 1497 dwt_writetodevice(OTP_IF_ID, OTP_WDAT, 4, wr_buf);
aungriah 0:a3b83d366423 1498
aungriah 0:a3b83d366423 1499 // Write the address [10:0]
aungriah 0:a3b83d366423 1500 wr_buf[1] = (address>>8) & 0x07;
aungriah 0:a3b83d366423 1501 wr_buf[0] = address & 0xff;
aungriah 0:a3b83d366423 1502 dwt_writetodevice(OTP_IF_ID, OTP_ADDR, 2, wr_buf);
aungriah 0:a3b83d366423 1503
aungriah 0:a3b83d366423 1504 // Enable Sequenced programming
aungriah 0:a3b83d366423 1505 wr_buf[0] = OTP_CTRL_OTPPROG;
aungriah 0:a3b83d366423 1506 dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
aungriah 0:a3b83d366423 1507 wr_buf[0] = 0x00; // And clear
aungriah 0:a3b83d366423 1508 dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
aungriah 0:a3b83d366423 1509
aungriah 0:a3b83d366423 1510 // WAIT for status to flag PRGM OK..
aungriah 0:a3b83d366423 1511 otp_done = 0;
aungriah 0:a3b83d366423 1512 while(otp_done == 0)
aungriah 0:a3b83d366423 1513 {
aungriah 0:a3b83d366423 1514 deca_sleep(1);
aungriah 0:a3b83d366423 1515 dwt_readfromdevice(OTP_IF_ID, OTP_STAT, 1, rd_buf);
aungriah 0:a3b83d366423 1516
aungriah 0:a3b83d366423 1517 if((rd_buf[0] & 0x01) == 0x01)
aungriah 0:a3b83d366423 1518 {
aungriah 0:a3b83d366423 1519 otp_done = 1;
aungriah 0:a3b83d366423 1520 }
aungriah 0:a3b83d366423 1521 }
aungriah 0:a3b83d366423 1522
aungriah 0:a3b83d366423 1523 return DWT_SUCCESS;
aungriah 0:a3b83d366423 1524 }
aungriah 0:a3b83d366423 1525
aungriah 0:a3b83d366423 1526 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1527 * @fn dwt_otpwriteandverify()
aungriah 0:a3b83d366423 1528 *
aungriah 0:a3b83d366423 1529 * @brief This is used to program 32-bit value into the DW1000 OTP memory.
aungriah 0:a3b83d366423 1530 *
aungriah 0:a3b83d366423 1531 * input parameters
aungriah 0:a3b83d366423 1532 * @param value - this is the 32-bit value to be programmed into OTP
aungriah 0:a3b83d366423 1533 * @param address - this is the 16-bit OTP address into which the 32-bit value is programmed
aungriah 0:a3b83d366423 1534 *
aungriah 0:a3b83d366423 1535 * output parameters
aungriah 0:a3b83d366423 1536 *
aungriah 0:a3b83d366423 1537 * returns DWT_SUCCESS for success, or DWT_ERROR for error
aungriah 0:a3b83d366423 1538 */
aungriah 0:a3b83d366423 1539 uint32 dwt_otpwriteandverify(uint32 value, uint16 address)
aungriah 0:a3b83d366423 1540 {
aungriah 0:a3b83d366423 1541 int prog_ok = DWT_SUCCESS;
aungriah 0:a3b83d366423 1542 int retry = 0;
aungriah 0:a3b83d366423 1543 // Firstly set the system clock to crystal
aungriah 0:a3b83d366423 1544 _dwt_enableclocks(FORCE_SYS_XTI); //set system clock to XTI
aungriah 0:a3b83d366423 1545
aungriah 0:a3b83d366423 1546 //
aungriah 0:a3b83d366423 1547 //!!!!!!!!!!!!!! NOTE !!!!!!!!!!!!!!!!!!!!!
aungriah 0:a3b83d366423 1548 //Set the supply to 3.7V
aungriah 0:a3b83d366423 1549 //
aungriah 0:a3b83d366423 1550
aungriah 0:a3b83d366423 1551 _dwt_otpsetmrregs(1); // Set mode for programming
aungriah 0:a3b83d366423 1552
aungriah 0:a3b83d366423 1553 // For each value to program - the readback/check is done couple of times to verify it has programmed successfully
aungriah 0:a3b83d366423 1554 while(1)
aungriah 0:a3b83d366423 1555 {
aungriah 0:a3b83d366423 1556 _dwt_otpprogword32(value, address);
aungriah 0:a3b83d366423 1557
aungriah 0:a3b83d366423 1558 if(_dwt_otpread(address) == value)
aungriah 0:a3b83d366423 1559 {
aungriah 0:a3b83d366423 1560 break;
aungriah 0:a3b83d366423 1561 }
aungriah 0:a3b83d366423 1562 retry++;
aungriah 0:a3b83d366423 1563 if(retry==5)
aungriah 0:a3b83d366423 1564 {
aungriah 0:a3b83d366423 1565 break;
aungriah 0:a3b83d366423 1566 }
aungriah 0:a3b83d366423 1567 }
aungriah 0:a3b83d366423 1568
aungriah 0:a3b83d366423 1569 // Even if the above does not exit before retry reaches 5, the programming has probably been successful
aungriah 0:a3b83d366423 1570
aungriah 0:a3b83d366423 1571 _dwt_otpsetmrregs(4); // Set mode for reading
aungriah 0:a3b83d366423 1572
aungriah 0:a3b83d366423 1573 if(_dwt_otpread(address) != value) // If this does not pass please check voltage supply on VDDIO
aungriah 0:a3b83d366423 1574 {
aungriah 0:a3b83d366423 1575 prog_ok = DWT_ERROR;
aungriah 0:a3b83d366423 1576 }
aungriah 0:a3b83d366423 1577
aungriah 0:a3b83d366423 1578 _dwt_otpsetmrregs(0); // Setting OTP mode register for low RM read - resetting the device would be alternative
aungriah 0:a3b83d366423 1579
aungriah 0:a3b83d366423 1580 return prog_ok;
aungriah 0:a3b83d366423 1581 }
aungriah 0:a3b83d366423 1582
aungriah 0:a3b83d366423 1583 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1584 * @fn _dwt_aonconfigupload()
aungriah 0:a3b83d366423 1585 *
aungriah 0:a3b83d366423 1586 * @brief This function uploads always on (AON) configuration, as set in the AON_CFG0_OFFSET register.
aungriah 0:a3b83d366423 1587 *
aungriah 0:a3b83d366423 1588 * input parameters
aungriah 0:a3b83d366423 1589 *
aungriah 0:a3b83d366423 1590 * output parameters
aungriah 0:a3b83d366423 1591 *
aungriah 0:a3b83d366423 1592 * no return value
aungriah 0:a3b83d366423 1593 */
aungriah 0:a3b83d366423 1594 void _dwt_aonconfigupload(void)
aungriah 0:a3b83d366423 1595 {
aungriah 0:a3b83d366423 1596 dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, AON_CTRL_UPL_CFG);
aungriah 0:a3b83d366423 1597 dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, 0x00); // Clear the register
aungriah 0:a3b83d366423 1598 }
aungriah 0:a3b83d366423 1599
aungriah 0:a3b83d366423 1600 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1601 * @fn _dwt_aonarrayupload()
aungriah 0:a3b83d366423 1602 *
aungriah 0:a3b83d366423 1603 * @brief This function uploads always on (AON) data array and configuration. Thus if this function is used, then _dwt_aonconfigupload
aungriah 0:a3b83d366423 1604 * is not necessary. The DW1000 will go so SLEEP straight after this if the DWT_SLP_EN has been set.
aungriah 0:a3b83d366423 1605 *
aungriah 0:a3b83d366423 1606 * input parameters
aungriah 0:a3b83d366423 1607 *
aungriah 0:a3b83d366423 1608 * output parameters
aungriah 0:a3b83d366423 1609 *
aungriah 0:a3b83d366423 1610 * no return value
aungriah 0:a3b83d366423 1611 */
aungriah 0:a3b83d366423 1612 void _dwt_aonarrayupload(void)
aungriah 0:a3b83d366423 1613 {
aungriah 0:a3b83d366423 1614 dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, 0x00); // Clear the register
aungriah 0:a3b83d366423 1615 dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, AON_CTRL_SAVE);
aungriah 0:a3b83d366423 1616 }
aungriah 0:a3b83d366423 1617
aungriah 0:a3b83d366423 1618 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1619 * @fn dwt_entersleep()
aungriah 0:a3b83d366423 1620 *
aungriah 0:a3b83d366423 1621 * @brief This function puts the device into deep sleep or sleep. dwt_configuresleep() should be called first
aungriah 0:a3b83d366423 1622 * to configure the sleep and on-wake/wake-up parameters
aungriah 0:a3b83d366423 1623 *
aungriah 0:a3b83d366423 1624 * input parameters
aungriah 0:a3b83d366423 1625 *
aungriah 0:a3b83d366423 1626 * output parameters
aungriah 0:a3b83d366423 1627 *
aungriah 0:a3b83d366423 1628 * no return value
aungriah 0:a3b83d366423 1629 */
aungriah 0:a3b83d366423 1630 void dwt_entersleep(void)
aungriah 0:a3b83d366423 1631 {
aungriah 0:a3b83d366423 1632 // Copy config to AON - upload the new configuration
aungriah 0:a3b83d366423 1633 _dwt_aonarrayupload();
aungriah 0:a3b83d366423 1634 }
aungriah 0:a3b83d366423 1635
aungriah 0:a3b83d366423 1636 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1637 * @fn dwt_configuresleepcnt()
aungriah 0:a3b83d366423 1638 *
aungriah 0:a3b83d366423 1639 * @brief sets the sleep counter to new value, this function programs the high 16-bits of the 28-bit counter
aungriah 0:a3b83d366423 1640 *
aungriah 0:a3b83d366423 1641 * NOTE: this function needs to be run before dwt_configuresleep, also the SPI frequency has to be < 3MHz
aungriah 0:a3b83d366423 1642 *
aungriah 0:a3b83d366423 1643 * input parameters
aungriah 0:a3b83d366423 1644 * @param sleepcnt - this it value of the sleep counter to program
aungriah 0:a3b83d366423 1645 *
aungriah 0:a3b83d366423 1646 * output parameters
aungriah 0:a3b83d366423 1647 *
aungriah 0:a3b83d366423 1648 * no return value
aungriah 0:a3b83d366423 1649 */
aungriah 0:a3b83d366423 1650 void dwt_configuresleepcnt(uint16 sleepcnt)
aungriah 0:a3b83d366423 1651 {
aungriah 0:a3b83d366423 1652 // Force system clock to crystal
aungriah 0:a3b83d366423 1653 _dwt_enableclocks(FORCE_SYS_XTI);
aungriah 0:a3b83d366423 1654
aungriah 0:a3b83d366423 1655 // Reset sleep configuration to make sure we don't accidentally go to sleep
aungriah 0:a3b83d366423 1656 dwt_write8bitoffsetreg(AON_ID, AON_CFG0_OFFSET, 0x00); // NB: this write change the default LPCLKDIVA value which is not used anyway.
aungriah 0:a3b83d366423 1657 dwt_write8bitoffsetreg(AON_ID, AON_CFG1_OFFSET, 0x00);
aungriah 0:a3b83d366423 1658
aungriah 0:a3b83d366423 1659 // Disable the sleep counter
aungriah 0:a3b83d366423 1660 _dwt_aonconfigupload();
aungriah 0:a3b83d366423 1661
aungriah 0:a3b83d366423 1662 // Set new value
aungriah 0:a3b83d366423 1663 dwt_write16bitoffsetreg(AON_ID, AON_CFG0_OFFSET + AON_CFG0_SLEEP_TIM_OFFSET, sleepcnt);
aungriah 0:a3b83d366423 1664 _dwt_aonconfigupload();
aungriah 0:a3b83d366423 1665
aungriah 0:a3b83d366423 1666 // Enable the sleep counter
aungriah 0:a3b83d366423 1667 dwt_write8bitoffsetreg(AON_ID, AON_CFG1_OFFSET, AON_CFG1_SLEEP_CEN);
aungriah 0:a3b83d366423 1668 _dwt_aonconfigupload();
aungriah 0:a3b83d366423 1669
aungriah 0:a3b83d366423 1670 // Put system PLL back on
aungriah 0:a3b83d366423 1671 _dwt_enableclocks(ENABLE_ALL_SEQ);
aungriah 0:a3b83d366423 1672 }
aungriah 0:a3b83d366423 1673
aungriah 0:a3b83d366423 1674
aungriah 0:a3b83d366423 1675 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1676 * @fn dwt_calibratesleepcnt()
aungriah 0:a3b83d366423 1677 *
aungriah 0:a3b83d366423 1678 * @brief calibrates the local oscillator as its frequency can vary between 7 and 13kHz depending on temp and voltage
aungriah 0:a3b83d366423 1679 *
aungriah 0:a3b83d366423 1680 * NOTE: this function needs to be run before dwt_configuresleepcnt, so that we know what the counter units are
aungriah 0:a3b83d366423 1681 *
aungriah 0:a3b83d366423 1682 * input parameters
aungriah 0:a3b83d366423 1683 *
aungriah 0:a3b83d366423 1684 * output parameters
aungriah 0:a3b83d366423 1685 *
aungriah 0:a3b83d366423 1686 * returns the number of XTAL/2 cycles per low-power oscillator cycle. LP OSC frequency = 19.2 MHz/return value
aungriah 0:a3b83d366423 1687 */
aungriah 0:a3b83d366423 1688 uint16 dwt_calibratesleepcnt(void)
aungriah 0:a3b83d366423 1689 {
aungriah 0:a3b83d366423 1690 uint16 result;
aungriah 0:a3b83d366423 1691
aungriah 0:a3b83d366423 1692 // Enable calibration of the sleep counter
aungriah 0:a3b83d366423 1693 dwt_write8bitoffsetreg(AON_ID, AON_CFG1_OFFSET, AON_CFG1_LPOSC_CAL);
aungriah 0:a3b83d366423 1694 _dwt_aonconfigupload();
aungriah 0:a3b83d366423 1695
aungriah 0:a3b83d366423 1696 // Disable calibration of the sleep counter
aungriah 0:a3b83d366423 1697 dwt_write8bitoffsetreg(AON_ID, AON_CFG1_OFFSET, 0x00);
aungriah 0:a3b83d366423 1698 _dwt_aonconfigupload();
aungriah 0:a3b83d366423 1699
aungriah 0:a3b83d366423 1700 // Force system clock to crystal
aungriah 0:a3b83d366423 1701 _dwt_enableclocks(FORCE_SYS_XTI);
aungriah 0:a3b83d366423 1702
aungriah 0:a3b83d366423 1703 deca_sleep(1);
aungriah 0:a3b83d366423 1704
aungriah 0:a3b83d366423 1705 // Read the number of XTAL/2 cycles one LP oscillator cycle took.
aungriah 0:a3b83d366423 1706 // Set up address - Read upper byte first
aungriah 0:a3b83d366423 1707 dwt_write8bitoffsetreg(AON_ID, AON_ADDR_OFFSET, AON_ADDR_LPOSC_CAL_1);
aungriah 0:a3b83d366423 1708
aungriah 0:a3b83d366423 1709 // Enable manual override
aungriah 0:a3b83d366423 1710 dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, AON_CTRL_DCA_ENAB);
aungriah 0:a3b83d366423 1711
aungriah 0:a3b83d366423 1712 // Read confirm data that was written
aungriah 0:a3b83d366423 1713 dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, AON_CTRL_DCA_ENAB | AON_CTRL_DCA_READ);
aungriah 0:a3b83d366423 1714
aungriah 0:a3b83d366423 1715 // Read back byte from AON
aungriah 0:a3b83d366423 1716 result = dwt_read8bitoffsetreg(AON_ID, AON_RDAT_OFFSET);
aungriah 0:a3b83d366423 1717 result <<= 8;
aungriah 0:a3b83d366423 1718
aungriah 0:a3b83d366423 1719 // Set up address - Read lower byte
aungriah 0:a3b83d366423 1720 dwt_write8bitoffsetreg(AON_ID, AON_ADDR_OFFSET, AON_ADDR_LPOSC_CAL_0);
aungriah 0:a3b83d366423 1721
aungriah 0:a3b83d366423 1722 // Enable manual override
aungriah 0:a3b83d366423 1723 dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, AON_CTRL_DCA_ENAB);
aungriah 0:a3b83d366423 1724
aungriah 0:a3b83d366423 1725 // Read confirm data that was written
aungriah 0:a3b83d366423 1726 dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, AON_CTRL_DCA_ENAB | AON_CTRL_DCA_READ);
aungriah 0:a3b83d366423 1727
aungriah 0:a3b83d366423 1728 // Read back byte from AON
aungriah 0:a3b83d366423 1729 result |= dwt_read8bitoffsetreg(AON_ID, AON_RDAT_OFFSET);
aungriah 0:a3b83d366423 1730
aungriah 0:a3b83d366423 1731 // Disable manual override
aungriah 0:a3b83d366423 1732 dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, 0x00);
aungriah 0:a3b83d366423 1733
aungriah 0:a3b83d366423 1734 // Put system PLL back on
aungriah 0:a3b83d366423 1735 _dwt_enableclocks(ENABLE_ALL_SEQ);
aungriah 0:a3b83d366423 1736
aungriah 0:a3b83d366423 1737 // Returns the number of XTAL/2 cycles per one LP OSC cycle
aungriah 0:a3b83d366423 1738 // This can be converted into LP OSC frequency by 19.2 MHz/result
aungriah 0:a3b83d366423 1739 return result;
aungriah 0:a3b83d366423 1740 }
aungriah 0:a3b83d366423 1741
aungriah 0:a3b83d366423 1742 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1743 * @fn dwt_configuresleep()
aungriah 0:a3b83d366423 1744 *
aungriah 0:a3b83d366423 1745 * @brief configures the device for both DEEP_SLEEP and SLEEP modes, and on-wake mode
aungriah 0:a3b83d366423 1746 * i.e. before entering the sleep, the device should be programmed for TX or RX, then upon "waking up" the TX/RX settings
aungriah 0:a3b83d366423 1747 * will be preserved and the device can immediately perform the desired action TX/RX
aungriah 0:a3b83d366423 1748 *
aungriah 0:a3b83d366423 1749 * NOTE: e.g. Tag operation - after deep sleep, the device needs to just load the TX buffer and send the frame
aungriah 0:a3b83d366423 1750 *
aungriah 0:a3b83d366423 1751 *
aungriah 0:a3b83d366423 1752 * mode: the array and LDE code (OTP/ROM) and LDO tune, and set sleep persist
aungriah 0:a3b83d366423 1753 * DWT_PRESRV_SLEEP 0x0100 - preserve sleep
aungriah 0:a3b83d366423 1754 * DWT_LOADOPSET 0x0080 - load operating parameter set on wakeup
aungriah 0:a3b83d366423 1755 * DWT_CONFIG 0x0040 - download the AON array into the HIF (configuration download)
aungriah 0:a3b83d366423 1756 * DWT_LOADEUI 0x0008
aungriah 0:a3b83d366423 1757 * DWT_GOTORX 0x0002
aungriah 0:a3b83d366423 1758 * DWT_TANDV 0x0001
aungriah 0:a3b83d366423 1759 *
aungriah 0:a3b83d366423 1760 * wake: wake up parameters
aungriah 0:a3b83d366423 1761 * DWT_XTAL_EN 0x10 - keep XTAL running during sleep
aungriah 0:a3b83d366423 1762 * DWT_WAKE_SLPCNT 0x8 - wake up after sleep count
aungriah 0:a3b83d366423 1763 * DWT_WAKE_CS 0x4 - wake up on chip select
aungriah 0:a3b83d366423 1764 * DWT_WAKE_WK 0x2 - wake up on WAKEUP PIN
aungriah 0:a3b83d366423 1765 * DWT_SLP_EN 0x1 - enable sleep/deep sleep functionality
aungriah 0:a3b83d366423 1766 *
aungriah 0:a3b83d366423 1767 * input parameters
aungriah 0:a3b83d366423 1768 * @param mode - config on-wake parameters
aungriah 0:a3b83d366423 1769 * @param wake - config wake up parameters
aungriah 0:a3b83d366423 1770 *
aungriah 0:a3b83d366423 1771 * output parameters
aungriah 0:a3b83d366423 1772 *
aungriah 0:a3b83d366423 1773 * no return value
aungriah 0:a3b83d366423 1774 */
aungriah 0:a3b83d366423 1775 void dwt_configuresleep(uint16 mode, uint8 wake)
aungriah 0:a3b83d366423 1776 {
aungriah 0:a3b83d366423 1777 // Add predefined sleep settings before writing the mode
aungriah 0:a3b83d366423 1778 mode |= dw1000local.sleep_mode;
aungriah 0:a3b83d366423 1779 dwt_write16bitoffsetreg(AON_ID, AON_WCFG_OFFSET, mode);
aungriah 0:a3b83d366423 1780
aungriah 0:a3b83d366423 1781 dwt_write8bitoffsetreg(AON_ID, AON_CFG0_OFFSET, wake);
aungriah 0:a3b83d366423 1782 }
aungriah 0:a3b83d366423 1783
aungriah 0:a3b83d366423 1784 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1785 * @fn dwt_entersleepaftertx(int enable)
aungriah 0:a3b83d366423 1786 *
aungriah 0:a3b83d366423 1787 * @brief sets the auto TX to sleep bit. This means that after a frame
aungriah 0:a3b83d366423 1788 * transmission the device will enter deep sleep mode. The dwt_configuresleep() function
aungriah 0:a3b83d366423 1789 * needs to be called before this to configure the on-wake settings
aungriah 0:a3b83d366423 1790 *
aungriah 0:a3b83d366423 1791 * NOTE: the IRQ line has to be low/inactive (i.e. no pending events)
aungriah 0:a3b83d366423 1792 *
aungriah 0:a3b83d366423 1793 * input parameters
aungriah 0:a3b83d366423 1794 * @param enable - 1 to configure the device to enter deep sleep after TX, 0 - disables the configuration
aungriah 0:a3b83d366423 1795 *
aungriah 0:a3b83d366423 1796 * output parameters
aungriah 0:a3b83d366423 1797 *
aungriah 0:a3b83d366423 1798 * no return value
aungriah 0:a3b83d366423 1799 */
aungriah 0:a3b83d366423 1800 void dwt_entersleepaftertx(int enable)
aungriah 0:a3b83d366423 1801 {
aungriah 0:a3b83d366423 1802 uint32 reg = dwt_read32bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET);
aungriah 0:a3b83d366423 1803 // Set the auto TX -> sleep bit
aungriah 0:a3b83d366423 1804 if(enable)
aungriah 0:a3b83d366423 1805 {
aungriah 0:a3b83d366423 1806 reg |= PMSC_CTRL1_ATXSLP;
aungriah 0:a3b83d366423 1807 }
aungriah 0:a3b83d366423 1808 else
aungriah 0:a3b83d366423 1809 {
aungriah 0:a3b83d366423 1810 reg &= ~(PMSC_CTRL1_ATXSLP);
aungriah 0:a3b83d366423 1811 }
aungriah 0:a3b83d366423 1812 dwt_write32bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET, reg);
aungriah 0:a3b83d366423 1813 }
aungriah 0:a3b83d366423 1814
aungriah 0:a3b83d366423 1815
aungriah 0:a3b83d366423 1816 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1817 * @fn dwt_spicswakeup()
aungriah 0:a3b83d366423 1818 *
aungriah 0:a3b83d366423 1819 * @brief wake up the device from sleep mode using the SPI read,
aungriah 0:a3b83d366423 1820 * the device will wake up on chip select line going low if the line is held low for at least 500us.
aungriah 0:a3b83d366423 1821 * To define the length depending on the time one wants to hold
aungriah 0:a3b83d366423 1822 * the chip select line low, use the following formula:
aungriah 0:a3b83d366423 1823 *
aungriah 0:a3b83d366423 1824 * length (bytes) = time (s) * byte_rate (Hz)
aungriah 0:a3b83d366423 1825 *
aungriah 0:a3b83d366423 1826 * where fastest byte_rate is spi_rate (Hz) / 8 if the SPI is sending the bytes back-to-back.
aungriah 0:a3b83d366423 1827 * To save time and power, a system designer could determine byte_rate value more precisely.
aungriah 0:a3b83d366423 1828 *
aungriah 0:a3b83d366423 1829 * NOTE: Alternatively the device can be waken up with WAKE_UP pin if configured for that operation
aungriah 0:a3b83d366423 1830 *
aungriah 0:a3b83d366423 1831 * input parameters
aungriah 0:a3b83d366423 1832 * @param buff - this is a pointer to the dummy buffer which will be used in the SPI read transaction used for the WAKE UP of the device
aungriah 0:a3b83d366423 1833 * @param length - this is the length of the dummy buffer
aungriah 0:a3b83d366423 1834 *
aungriah 0:a3b83d366423 1835 * output parameters
aungriah 0:a3b83d366423 1836 *
aungriah 0:a3b83d366423 1837 * returns DWT_SUCCESS for success, or DWT_ERROR for error
aungriah 0:a3b83d366423 1838 */
aungriah 0:a3b83d366423 1839 int dwt_spicswakeup(uint8 *buff, uint16 length)
aungriah 0:a3b83d366423 1840 {
aungriah 0:a3b83d366423 1841 if(dwt_readdevid() != DWT_DEVICE_ID) // Device was in deep sleep (the first read fails)
aungriah 0:a3b83d366423 1842 {
aungriah 0:a3b83d366423 1843 // Need to keep chip select line low for at least 500us
aungriah 0:a3b83d366423 1844 dwt_readfromdevice(0x0, 0x0, length, buff); // Do a long read to wake up the chip (hold the chip select low)
aungriah 0:a3b83d366423 1845
aungriah 0:a3b83d366423 1846 // Need 5ms for XTAL to start and stabilise (could wait for PLL lock IRQ status bit !!!)
aungriah 0:a3b83d366423 1847 // NOTE: Polling of the STATUS register is not possible unless frequency is < 3MHz
aungriah 0:a3b83d366423 1848 deca_sleep(5);
aungriah 0:a3b83d366423 1849 }
aungriah 0:a3b83d366423 1850 else
aungriah 0:a3b83d366423 1851 {
aungriah 0:a3b83d366423 1852 return DWT_SUCCESS;
aungriah 0:a3b83d366423 1853 }
aungriah 0:a3b83d366423 1854 // DEBUG - check if still in sleep mode
aungriah 0:a3b83d366423 1855 if(dwt_readdevid() != DWT_DEVICE_ID)
aungriah 0:a3b83d366423 1856 {
aungriah 0:a3b83d366423 1857 return DWT_ERROR;
aungriah 0:a3b83d366423 1858 }
aungriah 0:a3b83d366423 1859
aungriah 0:a3b83d366423 1860 return DWT_SUCCESS;
aungriah 0:a3b83d366423 1861 }
aungriah 0:a3b83d366423 1862
aungriah 0:a3b83d366423 1863 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1864 * @fn _dwt_configlde()
aungriah 0:a3b83d366423 1865 *
aungriah 0:a3b83d366423 1866 * @brief configure LDE algorithm parameters
aungriah 0:a3b83d366423 1867 *
aungriah 0:a3b83d366423 1868 * input parameters
aungriah 0:a3b83d366423 1869 * @param prf - this is the PRF index (0 or 1) 0 corresponds to 16 and 1 to 64 PRF
aungriah 0:a3b83d366423 1870 *
aungriah 0:a3b83d366423 1871 * output parameters
aungriah 0:a3b83d366423 1872 *
aungriah 0:a3b83d366423 1873 * no return value
aungriah 0:a3b83d366423 1874 */
aungriah 0:a3b83d366423 1875 void _dwt_configlde(int prfIndex)
aungriah 0:a3b83d366423 1876 {
aungriah 0:a3b83d366423 1877 dwt_write8bitoffsetreg(LDE_IF_ID, LDE_CFG1_OFFSET, LDE_PARAM1); // 8-bit configuration register
aungriah 0:a3b83d366423 1878
aungriah 0:a3b83d366423 1879 if(prfIndex)
aungriah 0:a3b83d366423 1880 {
aungriah 0:a3b83d366423 1881 dwt_write16bitoffsetreg( LDE_IF_ID, LDE_CFG2_OFFSET, (uint16) LDE_PARAM3_64); // 16-bit LDE configuration tuning register
aungriah 0:a3b83d366423 1882 }
aungriah 0:a3b83d366423 1883 else
aungriah 0:a3b83d366423 1884 {
aungriah 0:a3b83d366423 1885 dwt_write16bitoffsetreg( LDE_IF_ID, LDE_CFG2_OFFSET, (uint16) LDE_PARAM3_16);
aungriah 0:a3b83d366423 1886 }
aungriah 0:a3b83d366423 1887 }
aungriah 0:a3b83d366423 1888
aungriah 0:a3b83d366423 1889
aungriah 0:a3b83d366423 1890 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1891 * @fn _dwt_loaducodefromrom()
aungriah 0:a3b83d366423 1892 *
aungriah 0:a3b83d366423 1893 * @brief load ucode from OTP MEMORY or ROM
aungriah 0:a3b83d366423 1894 *
aungriah 0:a3b83d366423 1895 * input parameters
aungriah 0:a3b83d366423 1896 *
aungriah 0:a3b83d366423 1897 * output parameters
aungriah 0:a3b83d366423 1898 *
aungriah 0:a3b83d366423 1899 * no return value
aungriah 0:a3b83d366423 1900 */
aungriah 0:a3b83d366423 1901 void _dwt_loaducodefromrom(void)
aungriah 0:a3b83d366423 1902 {
aungriah 0:a3b83d366423 1903 // Set up clocks
aungriah 0:a3b83d366423 1904 _dwt_enableclocks(FORCE_LDE);
aungriah 0:a3b83d366423 1905
aungriah 0:a3b83d366423 1906 // Kick off the LDE load
aungriah 0:a3b83d366423 1907 dwt_write16bitoffsetreg(OTP_IF_ID, OTP_CTRL, OTP_CTRL_LDELOAD); // Set load LDE kick bit
aungriah 0:a3b83d366423 1908
aungriah 0:a3b83d366423 1909 deca_sleep(1); // Allow time for code to upload (should take up to 120 us)
aungriah 0:a3b83d366423 1910
aungriah 0:a3b83d366423 1911 // Default clocks (ENABLE_ALL_SEQ)
aungriah 0:a3b83d366423 1912 _dwt_enableclocks(ENABLE_ALL_SEQ); // Enable clocks for sequencing
aungriah 0:a3b83d366423 1913 }
aungriah 0:a3b83d366423 1914
aungriah 0:a3b83d366423 1915 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1916 * @fn dwt_loadopsettabfromotp()
aungriah 0:a3b83d366423 1917 *
aungriah 0:a3b83d366423 1918 * @brief This is used to select which Operational Parameter Set table to load from OTP memory
aungriah 0:a3b83d366423 1919 *
aungriah 0:a3b83d366423 1920 * input parameters
aungriah 0:a3b83d366423 1921 * @param ops_sel - Operational Parameter Set table to load:
aungriah 0:a3b83d366423 1922 * DWT_OPSET_64LEN = 0x0 - load the operational parameter set table for 64 length preamble configuration
aungriah 0:a3b83d366423 1923 * DWT_OPSET_TIGHT = 0x1 - load the operational parameter set table for tight xtal offsets (<1ppm)
aungriah 0:a3b83d366423 1924 * DWT_OPSET_DEFLT = 0x2 - load the default operational parameter set table (this is loaded from reset)
aungriah 0:a3b83d366423 1925 *
aungriah 0:a3b83d366423 1926 * output parameters
aungriah 0:a3b83d366423 1927 *
aungriah 0:a3b83d366423 1928 * no return value
aungriah 0:a3b83d366423 1929 */
aungriah 0:a3b83d366423 1930 void dwt_loadopsettabfromotp(uint8 ops_sel)
aungriah 0:a3b83d366423 1931 {
aungriah 0:a3b83d366423 1932 uint16 reg = ((ops_sel << OTP_SF_OPS_SEL_SHFT) & OTP_SF_OPS_SEL_MASK) | OTP_SF_OPS_KICK; // Select defined OPS table and trigger its loading
aungriah 0:a3b83d366423 1933
aungriah 0:a3b83d366423 1934 // Set up clocks
aungriah 0:a3b83d366423 1935 _dwt_enableclocks(FORCE_LDE);
aungriah 0:a3b83d366423 1936
aungriah 0:a3b83d366423 1937 dwt_write16bitoffsetreg(OTP_IF_ID, OTP_SF, reg);
aungriah 0:a3b83d366423 1938
aungriah 0:a3b83d366423 1939 // Default clocks (ENABLE_ALL_SEQ)
aungriah 0:a3b83d366423 1940 _dwt_enableclocks(ENABLE_ALL_SEQ); // Enable clocks for sequencing
aungriah 0:a3b83d366423 1941
aungriah 0:a3b83d366423 1942 }
aungriah 0:a3b83d366423 1943
aungriah 0:a3b83d366423 1944 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1945 * @fn dwt_setsmarttxpower()
aungriah 0:a3b83d366423 1946 *
aungriah 0:a3b83d366423 1947 * @brief This call enables or disables the smart TX power feature.
aungriah 0:a3b83d366423 1948 *
aungriah 0:a3b83d366423 1949 * input parameters
aungriah 0:a3b83d366423 1950 * @param enable - this enables or disables the TX smart power (1 = enable, 0 = disable)
aungriah 0:a3b83d366423 1951 *
aungriah 0:a3b83d366423 1952 * output parameters
aungriah 0:a3b83d366423 1953 *
aungriah 0:a3b83d366423 1954 * no return value
aungriah 0:a3b83d366423 1955 */
aungriah 0:a3b83d366423 1956 void dwt_setsmarttxpower(int enable)
aungriah 0:a3b83d366423 1957 {
aungriah 0:a3b83d366423 1958 // Config system register
aungriah 0:a3b83d366423 1959 dw1000local.sysCFGreg = dwt_read32bitreg(SYS_CFG_ID) ; // Read sysconfig register
aungriah 0:a3b83d366423 1960
aungriah 0:a3b83d366423 1961 // Disable smart power configuration
aungriah 0:a3b83d366423 1962 if(enable)
aungriah 0:a3b83d366423 1963 {
aungriah 0:a3b83d366423 1964 dw1000local.sysCFGreg &= ~(SYS_CFG_DIS_STXP) ;
aungriah 0:a3b83d366423 1965 }
aungriah 0:a3b83d366423 1966 else
aungriah 0:a3b83d366423 1967 {
aungriah 0:a3b83d366423 1968 dw1000local.sysCFGreg |= SYS_CFG_DIS_STXP ;
aungriah 0:a3b83d366423 1969 }
aungriah 0:a3b83d366423 1970
aungriah 0:a3b83d366423 1971 dwt_write32bitreg(SYS_CFG_ID,dw1000local.sysCFGreg) ;
aungriah 0:a3b83d366423 1972 }
aungriah 0:a3b83d366423 1973
aungriah 0:a3b83d366423 1974
aungriah 0:a3b83d366423 1975 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1976 * @fn dwt_enableautoack()
aungriah 0:a3b83d366423 1977 *
aungriah 0:a3b83d366423 1978 * @brief This call enables the auto-ACK feature. If the responseDelayTime (parameter) is 0, the ACK will be sent a.s.a.p.
aungriah 0:a3b83d366423 1979 * otherwise it will be sent with a programmed delay (in symbols), max is 255.
aungriah 0:a3b83d366423 1980 * NOTE: needs to have frame filtering enabled as well
aungriah 0:a3b83d366423 1981 *
aungriah 0:a3b83d366423 1982 * input parameters
aungriah 0:a3b83d366423 1983 * @param responseDelayTime - if non-zero the ACK is sent after this delay, max is 255.
aungriah 0:a3b83d366423 1984 *
aungriah 0:a3b83d366423 1985 * output parameters
aungriah 0:a3b83d366423 1986 *
aungriah 0:a3b83d366423 1987 * no return value
aungriah 0:a3b83d366423 1988 */
aungriah 0:a3b83d366423 1989 void dwt_enableautoack(uint8 responseDelayTime)
aungriah 0:a3b83d366423 1990 {
aungriah 0:a3b83d366423 1991 // Set auto ACK reply delay
aungriah 0:a3b83d366423 1992 dwt_write8bitoffsetreg(ACK_RESP_T_ID, ACK_RESP_T_ACK_TIM_OFFSET, responseDelayTime); // In symbols
aungriah 0:a3b83d366423 1993 // Enable auto ACK
aungriah 0:a3b83d366423 1994 dw1000local.sysCFGreg |= SYS_CFG_AUTOACK;
aungriah 0:a3b83d366423 1995 dwt_write32bitreg(SYS_CFG_ID,dw1000local.sysCFGreg) ;
aungriah 0:a3b83d366423 1996 }
aungriah 0:a3b83d366423 1997
aungriah 0:a3b83d366423 1998 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 1999 * @fn dwt_setdblrxbuffmode()
aungriah 0:a3b83d366423 2000 *
aungriah 0:a3b83d366423 2001 * @brief This call enables the double receive buffer mode
aungriah 0:a3b83d366423 2002 *
aungriah 0:a3b83d366423 2003 * input parameters
aungriah 0:a3b83d366423 2004 * @param enable - 1 to enable, 0 to disable the double buffer mode
aungriah 0:a3b83d366423 2005 *
aungriah 0:a3b83d366423 2006 * output parameters
aungriah 0:a3b83d366423 2007 *
aungriah 0:a3b83d366423 2008 * no return value
aungriah 0:a3b83d366423 2009 */
aungriah 0:a3b83d366423 2010 void dwt_setdblrxbuffmode(int enable)
aungriah 0:a3b83d366423 2011 {
aungriah 0:a3b83d366423 2012 if(enable)
aungriah 0:a3b83d366423 2013 {
aungriah 0:a3b83d366423 2014 // Enable double RX buffer mode
aungriah 0:a3b83d366423 2015 dw1000local.sysCFGreg &= ~SYS_CFG_DIS_DRXB;
aungriah 0:a3b83d366423 2016 dw1000local.dblbuffon = 1;
aungriah 0:a3b83d366423 2017 }
aungriah 0:a3b83d366423 2018 else
aungriah 0:a3b83d366423 2019 {
aungriah 0:a3b83d366423 2020 // Disable double RX buffer mode
aungriah 0:a3b83d366423 2021 dw1000local.sysCFGreg |= SYS_CFG_DIS_DRXB;
aungriah 0:a3b83d366423 2022 dw1000local.dblbuffon = 0;
aungriah 0:a3b83d366423 2023 }
aungriah 0:a3b83d366423 2024
aungriah 0:a3b83d366423 2025 dwt_write32bitreg(SYS_CFG_ID,dw1000local.sysCFGreg) ;
aungriah 0:a3b83d366423 2026 }
aungriah 0:a3b83d366423 2027
aungriah 0:a3b83d366423 2028 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2029 * @fn dwt_setrxaftertxdelay()
aungriah 0:a3b83d366423 2030 *
aungriah 0:a3b83d366423 2031 * @brief This sets the receiver turn on delay time after a transmission of a frame
aungriah 0:a3b83d366423 2032 *
aungriah 0:a3b83d366423 2033 * input parameters
aungriah 0:a3b83d366423 2034 * @param rxDelayTime - (20 bits) - the delay is in UWB microseconds
aungriah 0:a3b83d366423 2035 *
aungriah 0:a3b83d366423 2036 * output parameters
aungriah 0:a3b83d366423 2037 *
aungriah 0:a3b83d366423 2038 * no return value
aungriah 0:a3b83d366423 2039 */
aungriah 0:a3b83d366423 2040 void dwt_setrxaftertxdelay(uint32 rxDelayTime)
aungriah 0:a3b83d366423 2041 {
aungriah 0:a3b83d366423 2042 uint32 val = dwt_read32bitreg(ACK_RESP_T_ID) ; // Read ACK_RESP_T_ID register
aungriah 0:a3b83d366423 2043
aungriah 0:a3b83d366423 2044 val &= ~(ACK_RESP_T_W4R_TIM_MASK) ; // Clear the timer (19:0)
aungriah 0:a3b83d366423 2045
aungriah 0:a3b83d366423 2046 val |= (rxDelayTime & ACK_RESP_T_W4R_TIM_MASK) ; // In UWB microseconds (e.g. turn the receiver on 20uus after TX)
aungriah 0:a3b83d366423 2047
aungriah 0:a3b83d366423 2048 dwt_write32bitreg(ACK_RESP_T_ID, val) ;
aungriah 0:a3b83d366423 2049 }
aungriah 0:a3b83d366423 2050
aungriah 0:a3b83d366423 2051 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2052 * @fn dwt_setcallbacks()
aungriah 0:a3b83d366423 2053 *
aungriah 0:a3b83d366423 2054 * @brief This function is used to register the different callbacks called when one of the corresponding event occurs.
aungriah 0:a3b83d366423 2055 *
aungriah 0:a3b83d366423 2056 * NOTE: Callbacks can be undefined (set to NULL). In this case, dwt_isr() will process the event as usual but the 'null'
aungriah 0:a3b83d366423 2057 * callback will not be called.
aungriah 0:a3b83d366423 2058 *
aungriah 0:a3b83d366423 2059 * input parameters
aungriah 0:a3b83d366423 2060 * @param cbTxDone - the pointer to the TX confirmation event callback function
aungriah 0:a3b83d366423 2061 * @param cbRxOk - the pointer to the RX good frame event callback function
aungriah 0:a3b83d366423 2062 * @param cbRxTo - the pointer to the RX timeout events callback function
aungriah 0:a3b83d366423 2063 * @param cbRxErr - the pointer to the RX error events callback function
aungriah 0:a3b83d366423 2064 *
aungriah 0:a3b83d366423 2065 * output parameters
aungriah 0:a3b83d366423 2066 *
aungriah 0:a3b83d366423 2067 * no return value
aungriah 0:a3b83d366423 2068 */
aungriah 0:a3b83d366423 2069 void dwt_setcallbacks(dwt_cb_t cbTxDone, dwt_cb_t cbRxOk, dwt_cb_t cbRxTo, dwt_cb_t cbRxErr)
aungriah 0:a3b83d366423 2070 {
aungriah 0:a3b83d366423 2071 dw1000local.cbTxDone = cbTxDone;
aungriah 0:a3b83d366423 2072 dw1000local.cbRxOk = cbRxOk;
aungriah 0:a3b83d366423 2073 dw1000local.cbRxTo = cbRxTo;
aungriah 0:a3b83d366423 2074 dw1000local.cbRxErr = cbRxErr;
aungriah 0:a3b83d366423 2075 }
aungriah 0:a3b83d366423 2076
aungriah 0:a3b83d366423 2077 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2078 * @fn dwt_checkirq()
aungriah 0:a3b83d366423 2079 *
aungriah 0:a3b83d366423 2080 * @brief This function checks if the IRQ line is active - this is used instead of interrupt handler
aungriah 0:a3b83d366423 2081 *
aungriah 0:a3b83d366423 2082 * input parameters
aungriah 0:a3b83d366423 2083 *
aungriah 0:a3b83d366423 2084 * output parameters
aungriah 0:a3b83d366423 2085 *
aungriah 0:a3b83d366423 2086 * return value is 1 if the IRQS bit is set and 0 otherwise
aungriah 0:a3b83d366423 2087 */
aungriah 0:a3b83d366423 2088 uint8 dwt_checkirq(void)
aungriah 0:a3b83d366423 2089 {
aungriah 0:a3b83d366423 2090 return (dwt_read8bitoffsetreg(SYS_STATUS_ID, SYS_STATUS_OFFSET) & SYS_STATUS_IRQS); // Reading the lower byte only is enough for this operation
aungriah 0:a3b83d366423 2091 }
aungriah 0:a3b83d366423 2092
aungriah 0:a3b83d366423 2093 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2094 * @fn dwt_isr()
aungriah 0:a3b83d366423 2095 *
aungriah 0:a3b83d366423 2096 * @brief This is the DW1000's general Interrupt Service Routine. It will process/report the following events:
aungriah 0:a3b83d366423 2097 * - RXFCG (through cbRxOk callback)
aungriah 0:a3b83d366423 2098 * - TXFRS (through cbTxDone callback)
aungriah 0:a3b83d366423 2099 * - RXRFTO/RXPTO (through cbRxTo callback)
aungriah 0:a3b83d366423 2100 * - RXPHE/RXFCE/RXRFSL/RXSFDTO/AFFREJ/LDEERR (through cbRxTo cbRxErr)
aungriah 0:a3b83d366423 2101 * For all events, corresponding interrupts are cleared and necessary resets are performed. In addition, in the RXFCG case,
aungriah 0:a3b83d366423 2102 * received frame information and frame control are read before calling the callback. If double buffering is activated, it
aungriah 0:a3b83d366423 2103 * will also toggle between reception buffers once the reception callback processing has ended.
aungriah 0:a3b83d366423 2104 *
aungriah 0:a3b83d366423 2105 * /!\ This version of the ISR supports double buffering but does not support automatic RX re-enabling!
aungriah 0:a3b83d366423 2106 *
aungriah 0:a3b83d366423 2107 * NOTE: In PC based system using (Cheetah or ARM) USB to SPI converter there can be no interrupts, however we still need something
aungriah 0:a3b83d366423 2108 * to take the place of it and operate in a polled way. In an embedded system this function should be configured to be triggered
aungriah 0:a3b83d366423 2109 * on any of the interrupts described above.
aungriah 0:a3b83d366423 2110
aungriah 0:a3b83d366423 2111 * input parameters
aungriah 0:a3b83d366423 2112 *
aungriah 0:a3b83d366423 2113 * output parameters
aungriah 0:a3b83d366423 2114 *
aungriah 0:a3b83d366423 2115 * no return value
aungriah 0:a3b83d366423 2116 */
aungriah 0:a3b83d366423 2117 void dwt_isr(void)
aungriah 0:a3b83d366423 2118 {
aungriah 0:a3b83d366423 2119 uint32 status = dw1000local.cbData.status = dwt_read32bitreg(SYS_STATUS_ID); // Read status register low 32bits
aungriah 0:a3b83d366423 2120
aungriah 0:a3b83d366423 2121 // Handle RX good frame event
aungriah 0:a3b83d366423 2122 if(status & SYS_STATUS_RXFCG)
aungriah 0:a3b83d366423 2123 {
aungriah 0:a3b83d366423 2124 uint16 finfo16;
aungriah 0:a3b83d366423 2125 uint16 len;
aungriah 0:a3b83d366423 2126
aungriah 0:a3b83d366423 2127 dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_ALL_RX_GOOD); // Clear all receive status bits
aungriah 0:a3b83d366423 2128
aungriah 0:a3b83d366423 2129 dw1000local.cbData.rx_flags = 0;
aungriah 0:a3b83d366423 2130
aungriah 0:a3b83d366423 2131 // Read frame info - Only the first two bytes of the register are used here.
aungriah 0:a3b83d366423 2132 finfo16 = dwt_read16bitoffsetreg(RX_FINFO_ID, RX_FINFO_OFFSET);
aungriah 0:a3b83d366423 2133
aungriah 0:a3b83d366423 2134 // Report frame length - Standard frame length up to 127, extended frame length up to 1023 bytes
aungriah 0:a3b83d366423 2135 len = finfo16 & RX_FINFO_RXFL_MASK_1023;
aungriah 0:a3b83d366423 2136 if(dw1000local.longFrames == 0)
aungriah 0:a3b83d366423 2137 {
aungriah 0:a3b83d366423 2138 len &= RX_FINFO_RXFLEN_MASK;
aungriah 0:a3b83d366423 2139 }
aungriah 0:a3b83d366423 2140 dw1000local.cbData.datalength = len;
aungriah 0:a3b83d366423 2141
aungriah 0:a3b83d366423 2142 // Report ranging bit
aungriah 0:a3b83d366423 2143 if(finfo16 & RX_FINFO_RNG)
aungriah 0:a3b83d366423 2144 {
aungriah 0:a3b83d366423 2145 dw1000local.cbData.rx_flags |= DWT_CB_DATA_RX_FLAG_RNG;
aungriah 0:a3b83d366423 2146 }
aungriah 0:a3b83d366423 2147
aungriah 0:a3b83d366423 2148 // Report frame control - First bytes of the received frame.
aungriah 0:a3b83d366423 2149 dwt_readfromdevice(RX_BUFFER_ID, 0, FCTRL_LEN_MAX, dw1000local.cbData.fctrl);
aungriah 0:a3b83d366423 2150
aungriah 0:a3b83d366423 2151 // Because of a previous frame not being received properly, AAT bit can be set upon the proper reception of a frame not requesting for
aungriah 0:a3b83d366423 2152 // acknowledgement (ACK frame is not actually sent though). If the AAT bit is set, check ACK request bit in frame control to confirm (this
aungriah 0:a3b83d366423 2153 // implementation works only for IEEE802.15.4-2011 compliant frames).
aungriah 0:a3b83d366423 2154 // This issue is not documented at the time of writing this code. It should be in next release of DW1000 User Manual (v2.09, from July 2016).
aungriah 0:a3b83d366423 2155 if((status & SYS_STATUS_AAT) && ((dw1000local.cbData.fctrl[0] & FCTRL_ACK_REQ_MASK) == 0))
aungriah 0:a3b83d366423 2156 {
aungriah 0:a3b83d366423 2157 dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_AAT); // Clear AAT status bit in register
aungriah 0:a3b83d366423 2158 dw1000local.cbData.status &= ~SYS_STATUS_AAT; // Clear AAT status bit in callback data register copy
aungriah 0:a3b83d366423 2159 dw1000local.wait4resp = 0;
aungriah 0:a3b83d366423 2160 }
aungriah 0:a3b83d366423 2161
aungriah 0:a3b83d366423 2162 // Call the corresponding callback if present
aungriah 0:a3b83d366423 2163 if(dw1000local.cbRxOk != NULL)
aungriah 0:a3b83d366423 2164 {
aungriah 0:a3b83d366423 2165 dw1000local.cbRxOk(&dw1000local.cbData);
aungriah 0:a3b83d366423 2166 }
aungriah 0:a3b83d366423 2167
aungriah 0:a3b83d366423 2168 if (dw1000local.dblbuffon)
aungriah 0:a3b83d366423 2169 {
aungriah 0:a3b83d366423 2170 // Toggle the Host side Receive Buffer Pointer
aungriah 0:a3b83d366423 2171 dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_HRBT_OFFSET, 1);
aungriah 0:a3b83d366423 2172 }
aungriah 0:a3b83d366423 2173 }
aungriah 0:a3b83d366423 2174
aungriah 0:a3b83d366423 2175 // Handle TX confirmation event
aungriah 0:a3b83d366423 2176 if(status & SYS_STATUS_TXFRS)
aungriah 0:a3b83d366423 2177 {
aungriah 0:a3b83d366423 2178 dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_ALL_TX); // Clear TX event bits
aungriah 0:a3b83d366423 2179
aungriah 0:a3b83d366423 2180 // In the case where this TXFRS interrupt is due to the automatic transmission of an ACK solicited by a response (with ACK request bit set)
aungriah 0:a3b83d366423 2181 // that we receive through using wait4resp to a previous TX (and assuming that the IRQ processing of that TX has already been handled), then
aungriah 0:a3b83d366423 2182 // we need to handle the IC issue which turns on the RX again in this situation (i.e. because it is wrongly applying the wait4resp after the
aungriah 0:a3b83d366423 2183 // ACK TX).
aungriah 0:a3b83d366423 2184 // See section "Transmit and automatically wait for response" in DW1000 User Manual
aungriah 0:a3b83d366423 2185 if((status & SYS_STATUS_AAT) && dw1000local.wait4resp)
aungriah 0:a3b83d366423 2186 {
aungriah 0:a3b83d366423 2187 dwt_forcetrxoff(); // Turn the RX off
aungriah 0:a3b83d366423 2188 dwt_rxreset(); // Reset in case we were late and a frame was already being received
aungriah 0:a3b83d366423 2189 }
aungriah 0:a3b83d366423 2190
aungriah 0:a3b83d366423 2191 // Call the corresponding callback if present
aungriah 0:a3b83d366423 2192 if(dw1000local.cbTxDone != NULL)
aungriah 0:a3b83d366423 2193 {
aungriah 0:a3b83d366423 2194 dw1000local.cbTxDone(&dw1000local.cbData);
aungriah 0:a3b83d366423 2195 }
aungriah 0:a3b83d366423 2196 }
aungriah 0:a3b83d366423 2197
aungriah 0:a3b83d366423 2198 // Handle frame reception/preamble detect timeout events
aungriah 0:a3b83d366423 2199 if(status & SYS_STATUS_ALL_RX_TO)
aungriah 0:a3b83d366423 2200 {
aungriah 0:a3b83d366423 2201 dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_RXRFTO); // Clear RX timeout event bits
aungriah 0:a3b83d366423 2202
aungriah 0:a3b83d366423 2203 dw1000local.wait4resp = 0;
aungriah 0:a3b83d366423 2204
aungriah 0:a3b83d366423 2205 // Because of an issue with receiver restart after error conditions, an RX reset must be applied after any error or timeout event to ensure
aungriah 0:a3b83d366423 2206 // the next good frame's timestamp is computed correctly.
aungriah 0:a3b83d366423 2207 // See section "RX Message timestamp" in DW1000 User Manual.
aungriah 0:a3b83d366423 2208 dwt_forcetrxoff();
aungriah 0:a3b83d366423 2209 dwt_rxreset();
aungriah 0:a3b83d366423 2210
aungriah 0:a3b83d366423 2211 // Call the corresponding callback if present
aungriah 0:a3b83d366423 2212 if(dw1000local.cbRxTo != NULL)
aungriah 0:a3b83d366423 2213 {
aungriah 0:a3b83d366423 2214 dw1000local.cbRxTo(&dw1000local.cbData);
aungriah 0:a3b83d366423 2215 }
aungriah 0:a3b83d366423 2216 }
aungriah 0:a3b83d366423 2217
aungriah 0:a3b83d366423 2218 // Handle RX errors events
aungriah 0:a3b83d366423 2219 if(status & SYS_STATUS_ALL_RX_ERR)
aungriah 0:a3b83d366423 2220 {
aungriah 0:a3b83d366423 2221 dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_ALL_RX_ERR); // Clear RX error event bits
aungriah 0:a3b83d366423 2222
aungriah 0:a3b83d366423 2223 dw1000local.wait4resp = 0;
aungriah 0:a3b83d366423 2224
aungriah 0:a3b83d366423 2225 // Because of an issue with receiver restart after error conditions, an RX reset must be applied after any error or timeout event to ensure
aungriah 0:a3b83d366423 2226 // the next good frame's timestamp is computed correctly.
aungriah 0:a3b83d366423 2227 // See section "RX Message timestamp" in DW1000 User Manual.
aungriah 0:a3b83d366423 2228 dwt_forcetrxoff();
aungriah 0:a3b83d366423 2229 dwt_rxreset();
aungriah 0:a3b83d366423 2230
aungriah 0:a3b83d366423 2231 // Call the corresponding callback if present
aungriah 0:a3b83d366423 2232 if(dw1000local.cbRxErr != NULL)
aungriah 0:a3b83d366423 2233 {
aungriah 0:a3b83d366423 2234 dw1000local.cbRxErr(&dw1000local.cbData);
aungriah 0:a3b83d366423 2235 }
aungriah 0:a3b83d366423 2236 }
aungriah 0:a3b83d366423 2237 }
aungriah 0:a3b83d366423 2238
aungriah 0:a3b83d366423 2239 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2240 * @fn dwt_isr_lplisten()
aungriah 0:a3b83d366423 2241 *
aungriah 0:a3b83d366423 2242 * @brief This is the DW1000's Interrupt Service Routine to use when low-power listening scheme is implemented. It will
aungriah 0:a3b83d366423 2243 * only process/report the RXFCG event (through cbRxOk callback).
aungriah 0:a3b83d366423 2244 * It clears RXFCG interrupt and reads received frame information and frame control before calling the callback.
aungriah 0:a3b83d366423 2245 *
aungriah 0:a3b83d366423 2246 * /!\ This version of the ISR is designed for single buffering case only!
aungriah 0:a3b83d366423 2247 *
aungriah 0:a3b83d366423 2248 * input parameters
aungriah 0:a3b83d366423 2249 *
aungriah 0:a3b83d366423 2250 * output parameters
aungriah 0:a3b83d366423 2251 *
aungriah 0:a3b83d366423 2252 * no return value
aungriah 0:a3b83d366423 2253 */
aungriah 0:a3b83d366423 2254 void dwt_lowpowerlistenisr(void)
aungriah 0:a3b83d366423 2255 {
aungriah 0:a3b83d366423 2256 uint32 status = dw1000local.cbData.status = dwt_read32bitreg(SYS_STATUS_ID); // Read status register low 32bits
aungriah 0:a3b83d366423 2257 uint16 finfo16;
aungriah 0:a3b83d366423 2258 uint16 len;
aungriah 0:a3b83d366423 2259
aungriah 0:a3b83d366423 2260 // The only interrupt handled when in low-power listening mode is RX good frame so proceed directly to the handling of the received frame.
aungriah 0:a3b83d366423 2261
aungriah 0:a3b83d366423 2262 // Deactivate low-power listening before clearing the interrupt. If not, the DW1000 will go back to sleep as soon as the interrupt is cleared.
aungriah 0:a3b83d366423 2263 dwt_setlowpowerlistening(0);
aungriah 0:a3b83d366423 2264
aungriah 0:a3b83d366423 2265 dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_ALL_RX_GOOD); // Clear all receive status bits
aungriah 0:a3b83d366423 2266
aungriah 0:a3b83d366423 2267 dw1000local.cbData.rx_flags = 0;
aungriah 0:a3b83d366423 2268
aungriah 0:a3b83d366423 2269 // Read frame info - Only the first two bytes of the register are used here.
aungriah 0:a3b83d366423 2270 finfo16 = dwt_read16bitoffsetreg(RX_FINFO_ID, 0);
aungriah 0:a3b83d366423 2271
aungriah 0:a3b83d366423 2272 // Report frame length - Standard frame length up to 127, extended frame length up to 1023 bytes
aungriah 0:a3b83d366423 2273 len = finfo16 & RX_FINFO_RXFL_MASK_1023;
aungriah 0:a3b83d366423 2274 if(dw1000local.longFrames == 0)
aungriah 0:a3b83d366423 2275 {
aungriah 0:a3b83d366423 2276 len &= RX_FINFO_RXFLEN_MASK;
aungriah 0:a3b83d366423 2277 }
aungriah 0:a3b83d366423 2278 dw1000local.cbData.datalength = len;
aungriah 0:a3b83d366423 2279
aungriah 0:a3b83d366423 2280 // Report ranging bit
aungriah 0:a3b83d366423 2281 if(finfo16 & RX_FINFO_RNG)
aungriah 0:a3b83d366423 2282 {
aungriah 0:a3b83d366423 2283 dw1000local.cbData.rx_flags |= DWT_CB_DATA_RX_FLAG_RNG;
aungriah 0:a3b83d366423 2284 }
aungriah 0:a3b83d366423 2285
aungriah 0:a3b83d366423 2286 // Report frame control - First bytes of the received frame.
aungriah 0:a3b83d366423 2287 dwt_readfromdevice(RX_BUFFER_ID, 0, FCTRL_LEN_MAX, dw1000local.cbData.fctrl);
aungriah 0:a3b83d366423 2288
aungriah 0:a3b83d366423 2289 // Because of a previous frame not being received properly, AAT bit can be set upon the proper reception of a frame not requesting for
aungriah 0:a3b83d366423 2290 // acknowledgement (ACK frame is not actually sent though). If the AAT bit is set, check ACK request bit in frame control to confirm (this
aungriah 0:a3b83d366423 2291 // implementation works only for IEEE802.15.4-2011 compliant frames).
aungriah 0:a3b83d366423 2292 // This issue is not documented at the time of writing this code. It should be in next release of DW1000 User Manual (v2.09, from July 2016).
aungriah 0:a3b83d366423 2293 if((status & SYS_STATUS_AAT) && ((dw1000local.cbData.fctrl[0] & FCTRL_ACK_REQ_MASK) == 0))
aungriah 0:a3b83d366423 2294 {
aungriah 0:a3b83d366423 2295 dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_AAT); // Clear AAT status bit in register
aungriah 0:a3b83d366423 2296 dw1000local.cbData.status &= ~SYS_STATUS_AAT; // Clear AAT status bit in callback data register copy
aungriah 0:a3b83d366423 2297 dw1000local.wait4resp = 0;
aungriah 0:a3b83d366423 2298 }
aungriah 0:a3b83d366423 2299
aungriah 0:a3b83d366423 2300 // Call the corresponding callback if present
aungriah 0:a3b83d366423 2301 if(dw1000local.cbRxOk != NULL)
aungriah 0:a3b83d366423 2302 {
aungriah 0:a3b83d366423 2303 dw1000local.cbRxOk(&dw1000local.cbData);
aungriah 0:a3b83d366423 2304 }
aungriah 0:a3b83d366423 2305 }
aungriah 0:a3b83d366423 2306
aungriah 0:a3b83d366423 2307 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2308 * @fn dwt_setleds()
aungriah 0:a3b83d366423 2309 *
aungriah 0:a3b83d366423 2310 * @brief This is used to set up Tx/Rx GPIOs which could be used to control LEDs
aungriah 0:a3b83d366423 2311 * Note: not completely IC dependent, also needs board with LEDS fitted on right I/O lines
aungriah 0:a3b83d366423 2312 * this function enables GPIOs 2 and 3 which are connected to LED3 and LED4 on EVB1000
aungriah 0:a3b83d366423 2313 *
aungriah 0:a3b83d366423 2314 * input parameters
aungriah 0:a3b83d366423 2315 * @param mode - this is a bit field interpreted as follows:
aungriah 0:a3b83d366423 2316 * - bit 0: 1 to enable LEDs, 0 to disable them
aungriah 0:a3b83d366423 2317 * - bit 1: 1 to make LEDs blink once on init. Only valid if bit 0 is set (enable LEDs)
aungriah 0:a3b83d366423 2318 * - bit 2 to 7: reserved
aungriah 0:a3b83d366423 2319 *
aungriah 0:a3b83d366423 2320 * output parameters none
aungriah 0:a3b83d366423 2321 *
aungriah 0:a3b83d366423 2322 * no return value
aungriah 0:a3b83d366423 2323 */
aungriah 0:a3b83d366423 2324 void dwt_setleds(uint8 mode)
aungriah 0:a3b83d366423 2325 {
aungriah 0:a3b83d366423 2326 uint32 reg;
aungriah 0:a3b83d366423 2327
aungriah 0:a3b83d366423 2328 if (mode & DWT_LEDS_ENABLE)
aungriah 0:a3b83d366423 2329 {
aungriah 0:a3b83d366423 2330 // Set up MFIO for LED output.
aungriah 0:a3b83d366423 2331 reg = dwt_read32bitoffsetreg(GPIO_CTRL_ID, GPIO_MODE_OFFSET);
aungriah 0:a3b83d366423 2332 reg &= ~(GPIO_MSGP2_MASK | GPIO_MSGP3_MASK);
aungriah 0:a3b83d366423 2333 reg |= (GPIO_PIN2_RXLED | GPIO_PIN3_TXLED);
aungriah 0:a3b83d366423 2334 dwt_write32bitoffsetreg(GPIO_CTRL_ID, GPIO_MODE_OFFSET, reg);
aungriah 0:a3b83d366423 2335
aungriah 0:a3b83d366423 2336 // Enable LP Oscillator to run from counter and turn on de-bounce clock.
aungriah 0:a3b83d366423 2337 reg = dwt_read32bitoffsetreg(PMSC_ID, PMSC_CTRL0_OFFSET);
aungriah 0:a3b83d366423 2338 reg |= (PMSC_CTRL0_GPDCE | PMSC_CTRL0_KHZCLEN);
aungriah 0:a3b83d366423 2339 dwt_write32bitoffsetreg(PMSC_ID, PMSC_CTRL0_OFFSET, reg);
aungriah 0:a3b83d366423 2340
aungriah 0:a3b83d366423 2341 // Enable LEDs to blink and set default blink time.
aungriah 0:a3b83d366423 2342 reg = PMSC_LEDC_BLNKEN | PMSC_LEDC_BLINK_TIME_DEF;
aungriah 0:a3b83d366423 2343 // Make LEDs blink once if requested.
aungriah 0:a3b83d366423 2344 if (mode & DWT_LEDS_INIT_BLINK)
aungriah 0:a3b83d366423 2345 {
aungriah 0:a3b83d366423 2346 reg |= PMSC_LEDC_BLINK_NOW_ALL;
aungriah 0:a3b83d366423 2347 }
aungriah 0:a3b83d366423 2348 dwt_write32bitoffsetreg(PMSC_ID, PMSC_LEDC_OFFSET, reg);
aungriah 0:a3b83d366423 2349 // Clear force blink bits if needed.
aungriah 0:a3b83d366423 2350 if(mode & DWT_LEDS_INIT_BLINK)
aungriah 0:a3b83d366423 2351 {
aungriah 0:a3b83d366423 2352 reg &= ~PMSC_LEDC_BLINK_NOW_ALL;
aungriah 0:a3b83d366423 2353 dwt_write32bitoffsetreg(PMSC_ID, PMSC_LEDC_OFFSET, reg);
aungriah 0:a3b83d366423 2354 }
aungriah 0:a3b83d366423 2355 }
aungriah 0:a3b83d366423 2356 else
aungriah 0:a3b83d366423 2357 {
aungriah 0:a3b83d366423 2358 // Clear the GPIO bits that are used for LED control.
aungriah 0:a3b83d366423 2359 reg = dwt_read32bitoffsetreg(GPIO_CTRL_ID, GPIO_MODE_OFFSET);
aungriah 0:a3b83d366423 2360 reg &= ~(GPIO_MSGP2_MASK | GPIO_MSGP3_MASK);
aungriah 0:a3b83d366423 2361 dwt_write32bitoffsetreg(GPIO_CTRL_ID, GPIO_MODE_OFFSET, reg);
aungriah 0:a3b83d366423 2362 }
aungriah 0:a3b83d366423 2363 }
aungriah 0:a3b83d366423 2364
aungriah 0:a3b83d366423 2365 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2366 * @fn _dwt_enableclocks()
aungriah 0:a3b83d366423 2367 *
aungriah 0:a3b83d366423 2368 * @brief function to enable/disable clocks to particular digital blocks/system
aungriah 0:a3b83d366423 2369 *
aungriah 0:a3b83d366423 2370 * input parameters
aungriah 0:a3b83d366423 2371 * @param clocks - set of clocks to enable/disable
aungriah 0:a3b83d366423 2372 *
aungriah 0:a3b83d366423 2373 * output parameters none
aungriah 0:a3b83d366423 2374 *
aungriah 0:a3b83d366423 2375 * no return value
aungriah 0:a3b83d366423 2376 */
aungriah 0:a3b83d366423 2377 void _dwt_enableclocks(int clocks)
aungriah 0:a3b83d366423 2378 {
aungriah 0:a3b83d366423 2379 uint8 reg[2];
aungriah 0:a3b83d366423 2380
aungriah 0:a3b83d366423 2381 dwt_readfromdevice(PMSC_ID, PMSC_CTRL0_OFFSET, 2, reg);
aungriah 0:a3b83d366423 2382 switch(clocks)
aungriah 0:a3b83d366423 2383 {
aungriah 0:a3b83d366423 2384 case ENABLE_ALL_SEQ:
aungriah 0:a3b83d366423 2385 {
aungriah 0:a3b83d366423 2386 reg[0] = 0x00 ;
aungriah 0:a3b83d366423 2387 reg[1] = reg[1] & 0xfe;
aungriah 0:a3b83d366423 2388 }
aungriah 0:a3b83d366423 2389 break;
aungriah 0:a3b83d366423 2390 case FORCE_SYS_XTI:
aungriah 0:a3b83d366423 2391 {
aungriah 0:a3b83d366423 2392 // System and RX
aungriah 0:a3b83d366423 2393 reg[0] = 0x01 | (reg[0] & 0xfc);
aungriah 0:a3b83d366423 2394 }
aungriah 0:a3b83d366423 2395 break;
aungriah 0:a3b83d366423 2396 case FORCE_SYS_PLL:
aungriah 0:a3b83d366423 2397 {
aungriah 0:a3b83d366423 2398 // System
aungriah 0:a3b83d366423 2399 reg[0] = 0x02 | (reg[0] & 0xfc);
aungriah 0:a3b83d366423 2400 }
aungriah 0:a3b83d366423 2401 break;
aungriah 0:a3b83d366423 2402 case READ_ACC_ON:
aungriah 0:a3b83d366423 2403 {
aungriah 0:a3b83d366423 2404 reg[0] = 0x48 | (reg[0] & 0xb3);
aungriah 0:a3b83d366423 2405 reg[1] = 0x80 | reg[1];
aungriah 0:a3b83d366423 2406 }
aungriah 0:a3b83d366423 2407 break;
aungriah 0:a3b83d366423 2408 case READ_ACC_OFF:
aungriah 0:a3b83d366423 2409 {
aungriah 0:a3b83d366423 2410 reg[0] = reg[0] & 0xb3;
aungriah 0:a3b83d366423 2411 reg[1] = 0x7f & reg[1];
aungriah 0:a3b83d366423 2412 }
aungriah 0:a3b83d366423 2413 break;
aungriah 0:a3b83d366423 2414 case FORCE_OTP_ON:
aungriah 0:a3b83d366423 2415 {
aungriah 0:a3b83d366423 2416 reg[1] = 0x02 | reg[1];
aungriah 0:a3b83d366423 2417 }
aungriah 0:a3b83d366423 2418 break;
aungriah 0:a3b83d366423 2419 case FORCE_OTP_OFF:
aungriah 0:a3b83d366423 2420 {
aungriah 0:a3b83d366423 2421 reg[1] = reg[1] & 0xfd;
aungriah 0:a3b83d366423 2422 }
aungriah 0:a3b83d366423 2423 break;
aungriah 0:a3b83d366423 2424 case FORCE_TX_PLL:
aungriah 0:a3b83d366423 2425 {
aungriah 0:a3b83d366423 2426 reg[0] = 0x20 | (reg[0] & 0xcf);
aungriah 0:a3b83d366423 2427 }
aungriah 0:a3b83d366423 2428 break;
aungriah 0:a3b83d366423 2429 case FORCE_LDE:
aungriah 0:a3b83d366423 2430 {
aungriah 0:a3b83d366423 2431 reg[0] = 0x01;
aungriah 0:a3b83d366423 2432 reg[1] = 0x03;
aungriah 0:a3b83d366423 2433 }
aungriah 0:a3b83d366423 2434 break;
aungriah 0:a3b83d366423 2435 default:
aungriah 0:a3b83d366423 2436 break;
aungriah 0:a3b83d366423 2437 }
aungriah 0:a3b83d366423 2438
aungriah 0:a3b83d366423 2439
aungriah 0:a3b83d366423 2440 // Need to write lower byte separately before setting the higher byte(s)
aungriah 0:a3b83d366423 2441 dwt_writetodevice(PMSC_ID, PMSC_CTRL0_OFFSET, 1, &reg[0]);
aungriah 0:a3b83d366423 2442 dwt_writetodevice(PMSC_ID, 0x1, 1, &reg[1]);
aungriah 0:a3b83d366423 2443
aungriah 0:a3b83d366423 2444 } // end _dwt_enableclocks()
aungriah 0:a3b83d366423 2445
aungriah 0:a3b83d366423 2446 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2447 * @fn _dwt_disablesequencing()
aungriah 0:a3b83d366423 2448 *
aungriah 0:a3b83d366423 2449 * @brief This function disables the TX blocks sequencing, it disables PMSC control of RF blocks, system clock is also set to XTAL
aungriah 0:a3b83d366423 2450 *
aungriah 0:a3b83d366423 2451 * input parameters none
aungriah 0:a3b83d366423 2452 *
aungriah 0:a3b83d366423 2453 * output parameters none
aungriah 0:a3b83d366423 2454 *
aungriah 0:a3b83d366423 2455 * no return value
aungriah 0:a3b83d366423 2456 */
aungriah 0:a3b83d366423 2457 void _dwt_disablesequencing(void) // Disable sequencing and go to state "INIT"
aungriah 0:a3b83d366423 2458 {
aungriah 0:a3b83d366423 2459 _dwt_enableclocks(FORCE_SYS_XTI); // Set system clock to XTI
aungriah 0:a3b83d366423 2460
aungriah 0:a3b83d366423 2461 dwt_write16bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET, PMSC_CTRL1_PKTSEQ_DISABLE); // Disable PMSC ctrl of RF and RX clk blocks
aungriah 0:a3b83d366423 2462 }
aungriah 0:a3b83d366423 2463
aungriah 0:a3b83d366423 2464 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2465 * @fn dwt_setdelayedtrxtime()
aungriah 0:a3b83d366423 2466 *
aungriah 0:a3b83d366423 2467 * @brief This API function configures the delayed transmit time or the delayed RX on time
aungriah 0:a3b83d366423 2468 *
aungriah 0:a3b83d366423 2469 * input parameters
aungriah 0:a3b83d366423 2470 * @param starttime - the TX/RX start time (the 32 bits should be the high 32 bits of the system time at which to send the message,
aungriah 0:a3b83d366423 2471 * or at which to turn on the receiver)
aungriah 0:a3b83d366423 2472 *
aungriah 0:a3b83d366423 2473 * output parameters none
aungriah 0:a3b83d366423 2474 *
aungriah 0:a3b83d366423 2475 * no return value
aungriah 0:a3b83d366423 2476 */
aungriah 0:a3b83d366423 2477 void dwt_setdelayedtrxtime(uint32 starttime)
aungriah 0:a3b83d366423 2478 {
aungriah 0:a3b83d366423 2479 dwt_write32bitoffsetreg(DX_TIME_ID, 1, starttime); // Write at offset 1 as the lower 9 bits of this register are ignored
aungriah 0:a3b83d366423 2480
aungriah 0:a3b83d366423 2481 } // end dwt_setdelayedtrxtime()
aungriah 0:a3b83d366423 2482
aungriah 0:a3b83d366423 2483 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2484 * @fn dwt_starttx()
aungriah 0:a3b83d366423 2485 *
aungriah 0:a3b83d366423 2486 * @brief This call initiates the transmission, input parameter indicates which TX mode is used see below
aungriah 0:a3b83d366423 2487 *
aungriah 0:a3b83d366423 2488 * input parameters:
aungriah 0:a3b83d366423 2489 * @param mode - if 0 immediate TX (no response expected)
aungriah 0:a3b83d366423 2490 * if 1 delayed TX (no response expected)
aungriah 0:a3b83d366423 2491 * if 2 immediate TX (response expected - so the receiver will be automatically turned on after TX is done)
aungriah 0:a3b83d366423 2492 * if 3 delayed TX (response expected - so the receiver will be automatically turned on after TX is done)
aungriah 0:a3b83d366423 2493 *
aungriah 0:a3b83d366423 2494 * output parameters
aungriah 0:a3b83d366423 2495 *
aungriah 0:a3b83d366423 2496 * returns DWT_SUCCESS for success, or DWT_ERROR for error (e.g. a delayed transmission will fail if the delayed time has passed)
aungriah 0:a3b83d366423 2497 */
aungriah 0:a3b83d366423 2498 int dwt_starttx(uint8 mode)
aungriah 0:a3b83d366423 2499 {
aungriah 0:a3b83d366423 2500 int retval = DWT_SUCCESS ;
aungriah 0:a3b83d366423 2501 uint8 temp = 0x00;
aungriah 0:a3b83d366423 2502 uint16 checkTxOK = 0 ;
aungriah 0:a3b83d366423 2503
aungriah 0:a3b83d366423 2504 if(mode & DWT_RESPONSE_EXPECTED)
aungriah 0:a3b83d366423 2505 {
aungriah 0:a3b83d366423 2506 temp = (uint8)SYS_CTRL_WAIT4RESP ; // Set wait4response bit
aungriah 0:a3b83d366423 2507 dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, temp);
aungriah 0:a3b83d366423 2508 dw1000local.wait4resp = 1;
aungriah 0:a3b83d366423 2509 }
aungriah 0:a3b83d366423 2510
aungriah 0:a3b83d366423 2511 if (mode & DWT_START_TX_DELAYED)
aungriah 0:a3b83d366423 2512 {
aungriah 0:a3b83d366423 2513 // Both SYS_CTRL_TXSTRT and SYS_CTRL_TXDLYS to correctly enable TX
aungriah 0:a3b83d366423 2514 temp |= (uint8)(SYS_CTRL_TXDLYS | SYS_CTRL_TXSTRT) ;
aungriah 0:a3b83d366423 2515 dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, temp);
aungriah 0:a3b83d366423 2516 checkTxOK = dwt_read16bitoffsetreg(SYS_STATUS_ID, 3); // Read at offset 3 to get the upper 2 bytes out of 5
aungriah 0:a3b83d366423 2517 if ((checkTxOK & SYS_STATUS_TXERR) == 0) // Transmit Delayed Send set over Half a Period away or Power Up error (there is enough time to send but not to power up individual blocks).
aungriah 0:a3b83d366423 2518 {
aungriah 0:a3b83d366423 2519 retval = DWT_SUCCESS ; // All okay
aungriah 0:a3b83d366423 2520 }
aungriah 0:a3b83d366423 2521 else
aungriah 0:a3b83d366423 2522 {
aungriah 0:a3b83d366423 2523 // I am taking DSHP set to Indicate that the TXDLYS was set too late for the specified DX_TIME.
aungriah 0:a3b83d366423 2524 // Remedial Action - (a) cancel delayed send
aungriah 0:a3b83d366423 2525 temp = (uint8)SYS_CTRL_TRXOFF; // This assumes the bit is in the lowest byte
aungriah 0:a3b83d366423 2526 dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, temp);
aungriah 0:a3b83d366423 2527 // Note event Delayed TX Time too Late
aungriah 0:a3b83d366423 2528 // Could fall through to start a normal send (below) just sending late.....
aungriah 0:a3b83d366423 2529 // ... instead return and assume return value of 1 will be used to detect and recover from the issue.
aungriah 0:a3b83d366423 2530 dw1000local.wait4resp = 0;
aungriah 0:a3b83d366423 2531 retval = DWT_ERROR ; // Failed !
aungriah 0:a3b83d366423 2532 }
aungriah 0:a3b83d366423 2533 }
aungriah 0:a3b83d366423 2534 else
aungriah 0:a3b83d366423 2535 {
aungriah 0:a3b83d366423 2536 temp |= (uint8)SYS_CTRL_TXSTRT ;
aungriah 0:a3b83d366423 2537 dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, temp);
aungriah 0:a3b83d366423 2538 }
aungriah 0:a3b83d366423 2539
aungriah 0:a3b83d366423 2540 return retval;
aungriah 0:a3b83d366423 2541
aungriah 0:a3b83d366423 2542 } // end dwt_starttx()
aungriah 0:a3b83d366423 2543
aungriah 0:a3b83d366423 2544 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2545 * @fn dwt_forcetrxoff()
aungriah 0:a3b83d366423 2546 *
aungriah 0:a3b83d366423 2547 * @brief This is used to turn off the transceiver
aungriah 0:a3b83d366423 2548 *
aungriah 0:a3b83d366423 2549 * input parameters
aungriah 0:a3b83d366423 2550 *
aungriah 0:a3b83d366423 2551 * output parameters
aungriah 0:a3b83d366423 2552 *
aungriah 0:a3b83d366423 2553 * no return value
aungriah 0:a3b83d366423 2554 */
aungriah 0:a3b83d366423 2555 void dwt_forcetrxoff(void)
aungriah 0:a3b83d366423 2556 {
aungriah 0:a3b83d366423 2557 decaIrqStatus_t stat ;
aungriah 0:a3b83d366423 2558 uint32 mask;
aungriah 0:a3b83d366423 2559
aungriah 0:a3b83d366423 2560 mask = dwt_read32bitreg(SYS_MASK_ID) ; // Read set interrupt mask
aungriah 0:a3b83d366423 2561
aungriah 0:a3b83d366423 2562 // Need to beware of interrupts occurring in the middle of following read modify write cycle
aungriah 0:a3b83d366423 2563 // We can disable the radio, but before the status is cleared an interrupt can be set (e.g. the
aungriah 0:a3b83d366423 2564 // event has just happened before the radio was disabled)
aungriah 0:a3b83d366423 2565 // thus we need to disable interrupt during this operation
aungriah 0:a3b83d366423 2566 stat = decamutexon() ;
aungriah 0:a3b83d366423 2567
aungriah 0:a3b83d366423 2568 dwt_write32bitreg(SYS_MASK_ID, 0) ; // Clear interrupt mask - so we don't get any unwanted events
aungriah 0:a3b83d366423 2569
aungriah 0:a3b83d366423 2570 dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, (uint8)SYS_CTRL_TRXOFF) ; // Disable the radio
aungriah 0:a3b83d366423 2571
aungriah 0:a3b83d366423 2572 // Forcing Transceiver off - so we do not want to see any new events that may have happened
aungriah 0:a3b83d366423 2573 dwt_write32bitreg(SYS_STATUS_ID, (SYS_STATUS_ALL_TX | SYS_STATUS_ALL_RX_ERR | SYS_STATUS_ALL_RX_TO | SYS_STATUS_ALL_RX_GOOD));
aungriah 0:a3b83d366423 2574
aungriah 0:a3b83d366423 2575 dwt_syncrxbufptrs();
aungriah 0:a3b83d366423 2576
aungriah 0:a3b83d366423 2577 dwt_write32bitreg(SYS_MASK_ID, mask) ; // Set interrupt mask to what it was
aungriah 0:a3b83d366423 2578
aungriah 0:a3b83d366423 2579 // Enable/restore interrupts again...
aungriah 0:a3b83d366423 2580 decamutexoff(stat) ;
aungriah 0:a3b83d366423 2581 dw1000local.wait4resp = 0;
aungriah 0:a3b83d366423 2582
aungriah 0:a3b83d366423 2583 } // end deviceforcetrxoff()
aungriah 0:a3b83d366423 2584
aungriah 0:a3b83d366423 2585 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2586 * @fn dwt_syncrxbufptrs()
aungriah 0:a3b83d366423 2587 *
aungriah 0:a3b83d366423 2588 * @brief this function synchronizes rx buffer pointers
aungriah 0:a3b83d366423 2589 * need to make sure that the host/IC buffer pointers are aligned before starting RX
aungriah 0:a3b83d366423 2590 *
aungriah 0:a3b83d366423 2591 * input parameters:
aungriah 0:a3b83d366423 2592 *
aungriah 0:a3b83d366423 2593 * output parameters
aungriah 0:a3b83d366423 2594 *
aungriah 0:a3b83d366423 2595 * no return value
aungriah 0:a3b83d366423 2596 */
aungriah 0:a3b83d366423 2597 void dwt_syncrxbufptrs(void)
aungriah 0:a3b83d366423 2598 {
aungriah 0:a3b83d366423 2599 uint8 buff ;
aungriah 0:a3b83d366423 2600 // Need to make sure that the host/IC buffer pointers are aligned before starting RX
aungriah 0:a3b83d366423 2601 buff = dwt_read8bitoffsetreg(SYS_STATUS_ID, 3); // Read 1 byte at offset 3 to get the 4th byte out of 5
aungriah 0:a3b83d366423 2602
aungriah 0:a3b83d366423 2603 if((buff & (SYS_STATUS_ICRBP >> 24)) != // IC side Receive Buffer Pointer
aungriah 0:a3b83d366423 2604 ((buff & (SYS_STATUS_HSRBP>>24)) << 1) ) // Host Side Receive Buffer Pointer
aungriah 0:a3b83d366423 2605 {
aungriah 0:a3b83d366423 2606 dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_HRBT_OFFSET , 0x01) ; // We need to swap RX buffer status reg (write one to toggle internally)
aungriah 0:a3b83d366423 2607 }
aungriah 0:a3b83d366423 2608 }
aungriah 0:a3b83d366423 2609
aungriah 0:a3b83d366423 2610 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2611 * @fn dwt_setsniffmode()
aungriah 0:a3b83d366423 2612 *
aungriah 0:a3b83d366423 2613 * @brief enable/disable and configure SNIFF mode.
aungriah 0:a3b83d366423 2614 *
aungriah 0:a3b83d366423 2615 * SNIFF mode is a low-power reception mode where the receiver is sequenced on and off instead of being on all the time.
aungriah 0:a3b83d366423 2616 * The time spent in each state (on/off) is specified through the parameters below.
aungriah 0:a3b83d366423 2617 * See DW1000 User Manual section 4.5 "Low-Power SNIFF mode" for more details.
aungriah 0:a3b83d366423 2618 *
aungriah 0:a3b83d366423 2619 * input parameters:
aungriah 0:a3b83d366423 2620 * @param enable - 1 to enable SNIFF mode, 0 to disable. When 0, all other parameters are not taken into account.
aungriah 0:a3b83d366423 2621 * @param timeOn - duration of receiver ON phase, expressed in multiples of PAC size. The counter automatically adds 1 PAC
aungriah 0:a3b83d366423 2622 * size to the value set. Min value that can be set is 1 (i.e. an ON time of 2 PAC size), max value is 15.
aungriah 0:a3b83d366423 2623 * @param timeOff - duration of receiver OFF phase, expressed in multiples of 128/125 µs (~1 µs). Max value is 255.
aungriah 0:a3b83d366423 2624 *
aungriah 0:a3b83d366423 2625 * output parameters
aungriah 0:a3b83d366423 2626 *
aungriah 0:a3b83d366423 2627 * no return value
aungriah 0:a3b83d366423 2628 */
aungriah 0:a3b83d366423 2629 void dwt_setsniffmode(int enable, uint8 timeOn, uint8 timeOff)
aungriah 0:a3b83d366423 2630 {
aungriah 0:a3b83d366423 2631 uint32 pmsc_reg;
aungriah 0:a3b83d366423 2632 if (enable)
aungriah 0:a3b83d366423 2633 {
aungriah 0:a3b83d366423 2634 /* Configure ON/OFF times and enable PLL2 on/off sequencing by SNIFF mode. */
aungriah 0:a3b83d366423 2635 uint16 sniff_reg = ((timeOff << 8) | timeOn) & RX_SNIFF_MASK;
aungriah 0:a3b83d366423 2636 dwt_write16bitoffsetreg(RX_SNIFF_ID, RX_SNIFF_OFFSET, sniff_reg);
aungriah 0:a3b83d366423 2637 pmsc_reg = dwt_read32bitoffsetreg(PMSC_ID, PMSC_CTRL0_OFFSET);
aungriah 0:a3b83d366423 2638 pmsc_reg |= PMSC_CTRL0_PLL2_SEQ_EN;
aungriah 0:a3b83d366423 2639 dwt_write32bitoffsetreg(PMSC_ID, PMSC_CTRL0_OFFSET, pmsc_reg);
aungriah 0:a3b83d366423 2640 }
aungriah 0:a3b83d366423 2641 else
aungriah 0:a3b83d366423 2642 {
aungriah 0:a3b83d366423 2643 /* Clear ON/OFF times and disable PLL2 on/off sequencing by SNIFF mode. */
aungriah 0:a3b83d366423 2644 dwt_write16bitoffsetreg(RX_SNIFF_ID, RX_SNIFF_OFFSET, 0x0000);
aungriah 0:a3b83d366423 2645 pmsc_reg = dwt_read32bitoffsetreg(PMSC_ID, PMSC_CTRL0_OFFSET);
aungriah 0:a3b83d366423 2646 pmsc_reg &= ~PMSC_CTRL0_PLL2_SEQ_EN;
aungriah 0:a3b83d366423 2647 dwt_write32bitoffsetreg(PMSC_ID, PMSC_CTRL0_OFFSET, pmsc_reg);
aungriah 0:a3b83d366423 2648 }
aungriah 0:a3b83d366423 2649 }
aungriah 0:a3b83d366423 2650
aungriah 0:a3b83d366423 2651 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2652 * @fn dwt_setlowpowerlistening()
aungriah 0:a3b83d366423 2653 *
aungriah 0:a3b83d366423 2654 * @brief enable/disable low-power listening mode.
aungriah 0:a3b83d366423 2655 *
aungriah 0:a3b83d366423 2656 * Low-power listening is a feature whereby the DW1000 is predominantly in the SLEEP state but wakes periodically, (after
aungriah 0:a3b83d366423 2657 * this "long sleep"), for a very short time to sample the air for a preamble sequence. This preamble sampling "listening"
aungriah 0:a3b83d366423 2658 * phase is actually two reception phases separated by a "short sleep" time. See DW1000 User Manual section "Low-Power
aungriah 0:a3b83d366423 2659 * Listening" for more details.
aungriah 0:a3b83d366423 2660 *
aungriah 0:a3b83d366423 2661 * NOTE: Before enabling low-power listening, the following functions have to be called to fully configure it:
aungriah 0:a3b83d366423 2662 * - dwt_configuresleep() to configure long sleep phase. "mode" parameter should at least have DWT_PRESRV_SLEEP,
aungriah 0:a3b83d366423 2663 * DWT_CONFIG and DWT_RX_EN set and "wake" parameter should at least have both DWT_WAKE_SLPCNT and DWT_SLP_EN set.
aungriah 0:a3b83d366423 2664 * - dwt_calibratesleepcnt() and dwt_configuresleepcnt() to define the "long sleep" phase duration.
aungriah 0:a3b83d366423 2665 * - dwt_setsnoozetime() to define the "short sleep" phase duration.
aungriah 0:a3b83d366423 2666 * - dwt_setpreambledetecttimeout() to define the reception phases duration.
aungriah 0:a3b83d366423 2667 * - dwt_setinterrupt() to activate RX good frame interrupt (DWT_INT_RFCG) only.
aungriah 0:a3b83d366423 2668 * When configured, low-power listening mode can be triggered either by putting the DW1000 to sleep (using
aungriah 0:a3b83d366423 2669 * dwt_entersleep()) or by activating reception (using dwt_rxenable()).
aungriah 0:a3b83d366423 2670 *
aungriah 0:a3b83d366423 2671 * Please refer to the low-power listening examples (examples 8a/8b accompanying the API distribution on Decawave's
aungriah 0:a3b83d366423 2672 * website). They form a working example code that shows how to use low-power listening correctly.
aungriah 0:a3b83d366423 2673 *
aungriah 0:a3b83d366423 2674 * input parameters:
aungriah 0:a3b83d366423 2675 * @param enable - 1 to enable low-power listening, 0 to disable.
aungriah 0:a3b83d366423 2676 *
aungriah 0:a3b83d366423 2677 * output parameters
aungriah 0:a3b83d366423 2678 *
aungriah 0:a3b83d366423 2679 * no return value
aungriah 0:a3b83d366423 2680 */
aungriah 0:a3b83d366423 2681 void dwt_setlowpowerlistening(int enable)
aungriah 0:a3b83d366423 2682 {
aungriah 0:a3b83d366423 2683 uint32 pmsc_reg = dwt_read32bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET);
aungriah 0:a3b83d366423 2684 if (enable)
aungriah 0:a3b83d366423 2685 {
aungriah 0:a3b83d366423 2686 /* Configure RX to sleep and snooze features. */
aungriah 0:a3b83d366423 2687 pmsc_reg |= (PMSC_CTRL1_ARXSLP | PMSC_CTRL1_SNOZE);
aungriah 0:a3b83d366423 2688 }
aungriah 0:a3b83d366423 2689 else
aungriah 0:a3b83d366423 2690 {
aungriah 0:a3b83d366423 2691 /* Reset RX to sleep and snooze features. */
aungriah 0:a3b83d366423 2692 pmsc_reg &= ~(PMSC_CTRL1_ARXSLP | PMSC_CTRL1_SNOZE);
aungriah 0:a3b83d366423 2693 }
aungriah 0:a3b83d366423 2694 dwt_write32bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET, pmsc_reg);
aungriah 0:a3b83d366423 2695 }
aungriah 0:a3b83d366423 2696
aungriah 0:a3b83d366423 2697 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2698 * @fn dwt_setsnoozetime()
aungriah 0:a3b83d366423 2699 *
aungriah 0:a3b83d366423 2700 * @brief Set duration of "short sleep" phase when in low-power listening mode.
aungriah 0:a3b83d366423 2701 *
aungriah 0:a3b83d366423 2702 * input parameters:
aungriah 0:a3b83d366423 2703 * @param snooze_time - "short sleep" phase duration, expressed in multiples of 512/19.2 µs (~26.7 µs). The counter
aungriah 0:a3b83d366423 2704 * automatically adds 1 to the value set. The smallest working value that should be set is 1,
aungriah 0:a3b83d366423 2705 * i.e. giving a snooze time of 2 units (or ~53 µs).
aungriah 0:a3b83d366423 2706 *
aungriah 0:a3b83d366423 2707 * output parameters
aungriah 0:a3b83d366423 2708 *
aungriah 0:a3b83d366423 2709 * no return value
aungriah 0:a3b83d366423 2710 */
aungriah 0:a3b83d366423 2711 void dwt_setsnoozetime(uint8 snooze_time)
aungriah 0:a3b83d366423 2712 {
aungriah 0:a3b83d366423 2713 dwt_write8bitoffsetreg(PMSC_ID, PMSC_SNOZT_OFFSET, snooze_time);
aungriah 0:a3b83d366423 2714 }
aungriah 0:a3b83d366423 2715
aungriah 0:a3b83d366423 2716 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2717 * @fn dwt_rxenable()
aungriah 0:a3b83d366423 2718 *
aungriah 0:a3b83d366423 2719 * @brief This call turns on the receiver, can be immediate or delayed (depending on the mode parameter). In the case of a
aungriah 0:a3b83d366423 2720 * "late" error the receiver will only be turned on if the DWT_IDLE_ON_DLY_ERR is not set.
aungriah 0:a3b83d366423 2721 * The receiver will stay turned on, listening to any messages until
aungriah 0:a3b83d366423 2722 * it either receives a good frame, an error (CRC, PHY header, Reed Solomon) or it times out (SFD, Preamble or Frame).
aungriah 0:a3b83d366423 2723 *
aungriah 0:a3b83d366423 2724 * input parameters
aungriah 0:a3b83d366423 2725 * @param mode - this can be one of the following allowed values:
aungriah 0:a3b83d366423 2726 *
aungriah 0:a3b83d366423 2727 * DWT_START_RX_IMMEDIATE 0 used to enbale receiver immediately
aungriah 0:a3b83d366423 2728 * DWT_START_RX_DELAYED 1 used to set up delayed RX, if "late" error triggers, then the RX will be enabled immediately
aungriah 0:a3b83d366423 2729 * (DWT_START_RX_DELAYED | DWT_IDLE_ON_DLY_ERR) 3 used to disable re-enabling of receiver if delayed RX failed due to "late" error
aungriah 0:a3b83d366423 2730 * (DWT_START_RX_IMMEDIATE | DWT_NO_SYNC_PTRS) 4 used to re-enable RX without trying to sync IC and host side buffer pointers, typically when
aungriah 0:a3b83d366423 2731 * performing manual RX re-enabling in double buffering mode
aungriah 0:a3b83d366423 2732 *
aungriah 0:a3b83d366423 2733 * returns DWT_SUCCESS for success, or DWT_ERROR for error (e.g. a delayed receive enable will be too far in the future if delayed time has passed)
aungriah 0:a3b83d366423 2734 */
aungriah 0:a3b83d366423 2735 int dwt_rxenable(int mode)
aungriah 0:a3b83d366423 2736 {
aungriah 0:a3b83d366423 2737 uint16 temp ;
aungriah 0:a3b83d366423 2738 uint8 temp1 ;
aungriah 0:a3b83d366423 2739
aungriah 0:a3b83d366423 2740 if ((mode & DWT_NO_SYNC_PTRS) == 0)
aungriah 0:a3b83d366423 2741 {
aungriah 0:a3b83d366423 2742 dwt_syncrxbufptrs();
aungriah 0:a3b83d366423 2743 }
aungriah 0:a3b83d366423 2744
aungriah 0:a3b83d366423 2745 temp = (uint16)SYS_CTRL_RXENAB ;
aungriah 0:a3b83d366423 2746
aungriah 0:a3b83d366423 2747 if (mode & DWT_START_RX_DELAYED)
aungriah 0:a3b83d366423 2748 {
aungriah 0:a3b83d366423 2749 temp |= (uint16)SYS_CTRL_RXDLYE ;
aungriah 0:a3b83d366423 2750 }
aungriah 0:a3b83d366423 2751
aungriah 0:a3b83d366423 2752 dwt_write16bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, temp);
aungriah 0:a3b83d366423 2753
aungriah 0:a3b83d366423 2754 if (mode & DWT_START_RX_DELAYED) // check for errors
aungriah 0:a3b83d366423 2755 {
aungriah 0:a3b83d366423 2756 temp1 = dwt_read8bitoffsetreg(SYS_STATUS_ID, 3); // Read 1 byte at offset 3 to get the 4th byte out of 5
aungriah 0:a3b83d366423 2757 if ((temp1 & (SYS_STATUS_HPDWARN >> 24)) != 0) // if delay has passed do immediate RX on unless DWT_IDLE_ON_DLY_ERR is true
aungriah 0:a3b83d366423 2758 {
aungriah 0:a3b83d366423 2759 dwt_forcetrxoff(); // turn the delayed receive off
aungriah 0:a3b83d366423 2760
aungriah 0:a3b83d366423 2761 if((mode & DWT_IDLE_ON_DLY_ERR) == 0) // if DWT_IDLE_ON_DLY_ERR not set then re-enable receiver
aungriah 0:a3b83d366423 2762 {
aungriah 0:a3b83d366423 2763 dwt_write16bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, SYS_CTRL_RXENAB);
aungriah 0:a3b83d366423 2764 }
aungriah 0:a3b83d366423 2765 return DWT_ERROR; // return warning indication
aungriah 0:a3b83d366423 2766 }
aungriah 0:a3b83d366423 2767 }
aungriah 0:a3b83d366423 2768
aungriah 0:a3b83d366423 2769 return DWT_SUCCESS;
aungriah 0:a3b83d366423 2770 } // end dwt_rxenable()
aungriah 0:a3b83d366423 2771
aungriah 0:a3b83d366423 2772 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2773 * @fn dwt_setrxtimeout()
aungriah 0:a3b83d366423 2774 *
aungriah 0:a3b83d366423 2775 * @brief This call enables RX timeout (SY_STAT_RFTO event)
aungriah 0:a3b83d366423 2776 *
aungriah 0:a3b83d366423 2777 * input parameters
aungriah 0:a3b83d366423 2778 * @param time - how long the receiver remains on from the RX enable command
aungriah 0:a3b83d366423 2779 * The time parameter used here is in 1.0256 us (512/499.2MHz) units
aungriah 0:a3b83d366423 2780 * If set to 0 the timeout is disabled.
aungriah 0:a3b83d366423 2781 *
aungriah 0:a3b83d366423 2782 * output parameters
aungriah 0:a3b83d366423 2783 *
aungriah 0:a3b83d366423 2784 * no return value
aungriah 0:a3b83d366423 2785 */
aungriah 0:a3b83d366423 2786 void dwt_setrxtimeout(uint16 time)
aungriah 0:a3b83d366423 2787 {
aungriah 0:a3b83d366423 2788 uint8 temp ;
aungriah 0:a3b83d366423 2789
aungriah 0:a3b83d366423 2790 temp = dwt_read8bitoffsetreg(SYS_CFG_ID, 3); // Read at offset 3 to get the upper byte only
aungriah 0:a3b83d366423 2791
aungriah 0:a3b83d366423 2792 if(time > 0)
aungriah 0:a3b83d366423 2793 {
aungriah 0:a3b83d366423 2794 dwt_write16bitoffsetreg(RX_FWTO_ID, RX_FWTO_OFFSET, time) ;
aungriah 0:a3b83d366423 2795
aungriah 0:a3b83d366423 2796 temp |= (uint8)(SYS_CFG_RXWTOE>>24); // Shift RXWTOE mask as we read the upper byte only
aungriah 0:a3b83d366423 2797 // OR in 32bit value (1 bit set), I know this is in high byte.
aungriah 0:a3b83d366423 2798 dw1000local.sysCFGreg |= SYS_CFG_RXWTOE;
aungriah 0:a3b83d366423 2799
aungriah 0:a3b83d366423 2800 dwt_write8bitoffsetreg(SYS_CFG_ID, 3, temp); // Write at offset 3 to write the upper byte only
aungriah 0:a3b83d366423 2801 }
aungriah 0:a3b83d366423 2802 else
aungriah 0:a3b83d366423 2803 {
aungriah 0:a3b83d366423 2804 temp &= ~((uint8)(SYS_CFG_RXWTOE>>24)); // Shift RXWTOE mask as we read the upper byte only
aungriah 0:a3b83d366423 2805 // AND in inverted 32bit value (1 bit clear), I know this is in high byte.
aungriah 0:a3b83d366423 2806 dw1000local.sysCFGreg &= ~(SYS_CFG_RXWTOE);
aungriah 0:a3b83d366423 2807
aungriah 0:a3b83d366423 2808 dwt_write8bitoffsetreg(SYS_CFG_ID, 3, temp); // Write at offset 3 to write the upper byte only
aungriah 0:a3b83d366423 2809 }
aungriah 0:a3b83d366423 2810
aungriah 0:a3b83d366423 2811 } // end dwt_setrxtimeout()
aungriah 0:a3b83d366423 2812
aungriah 0:a3b83d366423 2813
aungriah 0:a3b83d366423 2814 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2815 * @fn dwt_setpreambledetecttimeout()
aungriah 0:a3b83d366423 2816 *
aungriah 0:a3b83d366423 2817 * @brief This call enables preamble timeout (SY_STAT_RXPTO event)
aungriah 0:a3b83d366423 2818 *
aungriah 0:a3b83d366423 2819 * input parameters
aungriah 0:a3b83d366423 2820 * @param timeout - Preamble detection timeout, expressed in multiples of PAC size. The counter automatically adds 1 PAC
aungriah 0:a3b83d366423 2821 * size to the value set. Min value that can be set is 1 (i.e. a timeout of 2 PAC size).
aungriah 0:a3b83d366423 2822 *
aungriah 0:a3b83d366423 2823 * output parameters
aungriah 0:a3b83d366423 2824 *
aungriah 0:a3b83d366423 2825 * no return value
aungriah 0:a3b83d366423 2826 */
aungriah 0:a3b83d366423 2827 void dwt_setpreambledetecttimeout(uint16 timeout)
aungriah 0:a3b83d366423 2828 {
aungriah 0:a3b83d366423 2829 dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_PRETOC_OFFSET, timeout);
aungriah 0:a3b83d366423 2830 }
aungriah 0:a3b83d366423 2831
aungriah 0:a3b83d366423 2832 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2833 * @fn void dwt_setinterrupt()
aungriah 0:a3b83d366423 2834 *
aungriah 0:a3b83d366423 2835 * @brief This function enables the specified events to trigger an interrupt.
aungriah 0:a3b83d366423 2836 * The following events can be enabled:
aungriah 0:a3b83d366423 2837 * DWT_INT_TFRS 0x00000080 // frame sent
aungriah 0:a3b83d366423 2838 * DWT_INT_RFCG 0x00004000 // frame received with good CRC
aungriah 0:a3b83d366423 2839 * DWT_INT_RPHE 0x00001000 // receiver PHY header error
aungriah 0:a3b83d366423 2840 * DWT_INT_RFCE 0x00008000 // receiver CRC error
aungriah 0:a3b83d366423 2841 * DWT_INT_RFSL 0x00010000 // receiver sync loss error
aungriah 0:a3b83d366423 2842 * DWT_INT_RFTO 0x00020000 // frame wait timeout
aungriah 0:a3b83d366423 2843 * DWT_INT_RXPTO 0x00200000 // preamble detect timeout
aungriah 0:a3b83d366423 2844 * DWT_INT_SFDT 0x04000000 // SFD timeout
aungriah 0:a3b83d366423 2845 * DWT_INT_ARFE 0x20000000 // frame rejected (due to frame filtering configuration)
aungriah 0:a3b83d366423 2846 *
aungriah 0:a3b83d366423 2847 *
aungriah 0:a3b83d366423 2848 * input parameters:
aungriah 0:a3b83d366423 2849 * @param bitmask - sets the events which will generate interrupt
aungriah 0:a3b83d366423 2850 * @param enable - if set the interrupts are enabled else they are cleared
aungriah 0:a3b83d366423 2851 *
aungriah 0:a3b83d366423 2852 * output parameters
aungriah 0:a3b83d366423 2853 *
aungriah 0:a3b83d366423 2854 * no return value
aungriah 0:a3b83d366423 2855 */
aungriah 0:a3b83d366423 2856 void dwt_setinterrupt(uint32 bitmask, uint8 enable)
aungriah 0:a3b83d366423 2857 {
aungriah 0:a3b83d366423 2858 decaIrqStatus_t stat ;
aungriah 0:a3b83d366423 2859 uint32 mask ;
aungriah 0:a3b83d366423 2860
aungriah 0:a3b83d366423 2861 // Need to beware of interrupts occurring in the middle of following read modify write cycle
aungriah 0:a3b83d366423 2862 stat = decamutexon() ;
aungriah 0:a3b83d366423 2863
aungriah 0:a3b83d366423 2864 mask = dwt_read32bitreg(SYS_MASK_ID) ; // Read register
aungriah 0:a3b83d366423 2865
aungriah 0:a3b83d366423 2866 if(enable)
aungriah 0:a3b83d366423 2867 {
aungriah 0:a3b83d366423 2868 mask |= bitmask ;
aungriah 0:a3b83d366423 2869 }
aungriah 0:a3b83d366423 2870 else
aungriah 0:a3b83d366423 2871 {
aungriah 0:a3b83d366423 2872 mask &= ~bitmask ; // Clear the bit
aungriah 0:a3b83d366423 2873 }
aungriah 0:a3b83d366423 2874 dwt_write32bitreg(SYS_MASK_ID,mask) ; // New value
aungriah 0:a3b83d366423 2875
aungriah 0:a3b83d366423 2876 decamutexoff(stat) ;
aungriah 0:a3b83d366423 2877 }
aungriah 0:a3b83d366423 2878
aungriah 0:a3b83d366423 2879 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2880 * @fn dwt_configeventcounters()
aungriah 0:a3b83d366423 2881 *
aungriah 0:a3b83d366423 2882 * @brief This is used to enable/disable the event counter in the IC
aungriah 0:a3b83d366423 2883 *
aungriah 0:a3b83d366423 2884 * input parameters
aungriah 0:a3b83d366423 2885 * @param - enable - 1 enables (and reset), 0 disables the event counters
aungriah 0:a3b83d366423 2886 * output parameters
aungriah 0:a3b83d366423 2887 *
aungriah 0:a3b83d366423 2888 * no return value
aungriah 0:a3b83d366423 2889 */
aungriah 0:a3b83d366423 2890 void dwt_configeventcounters(int enable)
aungriah 0:a3b83d366423 2891 {
aungriah 0:a3b83d366423 2892 // Need to clear and disable, can't just clear
aungriah 0:a3b83d366423 2893 dwt_write8bitoffsetreg(DIG_DIAG_ID, EVC_CTRL_OFFSET, (uint8)(EVC_CLR));
aungriah 0:a3b83d366423 2894
aungriah 0:a3b83d366423 2895 if(enable)
aungriah 0:a3b83d366423 2896 {
aungriah 0:a3b83d366423 2897 dwt_write8bitoffsetreg(DIG_DIAG_ID, EVC_CTRL_OFFSET, (uint8)(EVC_EN)); // Enable
aungriah 0:a3b83d366423 2898 }
aungriah 0:a3b83d366423 2899 }
aungriah 0:a3b83d366423 2900
aungriah 0:a3b83d366423 2901 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2902 * @fn dwt_readeventcounters()
aungriah 0:a3b83d366423 2903 *
aungriah 0:a3b83d366423 2904 * @brief This is used to read the event counters in the IC
aungriah 0:a3b83d366423 2905 *
aungriah 0:a3b83d366423 2906 * input parameters
aungriah 0:a3b83d366423 2907 * @param counters - pointer to the dwt_deviceentcnts_t structure which will hold the read data
aungriah 0:a3b83d366423 2908 *
aungriah 0:a3b83d366423 2909 * output parameters
aungriah 0:a3b83d366423 2910 *
aungriah 0:a3b83d366423 2911 * no return value
aungriah 0:a3b83d366423 2912 */
aungriah 0:a3b83d366423 2913 void dwt_readeventcounters(dwt_deviceentcnts_t *counters)
aungriah 0:a3b83d366423 2914 {
aungriah 0:a3b83d366423 2915 uint32 temp;
aungriah 0:a3b83d366423 2916
aungriah 0:a3b83d366423 2917 temp= dwt_read32bitoffsetreg(DIG_DIAG_ID, EVC_PHE_OFFSET); // Read sync loss (31-16), PHE (15-0)
aungriah 0:a3b83d366423 2918 counters->PHE = temp & 0xFFF;
aungriah 0:a3b83d366423 2919 counters->RSL = (temp >> 16) & 0xFFF;
aungriah 0:a3b83d366423 2920
aungriah 0:a3b83d366423 2921 temp = dwt_read32bitoffsetreg(DIG_DIAG_ID, EVC_FCG_OFFSET); // Read CRC bad (31-16), CRC good (15-0)
aungriah 0:a3b83d366423 2922 counters->CRCG = temp & 0xFFF;
aungriah 0:a3b83d366423 2923 counters->CRCB = (temp >> 16) & 0xFFF;
aungriah 0:a3b83d366423 2924
aungriah 0:a3b83d366423 2925 temp = dwt_read32bitoffsetreg(DIG_DIAG_ID, EVC_FFR_OFFSET); // Overruns (31-16), address errors (15-0)
aungriah 0:a3b83d366423 2926 counters->ARFE = temp & 0xFFF;
aungriah 0:a3b83d366423 2927 counters->OVER = (temp >> 16) & 0xFFF;
aungriah 0:a3b83d366423 2928
aungriah 0:a3b83d366423 2929 temp = dwt_read32bitoffsetreg(DIG_DIAG_ID, EVC_STO_OFFSET); // Read PTO (31-16), SFDTO (15-0)
aungriah 0:a3b83d366423 2930 counters->PTO = (temp >> 16) & 0xFFF;
aungriah 0:a3b83d366423 2931 counters->SFDTO = temp & 0xFFF;
aungriah 0:a3b83d366423 2932
aungriah 0:a3b83d366423 2933 temp = dwt_read32bitoffsetreg(DIG_DIAG_ID, EVC_FWTO_OFFSET); // Read RX TO (31-16), TXFRAME (15-0)
aungriah 0:a3b83d366423 2934 counters->TXF = (temp >> 16) & 0xFFF;
aungriah 0:a3b83d366423 2935 counters->RTO = temp & 0xFFF;
aungriah 0:a3b83d366423 2936
aungriah 0:a3b83d366423 2937 temp = dwt_read32bitoffsetreg(DIG_DIAG_ID, EVC_HPW_OFFSET); // Read half period warning events
aungriah 0:a3b83d366423 2938 counters->HPW = temp & 0xFFF;
aungriah 0:a3b83d366423 2939 counters->TXW = (temp >> 16) & 0xFFF; // Power-up warning events
aungriah 0:a3b83d366423 2940
aungriah 0:a3b83d366423 2941 }
aungriah 0:a3b83d366423 2942
aungriah 0:a3b83d366423 2943 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2944 * @fn dwt_rxreset()
aungriah 0:a3b83d366423 2945 *
aungriah 0:a3b83d366423 2946 * @brief this function resets the receiver of the DW1000
aungriah 0:a3b83d366423 2947 *
aungriah 0:a3b83d366423 2948 * input parameters:
aungriah 0:a3b83d366423 2949 *
aungriah 0:a3b83d366423 2950 * output parameters
aungriah 0:a3b83d366423 2951 *
aungriah 0:a3b83d366423 2952 * no return value
aungriah 0:a3b83d366423 2953 */
aungriah 0:a3b83d366423 2954 void dwt_rxreset(void)
aungriah 0:a3b83d366423 2955 {
aungriah 0:a3b83d366423 2956 // Set RX reset
aungriah 0:a3b83d366423 2957 dwt_write8bitoffsetreg(PMSC_ID, PMSC_CTRL0_SOFTRESET_OFFSET, PMSC_CTRL0_RESET_RX);
aungriah 0:a3b83d366423 2958
aungriah 0:a3b83d366423 2959 // Clear RX reset
aungriah 0:a3b83d366423 2960 dwt_write8bitoffsetreg(PMSC_ID, PMSC_CTRL0_SOFTRESET_OFFSET, PMSC_CTRL0_RESET_CLEAR);
aungriah 0:a3b83d366423 2961 }
aungriah 0:a3b83d366423 2962
aungriah 0:a3b83d366423 2963 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2964 * @fn dwt_softreset()
aungriah 0:a3b83d366423 2965 *
aungriah 0:a3b83d366423 2966 * @brief this function resets the DW1000
aungriah 0:a3b83d366423 2967 *
aungriah 0:a3b83d366423 2968 * input parameters:
aungriah 0:a3b83d366423 2969 *
aungriah 0:a3b83d366423 2970 * output parameters
aungriah 0:a3b83d366423 2971 *
aungriah 0:a3b83d366423 2972 * no return value
aungriah 0:a3b83d366423 2973 */
aungriah 0:a3b83d366423 2974 void dwt_softreset(void)
aungriah 0:a3b83d366423 2975 {
aungriah 0:a3b83d366423 2976 _dwt_disablesequencing();
aungriah 0:a3b83d366423 2977
aungriah 0:a3b83d366423 2978 // Clear any AON auto download bits (as reset will trigger AON download)
aungriah 0:a3b83d366423 2979 dwt_write16bitoffsetreg(AON_ID, AON_WCFG_OFFSET, 0x00);
aungriah 0:a3b83d366423 2980 // Clear the wake-up configuration
aungriah 0:a3b83d366423 2981 dwt_write8bitoffsetreg(AON_ID, AON_CFG0_OFFSET, 0x00);
aungriah 0:a3b83d366423 2982 // Upload the new configuration
aungriah 0:a3b83d366423 2983 _dwt_aonarrayupload();
aungriah 0:a3b83d366423 2984
aungriah 0:a3b83d366423 2985 // Reset HIF, TX, RX and PMSC
aungriah 0:a3b83d366423 2986 dwt_write8bitoffsetreg(PMSC_ID, PMSC_CTRL0_SOFTRESET_OFFSET, PMSC_CTRL0_RESET_ALL);
aungriah 0:a3b83d366423 2987
aungriah 0:a3b83d366423 2988 // DW1000 needs a 10us sleep to let clk PLL lock after reset - the PLL will automatically lock after the reset
aungriah 0:a3b83d366423 2989 // Could also have polled the PLL lock flag, but then the SPI needs to be < 3MHz !! So a simple delay is easier
aungriah 0:a3b83d366423 2990 deca_sleep(1);
aungriah 0:a3b83d366423 2991
aungriah 0:a3b83d366423 2992 // Clear reset
aungriah 0:a3b83d366423 2993 dwt_write8bitoffsetreg(PMSC_ID, PMSC_CTRL0_SOFTRESET_OFFSET, PMSC_CTRL0_RESET_CLEAR);
aungriah 0:a3b83d366423 2994
aungriah 0:a3b83d366423 2995 dw1000local.wait4resp = 0;
aungriah 0:a3b83d366423 2996 }
aungriah 0:a3b83d366423 2997
aungriah 0:a3b83d366423 2998 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 2999 * @fn dwt_setxtaltrim()
aungriah 0:a3b83d366423 3000 *
aungriah 0:a3b83d366423 3001 * @brief This is used to adjust the crystal frequency
aungriah 0:a3b83d366423 3002 *
aungriah 0:a3b83d366423 3003 * input parameters:
aungriah 0:a3b83d366423 3004 * @param value - crystal trim value (in range 0x0 to 0x1F) 31 steps (~1.5ppm per step)
aungriah 0:a3b83d366423 3005 *
aungriah 0:a3b83d366423 3006 * output parameters
aungriah 0:a3b83d366423 3007 *
aungriah 0:a3b83d366423 3008 * no return value
aungriah 0:a3b83d366423 3009 */
aungriah 0:a3b83d366423 3010 void dwt_setxtaltrim(uint8 value)
aungriah 0:a3b83d366423 3011 {
aungriah 0:a3b83d366423 3012 // The 3 MSb in this 8-bit register must be kept to 0b011 to avoid any malfunction.
aungriah 0:a3b83d366423 3013 uint8 reg_val = (3 << 5) | (value & FS_XTALT_MASK);
aungriah 0:a3b83d366423 3014 dwt_write8bitoffsetreg(FS_CTRL_ID, FS_XTALT_OFFSET, reg_val);
aungriah 0:a3b83d366423 3015 }
aungriah 0:a3b83d366423 3016
aungriah 0:a3b83d366423 3017 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 3018 * @fn dwt_getinitxtaltrim()
aungriah 0:a3b83d366423 3019 *
aungriah 0:a3b83d366423 3020 * @brief This function returns the value of XTAL trim that has been applied during initialisation (dwt_init). This can
aungriah 0:a3b83d366423 3021 * be either the value read in OTP memory or a default value.
aungriah 0:a3b83d366423 3022 *
aungriah 0:a3b83d366423 3023 * NOTE: The value returned by this function is the initial value only! It is not updated on dwt_setxtaltrim calls.
aungriah 0:a3b83d366423 3024 *
aungriah 0:a3b83d366423 3025 * input parameters
aungriah 0:a3b83d366423 3026 *
aungriah 0:a3b83d366423 3027 * output parameters
aungriah 0:a3b83d366423 3028 *
aungriah 0:a3b83d366423 3029 * returns the XTAL trim value set upon initialisation
aungriah 0:a3b83d366423 3030 */
aungriah 0:a3b83d366423 3031 uint8 dwt_getinitxtaltrim(void)
aungriah 0:a3b83d366423 3032 {
aungriah 0:a3b83d366423 3033 return dw1000local.init_xtrim;
aungriah 0:a3b83d366423 3034 }
aungriah 0:a3b83d366423 3035
aungriah 0:a3b83d366423 3036 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 3037 * @fn dwt_configcwmode()
aungriah 0:a3b83d366423 3038 *
aungriah 0:a3b83d366423 3039 * @brief this function sets the DW1000 to transmit cw signal at specific channel frequency
aungriah 0:a3b83d366423 3040 *
aungriah 0:a3b83d366423 3041 * input parameters:
aungriah 0:a3b83d366423 3042 * @param chan - specifies the operating channel (e.g. 1, 2, 3, 4, 5, 6 or 7)
aungriah 0:a3b83d366423 3043 *
aungriah 0:a3b83d366423 3044 * output parameters
aungriah 0:a3b83d366423 3045 *
aungriah 0:a3b83d366423 3046 * no return value
aungriah 0:a3b83d366423 3047 */
aungriah 0:a3b83d366423 3048 void dwt_configcwmode(uint8 chan)
aungriah 0:a3b83d366423 3049 {
aungriah 0:a3b83d366423 3050 #ifdef DWT_API_ERROR_CHECK
aungriah 0:a3b83d366423 3051 assert((chan >= 1) && (chan <= 7) && (chan != 6));
aungriah 0:a3b83d366423 3052 #endif
aungriah 0:a3b83d366423 3053
aungriah 0:a3b83d366423 3054 //
aungriah 0:a3b83d366423 3055 // Disable TX/RX RF block sequencing (needed for cw frame mode)
aungriah 0:a3b83d366423 3056 //
aungriah 0:a3b83d366423 3057 _dwt_disablesequencing();
aungriah 0:a3b83d366423 3058
aungriah 0:a3b83d366423 3059 // Config RF pll (for a given channel)
aungriah 0:a3b83d366423 3060 // Configure PLL2/RF PLL block CFG/TUNE
aungriah 0:a3b83d366423 3061 dwt_write32bitoffsetreg(FS_CTRL_ID, FS_PLLCFG_OFFSET, fs_pll_cfg[chan_idx[chan]]);
aungriah 0:a3b83d366423 3062 dwt_write8bitoffsetreg(FS_CTRL_ID, FS_PLLTUNE_OFFSET, fs_pll_tune[chan_idx[chan]]);
aungriah 0:a3b83d366423 3063 // PLL wont be enabled until a TX/RX enable is issued later on
aungriah 0:a3b83d366423 3064 // Configure RF TX blocks (for specified channel and prf)
aungriah 0:a3b83d366423 3065 // Config RF TX control
aungriah 0:a3b83d366423 3066 dwt_write32bitoffsetreg(RF_CONF_ID, RF_TXCTRL_OFFSET, tx_config[chan_idx[chan]]);
aungriah 0:a3b83d366423 3067
aungriah 0:a3b83d366423 3068 //
aungriah 0:a3b83d366423 3069 // Enable RF PLL
aungriah 0:a3b83d366423 3070 //
aungriah 0:a3b83d366423 3071 dwt_write32bitreg(RF_CONF_ID, RF_CONF_TXPLLPOWEN_MASK); // Enable LDO and RF PLL blocks
aungriah 0:a3b83d366423 3072 dwt_write32bitreg(RF_CONF_ID, RF_CONF_TXALLEN_MASK); // Enable the rest of TX blocks
aungriah 0:a3b83d366423 3073
aungriah 0:a3b83d366423 3074 //
aungriah 0:a3b83d366423 3075 // Configure TX clocks
aungriah 0:a3b83d366423 3076 //
aungriah 0:a3b83d366423 3077 dwt_write8bitoffsetreg(PMSC_ID, PMSC_CTRL0_OFFSET, 0x22);
aungriah 0:a3b83d366423 3078 dwt_write8bitoffsetreg(PMSC_ID, 0x1, 0x07);
aungriah 0:a3b83d366423 3079
aungriah 0:a3b83d366423 3080 // Disable fine grain TX sequencing
aungriah 0:a3b83d366423 3081 dwt_setfinegraintxseq(0);
aungriah 0:a3b83d366423 3082
aungriah 0:a3b83d366423 3083 // Configure CW mode
aungriah 0:a3b83d366423 3084 dwt_write8bitoffsetreg(TX_CAL_ID, TC_PGTEST_OFFSET, TC_PGTEST_CW);
aungriah 0:a3b83d366423 3085 }
aungriah 0:a3b83d366423 3086
aungriah 0:a3b83d366423 3087 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 3088 * @fn dwt_configcontinuousframemode()
aungriah 0:a3b83d366423 3089 *
aungriah 0:a3b83d366423 3090 * @brief this function sets the DW1000 to continuous tx frame mode for regulatory approvals testing.
aungriah 0:a3b83d366423 3091 *
aungriah 0:a3b83d366423 3092 * input parameters:
aungriah 0:a3b83d366423 3093 * @param framerepetitionrate - This is a 32-bit value that is used to set the interval between transmissions.
aungriah 0:a3b83d366423 3094 * The minimum value is 4. The units are approximately 8 ns. (or more precisely 512/(499.2e6*128) seconds)).
aungriah 0:a3b83d366423 3095 *
aungriah 0:a3b83d366423 3096 * output parameters
aungriah 0:a3b83d366423 3097 *
aungriah 0:a3b83d366423 3098 * no return value
aungriah 0:a3b83d366423 3099 */
aungriah 0:a3b83d366423 3100 void dwt_configcontinuousframemode(uint32 framerepetitionrate)
aungriah 0:a3b83d366423 3101 {
aungriah 0:a3b83d366423 3102 //
aungriah 0:a3b83d366423 3103 // Disable TX/RX RF block sequencing (needed for continuous frame mode)
aungriah 0:a3b83d366423 3104 //
aungriah 0:a3b83d366423 3105 _dwt_disablesequencing();
aungriah 0:a3b83d366423 3106
aungriah 0:a3b83d366423 3107 //
aungriah 0:a3b83d366423 3108 // Enable RF PLL and TX blocks
aungriah 0:a3b83d366423 3109 //
aungriah 0:a3b83d366423 3110 dwt_write32bitreg(RF_CONF_ID, RF_CONF_TXPLLPOWEN_MASK); // Enable LDO and RF PLL blocks
aungriah 0:a3b83d366423 3111 dwt_write32bitreg(RF_CONF_ID, RF_CONF_TXALLEN_MASK); // Enable the rest of TX blocks
aungriah 0:a3b83d366423 3112
aungriah 0:a3b83d366423 3113 //
aungriah 0:a3b83d366423 3114 // Configure TX clocks
aungriah 0:a3b83d366423 3115 //
aungriah 0:a3b83d366423 3116 _dwt_enableclocks(FORCE_SYS_PLL);
aungriah 0:a3b83d366423 3117 _dwt_enableclocks(FORCE_TX_PLL);
aungriah 0:a3b83d366423 3118
aungriah 0:a3b83d366423 3119 // Set the frame repetition rate
aungriah 0:a3b83d366423 3120 if(framerepetitionrate < 4)
aungriah 0:a3b83d366423 3121 {
aungriah 0:a3b83d366423 3122 framerepetitionrate = 4;
aungriah 0:a3b83d366423 3123 }
aungriah 0:a3b83d366423 3124 dwt_write32bitreg(DX_TIME_ID, framerepetitionrate);
aungriah 0:a3b83d366423 3125
aungriah 0:a3b83d366423 3126 //
aungriah 0:a3b83d366423 3127 // Configure continuous frame TX
aungriah 0:a3b83d366423 3128 //
aungriah 0:a3b83d366423 3129 dwt_write8bitoffsetreg(DIG_DIAG_ID, DIAG_TMC_OFFSET, (uint8)(DIAG_TMC_TX_PSTM)); // Turn the tx power spectrum test mode - continuous sending of frames
aungriah 0:a3b83d366423 3130 }
aungriah 0:a3b83d366423 3131
aungriah 0:a3b83d366423 3132 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 3133 * @fn dwt_readtempvbat()
aungriah 0:a3b83d366423 3134 *
aungriah 0:a3b83d366423 3135 * @brief this function reads the battery voltage and temperature of the MP
aungriah 0:a3b83d366423 3136 * The values read here will be the current values sampled by DW1000 AtoD converters.
aungriah 0:a3b83d366423 3137 * Note on Temperature: the temperature value needs to be converted to give the real temperature
aungriah 0:a3b83d366423 3138 * the formula is: 1.13 * reading - 113.0
aungriah 0:a3b83d366423 3139 * Note on Voltage: the voltage value needs to be converted to give the real voltage
aungriah 0:a3b83d366423 3140 * the formula is: 0.0057 * reading + 2.3
aungriah 0:a3b83d366423 3141 *
aungriah 0:a3b83d366423 3142 * NB: To correctly read the temperature this read should be done with xtal clock
aungriah 0:a3b83d366423 3143 * however that means that the receiver will be switched off, if receiver needs to be on then
aungriah 0:a3b83d366423 3144 * the timer is used to make sure the value is stable before reading
aungriah 0:a3b83d366423 3145 *
aungriah 0:a3b83d366423 3146 * input parameters:
aungriah 0:a3b83d366423 3147 * @param fastSPI - set to 1 if SPI rate > than 3MHz is used
aungriah 0:a3b83d366423 3148 *
aungriah 0:a3b83d366423 3149 * output parameters
aungriah 0:a3b83d366423 3150 *
aungriah 0:a3b83d366423 3151 * returns (temp_raw<<8)|(vbat_raw)
aungriah 0:a3b83d366423 3152 */
aungriah 0:a3b83d366423 3153 uint16 dwt_readtempvbat(uint8 fastSPI)
aungriah 0:a3b83d366423 3154 {
aungriah 0:a3b83d366423 3155 uint8 wr_buf[2];
aungriah 0:a3b83d366423 3156 uint8 vbat_raw;
aungriah 0:a3b83d366423 3157 uint8 temp_raw;
aungriah 0:a3b83d366423 3158
aungriah 0:a3b83d366423 3159 // These writes should be single writes and in sequence
aungriah 0:a3b83d366423 3160 wr_buf[0] = 0x80; // Enable TLD Bias
aungriah 0:a3b83d366423 3161 dwt_writetodevice(RF_CONF_ID,0x11,1,wr_buf);
aungriah 0:a3b83d366423 3162
aungriah 0:a3b83d366423 3163 wr_buf[0] = 0x0A; // Enable TLD Bias and ADC Bias
aungriah 0:a3b83d366423 3164 dwt_writetodevice(RF_CONF_ID,0x12,1,wr_buf);
aungriah 0:a3b83d366423 3165
aungriah 0:a3b83d366423 3166 wr_buf[0] = 0x0f; // Enable Outputs (only after Biases are up and running)
aungriah 0:a3b83d366423 3167 dwt_writetodevice(RF_CONF_ID,0x12,1,wr_buf); //
aungriah 0:a3b83d366423 3168
aungriah 0:a3b83d366423 3169 // Reading All SAR inputs
aungriah 0:a3b83d366423 3170 wr_buf[0] = 0x00;
aungriah 0:a3b83d366423 3171 dwt_writetodevice(TX_CAL_ID, TC_SARL_SAR_C,1,wr_buf);
aungriah 0:a3b83d366423 3172 wr_buf[0] = 0x01; // Set SAR enable
aungriah 0:a3b83d366423 3173 dwt_writetodevice(TX_CAL_ID, TC_SARL_SAR_C,1,wr_buf);
aungriah 0:a3b83d366423 3174
aungriah 0:a3b83d366423 3175 if(fastSPI == 1)
aungriah 0:a3b83d366423 3176 {
aungriah 0:a3b83d366423 3177 deca_sleep(1); // If using PLL clocks(and fast SPI rate) then this sleep is needed
aungriah 0:a3b83d366423 3178 // Read voltage and temperature.
aungriah 0:a3b83d366423 3179 dwt_readfromdevice(TX_CAL_ID, TC_SARL_SAR_LVBAT_OFFSET,2,wr_buf);
aungriah 0:a3b83d366423 3180 }
aungriah 0:a3b83d366423 3181 else //change to a slow clock
aungriah 0:a3b83d366423 3182 {
aungriah 0:a3b83d366423 3183 _dwt_enableclocks(FORCE_SYS_XTI); // NOTE: set system clock to XTI - this is necessary to make sure the values read are reliable
aungriah 0:a3b83d366423 3184 // Read voltage and temperature.
aungriah 0:a3b83d366423 3185 dwt_readfromdevice(TX_CAL_ID, TC_SARL_SAR_LVBAT_OFFSET,2,wr_buf);
aungriah 0:a3b83d366423 3186 // Default clocks (ENABLE_ALL_SEQ)
aungriah 0:a3b83d366423 3187 _dwt_enableclocks(ENABLE_ALL_SEQ); // Enable clocks for sequencing
aungriah 0:a3b83d366423 3188 }
aungriah 0:a3b83d366423 3189
aungriah 0:a3b83d366423 3190 vbat_raw = wr_buf[0];
aungriah 0:a3b83d366423 3191 temp_raw = wr_buf[1];
aungriah 0:a3b83d366423 3192
aungriah 0:a3b83d366423 3193 wr_buf[0] = 0x00; // Clear SAR enable
aungriah 0:a3b83d366423 3194 dwt_writetodevice(TX_CAL_ID, TC_SARL_SAR_C,1,wr_buf);
aungriah 0:a3b83d366423 3195
aungriah 0:a3b83d366423 3196 return ((temp_raw<<8)|(vbat_raw));
aungriah 0:a3b83d366423 3197 }
aungriah 0:a3b83d366423 3198
aungriah 0:a3b83d366423 3199 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 3200 * @fn dwt_readwakeuptemp()
aungriah 0:a3b83d366423 3201 *
aungriah 0:a3b83d366423 3202 * @brief this function reads the temperature of the DW1000 that was sampled
aungriah 0:a3b83d366423 3203 * on waking from Sleep/Deepsleep. They are not current values, but read on last
aungriah 0:a3b83d366423 3204 * wakeup if DWT_TANDV bit is set in mode parameter of dwt_configuresleep
aungriah 0:a3b83d366423 3205 *
aungriah 0:a3b83d366423 3206 * input parameters:
aungriah 0:a3b83d366423 3207 *
aungriah 0:a3b83d366423 3208 * output parameters:
aungriah 0:a3b83d366423 3209 *
aungriah 0:a3b83d366423 3210 * returns: 8-bit raw temperature sensor value
aungriah 0:a3b83d366423 3211 */
aungriah 0:a3b83d366423 3212 uint8 dwt_readwakeuptemp(void)
aungriah 0:a3b83d366423 3213 {
aungriah 0:a3b83d366423 3214 return dwt_read8bitoffsetreg(TX_CAL_ID, TC_SARL_SAR_LTEMP_OFFSET);
aungriah 0:a3b83d366423 3215 }
aungriah 0:a3b83d366423 3216
aungriah 0:a3b83d366423 3217 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:a3b83d366423 3218 * @fn dwt_readwakeupvbat()
aungriah 0:a3b83d366423 3219 *
aungriah 0:a3b83d366423 3220 * @brief this function reads the battery voltage of the DW1000 that was sampled
aungriah 0:a3b83d366423 3221 * on waking from Sleep/Deepsleep. They are not current values, but read on last
aungriah 0:a3b83d366423 3222 * wakeup if DWT_TANDV bit is set in mode parameter of dwt_configuresleep
aungriah 0:a3b83d366423 3223 *
aungriah 0:a3b83d366423 3224 * input parameters:
aungriah 0:a3b83d366423 3225 *
aungriah 0:a3b83d366423 3226 * output parameters:
aungriah 0:a3b83d366423 3227 *
aungriah 0:a3b83d366423 3228 * returns: 8-bit raw battery voltage sensor value
aungriah 0:a3b83d366423 3229 */
aungriah 0:a3b83d366423 3230 uint8 dwt_readwakeupvbat(void)
aungriah 0:a3b83d366423 3231 {
aungriah 0:a3b83d366423 3232 return dwt_read8bitoffsetreg(TX_CAL_ID, TC_SARL_SAR_LVBAT_OFFSET);
aungriah 0:a3b83d366423 3233 }
aungriah 0:a3b83d366423 3234
aungriah 0:a3b83d366423 3235
aungriah 0:a3b83d366423 3236 /* ===============================================================================================
aungriah 0:a3b83d366423 3237 List of expected (known) device ID handled by this software
aungriah 0:a3b83d366423 3238 ===============================================================================================
aungriah 0:a3b83d366423 3239
aungriah 0:a3b83d366423 3240 0xDECA0130 // DW1000 - MP
aungriah 0:a3b83d366423 3241
aungriah 0:a3b83d366423 3242 ===============================================================================================
aungriah 0:a3b83d366423 3243 */
aungriah 0:a3b83d366423 3244
aungriah 0:a3b83d366423 3245