Diff: I2C_busreset.cpp

Revision:

1:fe493f707844

Parent:

0:e9beb537cf77

Child:

2:a166055977ec

--- a/I2C_busreset.cpp	Wed Feb 19 19:18:49 2014 +0000
+++ b/I2C_busreset.cpp	Tue Feb 24 12:49:17 2015 +0000
@@ -11,6 +11,32 @@
 
 void I2C_busreset(void)
 {
+    // Chris Heald [23 Feb 2015]: Adding I2C on PTC9, PTC8, PCR MUX 2..
+    if((PORTC->PCR[8] & PORT_PCR_MUX(2)) && (PORTC->PCR[9] & PORT_PCR_MUX(2)))
+    {
+        I2C0->C1 &= 0x7f;                 // Disable I2C0 bus
+        PORTC->PCR[8] = PORT_PCR_MUX(1);  // PTC8 Alt1 (pin)
+        PORTC->PCR[9] = PORT_PCR_MUX(1);  // PTC9 Alt1 (pin)
+        if((PTC->PDIR & 0x3) != 3)        // When PTC8 / PTC9 are not 1 : I2C1 bus lock-up
+        {
+            PTC->PDDR |= 0x2;             // Set PTE1 as a GPIO output so we can bit bang it
+            PTC->PDOR |= 0x2;             // Set PTE1 (SCL) pin high;
+            wait_ms(1);
+            while(!(PTC->PDIR & 0x1))     // bit bang SCL until the offending device releases the bus
+            {   
+                PTC->PDOR &= 0xfffffffd;  // Set PTE1 (SCL) pin low;
+                wait_ms(1);
+                PTC->PDOR |= 0x2;         // Set PTE1 (SCL) pin high;
+                wait_ms(1);
+            }
+        }
+        // Reinstate I2C1 bus pins
+        PORTC->PCR[8] = PORT_PCR_MUX(2);  // PTE1 Alt2 (SCL)
+        PORTC->PCR[9] = PORT_PCR_MUX(2);  // PTE0 Alt2 (SDA)
+        I2C0->C1 |= 0x80;                 // Enable I2C0 bus
+    }
+
+
     if((PORTE->PCR[1] & PORT_PCR_MUX(6)) && (PORTE->PCR[0] & PORT_PCR_MUX(6)))
     {
         I2C1->C1 &= 0x7f;                 // Disable I2C1 bus