Chris Heald / KL25Z_I2C_busreset

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Fork of KL25Z_I2C_busreset by Frank Vannieuwkerke

I2C_busreset.cpp@2:a166055977ec, 2015-02-24 (annotated)

Committer:
ateyercheese
Date:
Tue Feb 24 17:49:59 2015 +0000
Revision:
2:a166055977ec
Parent:
1:fe493f707844
Child:
3:7584a206afd4
Updated Comments inline with pin changes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
frankvnk 0:e9beb537cf77 1 /**************************************************************************************************
frankvnk 0:e9beb537cf77 2 ***** *****
frankvnk 0:e9beb537cf77 3 ***** Name: KL25Z I2C_busreset.cpp *****
frankvnk 0:e9beb537cf77 4 ***** Date: 24/11/2013 *****
frankvnk 0:e9beb537cf77 5 ***** Auth: Frank Vannieuwkerke *****
frankvnk 0:e9beb537cf77 6 ***** Func: library for unblocking I2C bus on KL25Z board *****
frankvnk 0:e9beb537cf77 7 ***** Info: MPL3115A2-AN4481 *****
frankvnk 0:e9beb537cf77 8 **************************************************************************************************/
frankvnk 0:e9beb537cf77 9
frankvnk 0:e9beb537cf77 10 #include "I2C_busreset.h"
frankvnk 0:e9beb537cf77 11
frankvnk 0:e9beb537cf77 12 void I2C_busreset(void)
frankvnk 0:e9beb537cf77 13 {
ateyercheese 1:fe493f707844 14 // Chris Heald [23 Feb 2015]: Adding I2C on PTC9, PTC8, PCR MUX 2..
ateyercheese 1:fe493f707844 15 if((PORTC->PCR[8] & PORT_PCR_MUX(2)) && (PORTC->PCR[9] & PORT_PCR_MUX(2)))
ateyercheese 1:fe493f707844 16 {
ateyercheese 1:fe493f707844 17 I2C0->C1 &= 0x7f; // Disable I2C0 bus
ateyercheese 1:fe493f707844 18 PORTC->PCR[8] = PORT_PCR_MUX(1); // PTC8 Alt1 (pin)
ateyercheese 1:fe493f707844 19 PORTC->PCR[9] = PORT_PCR_MUX(1); // PTC9 Alt1 (pin)
ateyercheese 2:a166055977ec 20 if((PTC->PDIR & 0x3) != 3) // When PTC8 / PTC9 are not 1 : I2C0 bus lock-up
ateyercheese 1:fe493f707844 21 {
ateyercheese 2:a166055977ec 22 PTC->PDDR |= 0x2; // Set PTC8 as a GPIO output so we can bit bang it
ateyercheese 2:a166055977ec 23 PTC->PDOR |= 0x2; // Set PTC8 (SCL) pin high;
ateyercheese 1:fe493f707844 24 wait_ms(1);
ateyercheese 1:fe493f707844 25 while(!(PTC->PDIR & 0x1)) // bit bang SCL until the offending device releases the bus
ateyercheese 1:fe493f707844 26 {
ateyercheese 2:a166055977ec 27 PTC->PDOR &= 0xfffffffd; // Set PTC8 (SCL) pin low;
ateyercheese 1:fe493f707844 28 wait_ms(1);
ateyercheese 2:a166055977ec 29 PTC->PDOR |= 0x2; // Set PTC8 (SCL) pin high;
ateyercheese 1:fe493f707844 30 wait_ms(1);
ateyercheese 1:fe493f707844 31 }
ateyercheese 1:fe493f707844 32 }
ateyercheese 1:fe493f707844 33 // Reinstate I2C1 bus pins
ateyercheese 2:a166055977ec 34 PORTC->PCR[8] = PORT_PCR_MUX(2); // PTC8 Alt2 (SCL)
ateyercheese 2:a166055977ec 35 PORTC->PCR[9] = PORT_PCR_MUX(2); // PTC9 Alt2 (SDA)
ateyercheese 1:fe493f707844 36 I2C0->C1 |= 0x80; // Enable I2C0 bus
ateyercheese 1:fe493f707844 37 }
ateyercheese 1:fe493f707844 38
ateyercheese 1:fe493f707844 39
frankvnk 0:e9beb537cf77 40 if((PORTE->PCR[1] & PORT_PCR_MUX(6)) && (PORTE->PCR[0] & PORT_PCR_MUX(6)))
frankvnk 0:e9beb537cf77 41 {
frankvnk 0:e9beb537cf77 42 I2C1->C1 &= 0x7f; // Disable I2C1 bus
frankvnk 0:e9beb537cf77 43 PORTE->PCR[1] = PORT_PCR_MUX(1); // PTE1 Alt1 (pin)
frankvnk 0:e9beb537cf77 44 PORTE->PCR[0] = PORT_PCR_MUX(1); // PTE0 Alt1 (pin)
frankvnk 0:e9beb537cf77 45 if((PTE->PDIR & 0x3) != 3) // When PTE0 / PTE1 are not 1 : I2C1 bus lock-up
frankvnk 0:e9beb537cf77 46 {
frankvnk 0:e9beb537cf77 47 PTE->PDDR |= 0x2; // Set PTE1 as a GPIO output so we can bit bang it
frankvnk 0:e9beb537cf77 48 PTE->PDOR |= 0x2; // Set PTE1 (SCL) pin high;
frankvnk 0:e9beb537cf77 49 wait_ms(1);
frankvnk 0:e9beb537cf77 50 while(!(PTE->PDIR & 0x1)) // bit bang SCL until the offending device releases the bus
frankvnk 0:e9beb537cf77 51 {
frankvnk 0:e9beb537cf77 52 PTE->PDOR &= 0xfffffffd; // Set PTE1 (SCL) pin low;
frankvnk 0:e9beb537cf77 53 wait_ms(1);
frankvnk 0:e9beb537cf77 54 PTE->PDOR |= 0x2; // Set PTE1 (SCL) pin high;
frankvnk 0:e9beb537cf77 55 wait_ms(1);
frankvnk 0:e9beb537cf77 56 }
frankvnk 0:e9beb537cf77 57 }
frankvnk 0:e9beb537cf77 58 // Reinstate I2C1 bus pins
frankvnk 0:e9beb537cf77 59 PORTE->PCR[1] = PORT_PCR_MUX(6); // PTE1 Alt6 (SCL)
frankvnk 0:e9beb537cf77 60 PORTE->PCR[0] = PORT_PCR_MUX(6); // PTE0 Alt6 (SDA)
frankvnk 0:e9beb537cf77 61 I2C1->C1 |= 0x80; // Enable I2C1 bus
frankvnk 0:e9beb537cf77 62 }
frankvnk 0:e9beb537cf77 63
frankvnk 0:e9beb537cf77 64 if((PORTE->PCR[24] & PORT_PCR_MUX(5)) && (PORTE->PCR[25] & PORT_PCR_MUX(5)))
frankvnk 0:e9beb537cf77 65 {
frankvnk 0:e9beb537cf77 66 I2C0->C1 &= 0x7f; // Disable I2C0 bus
frankvnk 0:e9beb537cf77 67 PORTE->PCR[24] = PORT_PCR_MUX(1); // PTE24 Alt1 (pin)
frankvnk 0:e9beb537cf77 68 PORTE->PCR[25] = PORT_PCR_MUX(1); // PTE25 Alt1 (pin)
frankvnk 0:e9beb537cf77 69 if((PTE->PDIR & 0x03000000) != 0x03000000) // When PTE24 / PTE25 are not 1 : I2C0 bus lock-up
frankvnk 0:e9beb537cf77 70 {
frankvnk 0:e9beb537cf77 71 PTE->PDDR |= 0x01000000; // Set PTE24 as a GPIO output so we can bit bang it
frankvnk 0:e9beb537cf77 72 PTE->PDOR |= 0x01000000; // Set PTE24 (SCL) pin high;
frankvnk 0:e9beb537cf77 73 wait_ms(1);
frankvnk 0:e9beb537cf77 74 while(!(PTE->PDIR & 0x1)) // bit bang SCL until the offending device releases the bus
frankvnk 0:e9beb537cf77 75 {
frankvnk 0:e9beb537cf77 76 PTE->PDOR &= 0xfeffffff; // Set PTE24 (SCL) pin low;
frankvnk 0:e9beb537cf77 77 wait_ms(1);
frankvnk 0:e9beb537cf77 78 PTE->PDOR |= 0x01000000; // Set PTE24 (SCL) pin high;
frankvnk 0:e9beb537cf77 79 wait_ms(1);
frankvnk 0:e9beb537cf77 80 }
frankvnk 0:e9beb537cf77 81 }
frankvnk 0:e9beb537cf77 82 // Reinstate I2C0 bus pins
frankvnk 0:e9beb537cf77 83 PORTE->PCR[24] = PORT_PCR_MUX(5); // PTE24 Alt6 (SCL)
frankvnk 0:e9beb537cf77 84 PORTE->PCR[25] = PORT_PCR_MUX(5); // PTE25 Alt6 (SDA)
frankvnk 0:e9beb537cf77 85 I2C0->C1 |= 0x80; // Enable I2C0 bus
frankvnk 0:e9beb537cf77 86 }
frankvnk 0:e9beb537cf77 87 }