Ashutosh Sharma
This Library is to establish communication between a transmitter and receivers formed by the combination of SX1272MB2DAS shield and FRDM kl25z board that uses Cortex M0+ architecture.
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sx1272.cpp
00001 /* 00002 / _____) _ | | 00003 ( (____ _____ ____ _| |_ _____ ____| |__ 00004 \____ \| ___ | (_ _) ___ |/ ___) _ \ 00005 _____) ) ____| | | || |_| ____( (___| | | | 00006 (______/|_____)_|_|_| \__)_____)\____)_| |_| 00007 (C) 2015 Semtech 00008 00009 Description: Actual implementation of a SX1272 radio, inherits Radio 00010 00011 License: Revised BSD License, see LICENSE.TXT file include in the project 00012 00013 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin 00014 */ 00015 #include "sx1272.h" 00016 00017 const FskBandwidth_t SX1272::FskBandwidths[] = 00018 { 00019 { 2600 , 0x17 }, 00020 { 3100 , 0x0F }, 00021 { 3900 , 0x07 }, 00022 { 5200 , 0x16 }, 00023 { 6300 , 0x0E }, 00024 { 7800 , 0x06 }, 00025 { 10400 , 0x15 }, 00026 { 12500 , 0x0D }, 00027 { 15600 , 0x05 }, 00028 { 20800 , 0x14 }, 00029 { 25000 , 0x0C }, 00030 { 31300 , 0x04 }, 00031 { 41700 , 0x13 }, 00032 { 50000 , 0x0B }, 00033 { 62500 , 0x03 }, 00034 { 83333 , 0x12 }, 00035 { 100000, 0x0A }, 00036 { 125000, 0x02 }, 00037 { 166700, 0x11 }, 00038 { 200000, 0x09 }, 00039 { 250000, 0x01 }, 00040 { 300000, 0x00 }, // Invalid Bandwidth 00041 }; 00042 00043 00044 SX1272::SX1272( RadioEvents_t *events, 00045 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset, 00046 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 ) 00047 : Radio ( events ), 00048 spi( mosi, miso, sclk ), 00049 nss( nss ), 00050 reset( reset ), 00051 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ), 00052 isRadioActive( false ) 00053 { 00054 wait_ms( 10 ); 00055 this->rxtxBuffer = new uint8_t[RX_BUFFER_SIZE]; 00056 00057 this->RadioEvents = events; 00058 00059 this->dioIrq = new DioIrqHandler[6]; 00060 00061 this->dioIrq [0] = &SX1272::OnDio0Irq; 00062 this->dioIrq [1] = &SX1272::OnDio1Irq; 00063 this->dioIrq [2] = &SX1272::OnDio2Irq; 00064 this->dioIrq [3] = &SX1272::OnDio3Irq; 00065 this->dioIrq [4] = &SX1272::OnDio4Irq; 00066 this->dioIrq [5] = NULL; 00067 00068 this->settings.State = RF_IDLE; 00069 } 00070 00071 SX1272::~SX1272( ) 00072 { 00073 delete this->rxtxBuffer; 00074 delete this->dioIrq ; 00075 } 00076 00077 void SX1272::Init( RadioEvents_t *events ) 00078 { 00079 this->RadioEvents = events; 00080 } 00081 00082 RadioState SX1272::GetStatus ( void ) 00083 { 00084 return this->settings.State; 00085 } 00086 00087 void SX1272::SetChannel( uint32_t freq ) 00088 { 00089 this->settings.Channel = freq; 00090 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP ); 00091 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) ); 00092 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) ); 00093 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) ); 00094 } 00095 00096 bool SX1272::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh ) 00097 { 00098 int16_t rssi = 0; 00099 00100 SetModem( modem ); 00101 00102 SetChannel( freq ); 00103 00104 SetOpMode( RF_OPMODE_RECEIVER ); 00105 00106 wait_ms( 1 ); 00107 00108 rssi = GetRssi( modem ); 00109 00110 Sleep( ); 00111 00112 if( rssi > rssiThresh ) 00113 { 00114 return false; 00115 } 00116 return true; 00117 } 00118 00119 uint32_t SX1272::Random( void ) 00120 { 00121 uint8_t i; 00122 uint32_t rnd = 0; 00123 00124 /* 00125 * Radio setup for random number generation 00126 */ 00127 // Set LoRa modem ON 00128 SetModem( MODEM_LORA ); 00129 00130 // Disable LoRa modem interrupts 00131 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | 00132 RFLR_IRQFLAGS_RXDONE | 00133 RFLR_IRQFLAGS_PAYLOADCRCERROR | 00134 RFLR_IRQFLAGS_VALIDHEADER | 00135 RFLR_IRQFLAGS_TXDONE | 00136 RFLR_IRQFLAGS_CADDONE | 00137 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00138 RFLR_IRQFLAGS_CADDETECTED ); 00139 00140 // Set radio in continuous reception 00141 SetOpMode( RF_OPMODE_RECEIVER ); 00142 00143 for( i = 0; i < 32; i++ ) 00144 { 00145 wait_ms( 1 ); 00146 // Unfiltered RSSI value reading. Only takes the LSB value 00147 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i; 00148 } 00149 00150 Sleep( ); 00151 00152 return rnd; 00153 } 00154 00155 /*! 00156 * Returns the known FSK bandwidth registers value 00157 * 00158 * \param [IN] bandwidth Bandwidth value in Hz 00159 * \retval regValue Bandwidth register value. 00160 */ 00161 uint8_t SX1272::GetFskBandwidthRegValue ( uint32_t bandwidth ) 00162 { 00163 uint8_t i; 00164 00165 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ ) 00166 { 00167 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) ) 00168 { 00169 return FskBandwidths[i].RegValue; 00170 } 00171 } 00172 // ERROR: Value not found 00173 while( 1 ); 00174 } 00175 00176 void SX1272::SetRxConfig( RadioModems_t modem, uint32_t bandwidth, 00177 uint32_t datarate, uint8_t coderate, 00178 uint32_t bandwidthAfc, uint16_t preambleLen, 00179 uint16_t symbTimeout, bool fixLen, 00180 uint8_t payloadLen, 00181 bool crcOn, bool freqHopOn, uint8_t hopPeriod, 00182 bool iqInverted, bool rxContinuous ) 00183 { 00184 SetModem( modem ); 00185 00186 switch( modem ) 00187 { 00188 case MODEM_FSK: 00189 { 00190 this->settings.Fsk.Bandwidth = bandwidth; 00191 this->settings.Fsk.Datarate = datarate; 00192 this->settings.Fsk.BandwidthAfc = bandwidthAfc; 00193 this->settings.Fsk.FixLen = fixLen; 00194 this->settings.Fsk.PayloadLen = payloadLen; 00195 this->settings.Fsk.CrcOn = crcOn; 00196 this->settings.Fsk.IqInverted = iqInverted; 00197 this->settings.Fsk.RxContinuous = rxContinuous; 00198 this->settings.Fsk.PreambleLen = preambleLen; 00199 this->settings.Fsk.RxSingleTimeout = symbTimeout * ( ( 1.0 / ( double )datarate ) * 8.0 ) * 1e3; 00200 00201 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate ); 00202 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) ); 00203 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) ); 00204 00205 Write( REG_RXBW, GetFskBandwidthRegValue ( bandwidth ) ); 00206 Write( REG_AFCBW, GetFskBandwidthRegValue ( bandwidthAfc ) ); 00207 00208 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) ); 00209 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) ); 00210 00211 if( fixLen == 1 ) 00212 { 00213 Write( REG_PAYLOADLENGTH, payloadLen ); 00214 } 00215 else 00216 { 00217 Write( REG_PAYLOADLENGTH, 0xFF ); // Set payload length to the maximum 00218 } 00219 00220 Write( REG_PACKETCONFIG1, 00221 ( Read( REG_PACKETCONFIG1 ) & 00222 RF_PACKETCONFIG1_CRC_MASK & 00223 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) | 00224 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) | 00225 ( crcOn << 4 ) ); 00226 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) ); 00227 } 00228 break; 00229 case MODEM_LORA: 00230 { 00231 this->settings.LoRa.Bandwidth = bandwidth; 00232 this->settings.LoRa.Datarate = datarate; 00233 this->settings.LoRa.Coderate = coderate; 00234 this->settings.LoRa.PreambleLen = preambleLen; 00235 this->settings.LoRa.FixLen = fixLen; 00236 this->settings.LoRa.PayloadLen = payloadLen; 00237 this->settings.LoRa.CrcOn = crcOn; 00238 this->settings.LoRa.FreqHopOn = freqHopOn; 00239 this->settings.LoRa.HopPeriod = hopPeriod; 00240 this->settings.LoRa.IqInverted = iqInverted; 00241 this->settings.LoRa.RxContinuous = rxContinuous; 00242 00243 if( datarate > 12 ) 00244 { 00245 datarate = 12; 00246 } 00247 else if( datarate < 6 ) 00248 { 00249 datarate = 6; 00250 } 00251 00252 if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || 00253 ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) 00254 { 00255 this->settings.LoRa.LowDatarateOptimize = 0x01; 00256 } 00257 else 00258 { 00259 this->settings.LoRa.LowDatarateOptimize = 0x00; 00260 } 00261 00262 Write( REG_LR_MODEMCONFIG1, 00263 ( Read( REG_LR_MODEMCONFIG1 ) & 00264 RFLR_MODEMCONFIG1_BW_MASK & 00265 RFLR_MODEMCONFIG1_CODINGRATE_MASK & 00266 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK & 00267 RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK & 00268 RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) | 00269 ( bandwidth << 6 ) | ( coderate << 3 ) | 00270 ( fixLen << 2 ) | ( crcOn << 1 ) | 00271 this->settings.LoRa.LowDatarateOptimize ); 00272 00273 Write( REG_LR_MODEMCONFIG2, 00274 ( Read( REG_LR_MODEMCONFIG2 ) & 00275 RFLR_MODEMCONFIG2_SF_MASK & 00276 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) | 00277 ( datarate << 4 ) | 00278 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) ); 00279 00280 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) ); 00281 00282 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) ); 00283 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) ); 00284 00285 if( fixLen == 1 ) 00286 { 00287 Write( REG_LR_PAYLOADLENGTH, payloadLen ); 00288 } 00289 00290 if( this->settings.LoRa.FreqHopOn == true ) 00291 { 00292 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON ); 00293 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod ); 00294 } 00295 00296 if( datarate == 6 ) 00297 { 00298 Write( REG_LR_DETECTOPTIMIZE, 00299 ( Read( REG_LR_DETECTOPTIMIZE ) & 00300 RFLR_DETECTIONOPTIMIZE_MASK ) | 00301 RFLR_DETECTIONOPTIMIZE_SF6 ); 00302 Write( REG_LR_DETECTIONTHRESHOLD, 00303 RFLR_DETECTIONTHRESH_SF6 ); 00304 } 00305 else 00306 { 00307 Write( REG_LR_DETECTOPTIMIZE, 00308 ( Read( REG_LR_DETECTOPTIMIZE ) & 00309 RFLR_DETECTIONOPTIMIZE_MASK ) | 00310 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 ); 00311 Write( REG_LR_DETECTIONTHRESHOLD, 00312 RFLR_DETECTIONTHRESH_SF7_TO_SF12 ); 00313 } 00314 } 00315 break; 00316 } 00317 } 00318 00319 void SX1272::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev, 00320 uint32_t bandwidth, uint32_t datarate, 00321 uint8_t coderate, uint16_t preambleLen, 00322 bool fixLen, bool crcOn, bool freqHopOn, 00323 uint8_t hopPeriod, bool iqInverted, uint32_t timeout ) 00324 { 00325 SetModem( modem ); 00326 00327 SetRfTxPower( power ); 00328 00329 switch( modem ) 00330 { 00331 case MODEM_FSK: 00332 { 00333 this->settings.Fsk.Power = power; 00334 this->settings.Fsk.Fdev = fdev; 00335 this->settings.Fsk.Bandwidth = bandwidth; 00336 this->settings.Fsk.Datarate = datarate; 00337 this->settings.Fsk.PreambleLen = preambleLen; 00338 this->settings.Fsk.FixLen = fixLen; 00339 this->settings.Fsk.CrcOn = crcOn; 00340 this->settings.Fsk.IqInverted = iqInverted; 00341 this->settings.Fsk.TxTimeout = timeout; 00342 00343 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP ); 00344 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) ); 00345 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) ); 00346 00347 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate ); 00348 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) ); 00349 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) ); 00350 00351 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF ); 00352 Write( REG_PREAMBLELSB, preambleLen & 0xFF ); 00353 00354 Write( REG_PACKETCONFIG1, 00355 ( Read( REG_PACKETCONFIG1 ) & 00356 RF_PACKETCONFIG1_CRC_MASK & 00357 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) | 00358 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) | 00359 ( crcOn << 4 ) ); 00360 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) ); 00361 } 00362 break; 00363 case MODEM_LORA: 00364 { 00365 this->settings.LoRa.Power = power; 00366 this->settings.LoRa.Bandwidth = bandwidth; 00367 this->settings.LoRa.Datarate = datarate; 00368 this->settings.LoRa.Coderate = coderate; 00369 this->settings.LoRa.PreambleLen = preambleLen; 00370 this->settings.LoRa.FixLen = fixLen; 00371 this->settings.LoRa.FreqHopOn = freqHopOn; 00372 this->settings.LoRa.HopPeriod = hopPeriod; 00373 this->settings.LoRa.CrcOn = crcOn; 00374 this->settings.LoRa.IqInverted = iqInverted; 00375 this->settings.LoRa.TxTimeout = timeout; 00376 00377 if( datarate > 12 ) 00378 { 00379 datarate = 12; 00380 } 00381 else if( datarate < 6 ) 00382 { 00383 datarate = 6; 00384 } 00385 if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || 00386 ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) 00387 { 00388 this->settings.LoRa.LowDatarateOptimize = 0x01; 00389 } 00390 else 00391 { 00392 this->settings.LoRa.LowDatarateOptimize = 0x00; 00393 } 00394 00395 if( this->settings.LoRa.FreqHopOn == true ) 00396 { 00397 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON ); 00398 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod ); 00399 } 00400 00401 Write( REG_LR_MODEMCONFIG1, 00402 ( Read( REG_LR_MODEMCONFIG1 ) & 00403 RFLR_MODEMCONFIG1_BW_MASK & 00404 RFLR_MODEMCONFIG1_CODINGRATE_MASK & 00405 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK & 00406 RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK & 00407 RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) | 00408 ( bandwidth << 6 ) | ( coderate << 3 ) | 00409 ( fixLen << 2 ) | ( crcOn << 1 ) | 00410 this->settings.LoRa.LowDatarateOptimize ); 00411 00412 Write( REG_LR_MODEMCONFIG2, 00413 ( Read( REG_LR_MODEMCONFIG2 ) & 00414 RFLR_MODEMCONFIG2_SF_MASK ) | 00415 ( datarate << 4 ) ); 00416 00417 00418 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF ); 00419 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF ); 00420 00421 if( datarate == 6 ) 00422 { 00423 Write( REG_LR_DETECTOPTIMIZE, 00424 ( Read( REG_LR_DETECTOPTIMIZE ) & 00425 RFLR_DETECTIONOPTIMIZE_MASK ) | 00426 RFLR_DETECTIONOPTIMIZE_SF6 ); 00427 Write( REG_LR_DETECTIONTHRESHOLD, 00428 RFLR_DETECTIONTHRESH_SF6 ); 00429 } 00430 else 00431 { 00432 Write( REG_LR_DETECTOPTIMIZE, 00433 ( Read( REG_LR_DETECTOPTIMIZE ) & 00434 RFLR_DETECTIONOPTIMIZE_MASK ) | 00435 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 ); 00436 Write( REG_LR_DETECTIONTHRESHOLD, 00437 RFLR_DETECTIONTHRESH_SF7_TO_SF12 ); 00438 } 00439 } 00440 break; 00441 } 00442 } 00443 00444 uint32_t SX1272::TimeOnAir( RadioModems_t modem, uint8_t pktLen ) 00445 { 00446 uint32_t airTime = 0; 00447 00448 switch( modem ) 00449 { 00450 case MODEM_FSK: 00451 { 00452 airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen + 00453 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) + 00454 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) + 00455 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) + 00456 pktLen + 00457 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) / 00458 this->settings.Fsk.Datarate ) * 1e3 ); 00459 } 00460 break; 00461 case MODEM_LORA: 00462 { 00463 double bw = 0.0; 00464 switch( this->settings.LoRa.Bandwidth ) 00465 { 00466 case 0: // 125 kHz 00467 bw = 125e3; 00468 break; 00469 case 1: // 250 kHz 00470 bw = 250e3; 00471 break; 00472 case 2: // 500 kHz 00473 bw = 500e3; 00474 break; 00475 } 00476 00477 // Symbol rate : time for one symbol (secs) 00478 double rs = bw / ( 1 << this->settings.LoRa.Datarate ); 00479 double ts = 1 / rs; 00480 // time of preamble 00481 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts; 00482 // Symbol length of payload and time 00483 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate + 00484 28 + 16 * this->settings.LoRa.CrcOn - 00485 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) / 00486 ( double )( 4 * ( this->settings.LoRa.Datarate - 00487 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) ) * 00488 ( this->settings.LoRa.Coderate + 4 ); 00489 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 ); 00490 double tPayload = nPayload * ts; 00491 // Time on air 00492 double tOnAir = tPreamble + tPayload; 00493 // return ms secs 00494 airTime = floor( tOnAir * 1e3 + 0.999 ); 00495 } 00496 break; 00497 } 00498 return airTime; 00499 } 00500 00501 void SX1272::Send( uint8_t *buffer, uint8_t size ) 00502 { 00503 uint32_t txTimeout = 0; 00504 00505 switch( this->settings.Modem ) 00506 { 00507 case MODEM_FSK: 00508 { 00509 this->settings.FskPacketHandler.NbBytes = 0; 00510 this->settings.FskPacketHandler.Size = size; 00511 00512 if( this->settings.Fsk.FixLen == false ) 00513 { 00514 WriteFifo( ( uint8_t* )&size, 1 ); 00515 } 00516 else 00517 { 00518 Write( REG_PAYLOADLENGTH, size ); 00519 } 00520 00521 if( ( size > 0 ) && ( size <= 64 ) ) 00522 { 00523 this->settings.FskPacketHandler.ChunkSize = size; 00524 } 00525 else 00526 { 00527 memcpy( rxtxBuffer, buffer, size ); 00528 this->settings.FskPacketHandler.ChunkSize = 32; 00529 } 00530 00531 // Write payload buffer 00532 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize ); 00533 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize; 00534 txTimeout = this->settings.Fsk.TxTimeout; 00535 } 00536 break; 00537 case MODEM_LORA: 00538 { 00539 if( this->settings.LoRa.IqInverted == true ) 00540 { 00541 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) ); 00542 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON ); 00543 } 00544 else 00545 { 00546 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) ); 00547 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF ); 00548 } 00549 00550 this->settings.LoRaPacketHandler.Size = size; 00551 00552 // Initializes the payload size 00553 Write( REG_LR_PAYLOADLENGTH, size ); 00554 00555 // Full buffer used for Tx 00556 Write( REG_LR_FIFOTXBASEADDR, 0 ); 00557 Write( REG_LR_FIFOADDRPTR, 0 ); 00558 00559 // FIFO operations can not take place in Sleep mode 00560 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP ) 00561 { 00562 Standby( ); 00563 wait_ms( 1 ); 00564 } 00565 // Write payload buffer 00566 WriteFifo( buffer, size ); 00567 txTimeout = this->settings.LoRa.TxTimeout; 00568 } 00569 break; 00570 } 00571 00572 Tx( txTimeout ); 00573 } 00574 00575 void SX1272::Sleep( void ) 00576 { 00577 txTimeoutTimer .detach( ); 00578 rxTimeoutTimer.detach( ); 00579 00580 SetOpMode( RF_OPMODE_SLEEP ); 00581 this->settings.State = RF_IDLE; 00582 } 00583 00584 void SX1272::Standby( void ) 00585 { 00586 txTimeoutTimer .detach( ); 00587 rxTimeoutTimer.detach( ); 00588 00589 SetOpMode( RF_OPMODE_STANDBY ); 00590 this->settings.State = RF_IDLE; 00591 } 00592 00593 void SX1272::Rx( uint32_t timeout ) 00594 { 00595 bool rxContinuous = false; 00596 00597 switch( this->settings.Modem ) 00598 { 00599 case MODEM_FSK: 00600 { 00601 rxContinuous = this->settings.Fsk.RxContinuous; 00602 00603 // DIO0=PayloadReady 00604 // DIO1=FifoLevel 00605 // DIO2=SyncAddr 00606 // DIO3=FifoEmpty 00607 // DIO4=Preamble 00608 // DIO5=ModeReady 00609 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & 00610 RF_DIOMAPPING1_DIO1_MASK & 00611 RF_DIOMAPPING1_DIO2_MASK ) | 00612 RF_DIOMAPPING1_DIO0_00 | 00613 RF_DIOMAPPING1_DIO1_00 | 00614 RF_DIOMAPPING1_DIO2_11 ); 00615 00616 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK & 00617 RF_DIOMAPPING2_MAP_MASK ) | 00618 RF_DIOMAPPING2_DIO4_11 | 00619 RF_DIOMAPPING2_MAP_PREAMBLEDETECT ); 00620 00621 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F; 00622 00623 Write( REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON | RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT ); 00624 00625 this->settings.FskPacketHandler.PreambleDetected = false; 00626 this->settings.FskPacketHandler.SyncWordDetected = false; 00627 this->settings.FskPacketHandler.NbBytes = 0; 00628 this->settings.FskPacketHandler.Size = 0; 00629 } 00630 break; 00631 case MODEM_LORA: 00632 { 00633 if( this->settings.LoRa.IqInverted == true ) 00634 { 00635 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) ); 00636 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON ); 00637 } 00638 else 00639 { 00640 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) ); 00641 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF ); 00642 } 00643 00644 rxContinuous = this->settings.LoRa.RxContinuous; 00645 00646 if( this->settings.LoRa.FreqHopOn == true ) 00647 { 00648 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT | 00649 //RFLR_IRQFLAGS_RXDONE | 00650 //RFLR_IRQFLAGS_PAYLOADCRCERROR | 00651 RFLR_IRQFLAGS_VALIDHEADER | 00652 RFLR_IRQFLAGS_TXDONE | 00653 RFLR_IRQFLAGS_CADDONE | 00654 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00655 RFLR_IRQFLAGS_CADDETECTED ); 00656 00657 // DIO0=RxDone, DIO2=FhssChangeChannel 00658 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 ); 00659 } 00660 else 00661 { 00662 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT | 00663 //RFLR_IRQFLAGS_RXDONE | 00664 //RFLR_IRQFLAGS_PAYLOADCRCERROR | 00665 RFLR_IRQFLAGS_VALIDHEADER | 00666 RFLR_IRQFLAGS_TXDONE | 00667 RFLR_IRQFLAGS_CADDONE | 00668 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00669 RFLR_IRQFLAGS_CADDETECTED ); 00670 00671 // DIO0=RxDone 00672 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 ); 00673 } 00674 Write( REG_LR_FIFORXBASEADDR, 0 ); 00675 Write( REG_LR_FIFOADDRPTR, 0 ); 00676 } 00677 break; 00678 } 00679 00680 memset( rxtxBuffer, 0, ( size_t )RX_BUFFER_SIZE ); 00681 00682 this->settings.State = RF_RX_RUNNING; 00683 if( timeout != 0 ) 00684 { 00685 rxTimeoutTimer.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ), timeout * 1e3 ); 00686 } 00687 00688 if( this->settings.Modem == MODEM_FSK ) 00689 { 00690 SetOpMode( RF_OPMODE_RECEIVER ); 00691 00692 if( rxContinuous == false ) 00693 { 00694 rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ), 00695 this->settings.Fsk.RxSingleTimeout * 1e3 ); 00696 } 00697 } 00698 else 00699 { 00700 if( rxContinuous == true ) 00701 { 00702 SetOpMode( RFLR_OPMODE_RECEIVER ); 00703 } 00704 else 00705 { 00706 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE ); 00707 } 00708 } 00709 } 00710 00711 void SX1272::Tx( uint32_t timeout ) 00712 { 00713 00714 switch( this->settings.Modem ) 00715 { 00716 case MODEM_FSK: 00717 { 00718 // DIO0=PacketSent 00719 // DIO1=FifoEmpty 00720 // DIO2=FifoFull 00721 // DIO3=FifoEmpty 00722 // DIO4=LowBat 00723 // DIO5=ModeReady 00724 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & 00725 RF_DIOMAPPING1_DIO1_MASK & 00726 RF_DIOMAPPING1_DIO2_MASK ) | 00727 RF_DIOMAPPING1_DIO1_01 ); 00728 00729 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK & 00730 RF_DIOMAPPING2_MAP_MASK ) ); 00731 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F; 00732 } 00733 break; 00734 case MODEM_LORA: 00735 { 00736 if( this->settings.LoRa.FreqHopOn == true ) 00737 { 00738 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | 00739 RFLR_IRQFLAGS_RXDONE | 00740 RFLR_IRQFLAGS_PAYLOADCRCERROR | 00741 RFLR_IRQFLAGS_VALIDHEADER | 00742 //RFLR_IRQFLAGS_TXDONE | 00743 RFLR_IRQFLAGS_CADDONE | 00744 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00745 RFLR_IRQFLAGS_CADDETECTED ); 00746 00747 // DIO0=TxDone, DIO2=FhssChangeChannel 00748 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 ); 00749 } 00750 else 00751 { 00752 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | 00753 RFLR_IRQFLAGS_RXDONE | 00754 RFLR_IRQFLAGS_PAYLOADCRCERROR | 00755 RFLR_IRQFLAGS_VALIDHEADER | 00756 //RFLR_IRQFLAGS_TXDONE | 00757 RFLR_IRQFLAGS_CADDONE | 00758 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00759 RFLR_IRQFLAGS_CADDETECTED ); 00760 00761 // DIO0=TxDone 00762 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 ); 00763 } 00764 } 00765 break; 00766 } 00767 00768 this->settings.State = RF_TX_RUNNING; 00769 txTimeoutTimer .attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ), timeout * 1e3 ); 00770 SetOpMode( RF_OPMODE_TRANSMITTER ); 00771 } 00772 00773 void SX1272::StartCad( void ) 00774 { 00775 switch( this->settings.Modem ) 00776 { 00777 case MODEM_FSK: 00778 { 00779 00780 } 00781 break; 00782 case MODEM_LORA: 00783 { 00784 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | 00785 RFLR_IRQFLAGS_RXDONE | 00786 RFLR_IRQFLAGS_PAYLOADCRCERROR | 00787 RFLR_IRQFLAGS_VALIDHEADER | 00788 RFLR_IRQFLAGS_TXDONE | 00789 //RFLR_IRQFLAGS_CADDONE | 00790 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // | 00791 //RFLR_IRQFLAGS_CADDETECTED 00792 ); 00793 00794 // DIO3=CADDone 00795 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO3_MASK ) | RFLR_DIOMAPPING1_DIO3_00 ); 00796 00797 this->settings.State = RF_CAD; 00798 SetOpMode( RFLR_OPMODE_CAD ); 00799 } 00800 break; 00801 default: 00802 break; 00803 } 00804 } 00805 00806 void SX1272::SetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time ) 00807 { 00808 uint32_t timeout = ( uint32_t )( time * 1e6 ); 00809 00810 SetChannel( freq ); 00811 00812 SetTxConfig( MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, timeout ); 00813 00814 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) & RF_PACKETCONFIG2_DATAMODE_MASK ) ); 00815 // Disable radio interrupts 00816 Write( REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11 ); 00817 Write( REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10 ); 00818 00819 this->settings.State = RF_TX_RUNNING; 00820 txTimeoutTimer .attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ), timeout ); 00821 SetOpMode( RF_OPMODE_TRANSMITTER ); 00822 } 00823 00824 int16_t SX1272::GetRssi( RadioModems_t modem ) 00825 { 00826 int16_t rssi = 0; 00827 00828 switch( modem ) 00829 { 00830 case MODEM_FSK: 00831 rssi = -( Read( REG_RSSIVALUE ) >> 1 ); 00832 break; 00833 case MODEM_LORA: 00834 rssi = RSSI_OFFSET + Read( REG_LR_RSSIVALUE ); 00835 break; 00836 default: 00837 rssi = -1; 00838 break; 00839 } 00840 return rssi; 00841 } 00842 00843 void SX1272::SetOpMode( uint8_t opMode ) 00844 { 00845 if( opMode == RF_OPMODE_SLEEP ) 00846 { 00847 SetAntSwLowPower( true ); 00848 } 00849 else 00850 { 00851 SetAntSwLowPower( false ); 00852 SetAntSw( opMode ); 00853 } 00854 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode ); 00855 } 00856 00857 void SX1272::SetModem( RadioModems_t modem ) 00858 { 00859 if( ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_ON ) != 0 ) 00860 { 00861 this->settings.Modem = MODEM_LORA; 00862 } 00863 else 00864 { 00865 this->settings.Modem = MODEM_FSK; 00866 } 00867 00868 if( this->settings.Modem == modem ) 00869 { 00870 return; 00871 } 00872 00873 this->settings.Modem = modem; 00874 switch( this->settings.Modem ) 00875 { 00876 default: 00877 case MODEM_FSK: 00878 Sleep( ); 00879 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF ); 00880 00881 Write( REG_DIOMAPPING1, 0x00 ); 00882 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady 00883 break; 00884 case MODEM_LORA: 00885 Sleep( ); 00886 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON ); 00887 00888 Write( REG_DIOMAPPING1, 0x00 ); 00889 Write( REG_DIOMAPPING2, 0x00 ); 00890 break; 00891 } 00892 } 00893 00894 void SX1272::SetMaxPayloadLength( RadioModems_t modem, uint8_t max ) 00895 { 00896 this->SetModem( modem ); 00897 00898 switch( modem ) 00899 { 00900 case MODEM_FSK: 00901 if( this->settings.Fsk.FixLen == false ) 00902 { 00903 this->Write( REG_PAYLOADLENGTH, max ); 00904 } 00905 break; 00906 case MODEM_LORA: 00907 this->Write( REG_LR_PAYLOADMAXLENGTH, max ); 00908 break; 00909 } 00910 } 00911 00912 void SX1272::SetPublicNetwork( bool enable ) 00913 { 00914 SetModem( MODEM_LORA ); 00915 this->settings.LoRa.PublicNetwork = enable; 00916 if( enable == true ) 00917 { 00918 // Change LoRa modem SyncWord 00919 Write( REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD ); 00920 } 00921 else 00922 { 00923 // Change LoRa modem SyncWord 00924 Write( REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD ); 00925 } 00926 } 00927 00928 void SX1272::OnTimeoutIrq( void ) 00929 { 00930 switch( this->settings.State ) 00931 { 00932 case RF_RX_RUNNING: 00933 if( this->settings.Modem == MODEM_FSK ) 00934 { 00935 this->settings.FskPacketHandler.PreambleDetected = false; 00936 this->settings.FskPacketHandler.SyncWordDetected = false; 00937 this->settings.FskPacketHandler.NbBytes = 0; 00938 this->settings.FskPacketHandler.Size = 0; 00939 00940 // Clear Irqs 00941 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI | 00942 RF_IRQFLAGS1_PREAMBLEDETECT | 00943 RF_IRQFLAGS1_SYNCADDRESSMATCH ); 00944 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN ); 00945 00946 if( this->settings.Fsk.RxContinuous == true ) 00947 { 00948 // Continuous mode restart Rx chain 00949 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK ); 00950 rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ), 00951 this->settings.Fsk.RxSingleTimeout * 1e3 ); 00952 } 00953 else 00954 { 00955 this->settings.State = RF_IDLE; 00956 rxTimeoutSyncWord.detach( ); 00957 } 00958 } 00959 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) ) 00960 { 00961 this->RadioEvents->RxTimeout( ); 00962 } 00963 break; 00964 case RF_TX_RUNNING: 00965 // Tx timeout shouldn't happen. 00966 // But it has been observed that when it happens it is a result of a corrupted SPI transfer 00967 // it depends on the platform design. 00968 // 00969 // The workaround is to put the radio in a known state. Thus, we re-initialize it. 00970 00971 // BEGIN WORKAROUND 00972 00973 // Reset the radio 00974 Reset( ); 00975 00976 // Initialize radio default values 00977 SetOpMode( RF_OPMODE_SLEEP ); 00978 00979 RadioRegistersInit( ); 00980 00981 SetModem( MODEM_FSK ); 00982 00983 // Restore previous network type setting. 00984 SetPublicNetwork( this->settings.LoRa.PublicNetwork ); 00985 // END WORKAROUND 00986 00987 this->settings.State = RF_IDLE; 00988 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) ) 00989 { 00990 this->RadioEvents->TxTimeout( ); 00991 } 00992 break; 00993 default: 00994 break; 00995 } 00996 } 00997 00998 void SX1272::OnDio0Irq( void ) 00999 { 01000 volatile uint8_t irqFlags = 0; 01001 01002 switch( this->settings.State ) 01003 { 01004 case RF_RX_RUNNING: 01005 //TimerStop( &RxTimeoutTimer ); 01006 // RxDone interrupt 01007 switch( this->settings.Modem ) 01008 { 01009 case MODEM_FSK: 01010 if( this->settings.Fsk.CrcOn == true ) 01011 { 01012 irqFlags = Read( REG_IRQFLAGS2 ); 01013 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK ) 01014 { 01015 // Clear Irqs 01016 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI | 01017 RF_IRQFLAGS1_PREAMBLEDETECT | 01018 RF_IRQFLAGS1_SYNCADDRESSMATCH ); 01019 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN ); 01020 01021 rxTimeoutTimer.detach( ); 01022 01023 if( this->settings.Fsk.RxContinuous == false ) 01024 { 01025 rxTimeoutSyncWord.detach( ); 01026 this->settings.State = RF_IDLE; 01027 } 01028 else 01029 { 01030 // Continuous mode restart Rx chain 01031 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK ); 01032 rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ), 01033 this->settings.Fsk.RxSingleTimeout * 1e3 ); 01034 } 01035 01036 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) ) 01037 { 01038 this->RadioEvents->RxError( ); 01039 } 01040 this->settings.FskPacketHandler.PreambleDetected = false; 01041 this->settings.FskPacketHandler.SyncWordDetected = false; 01042 this->settings.FskPacketHandler.NbBytes = 0; 01043 this->settings.FskPacketHandler.Size = 0; 01044 break; 01045 } 01046 } 01047 01048 // Read received packet size 01049 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) ) 01050 { 01051 if( this->settings.Fsk.FixLen == false ) 01052 { 01053 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 ); 01054 } 01055 else 01056 { 01057 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH ); 01058 } 01059 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); 01060 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); 01061 } 01062 else 01063 { 01064 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); 01065 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); 01066 } 01067 01068 rxTimeoutTimer.detach( ); 01069 01070 if( this->settings.Fsk.RxContinuous == false ) 01071 { 01072 this->settings.State = RF_IDLE; 01073 rxTimeoutSyncWord.detach( ); 01074 } 01075 else 01076 { 01077 // Continuous mode restart Rx chain 01078 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK ); 01079 rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ), 01080 this->settings.Fsk.RxSingleTimeout * 1e3 ); 01081 } 01082 01083 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) ) 01084 { 01085 this->RadioEvents->RxDone( rxtxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 ); 01086 } 01087 this->settings.FskPacketHandler.PreambleDetected = false; 01088 this->settings.FskPacketHandler.SyncWordDetected = false; 01089 this->settings.FskPacketHandler.NbBytes = 0; 01090 this->settings.FskPacketHandler.Size = 0; 01091 break; 01092 case MODEM_LORA: 01093 { 01094 int8_t snr = 0; 01095 01096 // Clear Irq 01097 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE ); 01098 01099 irqFlags = Read( REG_LR_IRQFLAGS ); 01100 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR ) 01101 { 01102 // Clear Irq 01103 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR ); 01104 01105 if( this->settings.LoRa.RxContinuous == false ) 01106 { 01107 this->settings.State = RF_IDLE; 01108 } 01109 rxTimeoutTimer.detach( ); 01110 01111 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) ) 01112 { 01113 this->RadioEvents->RxError( ); 01114 } 01115 break; 01116 } 01117 01118 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE ); 01119 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1 01120 { 01121 // Invert and divide by 4 01122 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2; 01123 snr = -snr; 01124 } 01125 else 01126 { 01127 // Divide by 4 01128 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2; 01129 } 01130 01131 int16_t rssi = Read( REG_LR_PKTRSSIVALUE ); 01132 if( snr < 0 ) 01133 { 01134 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 ) + 01135 snr; 01136 } 01137 else 01138 { 01139 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 ); 01140 } 01141 01142 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES ); 01143 ReadFifo( rxtxBuffer, this->settings.LoRaPacketHandler.Size ); 01144 01145 if( this->settings.LoRa.RxContinuous == false ) 01146 { 01147 this->settings.State = RF_IDLE; 01148 } 01149 rxTimeoutTimer.detach( ); 01150 01151 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) ) 01152 { 01153 this->RadioEvents->RxDone( rxtxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue ); 01154 } 01155 } 01156 break; 01157 default: 01158 break; 01159 } 01160 break; 01161 case RF_TX_RUNNING: 01162 txTimeoutTimer .detach( ); 01163 // TxDone interrupt 01164 switch( this->settings.Modem ) 01165 { 01166 case MODEM_LORA: 01167 // Clear Irq 01168 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE ); 01169 // Intentional fall through 01170 case MODEM_FSK: 01171 default: 01172 this->settings.State = RF_IDLE; 01173 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) ) 01174 { 01175 this->RadioEvents->TxDone( ); 01176 } 01177 break; 01178 } 01179 break; 01180 default: 01181 break; 01182 } 01183 } 01184 01185 void SX1272::OnDio1Irq( void ) 01186 { 01187 switch( this->settings.State ) 01188 { 01189 case RF_RX_RUNNING: 01190 switch( this->settings.Modem ) 01191 { 01192 case MODEM_FSK: 01193 // FifoLevel interrupt 01194 // Read received packet size 01195 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) ) 01196 { 01197 if( this->settings.Fsk.FixLen == false ) 01198 { 01199 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 ); 01200 } 01201 else 01202 { 01203 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH ); 01204 } 01205 } 01206 01207 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh ) 01208 { 01209 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh ); 01210 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh; 01211 } 01212 else 01213 { 01214 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); 01215 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); 01216 } 01217 break; 01218 case MODEM_LORA: 01219 // Sync time out 01220 rxTimeoutTimer.detach( ); 01221 // Clear Irq 01222 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXTIMEOUT ); 01223 01224 this->settings.State = RF_IDLE; 01225 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) ) 01226 { 01227 this->RadioEvents->RxTimeout( ); 01228 } 01229 break; 01230 default: 01231 break; 01232 } 01233 break; 01234 case RF_TX_RUNNING: 01235 switch( this->settings.Modem ) 01236 { 01237 case MODEM_FSK: 01238 // FifoEmpty interrupt 01239 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize ) 01240 { 01241 WriteFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize ); 01242 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize; 01243 } 01244 else 01245 { 01246 // Write the last chunk of data 01247 WriteFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); 01248 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes; 01249 } 01250 break; 01251 case MODEM_LORA: 01252 break; 01253 default: 01254 break; 01255 } 01256 break; 01257 default: 01258 break; 01259 } 01260 } 01261 01262 void SX1272::OnDio2Irq( void ) 01263 { 01264 switch( this->settings.State ) 01265 { 01266 case RF_RX_RUNNING: 01267 switch( this->settings.Modem ) 01268 { 01269 case MODEM_FSK: 01270 // Checks if DIO4 is connected. If it is not PreambleDtected is set to true. 01271 if( this->dioIrq [4] == NULL ) 01272 { 01273 this->settings.FskPacketHandler.PreambleDetected = true; 01274 } 01275 01276 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) ) 01277 { 01278 rxTimeoutSyncWord.detach( ); 01279 01280 this->settings.FskPacketHandler.SyncWordDetected = true; 01281 01282 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 ); 01283 01284 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) | 01285 ( uint16_t )Read( REG_AFCLSB ) ) * 01286 ( double )FREQ_STEP; 01287 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07; 01288 } 01289 break; 01290 case MODEM_LORA: 01291 if( this->settings.LoRa.FreqHopOn == true ) 01292 { 01293 // Clear Irq 01294 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL ); 01295 01296 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) ) 01297 { 01298 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) ); 01299 } 01300 } 01301 break; 01302 default: 01303 break; 01304 } 01305 break; 01306 case RF_TX_RUNNING: 01307 switch( this->settings.Modem ) 01308 { 01309 case MODEM_FSK: 01310 break; 01311 case MODEM_LORA: 01312 if( this->settings.LoRa.FreqHopOn == true ) 01313 { 01314 // Clear Irq 01315 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL ); 01316 01317 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) ) 01318 { 01319 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) ); 01320 } 01321 } 01322 break; 01323 default: 01324 break; 01325 } 01326 break; 01327 default: 01328 break; 01329 } 01330 } 01331 01332 void SX1272::OnDio3Irq( void ) 01333 { 01334 switch( this->settings.Modem ) 01335 { 01336 case MODEM_FSK: 01337 break; 01338 case MODEM_LORA: 01339 if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED ) 01340 { 01341 // Clear Irq 01342 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE ); 01343 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) ) 01344 { 01345 this->RadioEvents->CadDone( true ); 01346 } 01347 } 01348 else 01349 { 01350 // Clear Irq 01351 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE ); 01352 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) ) 01353 { 01354 this->RadioEvents->CadDone( false ); 01355 } 01356 } 01357 break; 01358 default: 01359 break; 01360 } 01361 } 01362 01363 void SX1272::OnDio4Irq( void ) 01364 { 01365 switch( this->settings.Modem ) 01366 { 01367 case MODEM_FSK: 01368 { 01369 if( this->settings.FskPacketHandler.PreambleDetected == false ) 01370 { 01371 this->settings.FskPacketHandler.PreambleDetected = true; 01372 } 01373 } 01374 break; 01375 case MODEM_LORA: 01376 break; 01377 default: 01378 break; 01379 } 01380 } 01381 01382 void SX1272::OnDio5Irq( void ) 01383 { 01384 switch( this->settings.Modem ) 01385 { 01386 case MODEM_FSK: 01387 break; 01388 case MODEM_LORA: 01389 break; 01390 default: 01391 break; 01392 } 01393 }
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