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nrf51.h
00001 /* 00002 * Copyright (c) Nordic Semiconductor ASA 00003 * All rights reserved. 00004 * 00005 * Redistribution and use in source and binary forms, with or without modification, 00006 * are permitted provided that the following conditions are met: 00007 * 00008 * 1. Redistributions of source code must retain the above copyright notice, this 00009 * list of conditions and the following disclaimer. 00010 * 00011 * 2. Redistributions in binary form must reproduce the above copyright notice, this 00012 * list of conditions and the following disclaimer in the documentation and/or 00013 * other materials provided with the distribution. 00014 * 00015 * 3. Neither the name of Nordic Semiconductor ASA nor the names of other 00016 * contributors to this software may be used to endorse or promote products 00017 * derived from this software without specific prior written permission. 00018 * 00019 * 00020 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 00021 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 00022 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00023 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 00024 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00025 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00026 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 00027 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00028 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 00029 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00030 * 00031 */ 00032 00033 #ifndef NRF51_H 00034 #define NRF51_H 00035 00036 #ifdef __cplusplus 00037 extern "C" { 00038 #endif 00039 00040 00041 /* ------------------------- Interrupt Number Definition ------------------------ */ 00042 00043 typedef enum { 00044 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ 00045 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ 00046 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ 00047 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ 00048 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ 00049 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ 00050 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ 00051 SysTick_IRQn = -1, /*!< 15 System Tick Timer */ 00052 /* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */ 00053 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 00054 RADIO_IRQn = 1, /*!< 1 RADIO */ 00055 UART0_IRQn = 2, /*!< 2 UART0 */ 00056 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */ 00057 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */ 00058 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 00059 ADC_IRQn = 7, /*!< 7 ADC */ 00060 TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 00061 TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 00062 TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 00063 RTC0_IRQn = 11, /*!< 11 RTC0 */ 00064 TEMP_IRQn = 12, /*!< 12 TEMP */ 00065 RNG_IRQn = 13, /*!< 13 RNG */ 00066 ECB_IRQn = 14, /*!< 14 ECB */ 00067 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 00068 WDT_IRQn = 16, /*!< 16 WDT */ 00069 RTC1_IRQn = 17, /*!< 17 RTC1 */ 00070 QDEC_IRQn = 18, /*!< 18 QDEC */ 00071 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */ 00072 SWI0_IRQn = 20, /*!< 20 SWI0 */ 00073 SWI1_IRQn = 21, /*!< 21 SWI1 */ 00074 SWI2_IRQn = 22, /*!< 22 SWI2 */ 00075 SWI3_IRQn = 23, /*!< 23 SWI3 */ 00076 SWI4_IRQn = 24, /*!< 24 SWI4 */ 00077 SWI5_IRQn = 25 /*!< 25 SWI5 */ 00078 } IRQn_Type; 00079 00080 00081 /** @addtogroup Configuration_of_CMSIS 00082 * @{ 00083 */ 00084 00085 00086 /* ================================================================================ */ 00087 /* ================ Processor and Core Peripheral Section ================ */ 00088 /* ================================================================================ */ 00089 00090 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */ 00091 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */ 00092 #define __MPU_PRESENT 0 /*!< MPU present or not */ 00093 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ 00094 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 00095 /** @} */ /* End of group Configuration_of_CMSIS */ 00096 00097 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ 00098 #include "system_nrf51.h" /*!< nrf51 System */ 00099 00100 00101 /* ================================================================================ */ 00102 /* ================ Device Specific Peripheral Section ================ */ 00103 /* ================================================================================ */ 00104 00105 00106 /** @addtogroup Device_Peripheral_Registers 00107 * @{ 00108 */ 00109 00110 00111 /* ------------------- Start of section using anonymous unions ------------------ */ 00112 #if defined(__CC_ARM) 00113 #pragma push 00114 #pragma anon_unions 00115 #elif defined(__ICCARM__) 00116 #pragma language=extended 00117 #elif defined(__GNUC__) 00118 /* anonymous unions are enabled by default */ 00119 #elif defined(__TMS470__) 00120 /* anonymous unions are enabled by default */ 00121 #elif defined(__TASKING__) 00122 #pragma warning 586 00123 #else 00124 #warning Not supported compiler type 00125 #endif 00126 00127 00128 typedef struct { 00129 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */ 00130 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */ 00131 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */ 00132 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */ 00133 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */ 00134 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */ 00135 } AMLI_RAMPRI_Type; 00136 00137 typedef struct { 00138 __IO uint32_t SCK; /*!< Pin select for SCK. */ 00139 __IO uint32_t MOSI; /*!< Pin select for MOSI. */ 00140 __IO uint32_t MISO; /*!< Pin select for MISO. */ 00141 } SPIM_PSEL_Type; 00142 00143 typedef struct { 00144 __IO uint32_t PTR; /*!< Data pointer. */ 00145 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */ 00146 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */ 00147 } SPIM_RXD_Type; 00148 00149 typedef struct { 00150 __IO uint32_t PTR; /*!< Data pointer. */ 00151 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */ 00152 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */ 00153 } SPIM_TXD_Type; 00154 00155 typedef struct { 00156 __O uint32_t EN; /*!< Enable channel group. */ 00157 __O uint32_t DIS; /*!< Disable channel group. */ 00158 } PPI_TASKS_CHG_Type; 00159 00160 typedef struct { 00161 __IO uint32_t EEP; /*!< Channel event end-point. */ 00162 __IO uint32_t TEP; /*!< Channel task end-point. */ 00163 } PPI_CH_Type; 00164 00165 00166 /* ================================================================================ */ 00167 /* ================ POWER ================ */ 00168 /* ================================================================================ */ 00169 00170 00171 /** 00172 * @brief Power Control. (POWER) 00173 */ 00174 00175 typedef struct { /*!< POWER Structure */ 00176 __I uint32_t RESERVED0[30]; 00177 __O uint32_t TASKS_CONSTLAT ; /*!< Enable constant latency mode. */ 00178 __O uint32_t TASKS_LOWPWR ; /*!< Enable low power mode (variable latency). */ 00179 __I uint32_t RESERVED1[34]; 00180 __IO uint32_t EVENTS_POFWARN ; /*!< Power failure warning. */ 00181 __I uint32_t RESERVED2[126]; 00182 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00183 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00184 __I uint32_t RESERVED3[61]; 00185 __IO uint32_t RESETREAS ; /*!< Reset reason. */ 00186 __I uint32_t RESERVED4[9]; 00187 __I uint32_t RAMSTATUS ; /*!< Ram status register. */ 00188 __I uint32_t RESERVED5[53]; 00189 __O uint32_t SYSTEMOFF ; /*!< System off register. */ 00190 __I uint32_t RESERVED6[3]; 00191 __IO uint32_t POFCON ; /*!< Power failure configuration. */ 00192 __I uint32_t RESERVED7[2]; 00193 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained 00194 register. */ 00195 __I uint32_t RESERVED8; 00196 __IO uint32_t RAMON ; /*!< Ram on/off. */ 00197 __I uint32_t RESERVED9[7]; 00198 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register 00199 is a retained register. */ 00200 __I uint32_t RESERVED10[3]; 00201 __IO uint32_t RAMONB ; /*!< Ram on/off. */ 00202 __I uint32_t RESERVED11[8]; 00203 __IO uint32_t DCDCEN ; /*!< DCDC converter enable configuration register. */ 00204 __I uint32_t RESERVED12[291]; 00205 __IO uint32_t DCDCFORCE ; /*!< DCDC power-up force register. */ 00206 } NRF_POWER_Type; 00207 00208 00209 /* ================================================================================ */ 00210 /* ================ CLOCK ================ */ 00211 /* ================================================================================ */ 00212 00213 00214 /** 00215 * @brief Clock control. (CLOCK) 00216 */ 00217 00218 typedef struct { /*!< CLOCK Structure */ 00219 __O uint32_t TASKS_HFCLKSTART ; /*!< Start HFCLK clock source. */ 00220 __O uint32_t TASKS_HFCLKSTOP ; /*!< Stop HFCLK clock source. */ 00221 __O uint32_t TASKS_LFCLKSTART ; /*!< Start LFCLK clock source. */ 00222 __O uint32_t TASKS_LFCLKSTOP ; /*!< Stop LFCLK clock source. */ 00223 __O uint32_t TASKS_CAL ; /*!< Start calibration of LFCLK RC oscillator. */ 00224 __O uint32_t TASKS_CTSTART ; /*!< Start calibration timer. */ 00225 __O uint32_t TASKS_CTSTOP ; /*!< Stop calibration timer. */ 00226 __I uint32_t RESERVED0[57]; 00227 __IO uint32_t EVENTS_HFCLKSTARTED ; /*!< HFCLK oscillator started. */ 00228 __IO uint32_t EVENTS_LFCLKSTARTED ; /*!< LFCLK oscillator started. */ 00229 __I uint32_t RESERVED1; 00230 __IO uint32_t EVENTS_DONE ; /*!< Calibration of LFCLK RC oscillator completed. */ 00231 __IO uint32_t EVENTS_CTTO ; /*!< Calibration timer timeout. */ 00232 __I uint32_t RESERVED2[124]; 00233 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00234 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00235 __I uint32_t RESERVED3[63]; 00236 __I uint32_t HFCLKRUN ; /*!< Task HFCLKSTART trigger status. */ 00237 __I uint32_t HFCLKSTAT ; /*!< High frequency clock status. */ 00238 __I uint32_t RESERVED4; 00239 __I uint32_t LFCLKRUN ; /*!< Task LFCLKSTART triggered status. */ 00240 __I uint32_t LFCLKSTAT ; /*!< Low frequency clock status. */ 00241 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is 00242 triggered. */ 00243 __I uint32_t RESERVED5[62]; 00244 __IO uint32_t LFCLKSRC ; /*!< Clock source for the LFCLK clock. */ 00245 __I uint32_t RESERVED6[7]; 00246 __IO uint32_t CTIV ; /*!< Calibration timer interval. */ 00247 __I uint32_t RESERVED7[5]; 00248 __IO uint32_t XTALFREQ ; /*!< Crystal frequency. */ 00249 } NRF_CLOCK_Type; 00250 00251 00252 /* ================================================================================ */ 00253 /* ================ MPU ================ */ 00254 /* ================================================================================ */ 00255 00256 00257 /** 00258 * @brief Memory Protection Unit. (MPU) 00259 */ 00260 00261 typedef struct { /*!< MPU Structure */ 00262 __I uint32_t RESERVED0[330]; 00263 __IO uint32_t PERR0 ; /*!< Configuration of peripherals in mpu regions. */ 00264 __IO uint32_t RLENR0 ; /*!< Length of RAM region 0. */ 00265 __I uint32_t RESERVED1[52]; 00266 __IO uint32_t PROTENSET0 ; /*!< Erase and write protection bit enable set register. */ 00267 __IO uint32_t PROTENSET1 ; /*!< Erase and write protection bit enable set register. */ 00268 __IO uint32_t DISABLEINDEBUG ; /*!< Disable erase and write protection mechanism in debug mode. */ 00269 __IO uint32_t PROTBLOCKSIZE ; /*!< Erase and write protection block size. */ 00270 } NRF_MPU_Type; 00271 00272 00273 /* ================================================================================ */ 00274 /* ================ PU ================ */ 00275 /* ================================================================================ */ 00276 00277 00278 /** 00279 * @brief Patch unit. (PU) 00280 */ 00281 00282 typedef struct { /*!< PU Structure */ 00283 __I uint32_t RESERVED0[448]; 00284 __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */ 00285 __I uint32_t RESERVED1[24]; 00286 __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */ 00287 __I uint32_t RESERVED2[24]; 00288 __IO uint32_t PATCHEN ; /*!< Patch enable register. */ 00289 __IO uint32_t PATCHENSET ; /*!< Patch enable register. */ 00290 __IO uint32_t PATCHENCLR ; /*!< Patch disable register. */ 00291 } NRF_PU_Type; 00292 00293 00294 /* ================================================================================ */ 00295 /* ================ AMLI ================ */ 00296 /* ================================================================================ */ 00297 00298 00299 /** 00300 * @brief AHB Multi-Layer Interface. (AMLI) 00301 */ 00302 00303 typedef struct { /*!< AMLI Structure */ 00304 __I uint32_t RESERVED0[896]; 00305 AMLI_RAMPRI_Type RAMPRI ; /*!< RAM configurable priority configuration structure. */ 00306 } NRF_AMLI_Type; 00307 00308 00309 /* ================================================================================ */ 00310 /* ================ RADIO ================ */ 00311 /* ================================================================================ */ 00312 00313 00314 /** 00315 * @brief The radio. (RADIO) 00316 */ 00317 00318 typedef struct { /*!< RADIO Structure */ 00319 __O uint32_t TASKS_TXEN ; /*!< Enable radio in TX mode. */ 00320 __O uint32_t TASKS_RXEN ; /*!< Enable radio in RX mode. */ 00321 __O uint32_t TASKS_START ; /*!< Start radio. */ 00322 __O uint32_t TASKS_STOP ; /*!< Stop radio. */ 00323 __O uint32_t TASKS_DISABLE ; /*!< Disable radio. */ 00324 __O uint32_t TASKS_RSSISTART ; /*!< Start the RSSI and take one sample of the receive signal strength. */ 00325 __O uint32_t TASKS_RSSISTOP ; /*!< Stop the RSSI measurement. */ 00326 __O uint32_t TASKS_BCSTART ; /*!< Start the bit counter. */ 00327 __O uint32_t TASKS_BCSTOP ; /*!< Stop the bit counter. */ 00328 __I uint32_t RESERVED0[55]; 00329 __IO uint32_t EVENTS_READY ; /*!< Ready event. */ 00330 __IO uint32_t EVENTS_ADDRESS ; /*!< Address event. */ 00331 __IO uint32_t EVENTS_PAYLOAD ; /*!< Payload event. */ 00332 __IO uint32_t EVENTS_END ; /*!< End event. */ 00333 __IO uint32_t EVENTS_DISABLED ; /*!< Disable event. */ 00334 __IO uint32_t EVENTS_DEVMATCH ; /*!< A device address match occurred on the last received packet. */ 00335 __IO uint32_t EVENTS_DEVMISS ; /*!< No device address match occurred on the last received packet. */ 00336 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI 00337 sample is ready for readout at the RSSISAMPLE register. */ 00338 __I uint32_t RESERVED1[2]; 00339 __IO uint32_t EVENTS_BCMATCH ; /*!< Bit counter reached bit count value specified in BCC register. */ 00340 __I uint32_t RESERVED2[53]; 00341 __IO uint32_t SHORTS ; /*!< Shortcuts for the radio. */ 00342 __I uint32_t RESERVED3[64]; 00343 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00344 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00345 __I uint32_t RESERVED4[61]; 00346 __I uint32_t CRCSTATUS ; /*!< CRC status of received packet. */ 00347 __I uint32_t CD ; /*!< Carrier detect. */ 00348 __I uint32_t RXMATCH ; /*!< Received address. */ 00349 __I uint32_t RXCRC ; /*!< Received CRC. */ 00350 __I uint32_t DAI ; /*!< Device address match index. */ 00351 __I uint32_t RESERVED5[60]; 00352 __IO uint32_t PACKETPTR ; /*!< Packet pointer. Decision point: START task. */ 00353 __IO uint32_t FREQUENCY ; /*!< Frequency. */ 00354 __IO uint32_t TXPOWER ; /*!< Output power. */ 00355 __IO uint32_t MODE ; /*!< Data rate and modulation. */ 00356 __IO uint32_t PCNF0 ; /*!< Packet configuration 0. */ 00357 __IO uint32_t PCNF1 ; /*!< Packet configuration 1. */ 00358 __IO uint32_t BASE0 ; /*!< Radio base address 0. Decision point: START task. */ 00359 __IO uint32_t BASE1 ; /*!< Radio base address 1. Decision point: START task. */ 00360 __IO uint32_t PREFIX0 ; /*!< Prefixes bytes for logical addresses 0 to 3. */ 00361 __IO uint32_t PREFIX1 ; /*!< Prefixes bytes for logical addresses 4 to 7. */ 00362 __IO uint32_t TXADDRESS ; /*!< Transmit address select. */ 00363 __IO uint32_t RXADDRESSES ; /*!< Receive address select. */ 00364 __IO uint32_t CRCCNF ; /*!< CRC configuration. */ 00365 __IO uint32_t CRCPOLY ; /*!< CRC polynomial. */ 00366 __IO uint32_t CRCINIT ; /*!< CRC initial value. */ 00367 __IO uint32_t TEST ; /*!< Test features enable register. */ 00368 __IO uint32_t TIFS ; /*!< Inter Frame Spacing in microseconds. */ 00369 __I uint32_t RSSISAMPLE ; /*!< RSSI sample. */ 00370 __I uint32_t RESERVED6; 00371 __I uint32_t STATE ; /*!< Current radio state. */ 00372 __IO uint32_t DATAWHITEIV ; /*!< Data whitening initial value. */ 00373 __I uint32_t RESERVED7[2]; 00374 __IO uint32_t BCC ; /*!< Bit counter compare. */ 00375 __I uint32_t RESERVED8[39]; 00376 __IO uint32_t DAB[8]; /*!< Device address base segment. */ 00377 __IO uint32_t DAP[8]; /*!< Device address prefix. */ 00378 __IO uint32_t DACNF ; /*!< Device address match configuration. */ 00379 __I uint32_t RESERVED9[56]; 00380 __IO uint32_t OVERRIDE0 ; /*!< Trim value override register 0. */ 00381 __IO uint32_t OVERRIDE1 ; /*!< Trim value override register 1. */ 00382 __IO uint32_t OVERRIDE2 ; /*!< Trim value override register 2. */ 00383 __IO uint32_t OVERRIDE3 ; /*!< Trim value override register 3. */ 00384 __IO uint32_t OVERRIDE4 ; /*!< Trim value override register 4. */ 00385 __I uint32_t RESERVED10[561]; 00386 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00387 } NRF_RADIO_Type; 00388 00389 00390 /* ================================================================================ */ 00391 /* ================ UART ================ */ 00392 /* ================================================================================ */ 00393 00394 00395 /** 00396 * @brief Universal Asynchronous Receiver/Transmitter. (UART) 00397 */ 00398 00399 typedef struct { /*!< UART Structure */ 00400 __O uint32_t TASKS_STARTRX ; /*!< Start UART receiver. */ 00401 __O uint32_t TASKS_STOPRX ; /*!< Stop UART receiver. */ 00402 __O uint32_t TASKS_STARTTX ; /*!< Start UART transmitter. */ 00403 __O uint32_t TASKS_STOPTX ; /*!< Stop UART transmitter. */ 00404 __I uint32_t RESERVED0[3]; 00405 __O uint32_t TASKS_SUSPEND ; /*!< Suspend UART. */ 00406 __I uint32_t RESERVED1[56]; 00407 __IO uint32_t EVENTS_CTS ; /*!< CTS activated. */ 00408 __IO uint32_t EVENTS_NCTS ; /*!< CTS deactivated. */ 00409 __IO uint32_t EVENTS_RXDRDY ; /*!< Data received in RXD. */ 00410 __I uint32_t RESERVED2[4]; 00411 __IO uint32_t EVENTS_TXDRDY ; /*!< Data sent from TXD. */ 00412 __I uint32_t RESERVED3; 00413 __IO uint32_t EVENTS_ERROR ; /*!< Error detected. */ 00414 __I uint32_t RESERVED4[7]; 00415 __IO uint32_t EVENTS_RXTO ; /*!< Receiver timeout. */ 00416 __I uint32_t RESERVED5[111]; 00417 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00418 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00419 __I uint32_t RESERVED6[93]; 00420 __IO uint32_t ERRORSRC ; /*!< Error source. Write error field to 1 to clear error. */ 00421 __I uint32_t RESERVED7[31]; 00422 __IO uint32_t ENABLE ; /*!< Enable UART and acquire IOs. */ 00423 __I uint32_t RESERVED8; 00424 __IO uint32_t PSELRTS ; /*!< Pin select for RTS. */ 00425 __IO uint32_t PSELTXD ; /*!< Pin select for TXD. */ 00426 __IO uint32_t PSELCTS ; /*!< Pin select for CTS. */ 00427 __IO uint32_t PSELRXD ; /*!< Pin select for RXD. */ 00428 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced. 00429 Once read the character is consumed. If read when no character 00430 available, the UART will stop working. */ 00431 __O uint32_t TXD ; /*!< TXD register. */ 00432 __I uint32_t RESERVED9; 00433 __IO uint32_t BAUDRATE ; /*!< UART Baudrate. */ 00434 __I uint32_t RESERVED10[17]; 00435 __IO uint32_t CONFIG ; /*!< Configuration of parity and hardware flow control register. */ 00436 __I uint32_t RESERVED11[675]; 00437 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00438 } NRF_UART_Type; 00439 00440 00441 /* ================================================================================ */ 00442 /* ================ SPI ================ */ 00443 /* ================================================================================ */ 00444 00445 00446 /** 00447 * @brief SPI master 0. (SPI) 00448 */ 00449 00450 typedef struct { /*!< SPI Structure */ 00451 __I uint32_t RESERVED0[66]; 00452 __IO uint32_t EVENTS_READY ; /*!< TXD byte sent and RXD byte received. */ 00453 __I uint32_t RESERVED1[126]; 00454 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00455 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00456 __I uint32_t RESERVED2[125]; 00457 __IO uint32_t ENABLE ; /*!< Enable SPI. */ 00458 __I uint32_t RESERVED3; 00459 __IO uint32_t PSELSCK ; /*!< Pin select for SCK. */ 00460 __IO uint32_t PSELMOSI ; /*!< Pin select for MOSI. */ 00461 __IO uint32_t PSELMISO ; /*!< Pin select for MISO. */ 00462 __I uint32_t RESERVED4; 00463 __I uint32_t RXD ; /*!< RX data. */ 00464 __IO uint32_t TXD ; /*!< TX data. */ 00465 __I uint32_t RESERVED5; 00466 __IO uint32_t FREQUENCY ; /*!< SPI frequency */ 00467 __I uint32_t RESERVED6[11]; 00468 __IO uint32_t CONFIG ; /*!< Configuration register. */ 00469 __I uint32_t RESERVED7[681]; 00470 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00471 } NRF_SPI_Type; 00472 00473 00474 /* ================================================================================ */ 00475 /* ================ TWI ================ */ 00476 /* ================================================================================ */ 00477 00478 00479 /** 00480 * @brief Two-wire interface master 0. (TWI) 00481 */ 00482 00483 typedef struct { /*!< TWI Structure */ 00484 __O uint32_t TASKS_STARTRX ; /*!< Start 2-Wire master receive sequence. */ 00485 __I uint32_t RESERVED0; 00486 __O uint32_t TASKS_STARTTX ; /*!< Start 2-Wire master transmit sequence. */ 00487 __I uint32_t RESERVED1[2]; 00488 __O uint32_t TASKS_STOP ; /*!< Stop 2-Wire transaction. */ 00489 __I uint32_t RESERVED2; 00490 __O uint32_t TASKS_SUSPEND ; /*!< Suspend 2-Wire transaction. */ 00491 __O uint32_t TASKS_RESUME ; /*!< Resume 2-Wire transaction. */ 00492 __I uint32_t RESERVED3[56]; 00493 __IO uint32_t EVENTS_STOPPED ; /*!< Two-wire stopped. */ 00494 __IO uint32_t EVENTS_RXDREADY ; /*!< Two-wire ready to deliver new RXD byte received. */ 00495 __I uint32_t RESERVED4[4]; 00496 __IO uint32_t EVENTS_TXDSENT ; /*!< Two-wire finished sending last TXD byte. */ 00497 __I uint32_t RESERVED5; 00498 __IO uint32_t EVENTS_ERROR ; /*!< Two-wire error detected. */ 00499 __I uint32_t RESERVED6[4]; 00500 __IO uint32_t EVENTS_BB ; /*!< Two-wire byte boundary. */ 00501 __I uint32_t RESERVED7[3]; 00502 __IO uint32_t EVENTS_SUSPENDED ; /*!< Two-wire suspended. */ 00503 __I uint32_t RESERVED8[45]; 00504 __IO uint32_t SHORTS ; /*!< Shortcuts for TWI. */ 00505 __I uint32_t RESERVED9[64]; 00506 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00507 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00508 __I uint32_t RESERVED10[110]; 00509 __IO uint32_t ERRORSRC ; /*!< Two-wire error source. Write error field to 1 to clear error. */ 00510 __I uint32_t RESERVED11[14]; 00511 __IO uint32_t ENABLE ; /*!< Enable two-wire master. */ 00512 __I uint32_t RESERVED12; 00513 __IO uint32_t PSELSCL ; /*!< Pin select for SCL. */ 00514 __IO uint32_t PSELSDA ; /*!< Pin select for SDA. */ 00515 __I uint32_t RESERVED13[2]; 00516 __I uint32_t RXD ; /*!< RX data register. */ 00517 __IO uint32_t TXD ; /*!< TX data register. */ 00518 __I uint32_t RESERVED14; 00519 __IO uint32_t FREQUENCY ; /*!< Two-wire frequency. */ 00520 __I uint32_t RESERVED15[24]; 00521 __IO uint32_t ADDRESS ; /*!< Address used in the two-wire transfer. */ 00522 __I uint32_t RESERVED16[668]; 00523 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00524 } NRF_TWI_Type; 00525 00526 00527 /* ================================================================================ */ 00528 /* ================ SPIS ================ */ 00529 /* ================================================================================ */ 00530 00531 00532 /** 00533 * @brief SPI slave 1. (SPIS) 00534 */ 00535 00536 typedef struct { /*!< SPIS Structure */ 00537 __I uint32_t RESERVED0[9]; 00538 __O uint32_t TASKS_ACQUIRE ; /*!< Acquire SPI semaphore. */ 00539 __O uint32_t TASKS_RELEASE ; /*!< Release SPI semaphore. */ 00540 __I uint32_t RESERVED1[54]; 00541 __IO uint32_t EVENTS_END ; /*!< Granted transaction completed. */ 00542 __I uint32_t RESERVED2[8]; 00543 __IO uint32_t EVENTS_ACQUIRED ; /*!< Semaphore acquired. */ 00544 __I uint32_t RESERVED3[53]; 00545 __IO uint32_t SHORTS ; /*!< Shortcuts for SPIS. */ 00546 __I uint32_t RESERVED4[64]; 00547 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00548 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00549 __I uint32_t RESERVED5[61]; 00550 __I uint32_t SEMSTAT ; /*!< Semaphore status. */ 00551 __I uint32_t RESERVED6[15]; 00552 __IO uint32_t STATUS ; /*!< Status from last transaction. */ 00553 __I uint32_t RESERVED7[47]; 00554 __IO uint32_t ENABLE ; /*!< Enable SPIS. */ 00555 __I uint32_t RESERVED8; 00556 __IO uint32_t PSELSCK ; /*!< Pin select for SCK. */ 00557 __IO uint32_t PSELMISO ; /*!< Pin select for MISO. */ 00558 __IO uint32_t PSELMOSI ; /*!< Pin select for MOSI. */ 00559 __IO uint32_t PSELCSN ; /*!< Pin select for CSN. */ 00560 __I uint32_t RESERVED9[7]; 00561 __IO uint32_t RXDPTR ; /*!< RX data pointer. */ 00562 __IO uint32_t MAXRX ; /*!< Maximum number of bytes in the receive buffer. */ 00563 __I uint32_t AMOUNTRX ; /*!< Number of bytes received in last granted transaction. */ 00564 __I uint32_t RESERVED10; 00565 __IO uint32_t TXDPTR ; /*!< TX data pointer. */ 00566 __IO uint32_t MAXTX ; /*!< Maximum number of bytes in the transmit buffer. */ 00567 __I uint32_t AMOUNTTX ; /*!< Number of bytes transmitted in last granted transaction. */ 00568 __I uint32_t RESERVED11; 00569 __IO uint32_t CONFIG ; /*!< Configuration register. */ 00570 __I uint32_t RESERVED12; 00571 __IO uint32_t DEF ; /*!< Default character. */ 00572 __I uint32_t RESERVED13[24]; 00573 __IO uint32_t ORC ; /*!< Over-read character. */ 00574 __I uint32_t RESERVED14[654]; 00575 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00576 } NRF_SPIS_Type; 00577 00578 00579 /* ================================================================================ */ 00580 /* ================ SPIM ================ */ 00581 /* ================================================================================ */ 00582 00583 00584 /** 00585 * @brief SPI master with easyDMA 1. (SPIM) 00586 */ 00587 00588 typedef struct { /*!< SPIM Structure */ 00589 __I uint32_t RESERVED0[4]; 00590 __O uint32_t TASKS_START ; /*!< Start SPI transaction. */ 00591 __O uint32_t TASKS_STOP ; /*!< Stop SPI transaction. */ 00592 __I uint32_t RESERVED1; 00593 __O uint32_t TASKS_SUSPEND ; /*!< Suspend SPI transaction. */ 00594 __O uint32_t TASKS_RESUME ; /*!< Resume SPI transaction. */ 00595 __I uint32_t RESERVED2[56]; 00596 __IO uint32_t EVENTS_STOPPED ; /*!< SPI transaction has stopped. */ 00597 __I uint32_t RESERVED3[2]; 00598 __IO uint32_t EVENTS_ENDRX ; /*!< End of RXD buffer reached. */ 00599 __I uint32_t RESERVED4; 00600 __IO uint32_t EVENTS_END ; /*!< End of RXD buffer and TXD buffer reached. */ 00601 __I uint32_t RESERVED5; 00602 __IO uint32_t EVENTS_ENDTX ; /*!< End of TXD buffer reached. */ 00603 __I uint32_t RESERVED6[10]; 00604 __IO uint32_t EVENTS_STARTED ; /*!< Transaction started. */ 00605 __I uint32_t RESERVED7[44]; 00606 __IO uint32_t SHORTS ; /*!< Shortcuts for SPIM. */ 00607 __I uint32_t RESERVED8[64]; 00608 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00609 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00610 __I uint32_t RESERVED9[125]; 00611 __IO uint32_t ENABLE ; /*!< Enable SPIM. */ 00612 __I uint32_t RESERVED10; 00613 SPIM_PSEL_Type PSEL ; /*!< Pin select configuration. */ 00614 __I uint32_t RESERVED11[4]; 00615 __IO uint32_t FREQUENCY ; /*!< SPI frequency. */ 00616 __I uint32_t RESERVED12[3]; 00617 SPIM_RXD_Type RXD ; /*!< RXD EasyDMA configuration and status. */ 00618 __I uint32_t RESERVED13; 00619 SPIM_TXD_Type TXD ; /*!< TXD EasyDMA configuration and status. */ 00620 __I uint32_t RESERVED14; 00621 __IO uint32_t CONFIG ; /*!< Configuration register. */ 00622 __I uint32_t RESERVED15[26]; 00623 __IO uint32_t ORC ; /*!< Over-read character. */ 00624 __I uint32_t RESERVED16[654]; 00625 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00626 } NRF_SPIM_Type; 00627 00628 00629 /* ================================================================================ */ 00630 /* ================ GPIOTE ================ */ 00631 /* ================================================================================ */ 00632 00633 00634 /** 00635 * @brief GPIO tasks and events. (GPIOTE) 00636 */ 00637 00638 typedef struct { /*!< GPIOTE Structure */ 00639 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */ 00640 __I uint32_t RESERVED0[60]; 00641 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */ 00642 __I uint32_t RESERVED1[27]; 00643 __IO uint32_t EVENTS_PORT ; /*!< Event generated from multiple pins. */ 00644 __I uint32_t RESERVED2[97]; 00645 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00646 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00647 __I uint32_t RESERVED3[129]; 00648 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */ 00649 __I uint32_t RESERVED4[695]; 00650 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00651 } NRF_GPIOTE_Type; 00652 00653 00654 /* ================================================================================ */ 00655 /* ================ ADC ================ */ 00656 /* ================================================================================ */ 00657 00658 00659 /** 00660 * @brief Analog to digital converter. (ADC) 00661 */ 00662 00663 typedef struct { /*!< ADC Structure */ 00664 __O uint32_t TASKS_START ; /*!< Start an ADC conversion. */ 00665 __O uint32_t TASKS_STOP ; /*!< Stop ADC. */ 00666 __I uint32_t RESERVED0[62]; 00667 __IO uint32_t EVENTS_END ; /*!< ADC conversion complete. */ 00668 __I uint32_t RESERVED1[128]; 00669 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00670 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00671 __I uint32_t RESERVED2[61]; 00672 __I uint32_t BUSY ; /*!< ADC busy register. */ 00673 __I uint32_t RESERVED3[63]; 00674 __IO uint32_t ENABLE ; /*!< ADC enable. */ 00675 __IO uint32_t CONFIG ; /*!< ADC configuration register. */ 00676 __I uint32_t RESULT ; /*!< Result of ADC conversion. */ 00677 __I uint32_t RESERVED4[700]; 00678 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00679 } NRF_ADC_Type; 00680 00681 00682 /* ================================================================================ */ 00683 /* ================ TIMER ================ */ 00684 /* ================================================================================ */ 00685 00686 00687 /** 00688 * @brief Timer 0. (TIMER) 00689 */ 00690 00691 typedef struct { /*!< TIMER Structure */ 00692 __O uint32_t TASKS_START ; /*!< Start Timer. */ 00693 __O uint32_t TASKS_STOP ; /*!< Stop Timer. */ 00694 __O uint32_t TASKS_COUNT ; /*!< Increment Timer (In counter mode). */ 00695 __O uint32_t TASKS_CLEAR ; /*!< Clear timer. */ 00696 __O uint32_t TASKS_SHUTDOWN ; /*!< Shutdown timer. */ 00697 __I uint32_t RESERVED0[11]; 00698 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */ 00699 __I uint32_t RESERVED1[60]; 00700 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */ 00701 __I uint32_t RESERVED2[44]; 00702 __IO uint32_t SHORTS ; /*!< Shortcuts for Timer. */ 00703 __I uint32_t RESERVED3[64]; 00704 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00705 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00706 __I uint32_t RESERVED4[126]; 00707 __IO uint32_t MODE ; /*!< Timer Mode selection. */ 00708 __IO uint32_t BITMODE ; /*!< Sets timer behaviour. */ 00709 __I uint32_t RESERVED5; 00710 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source 00711 clock frequency is divided by 2^SCALE. */ 00712 __I uint32_t RESERVED6[11]; 00713 __IO uint32_t CC[4]; /*!< Capture/compare registers. */ 00714 __I uint32_t RESERVED7[683]; 00715 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00716 } NRF_TIMER_Type; 00717 00718 00719 /* ================================================================================ */ 00720 /* ================ RTC ================ */ 00721 /* ================================================================================ */ 00722 00723 00724 /** 00725 * @brief Real time counter 0. (RTC) 00726 */ 00727 00728 typedef struct { /*!< RTC Structure */ 00729 __O uint32_t TASKS_START ; /*!< Start RTC Counter. */ 00730 __O uint32_t TASKS_STOP ; /*!< Stop RTC Counter. */ 00731 __O uint32_t TASKS_CLEAR ; /*!< Clear RTC Counter. */ 00732 __O uint32_t TASKS_TRIGOVRFLW ; /*!< Set COUNTER to 0xFFFFFFF0. */ 00733 __I uint32_t RESERVED0[60]; 00734 __IO uint32_t EVENTS_TICK ; /*!< Event on COUNTER increment. */ 00735 __IO uint32_t EVENTS_OVRFLW ; /*!< Event on COUNTER overflow. */ 00736 __I uint32_t RESERVED1[14]; 00737 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */ 00738 __I uint32_t RESERVED2[109]; 00739 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00740 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00741 __I uint32_t RESERVED3[13]; 00742 __IO uint32_t EVTEN ; /*!< Configures event enable routing to PPI for each RTC event. */ 00743 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives 00744 the value of EVTEN. */ 00745 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register 00746 gives the value of EVTEN. */ 00747 __I uint32_t RESERVED4[110]; 00748 __I uint32_t COUNTER ; /*!< Current COUNTER value. */ 00749 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). 00750 Must be written when RTC is STOPed. */ 00751 __I uint32_t RESERVED5[13]; 00752 __IO uint32_t CC[4]; /*!< Capture/compare registers. */ 00753 __I uint32_t RESERVED6[683]; 00754 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00755 } NRF_RTC_Type; 00756 00757 00758 /* ================================================================================ */ 00759 /* ================ TEMP ================ */ 00760 /* ================================================================================ */ 00761 00762 00763 /** 00764 * @brief Temperature Sensor. (TEMP) 00765 */ 00766 00767 typedef struct { /*!< TEMP Structure */ 00768 __O uint32_t TASKS_START ; /*!< Start temperature measurement. */ 00769 __O uint32_t TASKS_STOP ; /*!< Stop temperature measurement. */ 00770 __I uint32_t RESERVED0[62]; 00771 __IO uint32_t EVENTS_DATARDY ; /*!< Temperature measurement complete, data ready event. */ 00772 __I uint32_t RESERVED1[128]; 00773 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00774 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00775 __I uint32_t RESERVED2[127]; 00776 __I int32_t TEMP ; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */ 00777 __I uint32_t RESERVED3[700]; 00778 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00779 } NRF_TEMP_Type; 00780 00781 00782 /* ================================================================================ */ 00783 /* ================ RNG ================ */ 00784 /* ================================================================================ */ 00785 00786 00787 /** 00788 * @brief Random Number Generator. (RNG) 00789 */ 00790 00791 typedef struct { /*!< RNG Structure */ 00792 __O uint32_t TASKS_START ; /*!< Start the random number generator. */ 00793 __O uint32_t TASKS_STOP ; /*!< Stop the random number generator. */ 00794 __I uint32_t RESERVED0[62]; 00795 __IO uint32_t EVENTS_VALRDY ; /*!< New random number generated and written to VALUE register. */ 00796 __I uint32_t RESERVED1[63]; 00797 __IO uint32_t SHORTS ; /*!< Shortcuts for the RNG. */ 00798 __I uint32_t RESERVED2[64]; 00799 __IO uint32_t INTENSET ; /*!< Interrupt enable set register */ 00800 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register */ 00801 __I uint32_t RESERVED3[126]; 00802 __IO uint32_t CONFIG ; /*!< Configuration register. */ 00803 __I uint32_t VALUE ; /*!< RNG random number. */ 00804 __I uint32_t RESERVED4[700]; 00805 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00806 } NRF_RNG_Type; 00807 00808 00809 /* ================================================================================ */ 00810 /* ================ ECB ================ */ 00811 /* ================================================================================ */ 00812 00813 00814 /** 00815 * @brief AES ECB Mode Encryption. (ECB) 00816 */ 00817 00818 typedef struct { /*!< ECB Structure */ 00819 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this 00820 will not initiate a new encryption and the ERRORECB event will 00821 be triggered. */ 00822 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running, 00823 this will will trigger the ERRORECB event. */ 00824 __I uint32_t RESERVED0[62]; 00825 __IO uint32_t EVENTS_ENDECB ; /*!< ECB block encrypt complete. */ 00826 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an 00827 error. */ 00828 __I uint32_t RESERVED1[127]; 00829 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00830 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00831 __I uint32_t RESERVED2[126]; 00832 __IO uint32_t ECBDATAPTR ; /*!< ECB block encrypt memory pointer. */ 00833 __I uint32_t RESERVED3[701]; 00834 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00835 } NRF_ECB_Type; 00836 00837 00838 /* ================================================================================ */ 00839 /* ================ AAR ================ */ 00840 /* ================================================================================ */ 00841 00842 00843 /** 00844 * @brief Accelerated Address Resolver. (AAR) 00845 */ 00846 00847 typedef struct { /*!< AAR Structure */ 00848 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK 00849 data structure. */ 00850 __I uint32_t RESERVED0; 00851 __O uint32_t TASKS_STOP ; /*!< Stop resolving addresses. */ 00852 __I uint32_t RESERVED1[61]; 00853 __IO uint32_t EVENTS_END ; /*!< Address resolution procedure completed. */ 00854 __IO uint32_t EVENTS_RESOLVED ; /*!< Address resolved. */ 00855 __IO uint32_t EVENTS_NOTRESOLVED ; /*!< Address not resolved. */ 00856 __I uint32_t RESERVED2[126]; 00857 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00858 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00859 __I uint32_t RESERVED3[61]; 00860 __I uint32_t STATUS ; /*!< Resolution status. */ 00861 __I uint32_t RESERVED4[63]; 00862 __IO uint32_t ENABLE ; /*!< Enable AAR. */ 00863 __IO uint32_t NIRK ; /*!< Number of Identity root Keys in the IRK data structure. */ 00864 __IO uint32_t IRKPTR ; /*!< Pointer to the IRK data structure. */ 00865 __I uint32_t RESERVED5; 00866 __IO uint32_t ADDRPTR ; /*!< Pointer to the resolvable address (6 bytes). */ 00867 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage 00868 during resolution. A minimum of 3 bytes must be reserved. */ 00869 __I uint32_t RESERVED6[697]; 00870 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00871 } NRF_AAR_Type; 00872 00873 00874 /* ================================================================================ */ 00875 /* ================ CCM ================ */ 00876 /* ================================================================================ */ 00877 00878 00879 /** 00880 * @brief AES CCM Mode Encryption. (CCM) 00881 */ 00882 00883 typedef struct { /*!< CCM Structure */ 00884 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by 00885 itself when completed. */ 00886 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when 00887 completed. */ 00888 __O uint32_t TASKS_STOP ; /*!< Stop encrypt/decrypt. */ 00889 __I uint32_t RESERVED0[61]; 00890 __IO uint32_t EVENTS_ENDKSGEN ; /*!< Keystream generation completed. */ 00891 __IO uint32_t EVENTS_ENDCRYPT ; /*!< Encrypt/decrypt completed. */ 00892 __IO uint32_t EVENTS_ERROR ; /*!< Error happened. */ 00893 __I uint32_t RESERVED1[61]; 00894 __IO uint32_t SHORTS ; /*!< Shortcuts for the CCM. */ 00895 __I uint32_t RESERVED2[64]; 00896 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00897 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00898 __I uint32_t RESERVED3[61]; 00899 __I uint32_t MICSTATUS ; /*!< CCM RX MIC check result. */ 00900 __I uint32_t RESERVED4[63]; 00901 __IO uint32_t ENABLE ; /*!< CCM enable. */ 00902 __IO uint32_t MODE ; /*!< Operation mode. */ 00903 __IO uint32_t CNFPTR ; /*!< Pointer to a data structure holding AES key and NONCE vector. */ 00904 __IO uint32_t INPTR ; /*!< Pointer to the input packet. */ 00905 __IO uint32_t OUTPTR ; /*!< Pointer to the output packet. */ 00906 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage 00907 during resolution. A minimum of 43 bytes must be reserved. */ 00908 __I uint32_t RESERVED5[697]; 00909 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00910 } NRF_CCM_Type; 00911 00912 00913 /* ================================================================================ */ 00914 /* ================ WDT ================ */ 00915 /* ================================================================================ */ 00916 00917 00918 /** 00919 * @brief Watchdog Timer. (WDT) 00920 */ 00921 00922 typedef struct { /*!< WDT Structure */ 00923 __O uint32_t TASKS_START ; /*!< Start the watchdog. */ 00924 __I uint32_t RESERVED0[63]; 00925 __IO uint32_t EVENTS_TIMEOUT ; /*!< Watchdog timeout. */ 00926 __I uint32_t RESERVED1[128]; 00927 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00928 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00929 __I uint32_t RESERVED2[61]; 00930 __I uint32_t RUNSTATUS ; /*!< Watchdog running status. */ 00931 __I uint32_t REQSTATUS ; /*!< Request status. */ 00932 __I uint32_t RESERVED3[63]; 00933 __IO uint32_t CRV ; /*!< Counter reload value in number of 32kiHz clock cycles. */ 00934 __IO uint32_t RREN ; /*!< Reload request enable. */ 00935 __IO uint32_t CONFIG ; /*!< Configuration register. */ 00936 __I uint32_t RESERVED4[60]; 00937 __O uint32_t RR[8]; /*!< Reload requests registers. */ 00938 __I uint32_t RESERVED5[631]; 00939 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00940 } NRF_WDT_Type; 00941 00942 00943 /* ================================================================================ */ 00944 /* ================ QDEC ================ */ 00945 /* ================================================================================ */ 00946 00947 00948 /** 00949 * @brief Rotary decoder. (QDEC) 00950 */ 00951 00952 typedef struct { /*!< QDEC Structure */ 00953 __O uint32_t TASKS_START ; /*!< Start the quadrature decoder. */ 00954 __O uint32_t TASKS_STOP ; /*!< Stop the quadrature decoder. */ 00955 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers, 00956 and clears the ACC registers. */ 00957 __I uint32_t RESERVED0[61]; 00958 __IO uint32_t EVENTS_SAMPLERDY ; /*!< A new sample is written to the sample register. */ 00959 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and 00960 ACC register different than zero. */ 00961 __IO uint32_t EVENTS_ACCOF ; /*!< ACC or ACCDBL register overflow. */ 00962 __I uint32_t RESERVED1[61]; 00963 __IO uint32_t SHORTS ; /*!< Shortcuts for the QDEC. */ 00964 __I uint32_t RESERVED2[64]; 00965 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00966 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00967 __I uint32_t RESERVED3[125]; 00968 __IO uint32_t ENABLE ; /*!< Enable the QDEC. */ 00969 __IO uint32_t LEDPOL ; /*!< LED output pin polarity. */ 00970 __IO uint32_t SAMPLEPER ; /*!< Sample period. */ 00971 __I int32_t SAMPLE ; /*!< Motion sample value. */ 00972 __IO uint32_t REPORTPER ; /*!< Number of samples to generate an EVENT_REPORTRDY. */ 00973 __I int32_t ACC ; /*!< Accumulated valid transitions register. */ 00974 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC 00975 task. */ 00976 __IO uint32_t PSELLED ; /*!< Pin select for LED output. */ 00977 __IO uint32_t PSELA ; /*!< Pin select for phase A input. */ 00978 __IO uint32_t PSELB ; /*!< Pin select for phase B input. */ 00979 __IO uint32_t DBFEN ; /*!< Enable debouncer input filters. */ 00980 __I uint32_t RESERVED4[5]; 00981 __IO uint32_t LEDPRE ; /*!< Time LED is switched ON before the sample. */ 00982 __I uint32_t ACCDBL ; /*!< Accumulated double (error) transitions register. */ 00983 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC 00984 task. */ 00985 __I uint32_t RESERVED5[684]; 00986 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00987 } NRF_QDEC_Type; 00988 00989 00990 /* ================================================================================ */ 00991 /* ================ LPCOMP ================ */ 00992 /* ================================================================================ */ 00993 00994 00995 /** 00996 * @brief Low power comparator. (LPCOMP) 00997 */ 00998 00999 typedef struct { /*!< LPCOMP Structure */ 01000 __O uint32_t TASKS_START ; /*!< Start the comparator. */ 01001 __O uint32_t TASKS_STOP ; /*!< Stop the comparator. */ 01002 __O uint32_t TASKS_SAMPLE ; /*!< Sample comparator value. */ 01003 __I uint32_t RESERVED0[61]; 01004 __IO uint32_t EVENTS_READY ; /*!< LPCOMP is ready and output is valid. */ 01005 __IO uint32_t EVENTS_DOWN ; /*!< Input voltage crossed the threshold going down. */ 01006 __IO uint32_t EVENTS_UP ; /*!< Input voltage crossed the threshold going up. */ 01007 __IO uint32_t EVENTS_CROSS ; /*!< Input voltage crossed the threshold in any direction. */ 01008 __I uint32_t RESERVED1[60]; 01009 __IO uint32_t SHORTS ; /*!< Shortcuts for the LPCOMP. */ 01010 __I uint32_t RESERVED2[64]; 01011 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 01012 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 01013 __I uint32_t RESERVED3[61]; 01014 __I uint32_t RESULT ; /*!< Result of last compare. */ 01015 __I uint32_t RESERVED4[63]; 01016 __IO uint32_t ENABLE ; /*!< Enable the LPCOMP. */ 01017 __IO uint32_t PSEL ; /*!< Input pin select. */ 01018 __IO uint32_t REFSEL ; /*!< Reference select. */ 01019 __IO uint32_t EXTREFSEL ; /*!< External reference select. */ 01020 __I uint32_t RESERVED5[4]; 01021 __IO uint32_t ANADETECT ; /*!< Analog detect configuration. */ 01022 __I uint32_t RESERVED6[694]; 01023 __IO uint32_t POWER ; /*!< Peripheral power control. */ 01024 } NRF_LPCOMP_Type; 01025 01026 01027 /* ================================================================================ */ 01028 /* ================ SWI ================ */ 01029 /* ================================================================================ */ 01030 01031 01032 /** 01033 * @brief SW Interrupts. (SWI) 01034 */ 01035 01036 typedef struct { /*!< SWI Structure */ 01037 __I uint32_t UNUSED ; /*!< Unused. */ 01038 } NRF_SWI_Type; 01039 01040 01041 /* ================================================================================ */ 01042 /* ================ NVMC ================ */ 01043 /* ================================================================================ */ 01044 01045 01046 /** 01047 * @brief Non Volatile Memory Controller. (NVMC) 01048 */ 01049 01050 typedef struct { /*!< NVMC Structure */ 01051 __I uint32_t RESERVED0[256]; 01052 __I uint32_t READY ; /*!< Ready flag. */ 01053 __I uint32_t RESERVED1[64]; 01054 __IO uint32_t CONFIG ; /*!< Configuration register. */ 01055 01056 union { 01057 __IO uint32_t ERASEPCR1 ; /*!< Register for erasing a non-protected non-volatile memory page. */ 01058 __IO uint32_t ERASEPAGE ; /*!< Register for erasing a non-protected non-volatile memory page. */ 01059 }; 01060 __IO uint32_t ERASEALL ; /*!< Register for erasing all non-volatile user memory. */ 01061 __IO uint32_t ERASEPCR0 ; /*!< Register for erasing a protected non-volatile memory page. */ 01062 __IO uint32_t ERASEUICR ; /*!< Register for start erasing User Information Congfiguration Registers. */ 01063 } NRF_NVMC_Type; 01064 01065 01066 /* ================================================================================ */ 01067 /* ================ PPI ================ */ 01068 /* ================================================================================ */ 01069 01070 01071 /** 01072 * @brief PPI controller. (PPI) 01073 */ 01074 01075 typedef struct { /*!< PPI Structure */ 01076 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */ 01077 __I uint32_t RESERVED0[312]; 01078 __IO uint32_t CHEN ; /*!< Channel enable. */ 01079 __IO uint32_t CHENSET ; /*!< Channel enable set. */ 01080 __IO uint32_t CHENCLR ; /*!< Channel enable clear. */ 01081 __I uint32_t RESERVED1; 01082 PPI_CH_Type CH[16]; /*!< PPI Channel. */ 01083 __I uint32_t RESERVED2[156]; 01084 __IO uint32_t CHG[4]; /*!< Channel group configuration. */ 01085 } NRF_PPI_Type; 01086 01087 01088 /* ================================================================================ */ 01089 /* ================ FICR ================ */ 01090 /* ================================================================================ */ 01091 01092 01093 /** 01094 * @brief Factory Information Configuration. (FICR) 01095 */ 01096 01097 typedef struct { /*!< FICR Structure */ 01098 __I uint32_t RESERVED0[4]; 01099 __I uint32_t CODEPAGESIZE ; /*!< Code memory page size in bytes. */ 01100 __I uint32_t CODESIZE ; /*!< Code memory size in pages. */ 01101 __I uint32_t RESERVED1[4]; 01102 __I uint32_t CLENR0 ; /*!< Length of code region 0 in bytes. */ 01103 __I uint32_t PPFC ; /*!< Pre-programmed factory code present. */ 01104 __I uint32_t RESERVED2; 01105 __I uint32_t NUMRAMBLOCK ; /*!< Number of individualy controllable RAM blocks. */ 01106 01107 union { 01108 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is 01109 kept for backward compatinility purposes. Use SIZERAMBLOCKS 01110 instead. */ 01111 __I uint32_t SIZERAMBLOCKS ; /*!< Size of RAM blocks in bytes. */ 01112 }; 01113 __I uint32_t RESERVED3[5]; 01114 __I uint32_t CONFIGID ; /*!< Configuration identifier. */ 01115 __I uint32_t DEVICEID[2]; /*!< Device identifier. */ 01116 __I uint32_t RESERVED4[6]; 01117 __I uint32_t ER[4]; /*!< Encryption root. */ 01118 __I uint32_t IR[4]; /*!< Identity root. */ 01119 __I uint32_t DEVICEADDRTYPE ; /*!< Device address type. */ 01120 __I uint32_t DEVICEADDR[2]; /*!< Device address. */ 01121 __I uint32_t OVERRIDEEN ; /*!< Radio calibration override enable. */ 01122 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit 01123 mode. */ 01124 __I uint32_t RESERVED5[10]; 01125 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit 01126 mode. */ 01127 } NRF_FICR_Type; 01128 01129 01130 /* ================================================================================ */ 01131 /* ================ UICR ================ */ 01132 /* ================================================================================ */ 01133 01134 01135 /** 01136 * @brief User Information Configuration. (UICR) 01137 */ 01138 01139 typedef struct { /*!< UICR Structure */ 01140 __IO uint32_t CLENR0 ; /*!< Length of code region 0. */ 01141 __IO uint32_t RBPCONF ; /*!< Readback protection configuration. */ 01142 __IO uint32_t XTALFREQ ; /*!< Reset value for CLOCK XTALFREQ register. */ 01143 __I uint32_t RESERVED0; 01144 __I uint32_t FWID ; /*!< Firmware ID. */ 01145 01146 union { 01147 __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */ 01148 __IO uint32_t BOOTLOADERADDR ; /*!< Bootloader start address. */ 01149 }; 01150 __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */ 01151 __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */ 01152 } NRF_UICR_Type; 01153 01154 01155 /* ================================================================================ */ 01156 /* ================ GPIO ================ */ 01157 /* ================================================================================ */ 01158 01159 01160 /** 01161 * @brief General purpose input and output. (GPIO) 01162 */ 01163 01164 typedef struct { /*!< GPIO Structure */ 01165 __I uint32_t RESERVED0[321]; 01166 __IO uint32_t OUT ; /*!< Write GPIO port. */ 01167 __IO uint32_t OUTSET ; /*!< Set individual bits in GPIO port. */ 01168 __IO uint32_t OUTCLR ; /*!< Clear individual bits in GPIO port. */ 01169 __I uint32_t IN ; /*!< Read GPIO port. */ 01170 __IO uint32_t DIR ; /*!< Direction of GPIO pins. */ 01171 __IO uint32_t DIRSET ; /*!< DIR set register. */ 01172 __IO uint32_t DIRCLR ; /*!< DIR clear register. */ 01173 __I uint32_t RESERVED1[120]; 01174 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */ 01175 } NRF_GPIO_Type; 01176 01177 01178 /* -------------------- End of section using anonymous unions ------------------- */ 01179 #if defined(__CC_ARM) 01180 #pragma pop 01181 #elif defined(__ICCARM__) 01182 /* leave anonymous unions enabled */ 01183 #elif defined(__GNUC__) 01184 /* anonymous unions are enabled by default */ 01185 #elif defined(__TMS470__) 01186 /* anonymous unions are enabled by default */ 01187 #elif defined(__TASKING__) 01188 #pragma warning restore 01189 #else 01190 #warning Not supported compiler type 01191 #endif 01192 01193 01194 01195 01196 /* ================================================================================ */ 01197 /* ================ Peripheral memory map ================ */ 01198 /* ================================================================================ */ 01199 01200 #define NRF_POWER_BASE 0x40000000UL 01201 #define NRF_CLOCK_BASE 0x40000000UL 01202 #define NRF_MPU_BASE 0x40000000UL 01203 #define NRF_PU_BASE 0x40000000UL 01204 #define NRF_AMLI_BASE 0x40000000UL 01205 #define NRF_RADIO_BASE 0x40001000UL 01206 #define NRF_UART0_BASE 0x40002000UL 01207 #define NRF_SPI0_BASE 0x40003000UL 01208 #define NRF_TWI0_BASE 0x40003000UL 01209 #define NRF_SPI1_BASE 0x40004000UL 01210 #define NRF_TWI1_BASE 0x40004000UL 01211 #define NRF_SPIS1_BASE 0x40004000UL 01212 #define NRF_SPIM1_BASE 0x40004000UL 01213 #define NRF_GPIOTE_BASE 0x40006000UL 01214 #define NRF_ADC_BASE 0x40007000UL 01215 #define NRF_TIMER0_BASE 0x40008000UL 01216 #define NRF_TIMER1_BASE 0x40009000UL 01217 #define NRF_TIMER2_BASE 0x4000A000UL 01218 #define NRF_RTC0_BASE 0x4000B000UL 01219 #define NRF_TEMP_BASE 0x4000C000UL 01220 #define NRF_RNG_BASE 0x4000D000UL 01221 #define NRF_ECB_BASE 0x4000E000UL 01222 #define NRF_AAR_BASE 0x4000F000UL 01223 #define NRF_CCM_BASE 0x4000F000UL 01224 #define NRF_WDT_BASE 0x40010000UL 01225 #define NRF_RTC1_BASE 0x40011000UL 01226 #define NRF_QDEC_BASE 0x40012000UL 01227 #define NRF_LPCOMP_BASE 0x40013000UL 01228 #define NRF_SWI_BASE 0x40014000UL 01229 #define NRF_NVMC_BASE 0x4001E000UL 01230 #define NRF_PPI_BASE 0x4001F000UL 01231 #define NRF_FICR_BASE 0x10000000UL 01232 #define NRF_UICR_BASE 0x10001000UL 01233 #define NRF_GPIO_BASE 0x50000000UL 01234 01235 01236 /* ================================================================================ */ 01237 /* ================ Peripheral declaration ================ */ 01238 /* ================================================================================ */ 01239 01240 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE) 01241 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE) 01242 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE) 01243 #define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE) 01244 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE) 01245 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE) 01246 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE) 01247 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE) 01248 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE) 01249 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) 01250 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) 01251 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE) 01252 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE) 01253 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE) 01254 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE) 01255 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE) 01256 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE) 01257 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE) 01258 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE) 01259 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE) 01260 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE) 01261 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE) 01262 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE) 01263 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE) 01264 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE) 01265 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE) 01266 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE) 01267 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE) 01268 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE) 01269 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE) 01270 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE) 01271 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE) 01272 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE) 01273 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE) 01274 01275 01276 /** @} */ /* End of group Device_Peripheral_Registers */ 01277 /** @} */ /* End of group nrf51 */ 01278 /** @} */ /* End of group Nordic Semiconductor */ 01279 01280 #ifdef __cplusplus 01281 } 01282 #endif 01283 01284 01285 #endif /* nrf51_H */
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