Doug Anson / mbedEndpointNetwork_6LowPAN

6LowPAN mesh-based network support for mbedConnectorInterface. The Atmel-based mbed 6LowPAN shield is the assumed network hardware.

Dependencies:   libnsdl Nanostack_lib

mesh_nework/AtmelRFDriverLib/driverAtmelRFInterface.c@13:17948fd0fe32, 2015-11-03 (annotated)

Committer:
ansond
Date:
Tue Nov 03 17:07:01 2015 +0000
Revision:
13:17948fd0fe32
Parent:
0:2a5a48a8b4d4 
updated buffer sizes, updated

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ansond 0:2a5a48a8b4d4 1 /*
ansond 0:2a5a48a8b4d4 2 * driverAtmelRFInterface.c
ansond 0:2a5a48a8b4d4 3 *
ansond 0:2a5a48a8b4d4 4 * Created on: 14 July 2014
ansond 0:2a5a48a8b4d4 5 * Author: mBed Team
ansond 0:2a5a48a8b4d4 6 */
ansond 0:2a5a48a8b4d4 7
ansond 0:2a5a48a8b4d4 8 #include "arm_hal_interrupt.h"
ansond 0:2a5a48a8b4d4 9 #include "arm_hal_phy.h"
ansond 0:2a5a48a8b4d4 10 #include "driverRFPhy.h"
ansond 0:2a5a48a8b4d4 11 #include "driverAtmelRFInterface.h"
ansond 0:2a5a48a8b4d4 12 #include "low_level_RF.h"
ansond 0:2a5a48a8b4d4 13
ansond 0:2a5a48a8b4d4 14 #include <stdio.h>
ansond 0:2a5a48a8b4d4 15
ansond 0:2a5a48a8b4d4 16 void (*app_rf_settings_cb)(void) = 0;
ansond 0:2a5a48a8b4d4 17 static uint8_t rf_part_num = 0;
ansond 0:2a5a48a8b4d4 18 static uint8_t rf_rx_lqi;
ansond 0:2a5a48a8b4d4 19 static int8_t rf_rx_rssi;
ansond 0:2a5a48a8b4d4 20 /*TODO: RSSI Base value setting*/
ansond 0:2a5a48a8b4d4 21 static int8_t rf_rssi_base_val = -91;
ansond 0:2a5a48a8b4d4 22 static uint8_t phy_timers_enabled = 0;
ansond 0:2a5a48a8b4d4 23
ansond 0:2a5a48a8b4d4 24 /*
ansond 0:2a5a48a8b4d4 25 * \brief Delay function for RF interface.
ansond 0:2a5a48a8b4d4 26 *
ansond 0:2a5a48a8b4d4 27 * \param ticks Number of delay ticks
ansond 0:2a5a48a8b4d4 28 *
ansond 0:2a5a48a8b4d4 29 * \return none
ansond 0:2a5a48a8b4d4 30 */
ansond 0:2a5a48a8b4d4 31 void rf_if_delay_function(uint16_t ticks)
ansond 0:2a5a48a8b4d4 32 {
ansond 0:2a5a48a8b4d4 33 while(ticks--);
ansond 0:2a5a48a8b4d4 34 }
ansond 0:2a5a48a8b4d4 35
ansond 0:2a5a48a8b4d4 36 /*
ansond 0:2a5a48a8b4d4 37 * \brief Function initialises the RF timer for ACK wait and calibration.
ansond 0:2a5a48a8b4d4 38 *
ansond 0:2a5a48a8b4d4 39 * \param none
ansond 0:2a5a48a8b4d4 40 *
ansond 0:2a5a48a8b4d4 41 * \return none
ansond 0:2a5a48a8b4d4 42 */
ansond 0:2a5a48a8b4d4 43 void rf_if_timer_init(void)
ansond 0:2a5a48a8b4d4 44 {
ansond 0:2a5a48a8b4d4 45 /* TODO */
ansond 0:2a5a48a8b4d4 46 }
ansond 0:2a5a48a8b4d4 47
ansond 0:2a5a48a8b4d4 48 /*
ansond 0:2a5a48a8b4d4 49 * \brief Function starts the ACK wait timeout.
ansond 0:2a5a48a8b4d4 50 *
ansond 0:2a5a48a8b4d4 51 * \param slots Given slots, resolution 50us
ansond 0:2a5a48a8b4d4 52 *
ansond 0:2a5a48a8b4d4 53 * \return none
ansond 0:2a5a48a8b4d4 54 */
ansond 0:2a5a48a8b4d4 55 void rf_if_ack_wait_timer_start(uint16_t slots)
ansond 0:2a5a48a8b4d4 56 {
ansond 0:2a5a48a8b4d4 57 /* TODO */
ansond 0:2a5a48a8b4d4 58 }
ansond 0:2a5a48a8b4d4 59
ansond 0:2a5a48a8b4d4 60 /*
ansond 0:2a5a48a8b4d4 61 * \brief Function starts the calibration interval.
ansond 0:2a5a48a8b4d4 62 *
ansond 0:2a5a48a8b4d4 63 * \param slots Given slots, resolution 50us
ansond 0:2a5a48a8b4d4 64 *
ansond 0:2a5a48a8b4d4 65 * \return none
ansond 0:2a5a48a8b4d4 66 */
ansond 0:2a5a48a8b4d4 67 void rf_if_calibration_timer_start(uint32_t slots)
ansond 0:2a5a48a8b4d4 68 {
ansond 0:2a5a48a8b4d4 69 /* TODO */
ansond 0:2a5a48a8b4d4 70 }
ansond 0:2a5a48a8b4d4 71
ansond 0:2a5a48a8b4d4 72 /*
ansond 0:2a5a48a8b4d4 73 * \brief Function stops the ACK wait timeout.
ansond 0:2a5a48a8b4d4 74 *
ansond 0:2a5a48a8b4d4 75 * \param none
ansond 0:2a5a48a8b4d4 76 *
ansond 0:2a5a48a8b4d4 77 * \return none
ansond 0:2a5a48a8b4d4 78 */
ansond 0:2a5a48a8b4d4 79 void rf_if_ack_wait_timer_stop(void)
ansond 0:2a5a48a8b4d4 80 {
ansond 0:2a5a48a8b4d4 81 phy_timers_enabled &= ~PHY_ACK_WAIT_TIMER;
ansond 0:2a5a48a8b4d4 82 }
ansond 0:2a5a48a8b4d4 83
ansond 0:2a5a48a8b4d4 84 /*
ansond 0:2a5a48a8b4d4 85 * \brief Function is a call back for ACK wait timeout.
ansond 0:2a5a48a8b4d4 86 *
ansond 0:2a5a48a8b4d4 87 * \param none
ansond 0:2a5a48a8b4d4 88 *
ansond 0:2a5a48a8b4d4 89 * \return none
ansond 0:2a5a48a8b4d4 90 */
ansond 0:2a5a48a8b4d4 91 void rf_if_ack_wait_timer_interrupt(void)
ansond 0:2a5a48a8b4d4 92 {
ansond 0:2a5a48a8b4d4 93 /* TODO */
ansond 0:2a5a48a8b4d4 94 }
ansond 0:2a5a48a8b4d4 95
ansond 0:2a5a48a8b4d4 96 /*
ansond 0:2a5a48a8b4d4 97 * \brief Function is a call back for calibration interval timer.
ansond 0:2a5a48a8b4d4 98 *
ansond 0:2a5a48a8b4d4 99 * \param none
ansond 0:2a5a48a8b4d4 100 *
ansond 0:2a5a48a8b4d4 101 * \return none
ansond 0:2a5a48a8b4d4 102 */
ansond 0:2a5a48a8b4d4 103 void rf_if_calibration_timer_interrupt(void)
ansond 0:2a5a48a8b4d4 104 {
ansond 0:2a5a48a8b4d4 105 /* TODO */
ansond 0:2a5a48a8b4d4 106 }
ansond 0:2a5a48a8b4d4 107
ansond 0:2a5a48a8b4d4 108 /*
ansond 0:2a5a48a8b4d4 109 * \brief Function sets SLP_TR pin high in RF interface.
ansond 0:2a5a48a8b4d4 110 *
ansond 0:2a5a48a8b4d4 111 * \param none
ansond 0:2a5a48a8b4d4 112 *
ansond 0:2a5a48a8b4d4 113 * \return none
ansond 0:2a5a48a8b4d4 114 */
ansond 0:2a5a48a8b4d4 115 void rf_if_slp_tr_pin_high(void)
ansond 0:2a5a48a8b4d4 116 {
ansond 0:2a5a48a8b4d4 117 RF_SLP_TR_Set(1);
ansond 0:2a5a48a8b4d4 118 }
ansond 0:2a5a48a8b4d4 119
ansond 0:2a5a48a8b4d4 120 /*
ansond 0:2a5a48a8b4d4 121 * \brief Function sets SLP_TR pin low in RF interface.
ansond 0:2a5a48a8b4d4 122 *
ansond 0:2a5a48a8b4d4 123 * \param none
ansond 0:2a5a48a8b4d4 124 *
ansond 0:2a5a48a8b4d4 125 * \return none
ansond 0:2a5a48a8b4d4 126 */
ansond 0:2a5a48a8b4d4 127 void rf_if_slp_tr_pin_low(void)
ansond 0:2a5a48a8b4d4 128 {
ansond 0:2a5a48a8b4d4 129 RF_SLP_TR_Set(0);
ansond 0:2a5a48a8b4d4 130 }
ansond 0:2a5a48a8b4d4 131
ansond 0:2a5a48a8b4d4 132 /*
ansond 0:2a5a48a8b4d4 133 * \brief Function returns peripheral ID for SPI interface.
ansond 0:2a5a48a8b4d4 134 *
ansond 0:2a5a48a8b4d4 135 * \param none
ansond 0:2a5a48a8b4d4 136 *
ansond 0:2a5a48a8b4d4 137 * \return peripheral ID
ansond 0:2a5a48a8b4d4 138 */
ansond 0:2a5a48a8b4d4 139 uint8_t rf_if_get_rf_spi_periph(uint8_t spi_interface)
ansond 0:2a5a48a8b4d4 140 {
ansond 0:2a5a48a8b4d4 141 uint8_t ret_val = 19 + spi_interface;
ansond 0:2a5a48a8b4d4 142 return ret_val;
ansond 0:2a5a48a8b4d4 143 }
ansond 0:2a5a48a8b4d4 144
ansond 0:2a5a48a8b4d4 145 /*
ansond 0:2a5a48a8b4d4 146 * \brief Function returns interrupt number for I/O port.
ansond 0:2a5a48a8b4d4 147 *
ansond 0:2a5a48a8b4d4 148 * \param none
ansond 0:2a5a48a8b4d4 149 *
ansond 0:2a5a48a8b4d4 150 * \return interrupt number
ansond 0:2a5a48a8b4d4 151 */
ansond 0:2a5a48a8b4d4 152 uint8_t rf_if_get_rf_irq_number(uint8_t port)
ansond 0:2a5a48a8b4d4 153 {
ansond 0:2a5a48a8b4d4 154 /* not needed in mBed */
ansond 0:2a5a48a8b4d4 155 return 0x00;
ansond 0:2a5a48a8b4d4 156 }
ansond 0:2a5a48a8b4d4 157
ansond 0:2a5a48a8b4d4 158
ansond 0:2a5a48a8b4d4 159 /*
ansond 0:2a5a48a8b4d4 160 * \brief Function enables RF irq pin interrupts in RF interface.
ansond 0:2a5a48a8b4d4 161 *
ansond 0:2a5a48a8b4d4 162 * \param none
ansond 0:2a5a48a8b4d4 163 *
ansond 0:2a5a48a8b4d4 164 * \return none
ansond 0:2a5a48a8b4d4 165 */
ansond 0:2a5a48a8b4d4 166 void rf_if_enable_irq(void)
ansond 0:2a5a48a8b4d4 167 {
ansond 0:2a5a48a8b4d4 168 /* not needed in mBed */
ansond 0:2a5a48a8b4d4 169 }
ansond 0:2a5a48a8b4d4 170
ansond 0:2a5a48a8b4d4 171
ansond 0:2a5a48a8b4d4 172 /*
ansond 0:2a5a48a8b4d4 173 * \brief Function initialises RF interrupt pin in RF interface.
ansond 0:2a5a48a8b4d4 174 *
ansond 0:2a5a48a8b4d4 175 * \param none
ansond 0:2a5a48a8b4d4 176 *
ansond 0:2a5a48a8b4d4 177 * \return none
ansond 0:2a5a48a8b4d4 178 */
ansond 0:2a5a48a8b4d4 179 void rf_if_init_irq_delete(void)
ansond 0:2a5a48a8b4d4 180 {
ansond 0:2a5a48a8b4d4 181 RF_IRQ_Init();
ansond 0:2a5a48a8b4d4 182 }
ansond 0:2a5a48a8b4d4 183
ansond 0:2a5a48a8b4d4 184 /*
ansond 0:2a5a48a8b4d4 185 * \brief Function initialises the SPI interface for RF.
ansond 0:2a5a48a8b4d4 186 *
ansond 0:2a5a48a8b4d4 187 * \param none
ansond 0:2a5a48a8b4d4 188 *
ansond 0:2a5a48a8b4d4 189 * \return none
ansond 0:2a5a48a8b4d4 190 */
ansond 0:2a5a48a8b4d4 191 void rf_if_spi_init(void)
ansond 0:2a5a48a8b4d4 192 {
ansond 0:2a5a48a8b4d4 193 /* not needed in mBed */
ansond 0:2a5a48a8b4d4 194 }
ansond 0:2a5a48a8b4d4 195
ansond 0:2a5a48a8b4d4 196 /*
ansond 0:2a5a48a8b4d4 197 * \brief Function initialises SLP_TR pin in RF interface.
ansond 0:2a5a48a8b4d4 198 *
ansond 0:2a5a48a8b4d4 199 * \param none
ansond 0:2a5a48a8b4d4 200 *
ansond 0:2a5a48a8b4d4 201 * \return none
ansond 0:2a5a48a8b4d4 202 */
ansond 0:2a5a48a8b4d4 203 void rf_if_init_slp_tr_pin(void)
ansond 0:2a5a48a8b4d4 204 {
ansond 0:2a5a48a8b4d4 205 /*Chip select*/
ansond 0:2a5a48a8b4d4 206 //RF_SLP_TR_Set(0); // moved to reset function
ansond 0:2a5a48a8b4d4 207 }
ansond 0:2a5a48a8b4d4 208
ansond 0:2a5a48a8b4d4 209 /*
ansond 0:2a5a48a8b4d4 210 * \brief Function returns peripheral ID for I/O port.
ansond 0:2a5a48a8b4d4 211 *
ansond 0:2a5a48a8b4d4 212 * \param none
ansond 0:2a5a48a8b4d4 213 *
ansond 0:2a5a48a8b4d4 214 * \return peripheral ID
ansond 0:2a5a48a8b4d4 215 */
ansond 0:2a5a48a8b4d4 216 uint8_t rf_if_get_port_peripheral_id(uint8_t port)
ansond 0:2a5a48a8b4d4 217 {
ansond 0:2a5a48a8b4d4 218 uint8_t ret_val = 9 + port;
ansond 0:2a5a48a8b4d4 219 return ret_val;
ansond 0:2a5a48a8b4d4 220 }
ansond 0:2a5a48a8b4d4 221
ansond 0:2a5a48a8b4d4 222 /*
ansond 0:2a5a48a8b4d4 223 * \brief Function initialises I/O pins for RF interface.
ansond 0:2a5a48a8b4d4 224 *
ansond 0:2a5a48a8b4d4 225 * \param none
ansond 0:2a5a48a8b4d4 226 *
ansond 0:2a5a48a8b4d4 227 * \return peripheral ID
ansond 0:2a5a48a8b4d4 228 */
ansond 0:2a5a48a8b4d4 229 void rf_if_init_spi_pins(void)
ansond 0:2a5a48a8b4d4 230 {
ansond 0:2a5a48a8b4d4 231 /* not needed in mBed */
ansond 0:2a5a48a8b4d4 232 }
ansond 0:2a5a48a8b4d4 233
ansond 0:2a5a48a8b4d4 234 /*
ansond 0:2a5a48a8b4d4 235 * \brief Function reads data from the given RF SRAM address.
ansond 0:2a5a48a8b4d4 236 *
ansond 0:2a5a48a8b4d4 237 * \param ptr Read pointer
ansond 0:2a5a48a8b4d4 238 * \param sram_address Read address in SRAM
ansond 0:2a5a48a8b4d4 239 * \param len Length of the read
ansond 0:2a5a48a8b4d4 240 *
ansond 0:2a5a48a8b4d4 241 * \return none
ansond 0:2a5a48a8b4d4 242 */
ansond 0:2a5a48a8b4d4 243 void rf_if_read_payload(uint8_t *ptr, uint8_t sram_address, uint8_t len)
ansond 0:2a5a48a8b4d4 244 {
ansond 0:2a5a48a8b4d4 245 uint8_t i;
ansond 0:2a5a48a8b4d4 246
ansond 0:2a5a48a8b4d4 247 RF_CS_Set(0);
ansond 0:2a5a48a8b4d4 248 spi_exchange(0x20);
ansond 0:2a5a48a8b4d4 249 spi_exchange(sram_address);
ansond 0:2a5a48a8b4d4 250 for(i=0; i<len; i++)
ansond 0:2a5a48a8b4d4 251 *ptr++ = spi_exchange(0);
ansond 0:2a5a48a8b4d4 252
ansond 0:2a5a48a8b4d4 253 /*Read LQI and RSSI in variable*/
ansond 0:2a5a48a8b4d4 254 rf_rx_lqi = spi_exchange(0);
ansond 0:2a5a48a8b4d4 255 rf_rx_rssi = (rf_rssi_base_val + spi_exchange(0));
ansond 0:2a5a48a8b4d4 256 RF_CS_Set(1);
ansond 0:2a5a48a8b4d4 257 }
ansond 0:2a5a48a8b4d4 258
ansond 0:2a5a48a8b4d4 259 /*
ansond 0:2a5a48a8b4d4 260 * \brief Function polls while the SPI chip select is active.
ansond 0:2a5a48a8b4d4 261 *
ansond 0:2a5a48a8b4d4 262 * \param none
ansond 0:2a5a48a8b4d4 263 *
ansond 0:2a5a48a8b4d4 264 * \return none
ansond 0:2a5a48a8b4d4 265 */
ansond 0:2a5a48a8b4d4 266 void rf_if_spi_poll_chip_select(void)
ansond 0:2a5a48a8b4d4 267 {
ansond 0:2a5a48a8b4d4 268 RF_CS_while_active();
ansond 0:2a5a48a8b4d4 269 }
ansond 0:2a5a48a8b4d4 270
ansond 0:2a5a48a8b4d4 271 void rf_if_set_bit(uint8_t addr, uint8_t bit, uint8_t bit_mask)
ansond 0:2a5a48a8b4d4 272 {
ansond 0:2a5a48a8b4d4 273 uint8_t reg = rf_if_read_register(addr);
ansond 0:2a5a48a8b4d4 274 reg &= ~bit_mask;
ansond 0:2a5a48a8b4d4 275 reg |= bit;
ansond 0:2a5a48a8b4d4 276 rf_if_write_register(addr, reg);
ansond 0:2a5a48a8b4d4 277 }
ansond 0:2a5a48a8b4d4 278
ansond 0:2a5a48a8b4d4 279 /*
ansond 0:2a5a48a8b4d4 280 * \brief Function clears bit(s) in given RF register.
ansond 0:2a5a48a8b4d4 281 *
ansond 0:2a5a48a8b4d4 282 * \param addr Address of the register to clear
ansond 0:2a5a48a8b4d4 283 * \param bit Bit(s) to clear
ansond 0:2a5a48a8b4d4 284 *
ansond 0:2a5a48a8b4d4 285 * \return none
ansond 0:2a5a48a8b4d4 286 */
ansond 0:2a5a48a8b4d4 287 void rf_if_clear_bit(uint8_t addr, uint8_t bit)
ansond 0:2a5a48a8b4d4 288 {
ansond 0:2a5a48a8b4d4 289 uint8_t reg = rf_if_read_register(addr);
ansond 0:2a5a48a8b4d4 290 reg &= ~bit;
ansond 0:2a5a48a8b4d4 291 rf_if_write_register(addr, reg);
ansond 0:2a5a48a8b4d4 292 }
ansond 0:2a5a48a8b4d4 293
ansond 0:2a5a48a8b4d4 294 /*
ansond 0:2a5a48a8b4d4 295 * \brief Function writes register in RF.
ansond 0:2a5a48a8b4d4 296 *
ansond 0:2a5a48a8b4d4 297 * \param addr Address on the RF
ansond 0:2a5a48a8b4d4 298 * \param data Written data
ansond 0:2a5a48a8b4d4 299 *
ansond 0:2a5a48a8b4d4 300 * \return none
ansond 0:2a5a48a8b4d4 301 */
ansond 0:2a5a48a8b4d4 302 void rf_if_write_register(uint8_t addr, uint8_t data)
ansond 0:2a5a48a8b4d4 303 {
ansond 0:2a5a48a8b4d4 304 uint8_t cmd = 0xC0;
ansond 0:2a5a48a8b4d4 305 arm_enter_critical();
ansond 0:2a5a48a8b4d4 306
ansond 0:2a5a48a8b4d4 307 spi_write(cmd | addr, data);
ansond 0:2a5a48a8b4d4 308
ansond 0:2a5a48a8b4d4 309 arm_exit_critical();
ansond 0:2a5a48a8b4d4 310 }
ansond 0:2a5a48a8b4d4 311
ansond 0:2a5a48a8b4d4 312 /*
ansond 0:2a5a48a8b4d4 313 * \brief Function reads RF register.
ansond 0:2a5a48a8b4d4 314 *
ansond 0:2a5a48a8b4d4 315 * \param addr Address on the RF
ansond 0:2a5a48a8b4d4 316 *
ansond 0:2a5a48a8b4d4 317 * \return Read data
ansond 0:2a5a48a8b4d4 318 */
ansond 0:2a5a48a8b4d4 319 uint8_t rf_if_read_register(uint8_t addr)
ansond 0:2a5a48a8b4d4 320 {
ansond 0:2a5a48a8b4d4 321 uint8_t cmd = 0x80;
ansond 0:2a5a48a8b4d4 322 uint8_t data;
ansond 0:2a5a48a8b4d4 323 arm_enter_critical();
ansond 0:2a5a48a8b4d4 324
ansond 0:2a5a48a8b4d4 325 data = spi_read(cmd | addr);
ansond 0:2a5a48a8b4d4 326 arm_exit_critical();
ansond 0:2a5a48a8b4d4 327 return data;
ansond 0:2a5a48a8b4d4 328 }
ansond 0:2a5a48a8b4d4 329
ansond 0:2a5a48a8b4d4 330 /*
ansond 0:2a5a48a8b4d4 331 * \brief Function resets the RF.
ansond 0:2a5a48a8b4d4 332 *
ansond 0:2a5a48a8b4d4 333 * \param none
ansond 0:2a5a48a8b4d4 334 *
ansond 0:2a5a48a8b4d4 335 * \return none
ansond 0:2a5a48a8b4d4 336 */
ansond 0:2a5a48a8b4d4 337 void rf_if_reset_radio(void)
ansond 0:2a5a48a8b4d4 338 {
ansond 0:2a5a48a8b4d4 339 /* Reset and init RF_CS - chip select */
ansond 0:2a5a48a8b4d4 340 RF_RST_Set(1);
ansond 0:2a5a48a8b4d4 341 rf_if_delay_function(65000);
ansond 0:2a5a48a8b4d4 342 RF_RST_Set(0);
ansond 0:2a5a48a8b4d4 343 rf_if_delay_function(65000);
ansond 0:2a5a48a8b4d4 344 /* Set default states */
ansond 0:2a5a48a8b4d4 345 RF_CS_Set(1);
ansond 0:2a5a48a8b4d4 346 RF_SLP_TR_Set(0);
ansond 0:2a5a48a8b4d4 347 rf_if_delay_function(65000);
ansond 0:2a5a48a8b4d4 348 RF_RST_Set(1);
ansond 0:2a5a48a8b4d4 349 rf_if_delay_function(65000);
ansond 0:2a5a48a8b4d4 350
ansond 0:2a5a48a8b4d4 351 /*Initialise RF interrupt pin*/
ansond 0:2a5a48a8b4d4 352 RF_IRQ_Init();
ansond 0:2a5a48a8b4d4 353 }
ansond 0:2a5a48a8b4d4 354
ansond 0:2a5a48a8b4d4 355 /*
ansond 0:2a5a48a8b4d4 356 * \brief Function enables the Front end usage.
ansond 0:2a5a48a8b4d4 357 *
ansond 0:2a5a48a8b4d4 358 * \param none
ansond 0:2a5a48a8b4d4 359 *
ansond 0:2a5a48a8b4d4 360 * \return none
ansond 0:2a5a48a8b4d4 361 */
ansond 0:2a5a48a8b4d4 362 void rf_if_enable_pa_ext(void)
ansond 0:2a5a48a8b4d4 363 {
ansond 0:2a5a48a8b4d4 364 /*Set PA_EXT_EN to enable controlling of external front end*/
ansond 0:2a5a48a8b4d4 365 rf_if_set_bit(TRX_CTRL_1, PA_EXT_EN, PA_EXT_EN);
ansond 0:2a5a48a8b4d4 366 }
ansond 0:2a5a48a8b4d4 367
ansond 0:2a5a48a8b4d4 368 /*
ansond 0:2a5a48a8b4d4 369 * \brief Function disables the Front end usage.
ansond 0:2a5a48a8b4d4 370 *
ansond 0:2a5a48a8b4d4 371 * \param none
ansond 0:2a5a48a8b4d4 372 *
ansond 0:2a5a48a8b4d4 373 * \return none
ansond 0:2a5a48a8b4d4 374 */
ansond 0:2a5a48a8b4d4 375 void rf_if_disable_pa_ext(void)
ansond 0:2a5a48a8b4d4 376 {
ansond 0:2a5a48a8b4d4 377 /*Clear PA_EXT_EN to disable controlling of external front end*/
ansond 0:2a5a48a8b4d4 378 rf_if_clear_bit(TRX_CTRL_1, PA_EXT_EN);
ansond 0:2a5a48a8b4d4 379 }
ansond 0:2a5a48a8b4d4 380
ansond 0:2a5a48a8b4d4 381 /*
ansond 0:2a5a48a8b4d4 382 * \brief Function enables the Antenna diversity usage.
ansond 0:2a5a48a8b4d4 383 *
ansond 0:2a5a48a8b4d4 384 * \param none
ansond 0:2a5a48a8b4d4 385 *
ansond 0:2a5a48a8b4d4 386 * \return none
ansond 0:2a5a48a8b4d4 387 */
ansond 0:2a5a48a8b4d4 388 void rf_if_enable_ant_div(void)
ansond 0:2a5a48a8b4d4 389 {
ansond 0:2a5a48a8b4d4 390 /*Set ANT_EXT_SW_EN to enable controlling of antenna diversity*/
ansond 0:2a5a48a8b4d4 391 rf_if_set_bit(ANT_DIV, ANT_EXT_SW_EN, ANT_EXT_SW_EN);
ansond 0:2a5a48a8b4d4 392 }
ansond 0:2a5a48a8b4d4 393
ansond 0:2a5a48a8b4d4 394 /*
ansond 0:2a5a48a8b4d4 395 * \brief Function disables the Antenna diversity usage.
ansond 0:2a5a48a8b4d4 396 *
ansond 0:2a5a48a8b4d4 397 * \param none
ansond 0:2a5a48a8b4d4 398 *
ansond 0:2a5a48a8b4d4 399 * \return none
ansond 0:2a5a48a8b4d4 400 */
ansond 0:2a5a48a8b4d4 401 void rf_if_disable_ant_div(void)
ansond 0:2a5a48a8b4d4 402 {
ansond 0:2a5a48a8b4d4 403 rf_if_clear_bit(ANT_DIV, ANT_EXT_SW_EN);
ansond 0:2a5a48a8b4d4 404 }
ansond 0:2a5a48a8b4d4 405
ansond 0:2a5a48a8b4d4 406 /*
ansond 0:2a5a48a8b4d4 407 * \brief Function sets the SLP TR pin.
ansond 0:2a5a48a8b4d4 408 *
ansond 0:2a5a48a8b4d4 409 * \param none
ansond 0:2a5a48a8b4d4 410 *
ansond 0:2a5a48a8b4d4 411 * \return none
ansond 0:2a5a48a8b4d4 412 */
ansond 0:2a5a48a8b4d4 413 void rf_if_enable_slptr(void)
ansond 0:2a5a48a8b4d4 414 {
ansond 0:2a5a48a8b4d4 415 RF_SLP_TR_Set(1);
ansond 0:2a5a48a8b4d4 416 }
ansond 0:2a5a48a8b4d4 417
ansond 0:2a5a48a8b4d4 418 /*
ansond 0:2a5a48a8b4d4 419 * \brief Function clears the SLP TR pin.
ansond 0:2a5a48a8b4d4 420 *
ansond 0:2a5a48a8b4d4 421 * \param none
ansond 0:2a5a48a8b4d4 422 *
ansond 0:2a5a48a8b4d4 423 * \return none
ansond 0:2a5a48a8b4d4 424 */
ansond 0:2a5a48a8b4d4 425 void rf_if_disable_slptr(void)
ansond 0:2a5a48a8b4d4 426 {
ansond 0:2a5a48a8b4d4 427 RF_SLP_TR_Set(0);
ansond 0:2a5a48a8b4d4 428 }
ansond 0:2a5a48a8b4d4 429
ansond 0:2a5a48a8b4d4 430 /*
ansond 0:2a5a48a8b4d4 431 * \brief Function writes the antenna diversity settings.
ansond 0:2a5a48a8b4d4 432 *
ansond 0:2a5a48a8b4d4 433 * \param none
ansond 0:2a5a48a8b4d4 434 *
ansond 0:2a5a48a8b4d4 435 * \return none
ansond 0:2a5a48a8b4d4 436 */
ansond 0:2a5a48a8b4d4 437 void rf_if_write_antenna_diversity_settings(void)
ansond 0:2a5a48a8b4d4 438 {
ansond 0:2a5a48a8b4d4 439 /*Recommended setting of PDT_THRES is 3 when antenna diversity is used*/
ansond 0:2a5a48a8b4d4 440 rf_if_set_bit(RX_CTRL, 0x03, 0x0f);
ansond 0:2a5a48a8b4d4 441 rf_if_write_register(ANT_DIV, ANT_DIV_EN | ANT_EXT_SW_EN | ANT_CTRL_DEFAULT);
ansond 0:2a5a48a8b4d4 442 }
ansond 0:2a5a48a8b4d4 443
ansond 0:2a5a48a8b4d4 444 /*
ansond 0:2a5a48a8b4d4 445 * \brief Function writes the TX output power register.
ansond 0:2a5a48a8b4d4 446 *
ansond 0:2a5a48a8b4d4 447 * \param value Given register value
ansond 0:2a5a48a8b4d4 448 *
ansond 0:2a5a48a8b4d4 449 * \return none
ansond 0:2a5a48a8b4d4 450 */
ansond 0:2a5a48a8b4d4 451 void rf_if_write_set_tx_power_register(uint8_t value)
ansond 0:2a5a48a8b4d4 452 {
ansond 0:2a5a48a8b4d4 453 rf_if_write_register(PHY_TX_PWR, value);
ansond 0:2a5a48a8b4d4 454 }
ansond 0:2a5a48a8b4d4 455
ansond 0:2a5a48a8b4d4 456 /*
ansond 0:2a5a48a8b4d4 457 * \brief Function writes the RPC register.
ansond 0:2a5a48a8b4d4 458 *
ansond 0:2a5a48a8b4d4 459 * \param value Given register value
ansond 0:2a5a48a8b4d4 460 *
ansond 0:2a5a48a8b4d4 461 * \return none
ansond 0:2a5a48a8b4d4 462 */
ansond 0:2a5a48a8b4d4 463 void rf_if_write_set_trx_rpc_register(uint8_t value)
ansond 0:2a5a48a8b4d4 464 {
ansond 0:2a5a48a8b4d4 465 rf_if_write_register(TRX_RPC, value);
ansond 0:2a5a48a8b4d4 466 }
ansond 0:2a5a48a8b4d4 467
ansond 0:2a5a48a8b4d4 468 /*
ansond 0:2a5a48a8b4d4 469 * \brief Function returns the RF part number.
ansond 0:2a5a48a8b4d4 470 *
ansond 0:2a5a48a8b4d4 471 * \param none
ansond 0:2a5a48a8b4d4 472 *
ansond 0:2a5a48a8b4d4 473 * \return part number
ansond 0:2a5a48a8b4d4 474 */
ansond 0:2a5a48a8b4d4 475 uint8_t rf_if_read_part_num_delete(void)
ansond 0:2a5a48a8b4d4 476 {
ansond 0:2a5a48a8b4d4 477 return rf_if_read_register(PART_NUM);
ansond 0:2a5a48a8b4d4 478 }
ansond 0:2a5a48a8b4d4 479
ansond 0:2a5a48a8b4d4 480 /*
ansond 0:2a5a48a8b4d4 481 * \brief Function writes the RF settings and initialises SPI interface.
ansond 0:2a5a48a8b4d4 482 *
ansond 0:2a5a48a8b4d4 483 * \param none
ansond 0:2a5a48a8b4d4 484 *
ansond 0:2a5a48a8b4d4 485 * \return none
ansond 0:2a5a48a8b4d4 486 */
ansond 0:2a5a48a8b4d4 487 void rf_if_write_rf_settings(void)
ansond 0:2a5a48a8b4d4 488 {
ansond 0:2a5a48a8b4d4 489 /* unslotted mode - max. frame & csma retries = 0 */
ansond 0:2a5a48a8b4d4 490 rf_if_write_register(XAH_CTRL_0,0);
ansond 0:2a5a48a8b4d4 491 if (rf_if_read_register(XAH_CTRL_0) != 0) {
ansond 0:2a5a48a8b4d4 492 printf("Error: XAH_CTRL_0 reg. incorrect!\r\n");
ansond 0:2a5a48a8b4d4 493 //while(1);
ansond 0:2a5a48a8b4d4 494 }
ansond 0:2a5a48a8b4d4 495
ansond 0:2a5a48a8b4d4 496 /* TX_AUTO_CRC On - IRQ_Mask_Mode = 0 - IRQ_Polarity = 0 (Pin IRQ is active high) */
ansond 0:2a5a48a8b4d4 497 rf_if_write_register(TRX_CTRL_1, 0x20);
ansond 0:2a5a48a8b4d4 498 if (rf_if_read_register(TRX_CTRL_1) != 0x20) {
ansond 0:2a5a48a8b4d4 499 printf("Error: TRX_CTRL_1 reg. incorrect!\r\n");
ansond 0:2a5a48a8b4d4 500 //while(1);
ansond 0:2a5a48a8b4d4 501 }
ansond 0:2a5a48a8b4d4 502
ansond 0:2a5a48a8b4d4 503 /*CCA Mode - Carrier sense OR energy above threshold. Channel list is set separately*/
ansond 0:2a5a48a8b4d4 504 rf_if_write_register(PHY_CC_CCA, 0x05);
ansond 0:2a5a48a8b4d4 505 if (rf_if_read_register(PHY_CC_CCA) != 0x05) {
ansond 0:2a5a48a8b4d4 506 printf("Error: PHY_CC_CCA reg. incorrect!\r\n");
ansond 0:2a5a48a8b4d4 507 //while(1);
ansond 0:2a5a48a8b4d4 508 }
ansond 0:2a5a48a8b4d4 509
ansond 0:2a5a48a8b4d4 510 /*Read transceiver PART_NUM*/
ansond 0:2a5a48a8b4d4 511 rf_part_num = rf_if_read_register(PART_NUM);
ansond 0:2a5a48a8b4d4 512
ansond 0:2a5a48a8b4d4 513 /*Sub-GHz RF settings*/
ansond 0:2a5a48a8b4d4 514 if(rf_part_num == PART_AT86RF212)
ansond 0:2a5a48a8b4d4 515 {
ansond 0:2a5a48a8b4d4 516 /*GC_TX_OFFS mode-dependent setting - OQPSK*/
ansond 0:2a5a48a8b4d4 517 rf_if_write_register(RF_CTRL_0, 0x32);
ansond 0:2a5a48a8b4d4 518
ansond 0:2a5a48a8b4d4 519 if(rf_if_read_register(VERSION_NUM) == VERSION_AT86RF212B)
ansond 0:2a5a48a8b4d4 520 {
ansond 0:2a5a48a8b4d4 521 /*TX Output Power setting - 0 dBm North American Band*/
ansond 0:2a5a48a8b4d4 522 rf_if_write_register(PHY_TX_PWR, 0x03);
ansond 0:2a5a48a8b4d4 523 }
ansond 0:2a5a48a8b4d4 524 else
ansond 0:2a5a48a8b4d4 525 {
ansond 0:2a5a48a8b4d4 526 /*TX Output Power setting - 0 dBm North American Band*/
ansond 0:2a5a48a8b4d4 527 rf_if_write_register(PHY_TX_PWR, 0x24);
ansond 0:2a5a48a8b4d4 528 }
ansond 0:2a5a48a8b4d4 529
ansond 0:2a5a48a8b4d4 530 /*PHY Mode: IEEE 802.15.4-2006/2011 - OQPSK-SIN-250*/
ansond 0:2a5a48a8b4d4 531 rf_if_write_register(TRX_CTRL_2, OQPSK_SIN_250);
ansond 0:2a5a48a8b4d4 532 rf_rssi_base_val = -98;
ansond 0:2a5a48a8b4d4 533 }
ansond 0:2a5a48a8b4d4 534 /*2.4GHz RF settings*/
ansond 0:2a5a48a8b4d4 535 else if (rf_part_num == PART_AT86RF233)
ansond 0:2a5a48a8b4d4 536 {
ansond 0:2a5a48a8b4d4 537 printf("Part detected: ATMEL AT86RF233\r\n");
ansond 0:2a5a48a8b4d4 538 /*PHY Mode: IEEE 802.15.4 - Data Rate 250 kb/s*/
ansond 0:2a5a48a8b4d4 539 rf_if_write_register(TRX_CTRL_2, 0);
ansond 0:2a5a48a8b4d4 540 rf_rssi_base_val = -91;
ansond 0:2a5a48a8b4d4 541 } else {
ansond 0:2a5a48a8b4d4 542 // other module not yet defined
ansond 0:2a5a48a8b4d4 543 printf("Error: RF Part Unknown!\r\n");
ansond 0:2a5a48a8b4d4 544 }
ansond 0:2a5a48a8b4d4 545 }
ansond 0:2a5a48a8b4d4 546
ansond 0:2a5a48a8b4d4 547
ansond 0:2a5a48a8b4d4 548 /*
ansond 0:2a5a48a8b4d4 549 * \brief Function checks the channel availability
ansond 0:2a5a48a8b4d4 550 *
ansond 0:2a5a48a8b4d4 551 * \param none
ansond 0:2a5a48a8b4d4 552 *
ansond 0:2a5a48a8b4d4 553 * \return 1 Channel clear
ansond 0:2a5a48a8b4d4 554 * \return 0 Channel not clear
ansond 0:2a5a48a8b4d4 555 */
ansond 0:2a5a48a8b4d4 556 uint8_t rf_if_check_cca(void)
ansond 0:2a5a48a8b4d4 557 {
ansond 0:2a5a48a8b4d4 558 uint8_t retval = 0;
ansond 0:2a5a48a8b4d4 559 if(rf_if_read_register(TRX_STATUS) & CCA_STATUS)
ansond 0:2a5a48a8b4d4 560 {
ansond 0:2a5a48a8b4d4 561 retval = 1;
ansond 0:2a5a48a8b4d4 562 }
ansond 0:2a5a48a8b4d4 563 return retval;
ansond 0:2a5a48a8b4d4 564 }
ansond 0:2a5a48a8b4d4 565
ansond 0:2a5a48a8b4d4 566 /*
ansond 0:2a5a48a8b4d4 567 * \brief Function checks if the CRC is valid in received frame
ansond 0:2a5a48a8b4d4 568 *
ansond 0:2a5a48a8b4d4 569 * \param none
ansond 0:2a5a48a8b4d4 570 *
ansond 0:2a5a48a8b4d4 571 * \return 1 CRC ok
ansond 0:2a5a48a8b4d4 572 * \return 0 CRC failed
ansond 0:2a5a48a8b4d4 573 */
ansond 0:2a5a48a8b4d4 574 uint8_t rf_if_check_crc(void)
ansond 0:2a5a48a8b4d4 575 {
ansond 0:2a5a48a8b4d4 576 uint8_t retval = 0;
ansond 0:2a5a48a8b4d4 577 if(rf_if_read_register(PHY_RSSI) & CRC_VALID)
ansond 0:2a5a48a8b4d4 578 {
ansond 0:2a5a48a8b4d4 579 retval = 1;
ansond 0:2a5a48a8b4d4 580 }
ansond 0:2a5a48a8b4d4 581 return retval;
ansond 0:2a5a48a8b4d4 582 }
ansond 0:2a5a48a8b4d4 583
ansond 0:2a5a48a8b4d4 584 /*
ansond 0:2a5a48a8b4d4 585 * \brief Function returns the RF state
ansond 0:2a5a48a8b4d4 586 *
ansond 0:2a5a48a8b4d4 587 * \param none
ansond 0:2a5a48a8b4d4 588 *
ansond 0:2a5a48a8b4d4 589 * \return RF state
ansond 0:2a5a48a8b4d4 590 */
ansond 0:2a5a48a8b4d4 591 uint8_t rf_if_read_trx_state(void)
ansond 0:2a5a48a8b4d4 592 {
ansond 0:2a5a48a8b4d4 593 return rf_if_read_register(TRX_STATUS) & 0x1F;
ansond 0:2a5a48a8b4d4 594 }
ansond 0:2a5a48a8b4d4 595
ansond 0:2a5a48a8b4d4 596 /*
ansond 0:2a5a48a8b4d4 597 * \brief Function reads data from RF SRAM.
ansond 0:2a5a48a8b4d4 598 *
ansond 0:2a5a48a8b4d4 599 * \param ptr Read pointer
ansond 0:2a5a48a8b4d4 600 * \param len Length of the read
ansond 0:2a5a48a8b4d4 601 *
ansond 0:2a5a48a8b4d4 602 * \return none
ansond 0:2a5a48a8b4d4 603 */
ansond 0:2a5a48a8b4d4 604 void rf_if_read_packet(uint8_t *ptr, uint8_t len)
ansond 0:2a5a48a8b4d4 605 {
ansond 0:2a5a48a8b4d4 606 if(rf_part_num == PART_AT86RF231 || rf_part_num == PART_AT86RF212)
ansond 0:2a5a48a8b4d4 607 rf_if_read_payload(ptr, 0, len);
ansond 0:2a5a48a8b4d4 608 else if(rf_part_num == PART_AT86RF233)
ansond 0:2a5a48a8b4d4 609 rf_if_read_payload(ptr, 1, len);
ansond 0:2a5a48a8b4d4 610 }
ansond 0:2a5a48a8b4d4 611
ansond 0:2a5a48a8b4d4 612 /*
ansond 0:2a5a48a8b4d4 613 * \brief Function writes RF short address registers
ansond 0:2a5a48a8b4d4 614 *
ansond 0:2a5a48a8b4d4 615 * \param short_address Given short address
ansond 0:2a5a48a8b4d4 616 *
ansond 0:2a5a48a8b4d4 617 * \return none
ansond 0:2a5a48a8b4d4 618 */
ansond 0:2a5a48a8b4d4 619 void rf_if_write_short_addr_registers(uint8_t *short_address)
ansond 0:2a5a48a8b4d4 620 {
ansond 0:2a5a48a8b4d4 621 rf_if_write_register(SHORT_ADDR_1, *short_address++);
ansond 0:2a5a48a8b4d4 622 rf_if_write_register(SHORT_ADDR_0, *short_address);
ansond 0:2a5a48a8b4d4 623 }
ansond 0:2a5a48a8b4d4 624
ansond 0:2a5a48a8b4d4 625 /*
ansond 0:2a5a48a8b4d4 626 * \brief Function sets the frame pending in ACK message
ansond 0:2a5a48a8b4d4 627 *
ansond 0:2a5a48a8b4d4 628 * \param state Given frame pending state
ansond 0:2a5a48a8b4d4 629 *
ansond 0:2a5a48a8b4d4 630 * \return none
ansond 0:2a5a48a8b4d4 631 */
ansond 0:2a5a48a8b4d4 632 void rf_if_ack_pending_ctrl(uint8_t state)
ansond 0:2a5a48a8b4d4 633 {
ansond 0:2a5a48a8b4d4 634 arm_enter_critical();
ansond 0:2a5a48a8b4d4 635 if(state)
ansond 0:2a5a48a8b4d4 636 {
ansond 0:2a5a48a8b4d4 637 rf_if_set_bit(CSMA_SEED_1, (1 << AACK_SET_PD), (1 << AACK_SET_PD));
ansond 0:2a5a48a8b4d4 638 }
ansond 0:2a5a48a8b4d4 639 else
ansond 0:2a5a48a8b4d4 640 {
ansond 0:2a5a48a8b4d4 641 rf_if_clear_bit(CSMA_SEED_1, (1 << AACK_SET_PD));
ansond 0:2a5a48a8b4d4 642 }
ansond 0:2a5a48a8b4d4 643 arm_exit_critical();
ansond 0:2a5a48a8b4d4 644 }
ansond 0:2a5a48a8b4d4 645
ansond 0:2a5a48a8b4d4 646 /*
ansond 0:2a5a48a8b4d4 647 * \brief Function returns the state of frame pending control
ansond 0:2a5a48a8b4d4 648 *
ansond 0:2a5a48a8b4d4 649 * \param none
ansond 0:2a5a48a8b4d4 650 *
ansond 0:2a5a48a8b4d4 651 * \return Frame pending state
ansond 0:2a5a48a8b4d4 652 */
ansond 0:2a5a48a8b4d4 653 uint8_t rf_if_last_acked_pending(void)
ansond 0:2a5a48a8b4d4 654 {
ansond 0:2a5a48a8b4d4 655 uint8_t last_acked_data_pending;
ansond 0:2a5a48a8b4d4 656
ansond 0:2a5a48a8b4d4 657 if(rf_if_read_register(CSMA_SEED_1) & 0x20)
ansond 0:2a5a48a8b4d4 658 last_acked_data_pending = 1;
ansond 0:2a5a48a8b4d4 659 else
ansond 0:2a5a48a8b4d4 660 last_acked_data_pending = 0;
ansond 0:2a5a48a8b4d4 661
ansond 0:2a5a48a8b4d4 662 return last_acked_data_pending;
ansond 0:2a5a48a8b4d4 663 }
ansond 0:2a5a48a8b4d4 664
ansond 0:2a5a48a8b4d4 665 /*
ansond 0:2a5a48a8b4d4 666 * \brief Function calibrates the RF part.
ansond 0:2a5a48a8b4d4 667 *
ansond 0:2a5a48a8b4d4 668 * \param none
ansond 0:2a5a48a8b4d4 669 *
ansond 0:2a5a48a8b4d4 670 * \return none
ansond 0:2a5a48a8b4d4 671 */
ansond 0:2a5a48a8b4d4 672 void rf_if_calibration(void)
ansond 0:2a5a48a8b4d4 673 {
ansond 0:2a5a48a8b4d4 674 rf_if_set_bit(FTN_CTRL, FTN_START, FTN_START);
ansond 0:2a5a48a8b4d4 675 /*Wait while calibration is running*/
ansond 0:2a5a48a8b4d4 676 while(rf_if_read_register(FTN_CTRL) & FTN_START);
ansond 0:2a5a48a8b4d4 677 }
ansond 0:2a5a48a8b4d4 678
ansond 0:2a5a48a8b4d4 679 /*
ansond 0:2a5a48a8b4d4 680 * \brief Function writes RF PAN Id registers
ansond 0:2a5a48a8b4d4 681 *
ansond 0:2a5a48a8b4d4 682 * \param pan_id Given PAN Id
ansond 0:2a5a48a8b4d4 683 *
ansond 0:2a5a48a8b4d4 684 * \return none
ansond 0:2a5a48a8b4d4 685 */
ansond 0:2a5a48a8b4d4 686 void rf_if_write_pan_id_registers(uint8_t *pan_id)
ansond 0:2a5a48a8b4d4 687 {
ansond 0:2a5a48a8b4d4 688 rf_if_write_register(PAN_ID_1, *pan_id++);
ansond 0:2a5a48a8b4d4 689 rf_if_write_register(PAN_ID_0, *pan_id);
ansond 0:2a5a48a8b4d4 690 }
ansond 0:2a5a48a8b4d4 691
ansond 0:2a5a48a8b4d4 692 /*
ansond 0:2a5a48a8b4d4 693 * \brief Function writes RF IEEE Address registers
ansond 0:2a5a48a8b4d4 694 *
ansond 0:2a5a48a8b4d4 695 * \param address Given IEEE Address
ansond 0:2a5a48a8b4d4 696 *
ansond 0:2a5a48a8b4d4 697 * \return none
ansond 0:2a5a48a8b4d4 698 */
ansond 0:2a5a48a8b4d4 699 void rf_if_write_ieee_addr_registers(uint8_t *address)
ansond 0:2a5a48a8b4d4 700 {
ansond 0:2a5a48a8b4d4 701 uint8_t i;
ansond 0:2a5a48a8b4d4 702 uint8_t temp = IEEE_ADDR_0;
ansond 0:2a5a48a8b4d4 703
ansond 0:2a5a48a8b4d4 704 for(i=0; i<8; i++)
ansond 0:2a5a48a8b4d4 705 rf_if_write_register(temp++, address[7-i]);
ansond 0:2a5a48a8b4d4 706 }
ansond 0:2a5a48a8b4d4 707
ansond 0:2a5a48a8b4d4 708 /*
ansond 0:2a5a48a8b4d4 709 * \brief Function writes data in RF frame buffer.
ansond 0:2a5a48a8b4d4 710 *
ansond 0:2a5a48a8b4d4 711 * \param ptr Pointer to data
ansond 0:2a5a48a8b4d4 712 * \param length Pointer to length
ansond 0:2a5a48a8b4d4 713 *
ansond 0:2a5a48a8b4d4 714 * \return none
ansond 0:2a5a48a8b4d4 715 */
ansond 0:2a5a48a8b4d4 716 void rf_if_write_frame_buffer(uint8_t *ptr, uint8_t length)
ansond 0:2a5a48a8b4d4 717 {
ansond 0:2a5a48a8b4d4 718 uint8_t i;
ansond 0:2a5a48a8b4d4 719 uint8_t cmd = 0x60;
ansond 0:2a5a48a8b4d4 720
ansond 0:2a5a48a8b4d4 721 RF_CS_Set(0);
ansond 0:2a5a48a8b4d4 722 spi_exchange(cmd);
ansond 0:2a5a48a8b4d4 723 spi_exchange(length + 2);
ansond 0:2a5a48a8b4d4 724 for(i=0; i<length; i++)
ansond 0:2a5a48a8b4d4 725 spi_exchange(*ptr++);
ansond 0:2a5a48a8b4d4 726
ansond 0:2a5a48a8b4d4 727 rf_if_delay_function(10);
ansond 0:2a5a48a8b4d4 728 RF_CS_Set(1);
ansond 0:2a5a48a8b4d4 729 }
ansond 0:2a5a48a8b4d4 730
ansond 0:2a5a48a8b4d4 731 /*
ansond 0:2a5a48a8b4d4 732 * \brief Function returns 8-bit random value.
ansond 0:2a5a48a8b4d4 733 *
ansond 0:2a5a48a8b4d4 734 * \param none
ansond 0:2a5a48a8b4d4 735 *
ansond 0:2a5a48a8b4d4 736 * \return random value
ansond 0:2a5a48a8b4d4 737 */
ansond 0:2a5a48a8b4d4 738 uint8_t rf_if_read_rnd(void)
ansond 0:2a5a48a8b4d4 739 {
ansond 0:2a5a48a8b4d4 740 uint8_t temp;
ansond 0:2a5a48a8b4d4 741
ansond 0:2a5a48a8b4d4 742 temp = ((rf_if_read_register(PHY_RSSI)>>5) << 6);
ansond 0:2a5a48a8b4d4 743 temp |= ((rf_if_read_register(PHY_RSSI)>>5) << 4);
ansond 0:2a5a48a8b4d4 744 temp |= ((rf_if_read_register(PHY_RSSI)>>5) << 2);
ansond 0:2a5a48a8b4d4 745 temp |= ((rf_if_read_register(PHY_RSSI)>>5));
ansond 0:2a5a48a8b4d4 746 return temp;
ansond 0:2a5a48a8b4d4 747 }
ansond 0:2a5a48a8b4d4 748
ansond 0:2a5a48a8b4d4 749 /*
ansond 0:2a5a48a8b4d4 750 * \brief Function changes the state of the RF.
ansond 0:2a5a48a8b4d4 751 *
ansond 0:2a5a48a8b4d4 752 * \param trx_state Given RF state
ansond 0:2a5a48a8b4d4 753 *
ansond 0:2a5a48a8b4d4 754 * \return none
ansond 0:2a5a48a8b4d4 755 */
ansond 0:2a5a48a8b4d4 756 void rf_if_change_trx_state(rf_trx_states_t trx_state)
ansond 0:2a5a48a8b4d4 757 {
ansond 0:2a5a48a8b4d4 758 arm_enter_critical();
ansond 0:2a5a48a8b4d4 759 rf_if_write_register(TRX_STATE, trx_state);
ansond 0:2a5a48a8b4d4 760 /*Wait while not in desired state*/
ansond 0:2a5a48a8b4d4 761 rf_poll_trx_state_change(trx_state);
ansond 0:2a5a48a8b4d4 762 arm_exit_critical();
ansond 0:2a5a48a8b4d4 763 }
ansond 0:2a5a48a8b4d4 764
ansond 0:2a5a48a8b4d4 765 /*
ansond 0:2a5a48a8b4d4 766 * \brief Function enables the TX END interrupt
ansond 0:2a5a48a8b4d4 767 *
ansond 0:2a5a48a8b4d4 768 * \param none
ansond 0:2a5a48a8b4d4 769 *
ansond 0:2a5a48a8b4d4 770 * \return none
ansond 0:2a5a48a8b4d4 771 */
ansond 0:2a5a48a8b4d4 772 void rf_if_enable_tx_end_interrupt(void)
ansond 0:2a5a48a8b4d4 773 {
ansond 0:2a5a48a8b4d4 774 rf_if_set_bit(IRQ_MASK, TRX_END, 0x08);
ansond 0:2a5a48a8b4d4 775 }
ansond 0:2a5a48a8b4d4 776
ansond 0:2a5a48a8b4d4 777 /*
ansond 0:2a5a48a8b4d4 778 * \brief Function enables the RX END interrupt
ansond 0:2a5a48a8b4d4 779 *
ansond 0:2a5a48a8b4d4 780 * \param none
ansond 0:2a5a48a8b4d4 781 *
ansond 0:2a5a48a8b4d4 782 * \return none
ansond 0:2a5a48a8b4d4 783 */
ansond 0:2a5a48a8b4d4 784 void rf_if_enable_rx_end_interrupt(void)
ansond 0:2a5a48a8b4d4 785 {
ansond 0:2a5a48a8b4d4 786 rf_if_set_bit(IRQ_MASK, TRX_END, 0x08);
ansond 0:2a5a48a8b4d4 787 }
ansond 0:2a5a48a8b4d4 788
ansond 0:2a5a48a8b4d4 789 /*
ansond 0:2a5a48a8b4d4 790 * \brief Function enables the RX START interrupt
ansond 0:2a5a48a8b4d4 791 *
ansond 0:2a5a48a8b4d4 792 * \param none
ansond 0:2a5a48a8b4d4 793 *
ansond 0:2a5a48a8b4d4 794 * \return none
ansond 0:2a5a48a8b4d4 795 */
ansond 0:2a5a48a8b4d4 796 void rf_if_enable_rx_start_interrupt(void)
ansond 0:2a5a48a8b4d4 797 {
ansond 0:2a5a48a8b4d4 798 rf_if_set_bit(IRQ_MASK, RX_START, 0x04);
ansond 0:2a5a48a8b4d4 799 }
ansond 0:2a5a48a8b4d4 800
ansond 0:2a5a48a8b4d4 801 /*
ansond 0:2a5a48a8b4d4 802 * \brief Function enables the CCA ED interrupt
ansond 0:2a5a48a8b4d4 803 *
ansond 0:2a5a48a8b4d4 804 * \param none
ansond 0:2a5a48a8b4d4 805 *
ansond 0:2a5a48a8b4d4 806 * \return none
ansond 0:2a5a48a8b4d4 807 */
ansond 0:2a5a48a8b4d4 808 void rf_if_enable_cca_ed_done_interrupt(void)
ansond 0:2a5a48a8b4d4 809 {
ansond 0:2a5a48a8b4d4 810 rf_if_set_bit(IRQ_MASK, CCA_ED_DONE, 0x10);
ansond 0:2a5a48a8b4d4 811 }
ansond 0:2a5a48a8b4d4 812
ansond 0:2a5a48a8b4d4 813 /*
ansond 0:2a5a48a8b4d4 814 * \brief Function starts the CCA process
ansond 0:2a5a48a8b4d4 815 *
ansond 0:2a5a48a8b4d4 816 * \param none
ansond 0:2a5a48a8b4d4 817 *
ansond 0:2a5a48a8b4d4 818 * \return none
ansond 0:2a5a48a8b4d4 819 */
ansond 0:2a5a48a8b4d4 820 void rf_if_start_cca_process(void)
ansond 0:2a5a48a8b4d4 821 {
ansond 0:2a5a48a8b4d4 822 rf_if_set_bit(PHY_CC_CCA, CCA_REQUEST, 0x80);
ansond 0:2a5a48a8b4d4 823 }
ansond 0:2a5a48a8b4d4 824
ansond 0:2a5a48a8b4d4 825 /*
ansond 0:2a5a48a8b4d4 826 * \brief Function returns the length of the received packet
ansond 0:2a5a48a8b4d4 827 *
ansond 0:2a5a48a8b4d4 828 * \param none
ansond 0:2a5a48a8b4d4 829 *
ansond 0:2a5a48a8b4d4 830 * \return packet length
ansond 0:2a5a48a8b4d4 831 */
ansond 0:2a5a48a8b4d4 832 uint8_t rf_if_read_received_frame_length(void)
ansond 0:2a5a48a8b4d4 833 {
ansond 0:2a5a48a8b4d4 834 uint8_t length;
ansond 0:2a5a48a8b4d4 835
ansond 0:2a5a48a8b4d4 836 RF_CS_Set(0);
ansond 0:2a5a48a8b4d4 837 spi_exchange(0x20);
ansond 0:2a5a48a8b4d4 838 length = spi_exchange(0);
ansond 0:2a5a48a8b4d4 839 RF_CS_Set(1);
ansond 0:2a5a48a8b4d4 840 return length;
ansond 0:2a5a48a8b4d4 841 }
ansond 0:2a5a48a8b4d4 842
ansond 0:2a5a48a8b4d4 843 /*
ansond 0:2a5a48a8b4d4 844 * \brief Function returns the LQI of the received packet
ansond 0:2a5a48a8b4d4 845 *
ansond 0:2a5a48a8b4d4 846 * \param none
ansond 0:2a5a48a8b4d4 847 *
ansond 0:2a5a48a8b4d4 848 * \return packet LQI
ansond 0:2a5a48a8b4d4 849 */
ansond 0:2a5a48a8b4d4 850 uint8_t rf_if_read_lqi(void)
ansond 0:2a5a48a8b4d4 851 {
ansond 0:2a5a48a8b4d4 852 return rf_rx_lqi;
ansond 0:2a5a48a8b4d4 853 }
ansond 0:2a5a48a8b4d4 854
ansond 0:2a5a48a8b4d4 855 /*
ansond 0:2a5a48a8b4d4 856 * \brief Function returns the RSSI of the received packet
ansond 0:2a5a48a8b4d4 857 *
ansond 0:2a5a48a8b4d4 858 * \param none
ansond 0:2a5a48a8b4d4 859 *
ansond 0:2a5a48a8b4d4 860 * \return packet RSSI
ansond 0:2a5a48a8b4d4 861 */
ansond 0:2a5a48a8b4d4 862 int8_t rf_if_read_rssi(void)
ansond 0:2a5a48a8b4d4 863 {
ansond 0:2a5a48a8b4d4 864 return rf_rx_rssi;
ansond 0:2a5a48a8b4d4 865 }
ansond 0:2a5a48a8b4d4 866
ansond 0:2a5a48a8b4d4 867 /*
ansond 0:2a5a48a8b4d4 868 * \brief Function sets the RF channel field
ansond 0:2a5a48a8b4d4 869 *
ansond 0:2a5a48a8b4d4 870 * \param Given channel
ansond 0:2a5a48a8b4d4 871 *
ansond 0:2a5a48a8b4d4 872 * \return none
ansond 0:2a5a48a8b4d4 873 */
ansond 0:2a5a48a8b4d4 874 void rf_if_set_channel_register(uint8_t channel)
ansond 0:2a5a48a8b4d4 875 {
ansond 0:2a5a48a8b4d4 876 rf_if_set_bit(PHY_CC_CCA, channel, 0x1f);
ansond 0:2a5a48a8b4d4 877 }
ansond 0:2a5a48a8b4d4 878
ansond 0:2a5a48a8b4d4 879 /*
ansond 0:2a5a48a8b4d4 880 * \brief Function returns the pointer to RF interrupt handler
ansond 0:2a5a48a8b4d4 881 *
ansond 0:2a5a48a8b4d4 882 * \param none
ansond 0:2a5a48a8b4d4 883 *
ansond 0:2a5a48a8b4d4 884 * \return RF interrupt handler function
ansond 0:2a5a48a8b4d4 885 */
ansond 0:2a5a48a8b4d4 886 void (*rf_if_get_rf_interrupt_function())(void)
ansond 0:2a5a48a8b4d4 887 {
ansond 0:2a5a48a8b4d4 888 return rf_if_interrupt_handler;
ansond 0:2a5a48a8b4d4 889 }
ansond 0:2a5a48a8b4d4 890
ansond 0:2a5a48a8b4d4 891 /*
ansond 0:2a5a48a8b4d4 892 * \brief Function is a RF interrupt vector. End of frame in RX and TX are handled here as well as CCA process interrupt.
ansond 0:2a5a48a8b4d4 893 *
ansond 0:2a5a48a8b4d4 894 * \param none
ansond 0:2a5a48a8b4d4 895 *
ansond 0:2a5a48a8b4d4 896 * \return none
ansond 0:2a5a48a8b4d4 897 */
ansond 0:2a5a48a8b4d4 898 void rf_if_interrupt_handler(void)
ansond 0:2a5a48a8b4d4 899 {
ansond 0:2a5a48a8b4d4 900 uint8_t irq_status;
ansond 0:2a5a48a8b4d4 901
ansond 0:2a5a48a8b4d4 902 /*Read interrupt flag*/
ansond 0:2a5a48a8b4d4 903 irq_status = rf_if_read_register(IRQ_STATUS);
ansond 0:2a5a48a8b4d4 904
ansond 0:2a5a48a8b4d4 905 /*Disable interrupt on RF*/
ansond 0:2a5a48a8b4d4 906 rf_if_clear_bit(IRQ_MASK, irq_status);
ansond 0:2a5a48a8b4d4 907 /*RX start interrupt*/
ansond 0:2a5a48a8b4d4 908 if(irq_status & RX_START)
ansond 0:2a5a48a8b4d4 909 {
ansond 0:2a5a48a8b4d4 910 }
ansond 0:2a5a48a8b4d4 911 /*Address matching interrupt*/
ansond 0:2a5a48a8b4d4 912 if(irq_status & AMI)
ansond 0:2a5a48a8b4d4 913 {
ansond 0:2a5a48a8b4d4 914 }
ansond 0:2a5a48a8b4d4 915 if(irq_status & TRX_UR)
ansond 0:2a5a48a8b4d4 916 {
ansond 0:2a5a48a8b4d4 917 }
ansond 0:2a5a48a8b4d4 918 /*Frame end interrupt (RX and TX)*/
ansond 0:2a5a48a8b4d4 919 if(irq_status & TRX_END)
ansond 0:2a5a48a8b4d4 920 {
ansond 0:2a5a48a8b4d4 921 /*TX done interrupt*/
ansond 0:2a5a48a8b4d4 922 if(rf_if_read_trx_state() == PLL_ON || rf_if_read_trx_state() == TX_ARET_ON)
ansond 0:2a5a48a8b4d4 923 {
ansond 0:2a5a48a8b4d4 924 rf_handle_tx_end();
ansond 0:2a5a48a8b4d4 925 }
ansond 0:2a5a48a8b4d4 926 /*Frame received interrupt*/
ansond 0:2a5a48a8b4d4 927 else
ansond 0:2a5a48a8b4d4 928 {
ansond 0:2a5a48a8b4d4 929 rf_handle_rx_end();
ansond 0:2a5a48a8b4d4 930 }
ansond 0:2a5a48a8b4d4 931 }
ansond 0:2a5a48a8b4d4 932 if(irq_status & CCA_ED_DONE)
ansond 0:2a5a48a8b4d4 933 {
ansond 0:2a5a48a8b4d4 934 rf_handle_cca_ed_done();
ansond 0:2a5a48a8b4d4 935 }
ansond 0:2a5a48a8b4d4 936 }
ansond 0:2a5a48a8b4d4 937