Diff: io/MySerial.cpp

Revision:

5:1b9734e68327

Parent:

4:17b8edf264c3

Child:

6:ef758ac3c928

--- a/io/MySerial.cpp	Thu Apr 16 17:10:19 2015 +0000
+++ b/io/MySerial.cpp	Fri Apr 17 04:20:07 2015 +0000
@@ -27,6 +27,9 @@
 {
     my_serial_init( &_my_serial, tx, rx, rts, cts, _my_baud );
     serial_irq_handler( &_my_serial, _irq_handler, (uint32_t)this );
+
+    // For uart errors
+    attach( this, &MySerialBase::error_handler, (Serial::IrqType)ErrIrq );
 }
 void MySerialBase::baud( int baudrate )
 {
@@ -45,16 +48,17 @@
 {
     return  serial_writable( &_my_serial );
 }
-void MySerialBase::attach( void (*fptr)(void), SerialBase::IrqType type )
+void MySerialBase::attach( void (*fptr)(void), Serial::IrqType type )
 {
     if( fptr )
     {
         _my_irq[type].attach( fptr );
-        serial_irq_set( &_my_serial, (SerialIrq)type, 1 );
+        my_serial_irq_set( &_my_serial, (IrqType)type, 1 );
+
     } else
-    {
-        serial_irq_set( &_my_serial, (SerialIrq)type, 0 );
-    }
+      {
+          my_serial_irq_set( &_my_serial, (IrqType)type, 0 );
+      }
 }
 void MySerialBase::my_serial_init( serial_t *obj, PinName tx, PinName rx, PinName rts, PinName cts, int baudrate )
 {
@@ -116,11 +120,76 @@
         memcpy(&stdio_uart, obj, sizeof(serial_t));
     }
 }
+// Replacement for serial_irq_set() in serial_api.c so we can grab uart errors.
+void MySerialBase::my_serial_irq_set( serial_t *obj, IrqType irq, uint32_t enable )
+{
+    IRQn_Type irq_n = (IRQn_Type)0;
+
+    switch( (int)obj->uart )
+    {
+      case UART_0:
+        irq_n = UART0_IRQn;
+        break;
+    }
+
+    if( enable )
+    {
+        switch( irq )
+        {
+          case RxIrq:
+            obj->uart->INTEN |= (UART_INTENSET_RXDRDY_Msk);
+            break;
+          case TxIrq:
+            obj->uart->INTEN |= (UART_INTENSET_TXDRDY_Msk);
+            break;
+          case ErrIrq:
+            obj->uart->INTEN |= (UART_INTENSET_ERROR_Msk);
+            break;
+        }
+        NVIC_SetPriority( irq_n, 3 );
+        NVIC_EnableIRQ( irq_n );
+
+    } else
+      { // disable
+          // masked writes to INTENSET dont disable and masked writes to
+          //  INTENCLR seemed to clear the entire register, not bits.
+          //  Added INTEN to memory map and seems to allow set and clearing of specific bits as desired
+          switch( irq )
+          {
+            case RxIrq:
+              obj->uart->INTEN &= ~(UART_INTENCLR_RXDRDY_Msk);
+              break;
+            case TxIrq:
+              obj->uart->INTEN &= ~(UART_INTENCLR_TXDRDY_Msk);
+              break;
+            case ErrIrq:
+              obj->uart->INTEN &= ~(UART_INTENCLR_ERROR_Msk);
+              break;
+          }
+
+          if( 0 == obj->uart->INTENCLR )
+          {
+              NVIC_DisableIRQ( irq_n );
+          }
+      }
+}
 void MySerialBase::_irq_handler( uint32_t id, SerialIrq irq_type )
 {
     MySerialBase *handler = (MySerialBase*)id;
     handler->_my_irq[irq_type].call();
 }
+void MySerialBase::error_handler()
+{
+    puts( "\r\nUART ERR!  " );
+
+    if( (UART_ERRORSRC_OVERRUN_Present << UART_ERRORSRC_OVERRUN_Pos) == (UART_ERRORSRC_OVERRUN_Msk & _my_serial.uart->ERRORSRC) )
+    {
+        puts( "\r\n[ERR: OVERRUN]\r\n" );
+
+        // Clear the error
+        _my_serial.uart->ERRORSRC = (UART_ERRORSRC_OVERRUN_Clear << UART_ERRORSRC_OVERRUN_Pos);
+    }
+}
 int MySerialBase::_base_getc()
 {
     return  serial_getc( &_my_serial );