A stack which works with or without an Mbed os library. Provides IPv4 or IPv6 with a full 1500 byte buffer.
Dependents: oldheating gps motorhome heating
link/nicdefs.h@70:74c11fb71a15, 2018-02-16 (annotated)
- Committer:
- andrewboyson
- Date:
- Fri Feb 16 17:31:52 2018 +0000
- Revision:
- 70:74c11fb71a15
- Parent:
- 59:e0e556c8bd46
- Child:
- 136:8a65abb0dc63
Removed need for defs.h
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
andrewboyson | 59:e0e556c8bd46 | 1 | |
andrewboyson | 59:e0e556c8bd46 | 2 | __packed struct RX_DESC_TypeDef { /* RX Descriptor struct */ |
andrewboyson | 59:e0e556c8bd46 | 3 | unsigned int Packet; |
andrewboyson | 59:e0e556c8bd46 | 4 | unsigned int Ctrl; |
andrewboyson | 59:e0e556c8bd46 | 5 | }; |
andrewboyson | 59:e0e556c8bd46 | 6 | typedef struct RX_DESC_TypeDef RX_DESC_TypeDef; |
andrewboyson | 59:e0e556c8bd46 | 7 | |
andrewboyson | 59:e0e556c8bd46 | 8 | __packed struct RX_STAT_TypeDef { /* RX Status struct */ |
andrewboyson | 59:e0e556c8bd46 | 9 | unsigned int Info; |
andrewboyson | 59:e0e556c8bd46 | 10 | unsigned int HashCRC; |
andrewboyson | 59:e0e556c8bd46 | 11 | }; |
andrewboyson | 59:e0e556c8bd46 | 12 | typedef struct RX_STAT_TypeDef RX_STAT_TypeDef; |
andrewboyson | 59:e0e556c8bd46 | 13 | |
andrewboyson | 59:e0e556c8bd46 | 14 | __packed struct TX_DESC_TypeDef { /* TX Descriptor struct */ |
andrewboyson | 59:e0e556c8bd46 | 15 | unsigned int Packet; |
andrewboyson | 59:e0e556c8bd46 | 16 | unsigned int Ctrl; |
andrewboyson | 59:e0e556c8bd46 | 17 | }; |
andrewboyson | 59:e0e556c8bd46 | 18 | typedef struct TX_DESC_TypeDef TX_DESC_TypeDef; |
andrewboyson | 59:e0e556c8bd46 | 19 | |
andrewboyson | 59:e0e556c8bd46 | 20 | __packed struct TX_STAT_TypeDef { /* TX Status struct */ |
andrewboyson | 59:e0e556c8bd46 | 21 | unsigned int Info; |
andrewboyson | 59:e0e556c8bd46 | 22 | }; |
andrewboyson | 59:e0e556c8bd46 | 23 | typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; |
andrewboyson | 59:e0e556c8bd46 | 24 | |
andrewboyson | 70:74c11fb71a15 | 25 | //Registers |
andrewboyson | 70:74c11fb71a15 | 26 | #define MAC1 (*((volatile unsigned *) 0x50000000)) |
andrewboyson | 70:74c11fb71a15 | 27 | #define MAC2 (*((volatile unsigned *) 0x50000004)) |
andrewboyson | 70:74c11fb71a15 | 28 | #define IPGT (*((volatile unsigned *) 0x50000008)) |
andrewboyson | 70:74c11fb71a15 | 29 | #define IPGR (*((volatile unsigned *) 0x5000000C)) |
andrewboyson | 70:74c11fb71a15 | 30 | #define CLRT (*((volatile unsigned *) 0x50000010)) |
andrewboyson | 70:74c11fb71a15 | 31 | #define MAXF (*((volatile unsigned *) 0x50000014)) |
andrewboyson | 70:74c11fb71a15 | 32 | #define SUPP (*((volatile unsigned *) 0x50000018)) |
andrewboyson | 70:74c11fb71a15 | 33 | #define MCFG (*((volatile unsigned *) 0x50000020)) |
andrewboyson | 70:74c11fb71a15 | 34 | #define MCMD (*((volatile unsigned *) 0x50000024)) |
andrewboyson | 70:74c11fb71a15 | 35 | #define MADR (*((volatile unsigned *) 0x50000028)) |
andrewboyson | 70:74c11fb71a15 | 36 | #define MWTD (*((volatile unsigned *) 0x5000002C)) |
andrewboyson | 70:74c11fb71a15 | 37 | #define MRDD (*((volatile unsigned *) 0x50000030)) |
andrewboyson | 70:74c11fb71a15 | 38 | #define MIND (*((volatile unsigned *) 0x50000034)) |
andrewboyson | 70:74c11fb71a15 | 39 | #define SA0 (*((volatile unsigned *) 0x50000040)) |
andrewboyson | 70:74c11fb71a15 | 40 | #define SA1 (*((volatile unsigned *) 0x50000044)) |
andrewboyson | 70:74c11fb71a15 | 41 | #define SA2 (*((volatile unsigned *) 0x50000048)) |
andrewboyson | 70:74c11fb71a15 | 42 | |
andrewboyson | 70:74c11fb71a15 | 43 | #define COMMAND (*((volatile unsigned *) 0x50000100)) |
andrewboyson | 70:74c11fb71a15 | 44 | #define STATUS (*((volatile unsigned *) 0x50000104)) |
andrewboyson | 70:74c11fb71a15 | 45 | |
andrewboyson | 70:74c11fb71a15 | 46 | #define RX_DESCRIPTOR (*((volatile unsigned *) 0x50000108)) |
andrewboyson | 70:74c11fb71a15 | 47 | #define RX_STATUS (*((volatile unsigned *) 0x5000010C)) |
andrewboyson | 70:74c11fb71a15 | 48 | #define RX_DESCRIPTOR_NUMBER (*((volatile unsigned *) 0x50000110)) |
andrewboyson | 70:74c11fb71a15 | 49 | #define RX_PRODUCE_INDEX (*((volatile unsigned *) 0x50000114)) |
andrewboyson | 70:74c11fb71a15 | 50 | #define RX_CONSUME_INDEX (*((volatile unsigned *) 0x50000118)) |
andrewboyson | 70:74c11fb71a15 | 51 | |
andrewboyson | 70:74c11fb71a15 | 52 | #define TX_DESCRIPTOR (*((volatile unsigned *) 0x5000011C)) |
andrewboyson | 70:74c11fb71a15 | 53 | #define TX_STATUS (*((volatile unsigned *) 0x50000120)) |
andrewboyson | 70:74c11fb71a15 | 54 | #define TX_DESCRIPTOR_NUMBER (*((volatile unsigned *) 0x50000124)) |
andrewboyson | 70:74c11fb71a15 | 55 | #define TX_PRODUCE_INDEX (*((volatile unsigned *) 0x50000128)) |
andrewboyson | 70:74c11fb71a15 | 56 | #define TX_CONSUME_INDEX (*((volatile unsigned *) 0x5000012C)) |
andrewboyson | 70:74c11fb71a15 | 57 | |
andrewboyson | 70:74c11fb71a15 | 58 | #define RX_FILTER_CTRL (*((volatile unsigned *) 0x50000200)) |
andrewboyson | 70:74c11fb71a15 | 59 | #define INT_ENABLE (*((volatile unsigned *) 0x50000FE4)) |
andrewboyson | 70:74c11fb71a15 | 60 | #define INT_CLEAR (*((volatile unsigned *) 0x50000FE8)) |
andrewboyson | 70:74c11fb71a15 | 61 | |
andrewboyson | 59:e0e556c8bd46 | 62 | /* MAC Configuration Register 1 */ |
andrewboyson | 59:e0e556c8bd46 | 63 | #define MAC1_REC_EN 0x00000001 /* Receive Enable */ |
andrewboyson | 59:e0e556c8bd46 | 64 | #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ |
andrewboyson | 59:e0e556c8bd46 | 65 | #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ |
andrewboyson | 59:e0e556c8bd46 | 66 | #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ |
andrewboyson | 59:e0e556c8bd46 | 67 | #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ |
andrewboyson | 59:e0e556c8bd46 | 68 | #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ |
andrewboyson | 59:e0e556c8bd46 | 69 | #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ |
andrewboyson | 59:e0e556c8bd46 | 70 | #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ |
andrewboyson | 59:e0e556c8bd46 | 71 | #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ |
andrewboyson | 59:e0e556c8bd46 | 72 | #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ |
andrewboyson | 59:e0e556c8bd46 | 73 | #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ |
andrewboyson | 59:e0e556c8bd46 | 74 | |
andrewboyson | 59:e0e556c8bd46 | 75 | /* MAC Configuration Register 2 */ |
andrewboyson | 59:e0e556c8bd46 | 76 | #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ |
andrewboyson | 59:e0e556c8bd46 | 77 | #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ |
andrewboyson | 59:e0e556c8bd46 | 78 | #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ |
andrewboyson | 59:e0e556c8bd46 | 79 | #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ |
andrewboyson | 59:e0e556c8bd46 | 80 | #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ |
andrewboyson | 59:e0e556c8bd46 | 81 | #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ |
andrewboyson | 59:e0e556c8bd46 | 82 | #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ |
andrewboyson | 59:e0e556c8bd46 | 83 | #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ |
andrewboyson | 59:e0e556c8bd46 | 84 | #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ |
andrewboyson | 59:e0e556c8bd46 | 85 | #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ |
andrewboyson | 59:e0e556c8bd46 | 86 | #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ |
andrewboyson | 59:e0e556c8bd46 | 87 | #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ |
andrewboyson | 59:e0e556c8bd46 | 88 | #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ |
andrewboyson | 59:e0e556c8bd46 | 89 | |
andrewboyson | 59:e0e556c8bd46 | 90 | /* Back-to-Back Inter-Packet-Gap Register */ |
andrewboyson | 59:e0e556c8bd46 | 91 | #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ |
andrewboyson | 59:e0e556c8bd46 | 92 | #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ |
andrewboyson | 59:e0e556c8bd46 | 93 | |
andrewboyson | 59:e0e556c8bd46 | 94 | /* Non Back-to-Back Inter-Packet-Gap Register */ |
andrewboyson | 59:e0e556c8bd46 | 95 | #define IPGR_DEF 0x00000012 /* Recommended value */ |
andrewboyson | 59:e0e556c8bd46 | 96 | |
andrewboyson | 59:e0e556c8bd46 | 97 | /* Collision Window/Retry Register */ |
andrewboyson | 59:e0e556c8bd46 | 98 | #define CLRT_DEF 0x0000370F /* Default value */ |
andrewboyson | 59:e0e556c8bd46 | 99 | |
andrewboyson | 59:e0e556c8bd46 | 100 | /* PHY Support Register */ |
andrewboyson | 59:e0e556c8bd46 | 101 | #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ |
andrewboyson | 59:e0e556c8bd46 | 102 | //#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ |
andrewboyson | 59:e0e556c8bd46 | 103 | #define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */ |
andrewboyson | 59:e0e556c8bd46 | 104 | |
andrewboyson | 59:e0e556c8bd46 | 105 | /* Test Register */ |
andrewboyson | 59:e0e556c8bd46 | 106 | #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ |
andrewboyson | 59:e0e556c8bd46 | 107 | #define TEST_TST_PAUSE 0x00000002 /* Test Pause */ |
andrewboyson | 59:e0e556c8bd46 | 108 | #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ |
andrewboyson | 59:e0e556c8bd46 | 109 | |
andrewboyson | 59:e0e556c8bd46 | 110 | /* MII Management Configuration Register */ |
andrewboyson | 59:e0e556c8bd46 | 111 | #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ |
andrewboyson | 59:e0e556c8bd46 | 112 | #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ |
andrewboyson | 59:e0e556c8bd46 | 113 | #define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */ |
andrewboyson | 59:e0e556c8bd46 | 114 | #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ |
andrewboyson | 59:e0e556c8bd46 | 115 | |
andrewboyson | 59:e0e556c8bd46 | 116 | /* MII Management Command Register */ |
andrewboyson | 59:e0e556c8bd46 | 117 | #define MCMD_READ 0x00000001 /* MII Read */ |
andrewboyson | 59:e0e556c8bd46 | 118 | #define MCMD_SCAN 0x00000002 /* MII Scan continuously */ |
andrewboyson | 59:e0e556c8bd46 | 119 | |
andrewboyson | 59:e0e556c8bd46 | 120 | #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ |
andrewboyson | 59:e0e556c8bd46 | 121 | #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ |
andrewboyson | 59:e0e556c8bd46 | 122 | |
andrewboyson | 59:e0e556c8bd46 | 123 | /* MII Management Address Register */ |
andrewboyson | 59:e0e556c8bd46 | 124 | #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ |
andrewboyson | 59:e0e556c8bd46 | 125 | #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ |
andrewboyson | 59:e0e556c8bd46 | 126 | |
andrewboyson | 59:e0e556c8bd46 | 127 | /* MII Management Indicators Register */ |
andrewboyson | 59:e0e556c8bd46 | 128 | #define MIND_BUSY 0x00000001 /* MII is Busy */ |
andrewboyson | 59:e0e556c8bd46 | 129 | #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ |
andrewboyson | 59:e0e556c8bd46 | 130 | #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ |
andrewboyson | 59:e0e556c8bd46 | 131 | #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ |
andrewboyson | 59:e0e556c8bd46 | 132 | |
andrewboyson | 59:e0e556c8bd46 | 133 | /* Command Register */ |
andrewboyson | 59:e0e556c8bd46 | 134 | #define CR_RX_EN 0x00000001 /* Enable Receive */ |
andrewboyson | 59:e0e556c8bd46 | 135 | #define CR_TX_EN 0x00000002 /* Enable Transmit */ |
andrewboyson | 59:e0e556c8bd46 | 136 | #define CR_REG_RES 0x00000008 /* Reset Host Registers */ |
andrewboyson | 59:e0e556c8bd46 | 137 | #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ |
andrewboyson | 59:e0e556c8bd46 | 138 | #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ |
andrewboyson | 59:e0e556c8bd46 | 139 | #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ |
andrewboyson | 59:e0e556c8bd46 | 140 | #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ |
andrewboyson | 59:e0e556c8bd46 | 141 | #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ |
andrewboyson | 59:e0e556c8bd46 | 142 | #define CR_RMII 0x00000200 /* Reduced MII Interface */ |
andrewboyson | 59:e0e556c8bd46 | 143 | #define CR_FULL_DUP 0x00000400 /* Full Duplex */ |
andrewboyson | 59:e0e556c8bd46 | 144 | |
andrewboyson | 59:e0e556c8bd46 | 145 | /* Status Register */ |
andrewboyson | 59:e0e556c8bd46 | 146 | #define SR_RX_EN 0x00000001 /* Enable Receive */ |
andrewboyson | 59:e0e556c8bd46 | 147 | #define SR_TX_EN 0x00000002 /* Enable Transmit */ |
andrewboyson | 59:e0e556c8bd46 | 148 | |
andrewboyson | 59:e0e556c8bd46 | 149 | /* Transmit Status Vector 0 Register */ |
andrewboyson | 59:e0e556c8bd46 | 150 | #define TSV0_CRC_ERR 0x00000001 /* CRC error */ |
andrewboyson | 59:e0e556c8bd46 | 151 | #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ |
andrewboyson | 59:e0e556c8bd46 | 152 | #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ |
andrewboyson | 59:e0e556c8bd46 | 153 | #define TSV0_DONE 0x00000008 /* Tramsmission Completed */ |
andrewboyson | 59:e0e556c8bd46 | 154 | #define TSV0_MCAST 0x00000010 /* Multicast Destination */ |
andrewboyson | 59:e0e556c8bd46 | 155 | #define TSV0_BCAST 0x00000020 /* Broadcast Destination */ |
andrewboyson | 59:e0e556c8bd46 | 156 | #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ |
andrewboyson | 59:e0e556c8bd46 | 157 | #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ |
andrewboyson | 59:e0e556c8bd46 | 158 | #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ |
andrewboyson | 59:e0e556c8bd46 | 159 | #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ |
andrewboyson | 59:e0e556c8bd46 | 160 | #define TSV0_GIANT 0x00000400 /* Giant Frame */ |
andrewboyson | 59:e0e556c8bd46 | 161 | #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ |
andrewboyson | 59:e0e556c8bd46 | 162 | #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ |
andrewboyson | 59:e0e556c8bd46 | 163 | #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ |
andrewboyson | 59:e0e556c8bd46 | 164 | #define TSV0_PAUSE 0x20000000 /* Pause Frame */ |
andrewboyson | 59:e0e556c8bd46 | 165 | #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ |
andrewboyson | 59:e0e556c8bd46 | 166 | #define TSV0_VLAN 0x80000000 /* VLAN Frame */ |
andrewboyson | 59:e0e556c8bd46 | 167 | |
andrewboyson | 59:e0e556c8bd46 | 168 | /* Transmit Status Vector 1 Register */ |
andrewboyson | 59:e0e556c8bd46 | 169 | #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ |
andrewboyson | 59:e0e556c8bd46 | 170 | #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ |
andrewboyson | 59:e0e556c8bd46 | 171 | |
andrewboyson | 59:e0e556c8bd46 | 172 | /* Receive Status Vector Register */ |
andrewboyson | 59:e0e556c8bd46 | 173 | #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ |
andrewboyson | 59:e0e556c8bd46 | 174 | #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ |
andrewboyson | 59:e0e556c8bd46 | 175 | #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ |
andrewboyson | 59:e0e556c8bd46 | 176 | #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ |
andrewboyson | 59:e0e556c8bd46 | 177 | #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ |
andrewboyson | 59:e0e556c8bd46 | 178 | #define RSV_CRC_ERR 0x00100000 /* CRC Error */ |
andrewboyson | 59:e0e556c8bd46 | 179 | #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ |
andrewboyson | 59:e0e556c8bd46 | 180 | #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ |
andrewboyson | 59:e0e556c8bd46 | 181 | #define RSV_REC_OK 0x00800000 /* Frame Received OK */ |
andrewboyson | 59:e0e556c8bd46 | 182 | #define RSV_MCAST 0x01000000 /* Multicast Frame */ |
andrewboyson | 59:e0e556c8bd46 | 183 | #define RSV_BCAST 0x02000000 /* Broadcast Frame */ |
andrewboyson | 59:e0e556c8bd46 | 184 | #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ |
andrewboyson | 59:e0e556c8bd46 | 185 | #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ |
andrewboyson | 59:e0e556c8bd46 | 186 | #define RSV_PAUSE 0x10000000 /* Pause Frame */ |
andrewboyson | 59:e0e556c8bd46 | 187 | #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ |
andrewboyson | 59:e0e556c8bd46 | 188 | #define RSV_VLAN 0x40000000 /* VLAN Frame */ |
andrewboyson | 59:e0e556c8bd46 | 189 | |
andrewboyson | 59:e0e556c8bd46 | 190 | /* Flow Control Counter Register */ |
andrewboyson | 59:e0e556c8bd46 | 191 | #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ |
andrewboyson | 59:e0e556c8bd46 | 192 | #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ |
andrewboyson | 59:e0e556c8bd46 | 193 | |
andrewboyson | 59:e0e556c8bd46 | 194 | /* Flow Control Status Register */ |
andrewboyson | 59:e0e556c8bd46 | 195 | #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ |
andrewboyson | 59:e0e556c8bd46 | 196 | |
andrewboyson | 59:e0e556c8bd46 | 197 | /* Receive Filter Control Register */ |
andrewboyson | 59:e0e556c8bd46 | 198 | #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ |
andrewboyson | 59:e0e556c8bd46 | 199 | #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ |
andrewboyson | 59:e0e556c8bd46 | 200 | #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ |
andrewboyson | 59:e0e556c8bd46 | 201 | #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ |
andrewboyson | 59:e0e556c8bd46 | 202 | #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ |
andrewboyson | 59:e0e556c8bd46 | 203 | #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ |
andrewboyson | 59:e0e556c8bd46 | 204 | #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ |
andrewboyson | 59:e0e556c8bd46 | 205 | #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ |
andrewboyson | 59:e0e556c8bd46 | 206 | |
andrewboyson | 59:e0e556c8bd46 | 207 | /* Receive Filter WoL Status/Clear Registers */ |
andrewboyson | 59:e0e556c8bd46 | 208 | #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ |
andrewboyson | 59:e0e556c8bd46 | 209 | #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ |
andrewboyson | 59:e0e556c8bd46 | 210 | #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ |
andrewboyson | 59:e0e556c8bd46 | 211 | #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ |
andrewboyson | 59:e0e556c8bd46 | 212 | #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ |
andrewboyson | 59:e0e556c8bd46 | 213 | #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ |
andrewboyson | 59:e0e556c8bd46 | 214 | #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ |
andrewboyson | 59:e0e556c8bd46 | 215 | #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ |
andrewboyson | 59:e0e556c8bd46 | 216 | |
andrewboyson | 59:e0e556c8bd46 | 217 | /* Interrupt Status/Enable/Clear/Set Registers */ |
andrewboyson | 59:e0e556c8bd46 | 218 | #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ |
andrewboyson | 59:e0e556c8bd46 | 219 | #define INT_RX_ERR 0x00000002 /* Receive Error */ |
andrewboyson | 59:e0e556c8bd46 | 220 | #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ |
andrewboyson | 59:e0e556c8bd46 | 221 | #define INT_RX_DONE 0x00000008 /* Receive Done */ |
andrewboyson | 59:e0e556c8bd46 | 222 | #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ |
andrewboyson | 59:e0e556c8bd46 | 223 | #define INT_TX_ERR 0x00000020 /* Transmit Error */ |
andrewboyson | 59:e0e556c8bd46 | 224 | #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ |
andrewboyson | 59:e0e556c8bd46 | 225 | #define INT_TX_DONE 0x00000080 /* Transmit Done */ |
andrewboyson | 59:e0e556c8bd46 | 226 | #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ |
andrewboyson | 59:e0e556c8bd46 | 227 | #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ |
andrewboyson | 59:e0e556c8bd46 | 228 | |
andrewboyson | 59:e0e556c8bd46 | 229 | /* Power Down Register */ |
andrewboyson | 59:e0e556c8bd46 | 230 | #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ |
andrewboyson | 59:e0e556c8bd46 | 231 | |
andrewboyson | 59:e0e556c8bd46 | 232 | /* RX Descriptor Control Word */ |
andrewboyson | 59:e0e556c8bd46 | 233 | #define RCTRL_SIZE 0x000007FF /* Buffer size mask */ |
andrewboyson | 59:e0e556c8bd46 | 234 | #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ |
andrewboyson | 59:e0e556c8bd46 | 235 | |
andrewboyson | 59:e0e556c8bd46 | 236 | /* RX Status Hash CRC Word */ |
andrewboyson | 59:e0e556c8bd46 | 237 | #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ |
andrewboyson | 59:e0e556c8bd46 | 238 | #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ |
andrewboyson | 59:e0e556c8bd46 | 239 | |
andrewboyson | 59:e0e556c8bd46 | 240 | /* RX Status Information Word */ |
andrewboyson | 59:e0e556c8bd46 | 241 | #define RINFO_SIZE 0x000007FF /* Data size in bytes */ |
andrewboyson | 59:e0e556c8bd46 | 242 | #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ |
andrewboyson | 59:e0e556c8bd46 | 243 | #define RINFO_VLAN 0x00080000 /* VLAN Frame */ |
andrewboyson | 59:e0e556c8bd46 | 244 | #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ |
andrewboyson | 59:e0e556c8bd46 | 245 | #define RINFO_MCAST 0x00200000 /* Multicast Frame */ |
andrewboyson | 59:e0e556c8bd46 | 246 | #define RINFO_BCAST 0x00400000 /* Broadcast Frame */ |
andrewboyson | 59:e0e556c8bd46 | 247 | #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ |
andrewboyson | 59:e0e556c8bd46 | 248 | #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ |
andrewboyson | 59:e0e556c8bd46 | 249 | #define RINFO_LEN_ERR 0x02000000 /* Length Error */ |
andrewboyson | 59:e0e556c8bd46 | 250 | #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ |
andrewboyson | 59:e0e556c8bd46 | 251 | #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ |
andrewboyson | 59:e0e556c8bd46 | 252 | #define RINFO_OVERRUN 0x10000000 /* Receive overrun */ |
andrewboyson | 59:e0e556c8bd46 | 253 | #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ |
andrewboyson | 59:e0e556c8bd46 | 254 | #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ |
andrewboyson | 59:e0e556c8bd46 | 255 | #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ |
andrewboyson | 59:e0e556c8bd46 | 256 | #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) |
andrewboyson | 59:e0e556c8bd46 | 257 | |
andrewboyson | 59:e0e556c8bd46 | 258 | /* TX Descriptor Control Word */ |
andrewboyson | 59:e0e556c8bd46 | 259 | #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ |
andrewboyson | 59:e0e556c8bd46 | 260 | #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ |
andrewboyson | 59:e0e556c8bd46 | 261 | #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ |
andrewboyson | 59:e0e556c8bd46 | 262 | #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ |
andrewboyson | 59:e0e556c8bd46 | 263 | #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ |
andrewboyson | 59:e0e556c8bd46 | 264 | #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ |
andrewboyson | 59:e0e556c8bd46 | 265 | #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ |
andrewboyson | 59:e0e556c8bd46 | 266 | |
andrewboyson | 59:e0e556c8bd46 | 267 | /* TX Status Information Word */ |
andrewboyson | 59:e0e556c8bd46 | 268 | #define TINFO_COL_CNT 0x01E00000 /* Collision Count */ |
andrewboyson | 59:e0e556c8bd46 | 269 | #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ |
andrewboyson | 59:e0e556c8bd46 | 270 | #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ |
andrewboyson | 59:e0e556c8bd46 | 271 | #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ |
andrewboyson | 59:e0e556c8bd46 | 272 | #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ |
andrewboyson | 59:e0e556c8bd46 | 273 | #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ |
andrewboyson | 59:e0e556c8bd46 | 274 | #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ |
andrewboyson | 59:e0e556c8bd46 | 275 | #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ |
andrewboyson | 59:e0e556c8bd46 | 276 | |
andrewboyson | 59:e0e556c8bd46 | 277 | /* ENET Device Revision ID */ |
andrewboyson | 59:e0e556c8bd46 | 278 | #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */ |
andrewboyson | 59:e0e556c8bd46 | 279 | |
andrewboyson | 59:e0e556c8bd46 | 280 | /* DP83848C PHY Registers */ |
andrewboyson | 59:e0e556c8bd46 | 281 | #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ |
andrewboyson | 59:e0e556c8bd46 | 282 | #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ |
andrewboyson | 59:e0e556c8bd46 | 283 | #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ |
andrewboyson | 59:e0e556c8bd46 | 284 | #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ |
andrewboyson | 59:e0e556c8bd46 | 285 | #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ |
andrewboyson | 59:e0e556c8bd46 | 286 | #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ |
andrewboyson | 59:e0e556c8bd46 | 287 | #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ |
andrewboyson | 59:e0e556c8bd46 | 288 | #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ |
andrewboyson | 59:e0e556c8bd46 | 289 | |
andrewboyson | 59:e0e556c8bd46 | 290 | /* PHY Extended Registers */ |
andrewboyson | 59:e0e556c8bd46 | 291 | #define PHY_REG_STS 0x10 /* Status Register */ |
andrewboyson | 59:e0e556c8bd46 | 292 | #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ |
andrewboyson | 59:e0e556c8bd46 | 293 | #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ |
andrewboyson | 59:e0e556c8bd46 | 294 | #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ |
andrewboyson | 59:e0e556c8bd46 | 295 | #define PHY_REG_RECR 0x15 /* Receive Error Counter */ |
andrewboyson | 59:e0e556c8bd46 | 296 | #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ |
andrewboyson | 59:e0e556c8bd46 | 297 | #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ |
andrewboyson | 59:e0e556c8bd46 | 298 | #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ |
andrewboyson | 59:e0e556c8bd46 | 299 | #define PHY_REG_PHYCR 0x19 /* PHY Control Register */ |
andrewboyson | 59:e0e556c8bd46 | 300 | #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ |
andrewboyson | 59:e0e556c8bd46 | 301 | #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ |
andrewboyson | 59:e0e556c8bd46 | 302 | #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ |
andrewboyson | 59:e0e556c8bd46 | 303 | |
andrewboyson | 59:e0e556c8bd46 | 304 | #define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */ |
andrewboyson | 59:e0e556c8bd46 | 305 | |
andrewboyson | 59:e0e556c8bd46 | 306 | #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ |
andrewboyson | 59:e0e556c8bd46 | 307 | #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ |
andrewboyson | 59:e0e556c8bd46 | 308 | #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ |
andrewboyson | 59:e0e556c8bd46 | 309 | #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ |
andrewboyson | 59:e0e556c8bd46 | 310 | #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ |
andrewboyson | 59:e0e556c8bd46 | 311 | |
andrewboyson | 59:e0e556c8bd46 | 312 | #define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ |
andrewboyson | 59:e0e556c8bd46 | 313 | #define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */ |
andrewboyson | 59:e0e556c8bd46 | 314 | |
andrewboyson | 59:e0e556c8bd46 | 315 | #define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */ |
andrewboyson | 59:e0e556c8bd46 | 316 | #define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */ |
andrewboyson | 59:e0e556c8bd46 | 317 | #define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */ |
andrewboyson | 59:e0e556c8bd46 | 318 | |
andrewboyson | 59:e0e556c8bd46 | 319 | #define PHY_BMCR_RESET 0x8000 /* PHY Reset */ |
andrewboyson | 59:e0e556c8bd46 | 320 | |
andrewboyson | 59:e0e556c8bd46 | 321 | #define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */ |
andrewboyson | 59:e0e556c8bd46 | 322 | |
andrewboyson | 59:e0e556c8bd46 | 323 | #define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */ |
andrewboyson | 59:e0e556c8bd46 | 324 | #define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */ |