Diff: link/nic.c

Revision:

70:74c11fb71a15

Parent:

67:b89a81c6ed99

Child:

99:962440a00ead

--- a/link/nic.c	Wed Jan 31 19:35:34 2018 +0000
+++ b/link/nic.c	Fri Feb 16 17:31:52 2018 +0000
@@ -1,6 +1,5 @@
 #include <stdint.h>
 
-#include "defs.h"
 #include "nicdefs.h"
 #include "nicmac.h"
 #include "log.h"
@@ -9,7 +8,6 @@
 #define NUM_TX_FRAMES       4           // Number of Tx Frames (== packets) was 2
 
 #define ETH_FRAME_LEN       1536        // Maximum Ethernet Frame Size
-
 /*
 Total length is NUM_RX * ((2 * 4) + (2 * 4) + 0x600) + NUM_TX * ((2 * 4) + (1 * 4) + 0x600)
                     1  *  1552                              1548    
@@ -28,31 +26,31 @@
 
 char* NicGetReceivedPacketOrNull(int* pSize)
 {    
-    if (LPC_EMAC->RxProduceIndex == LPC_EMAC->RxConsumeIndex) return NULL;
+    if (RX_PRODUCE_INDEX == RX_CONSUME_INDEX) return NULL;
         
-    uint32_t info = r_stat[LPC_EMAC->RxConsumeIndex].Info;
+    uint32_t info = r_stat[RX_CONSUME_INDEX].Info;
     *pSize = (info & RINFO_SIZE) + 1 - 4; // exclude checksum
         
-    return (char*)r_buff[LPC_EMAC->RxConsumeIndex];
+    return (char*)r_buff[RX_CONSUME_INDEX];
 }
 void NicReleaseReceivedPacket()
 {
-    if (LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxDescriptorNumber) LPC_EMAC->RxConsumeIndex = 0;
-    else                                                          LPC_EMAC->RxConsumeIndex++;
+    if (RX_CONSUME_INDEX == RX_DESCRIPTOR_NUMBER) RX_CONSUME_INDEX = 0;
+    else                                          RX_CONSUME_INDEX++;
 }
 char* NicGetTransmitPacketOrNull(int* pSize)
 {
-    if (LPC_EMAC->TxConsumeIndex == 0 && LPC_EMAC->TxProduceIndex == LPC_EMAC->TxDescriptorNumber) return NULL;
-    if (LPC_EMAC->TxProduceIndex == LPC_EMAC->TxConsumeIndex - 1)                                  return NULL;
+    if (TX_CONSUME_INDEX == 0 && TX_PRODUCE_INDEX == TX_DESCRIPTOR_NUMBER) return NULL;
+    if (TX_PRODUCE_INDEX == TX_CONSUME_INDEX - 1)                          return NULL;
     *pSize = ETH_FRAME_LEN - 4;
-    return (char*)t_buff[LPC_EMAC->TxProduceIndex];
+    return (char*)t_buff[TX_PRODUCE_INDEX];
 }
 void NicSendTransmitPacket(int size)
 {
     if (size == 0) return;
-    t_desc[LPC_EMAC->TxProduceIndex].Ctrl = (size - 1) | (TCTRL_INT | TCTRL_LAST);
-    if (LPC_EMAC->TxProduceIndex == LPC_EMAC->TxDescriptorNumber) LPC_EMAC->TxProduceIndex = 0;
-    else                                                          LPC_EMAC->TxProduceIndex++;
+    t_desc[TX_PRODUCE_INDEX].Ctrl = (size - 1) | (TCTRL_INT | TCTRL_LAST);
+    if (TX_PRODUCE_INDEX == TX_DESCRIPTOR_NUMBER) TX_PRODUCE_INDEX = 0;
+    else                                          TX_PRODUCE_INDEX++;
 }
 
 static void txdscr_init()
@@ -66,11 +64,11 @@
         t_stat[i].Info   = 0;
     }
 
-    LPC_EMAC->TxDescriptor       = (uint32_t)t_desc;         /* Set EMAC Transmit Descriptor Registers. */
-    LPC_EMAC->TxStatus           = (uint32_t)t_stat;
-    LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAMES - 1;
+    TX_DESCRIPTOR       = (uint32_t)t_desc;         /* Set EMAC Transmit Descriptor Registers. */
+    TX_STATUS           = (uint32_t)t_stat;
+    TX_DESCRIPTOR_NUMBER = NUM_TX_FRAMES - 1;
 
-    LPC_EMAC->TxProduceIndex  = 0;                           /* Tx Descriptors Point to 0 */
+    TX_PRODUCE_INDEX  = 0;                           /* Tx Descriptors Point to 0 */
 }
 
 static void rxdscr_init()
@@ -85,23 +83,23 @@
         r_stat[i].HashCRC = 0;
     }
 
-    LPC_EMAC->RxDescriptor       = (uint32_t)r_desc;        /* Set EMAC Receive Descriptor Registers. */
-    LPC_EMAC->RxStatus           = (uint32_t)r_stat;        //Must be aligned on an 8 byte boundary
-    LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAMES - 1;
+    RX_DESCRIPTOR       = (uint32_t)r_desc;        /* Set EMAC Receive Descriptor Registers. */
+    RX_STATUS           = (uint32_t)r_stat;        //Must be aligned on an 8 byte boundary
+    RX_DESCRIPTOR_NUMBER = NUM_RX_FRAMES - 1;
 
-    LPC_EMAC->RxConsumeIndex  = 0;                          /* Rx Descriptors Point to 0 */
+    RX_CONSUME_INDEX  = 0;                          /* Rx Descriptors Point to 0 */
 }
 static int phy_write(unsigned int PhyReg, unsigned short Data)
 {
     unsigned int timeOut;
 
-    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
-    LPC_EMAC->MWTD = Data;
+    MADR = DP83848C_DEF_ADR | PhyReg;
+    MWTD = Data;
 
     // Wait until operation completed
     for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++)
     {
-        if((LPC_EMAC->MIND & MIND_BUSY) == 0)  return 0;
+        if((MIND & MIND_BUSY) == 0)  return 0;
     }
 
     //Timed out
@@ -112,16 +110,16 @@
 {
     unsigned int timeOut;
 
-    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
-    LPC_EMAC->MCMD = MCMD_READ;
+    MADR = DP83848C_DEF_ADR | PhyReg;
+    MCMD = MCMD_READ;
 
     // Wait until operation completed
     for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++)
     {
-        if((LPC_EMAC->MIND & MIND_BUSY) == 0)
+        if((MIND & MIND_BUSY) == 0)
         {
-            LPC_EMAC->MCMD = 0;
-            return LPC_EMAC->MRDD; // Return a 16-bit value.
+            MCMD = 0;
+            return MRDD; // Return a 16-bit value.
         }
     }
     return -1;
@@ -129,12 +127,12 @@
 
 void NicLinkAddress(char *mac)
 {
-    mac[5] = LPC_EMAC->SA0 >> 8;
-    mac[4] = LPC_EMAC->SA0 & 0xFF;
-    mac[3] = LPC_EMAC->SA1 >> 8;
-    mac[2] = LPC_EMAC->SA1 & 0xFF;
-    mac[1] = LPC_EMAC->SA2 >> 8;
-    mac[0] = LPC_EMAC->SA2 & 0xFF;
+    mac[5] = SA0 >> 8;
+    mac[4] = SA0 & 0xFF;
+    mac[3] = SA1 >> 8;
+    mac[2] = SA1 & 0xFF;
+    mac[1] = SA2 >> 8;
+    mac[0] = SA2 & 0xFF;
 }
 
 void NicLinkSetSpeedDuplex(int speed, int duplex)
@@ -153,24 +151,24 @@
 
     if(phy_data & PHY_STS_DUPLEX)
     {
-        LPC_EMAC->MAC2    |= MAC2_FULL_DUP;
-        LPC_EMAC->Command |=   CR_FULL_DUP;
-        LPC_EMAC->IPGT     = IPGT_FULL_DUP;
+        MAC2    |= MAC2_FULL_DUP;
+        COMMAND |=   CR_FULL_DUP;
+        IPGT     = IPGT_FULL_DUP;
     }
     else
     {
-        LPC_EMAC->MAC2    &= ~MAC2_FULL_DUP;
-        LPC_EMAC->Command &=   ~CR_FULL_DUP;
-        LPC_EMAC->IPGT     =  IPGT_HALF_DUP;
+        MAC2    &= ~MAC2_FULL_DUP;
+        COMMAND &=   ~CR_FULL_DUP;
+        IPGT     =  IPGT_HALF_DUP;
     }
 
     if(phy_data & PHY_STS_SPEED)
     {
-        LPC_EMAC->SUPP &= ~SUPP_SPEED;
+        SUPP &= ~SUPP_SPEED;
     }
     else
     {
-        LPC_EMAC->SUPP |= SUPP_SPEED;
+        SUPP |= SUPP_SPEED;
     }
 }
 
@@ -209,45 +207,41 @@
     char mac[6];
     unsigned int clock = 10; //96,000,000
     
-    // Enable P1 Ethernet Pins.
-    LPC_PINCON->PINSEL2 = 0x50150105;                 
-    LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
-    
     // Reset all EMAC internal modules.
-    LPC_EMAC->MAC1    = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
-    LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
+    MAC1    = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
+    COMMAND = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
     
     // A short delay after reset.
     for(tout = 100; tout; tout--) __nop();             
     
     // Initialize MAC control registers.
-    LPC_EMAC->MAC1 = MAC1_PASS_ALL;                   
-    LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
-    LPC_EMAC->MAXF = ETH_FRAME_LEN;
-    LPC_EMAC->CLRT = CLRT_DEF;
-    LPC_EMAC->IPGR = IPGR_DEF;
+    MAC1 = MAC1_PASS_ALL;                   
+    MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
+    MAXF = ETH_FRAME_LEN;
+    CLRT = CLRT_DEF;
+    IPGR = IPGR_DEF;
     
     // Enable Reduced MII interface.
-    LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;    
+    COMMAND = CR_RMII | CR_PASS_RUNT_FRM;    
     
     // Set clock and reset
-    LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;
-    LPC_EMAC->MCFG |= MCFG_RES_MII;
+    MCFG = (clock << 0x2) & MCFG_CLK_SEL;
+    MCFG |= MCFG_RES_MII;
     
     // A short delay after reset
     for(tout = 100; tout; tout--) __nop();
     
     // Set clock
-    LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;
-    LPC_EMAC->MCMD = 0;
+    MCFG = (clock << 0x2) & MCFG_CLK_SEL;
+    MCMD = 0;
     
     // Reset Reduced MII Logic.
-    LPC_EMAC->SUPP = SUPP_RES_RMII;                    
+    SUPP = SUPP_RES_RMII;                    
     
     // A short delay
     for (tout = 100; tout; tout--) __nop();
     
-    LPC_EMAC->SUPP = 0;
+    SUPP = 0;
     
     //Reset the PHY
     if (phy_reset()) return -1;
@@ -257,24 +251,24 @@
     
     // Set the Ethernet MAC Address registers
     NicMac(mac);
-    LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4];
-    LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2];
-    LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0];
+    SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4];
+    SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2];
+    SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0];
     
     //Initialise DMA descriptors
     txdscr_init();
     rxdscr_init();
     
     // Set filter
-    LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
+    RX_FILTER_CTRL = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
                                                       
     // Disable and clear EMAC interrupts
-    LPC_EMAC->IntEnable = 0;
-    LPC_EMAC->IntClear  = 0xFFFF;
+    INT_ENABLE = 0;
+    INT_CLEAR  = 0xFFFF;
     
     //Enable receive and transmit
-    LPC_EMAC->Command  |= (CR_RX_EN | CR_TX_EN);
-    LPC_EMAC->MAC1     |= MAC1_REC_EN;
+    COMMAND  |= (CR_RX_EN | CR_TX_EN);
+    MAC1     |= MAC1_REC_EN;
     
     //Return success
     return 0;