Andrew Boyson / net

A stack which works with or without an Mbed os library. Provides IPv4 or IPv6 with a full 1500 byte buffer.

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link/nic.c@64:2f5db0839b09, 2018-01-17 (annotated)

Committer:
andrewboyson
Date:
Wed Jan 17 20:44:04 2018 +0000
Revision:
64:2f5db0839b09
Parent:
61:aad055f1b0d1
Child:
67:b89a81c6ed99
Moved power enable out of init

Who changed what in which revision?

UserRevisionLine numberNew contents of line
andrewboyson 60:1d8c7a1e7483 1 #include <stdint.h>
andrewboyson 61:aad055f1b0d1 2
andrewboyson 61:aad055f1b0d1 3 #include "peripherals.h"
andrewboyson 59:e0e556c8bd46 4 #include "nicdefs.h"
andrewboyson 60:1d8c7a1e7483 5 #include "nicmac.h"
andrewboyson 59:e0e556c8bd46 6 #include "log.h"
andrewboyson 59:e0e556c8bd46 7
andrewboyson 61:aad055f1b0d1 8 #define NUM_RX_FRAMES 6 // Number of Rx Frames (== packets) was 3
andrewboyson 61:aad055f1b0d1 9 #define NUM_TX_FRAMES 4 // Number of Tx Frames (== packets) was 2
andrewboyson 59:e0e556c8bd46 10
andrewboyson 59:e0e556c8bd46 11 #define ETH_FRAME_LEN 1536 // Maximum Ethernet Frame Size
andrewboyson 59:e0e556c8bd46 12
andrewboyson 61:aad055f1b0d1 13 /*
andrewboyson 61:aad055f1b0d1 14 Total length is NUM_RX * ((2 * 4) + (2 * 4) + 0x600) + NUM_TX * ((2 * 4) + (1 * 4) + 0x600)
andrewboyson 61:aad055f1b0d1 15 1 * 1552 1548
andrewboyson 61:aad055f1b0d1 16
andrewboyson 61:aad055f1b0d1 17 Can fit up to 10 in total
andrewboyson 61:aad055f1b0d1 18 eg 6 * 1552 + 4 * 1548 = 9312 + 6192 = 15504
andrewboyson 61:aad055f1b0d1 19 */
andrewboyson 61:aad055f1b0d1 20
andrewboyson 61:aad055f1b0d1 21
andrewboyson 61:aad055f1b0d1 22 __attribute__((section("AHBSRAM1"),aligned(4))) static volatile uint8_t r_buff[NUM_RX_FRAMES][ETH_FRAME_LEN];
andrewboyson 61:aad055f1b0d1 23 __attribute__((section("AHBSRAM1"),aligned(4))) static volatile uint8_t t_buff[NUM_TX_FRAMES][ETH_FRAME_LEN];
andrewboyson 61:aad055f1b0d1 24 __attribute__((section("AHBSRAM1"),aligned(4))) static volatile RX_DESC_TypeDef r_desc[NUM_RX_FRAMES];
andrewboyson 61:aad055f1b0d1 25 __attribute__((section("AHBSRAM1"),aligned(8))) static volatile RX_STAT_TypeDef r_stat[NUM_RX_FRAMES]; //Must be aligned on an 8 byte boundary
andrewboyson 61:aad055f1b0d1 26 __attribute__((section("AHBSRAM1"),aligned(4))) static volatile TX_DESC_TypeDef t_desc[NUM_TX_FRAMES];
andrewboyson 61:aad055f1b0d1 27 __attribute__((section("AHBSRAM1"),aligned(4))) static volatile TX_STAT_TypeDef t_stat[NUM_TX_FRAMES];
andrewboyson 59:e0e556c8bd46 28
andrewboyson 59:e0e556c8bd46 29 char* NicGetReceivedPacketOrNull(int* pSize)
andrewboyson 59:e0e556c8bd46 30 {
andrewboyson 59:e0e556c8bd46 31 if (LPC_EMAC->RxProduceIndex == LPC_EMAC->RxConsumeIndex) return NULL;
andrewboyson 59:e0e556c8bd46 32
andrewboyson 59:e0e556c8bd46 33 uint32_t info = r_stat[LPC_EMAC->RxConsumeIndex].Info;
andrewboyson 59:e0e556c8bd46 34 *pSize = (info & RINFO_SIZE) + 1 - 4; // exclude checksum
andrewboyson 59:e0e556c8bd46 35
andrewboyson 59:e0e556c8bd46 36 return (char*)r_buff[LPC_EMAC->RxConsumeIndex];
andrewboyson 59:e0e556c8bd46 37 }
andrewboyson 59:e0e556c8bd46 38 void NicReleaseReceivedPacket()
andrewboyson 59:e0e556c8bd46 39 {
andrewboyson 59:e0e556c8bd46 40 if (LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxDescriptorNumber) LPC_EMAC->RxConsumeIndex = 0;
andrewboyson 59:e0e556c8bd46 41 else LPC_EMAC->RxConsumeIndex++;
andrewboyson 59:e0e556c8bd46 42 }
andrewboyson 59:e0e556c8bd46 43 char* NicGetTransmitPacketOrNull(int* pSize)
andrewboyson 59:e0e556c8bd46 44 {
andrewboyson 59:e0e556c8bd46 45 if (LPC_EMAC->TxConsumeIndex == 0 && LPC_EMAC->TxProduceIndex == LPC_EMAC->TxDescriptorNumber) return NULL;
andrewboyson 59:e0e556c8bd46 46 if (LPC_EMAC->TxProduceIndex == LPC_EMAC->TxConsumeIndex - 1) return NULL;
andrewboyson 59:e0e556c8bd46 47 *pSize = ETH_FRAME_LEN - 4;
andrewboyson 59:e0e556c8bd46 48 return (char*)t_buff[LPC_EMAC->TxProduceIndex];
andrewboyson 59:e0e556c8bd46 49 }
andrewboyson 59:e0e556c8bd46 50 void NicSendTransmitPacket(int size)
andrewboyson 59:e0e556c8bd46 51 {
andrewboyson 59:e0e556c8bd46 52 if (size == 0) return;
andrewboyson 59:e0e556c8bd46 53 t_desc[LPC_EMAC->TxProduceIndex].Ctrl = (size - 1) | (TCTRL_INT | TCTRL_LAST);
andrewboyson 59:e0e556c8bd46 54 if (LPC_EMAC->TxProduceIndex == LPC_EMAC->TxDescriptorNumber) LPC_EMAC->TxProduceIndex = 0;
andrewboyson 59:e0e556c8bd46 55 else LPC_EMAC->TxProduceIndex++;
andrewboyson 59:e0e556c8bd46 56 }
andrewboyson 59:e0e556c8bd46 57
andrewboyson 59:e0e556c8bd46 58 static void txdscr_init()
andrewboyson 59:e0e556c8bd46 59 {
andrewboyson 59:e0e556c8bd46 60 int i;
andrewboyson 59:e0e556c8bd46 61
andrewboyson 59:e0e556c8bd46 62 for(i = 0; i < NUM_TX_FRAMES; i++)
andrewboyson 59:e0e556c8bd46 63 {
andrewboyson 59:e0e556c8bd46 64 t_desc[i].Packet = (uint32_t)&t_buff[i];
andrewboyson 59:e0e556c8bd46 65 t_desc[i].Ctrl = 0;
andrewboyson 59:e0e556c8bd46 66 t_stat[i].Info = 0;
andrewboyson 59:e0e556c8bd46 67 }
andrewboyson 59:e0e556c8bd46 68
andrewboyson 59:e0e556c8bd46 69 LPC_EMAC->TxDescriptor = (uint32_t)t_desc; /* Set EMAC Transmit Descriptor Registers. */
andrewboyson 59:e0e556c8bd46 70 LPC_EMAC->TxStatus = (uint32_t)t_stat;
andrewboyson 59:e0e556c8bd46 71 LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAMES - 1;
andrewboyson 59:e0e556c8bd46 72
andrewboyson 59:e0e556c8bd46 73 LPC_EMAC->TxProduceIndex = 0; /* Tx Descriptors Point to 0 */
andrewboyson 59:e0e556c8bd46 74 }
andrewboyson 59:e0e556c8bd46 75
andrewboyson 59:e0e556c8bd46 76 static void rxdscr_init()
andrewboyson 59:e0e556c8bd46 77 {
andrewboyson 59:e0e556c8bd46 78 int i;
andrewboyson 59:e0e556c8bd46 79
andrewboyson 59:e0e556c8bd46 80 for(i = 0; i < NUM_RX_FRAMES; i++)
andrewboyson 59:e0e556c8bd46 81 {
andrewboyson 59:e0e556c8bd46 82 r_desc[i].Packet = (uint32_t)&r_buff[i];
andrewboyson 59:e0e556c8bd46 83 r_desc[i].Ctrl = RCTRL_INT | (ETH_FRAME_LEN-1);
andrewboyson 59:e0e556c8bd46 84 r_stat[i].Info = 0;
andrewboyson 59:e0e556c8bd46 85 r_stat[i].HashCRC = 0;
andrewboyson 59:e0e556c8bd46 86 }
andrewboyson 59:e0e556c8bd46 87
andrewboyson 59:e0e556c8bd46 88 LPC_EMAC->RxDescriptor = (uint32_t)r_desc; /* Set EMAC Receive Descriptor Registers. */
andrewboyson 59:e0e556c8bd46 89 LPC_EMAC->RxStatus = (uint32_t)r_stat; //Must be aligned on an 8 byte boundary
andrewboyson 59:e0e556c8bd46 90 LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAMES - 1;
andrewboyson 59:e0e556c8bd46 91
andrewboyson 59:e0e556c8bd46 92 LPC_EMAC->RxConsumeIndex = 0; /* Rx Descriptors Point to 0 */
andrewboyson 59:e0e556c8bd46 93 }
andrewboyson 59:e0e556c8bd46 94 static int phy_write(unsigned int PhyReg, unsigned short Data)
andrewboyson 59:e0e556c8bd46 95 {
andrewboyson 59:e0e556c8bd46 96 unsigned int timeOut;
andrewboyson 59:e0e556c8bd46 97
andrewboyson 59:e0e556c8bd46 98 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
andrewboyson 59:e0e556c8bd46 99 LPC_EMAC->MWTD = Data;
andrewboyson 59:e0e556c8bd46 100
andrewboyson 59:e0e556c8bd46 101 // Wait until operation completed
andrewboyson 59:e0e556c8bd46 102 for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++)
andrewboyson 59:e0e556c8bd46 103 {
andrewboyson 59:e0e556c8bd46 104 if((LPC_EMAC->MIND & MIND_BUSY) == 0) return 0;
andrewboyson 59:e0e556c8bd46 105 }
andrewboyson 59:e0e556c8bd46 106
andrewboyson 59:e0e556c8bd46 107 //Timed out
andrewboyson 59:e0e556c8bd46 108 return -1;
andrewboyson 59:e0e556c8bd46 109 }
andrewboyson 59:e0e556c8bd46 110
andrewboyson 59:e0e556c8bd46 111 static int phy_read(unsigned int PhyReg)
andrewboyson 59:e0e556c8bd46 112 {
andrewboyson 59:e0e556c8bd46 113 unsigned int timeOut;
andrewboyson 59:e0e556c8bd46 114
andrewboyson 59:e0e556c8bd46 115 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
andrewboyson 59:e0e556c8bd46 116 LPC_EMAC->MCMD = MCMD_READ;
andrewboyson 59:e0e556c8bd46 117
andrewboyson 59:e0e556c8bd46 118 // Wait until operation completed
andrewboyson 59:e0e556c8bd46 119 for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++)
andrewboyson 59:e0e556c8bd46 120 {
andrewboyson 59:e0e556c8bd46 121 if((LPC_EMAC->MIND & MIND_BUSY) == 0)
andrewboyson 59:e0e556c8bd46 122 {
andrewboyson 59:e0e556c8bd46 123 LPC_EMAC->MCMD = 0;
andrewboyson 59:e0e556c8bd46 124 return LPC_EMAC->MRDD; // Return a 16-bit value.
andrewboyson 59:e0e556c8bd46 125 }
andrewboyson 59:e0e556c8bd46 126 }
andrewboyson 59:e0e556c8bd46 127 return -1;
andrewboyson 59:e0e556c8bd46 128 }
andrewboyson 59:e0e556c8bd46 129
andrewboyson 59:e0e556c8bd46 130 void NicLinkAddress(char *mac)
andrewboyson 59:e0e556c8bd46 131 {
andrewboyson 60:1d8c7a1e7483 132 mac[5] = LPC_EMAC->SA0 >> 8;
andrewboyson 60:1d8c7a1e7483 133 mac[4] = LPC_EMAC->SA0 & 0xFF;
andrewboyson 60:1d8c7a1e7483 134 mac[3] = LPC_EMAC->SA1 >> 8;
andrewboyson 60:1d8c7a1e7483 135 mac[2] = LPC_EMAC->SA1 & 0xFF;
andrewboyson 60:1d8c7a1e7483 136 mac[1] = LPC_EMAC->SA2 >> 8;
andrewboyson 60:1d8c7a1e7483 137 mac[0] = LPC_EMAC->SA2 & 0xFF;
andrewboyson 59:e0e556c8bd46 138 }
andrewboyson 59:e0e556c8bd46 139
andrewboyson 59:e0e556c8bd46 140 void NicLinkSetSpeedDuplex(int speed, int duplex)
andrewboyson 59:e0e556c8bd46 141 {
andrewboyson 59:e0e556c8bd46 142 unsigned short phy_data;
andrewboyson 59:e0e556c8bd46 143 int tout;
andrewboyson 59:e0e556c8bd46 144
andrewboyson 59:e0e556c8bd46 145 if((speed < 0) || (speed > 1)) phy_data = PHY_AUTO_NEG;
andrewboyson 59:e0e556c8bd46 146 else phy_data = (((unsigned short) speed << 13) | ((unsigned short) duplex << 8));
andrewboyson 59:e0e556c8bd46 147
andrewboyson 59:e0e556c8bd46 148 phy_write(PHY_REG_BMCR, phy_data);
andrewboyson 59:e0e556c8bd46 149
andrewboyson 61:aad055f1b0d1 150 for(tout = 100; tout; tout--) __nop(); /* A short delay */
andrewboyson 59:e0e556c8bd46 151
andrewboyson 59:e0e556c8bd46 152 phy_data = phy_read(PHY_REG_STS);
andrewboyson 59:e0e556c8bd46 153
andrewboyson 59:e0e556c8bd46 154 if(phy_data & PHY_STS_DUPLEX)
andrewboyson 59:e0e556c8bd46 155 {
andrewboyson 59:e0e556c8bd46 156 LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
andrewboyson 59:e0e556c8bd46 157 LPC_EMAC->Command |= CR_FULL_DUP;
andrewboyson 59:e0e556c8bd46 158 LPC_EMAC->IPGT = IPGT_FULL_DUP;
andrewboyson 59:e0e556c8bd46 159 }
andrewboyson 59:e0e556c8bd46 160 else
andrewboyson 59:e0e556c8bd46 161 {
andrewboyson 59:e0e556c8bd46 162 LPC_EMAC->MAC2 &= ~MAC2_FULL_DUP;
andrewboyson 59:e0e556c8bd46 163 LPC_EMAC->Command &= ~CR_FULL_DUP;
andrewboyson 59:e0e556c8bd46 164 LPC_EMAC->IPGT = IPGT_HALF_DUP;
andrewboyson 59:e0e556c8bd46 165 }
andrewboyson 59:e0e556c8bd46 166
andrewboyson 59:e0e556c8bd46 167 if(phy_data & PHY_STS_SPEED)
andrewboyson 59:e0e556c8bd46 168 {
andrewboyson 59:e0e556c8bd46 169 LPC_EMAC->SUPP &= ~SUPP_SPEED;
andrewboyson 59:e0e556c8bd46 170 }
andrewboyson 59:e0e556c8bd46 171 else
andrewboyson 59:e0e556c8bd46 172 {
andrewboyson 59:e0e556c8bd46 173 LPC_EMAC->SUPP |= SUPP_SPEED;
andrewboyson 59:e0e556c8bd46 174 }
andrewboyson 59:e0e556c8bd46 175 }
andrewboyson 59:e0e556c8bd46 176
andrewboyson 59:e0e556c8bd46 177 int NicLinkIsUp(void)
andrewboyson 59:e0e556c8bd46 178 {
andrewboyson 59:e0e556c8bd46 179 return (phy_read(PHY_REG_STS) & PHY_STS_LINK);
andrewboyson 59:e0e556c8bd46 180 }
andrewboyson 59:e0e556c8bd46 181 static int phy_reset()
andrewboyson 59:e0e556c8bd46 182 {
andrewboyson 59:e0e556c8bd46 183 int regv, tout;
andrewboyson 59:e0e556c8bd46 184
andrewboyson 59:e0e556c8bd46 185 // perform PHY reset
andrewboyson 59:e0e556c8bd46 186 phy_write(PHY_REG_BMCR, PHY_BMCR_RESET);
andrewboyson 59:e0e556c8bd46 187
andrewboyson 59:e0e556c8bd46 188 // Wait for hardware reset to end.
andrewboyson 59:e0e556c8bd46 189 for(tout = 0x20000; ; tout--)
andrewboyson 59:e0e556c8bd46 190 {
andrewboyson 59:e0e556c8bd46 191 regv = phy_read(PHY_REG_BMCR);
andrewboyson 59:e0e556c8bd46 192 if(regv < 0 || tout == 0) return -1; // Error
andrewboyson 59:e0e556c8bd46 193 if(!(regv & PHY_BMCR_RESET)) break; // Reset complete.
andrewboyson 59:e0e556c8bd46 194 }
andrewboyson 59:e0e556c8bd46 195 uint32_t phy_id = (phy_read(PHY_REG_IDR1) << 16);
andrewboyson 59:e0e556c8bd46 196 phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0);
andrewboyson 59:e0e556c8bd46 197
andrewboyson 59:e0e556c8bd46 198 //Check is the right PHY
andrewboyson 59:e0e556c8bd46 199 if (phy_id != DP83848C_ID)
andrewboyson 59:e0e556c8bd46 200 {
andrewboyson 60:1d8c7a1e7483 201 LogTimeF("Unknown Ethernet PHY (%x)", (unsigned int)phy_id);
andrewboyson 59:e0e556c8bd46 202 return -1;
andrewboyson 59:e0e556c8bd46 203 }
andrewboyson 59:e0e556c8bd46 204 return 0;
andrewboyson 59:e0e556c8bd46 205 }
andrewboyson 59:e0e556c8bd46 206 int NicInit()
andrewboyson 59:e0e556c8bd46 207 {
andrewboyson 59:e0e556c8bd46 208 int tout;
andrewboyson 59:e0e556c8bd46 209 char mac[6];
andrewboyson 59:e0e556c8bd46 210 unsigned int clock = 10; //96,000,000
andrewboyson 59:e0e556c8bd46 211
andrewboyson 59:e0e556c8bd46 212 // Enable P1 Ethernet Pins.
andrewboyson 59:e0e556c8bd46 213 LPC_PINCON->PINSEL2 = 0x50150105;
andrewboyson 59:e0e556c8bd46 214 LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
andrewboyson 59:e0e556c8bd46 215
andrewboyson 59:e0e556c8bd46 216 // Reset all EMAC internal modules.
andrewboyson 59:e0e556c8bd46 217 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
andrewboyson 59:e0e556c8bd46 218 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
andrewboyson 59:e0e556c8bd46 219
andrewboyson 59:e0e556c8bd46 220 // A short delay after reset.
andrewboyson 61:aad055f1b0d1 221 for(tout = 100; tout; tout--) __nop();
andrewboyson 59:e0e556c8bd46 222
andrewboyson 59:e0e556c8bd46 223 // Initialize MAC control registers.
andrewboyson 59:e0e556c8bd46 224 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
andrewboyson 59:e0e556c8bd46 225 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
andrewboyson 59:e0e556c8bd46 226 LPC_EMAC->MAXF = ETH_FRAME_LEN;
andrewboyson 59:e0e556c8bd46 227 LPC_EMAC->CLRT = CLRT_DEF;
andrewboyson 59:e0e556c8bd46 228 LPC_EMAC->IPGR = IPGR_DEF;
andrewboyson 59:e0e556c8bd46 229
andrewboyson 59:e0e556c8bd46 230 // Enable Reduced MII interface.
andrewboyson 59:e0e556c8bd46 231 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
andrewboyson 59:e0e556c8bd46 232
andrewboyson 59:e0e556c8bd46 233 // Set clock and reset
andrewboyson 59:e0e556c8bd46 234 LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;
andrewboyson 59:e0e556c8bd46 235 LPC_EMAC->MCFG |= MCFG_RES_MII;
andrewboyson 59:e0e556c8bd46 236
andrewboyson 59:e0e556c8bd46 237 // A short delay after reset
andrewboyson 61:aad055f1b0d1 238 for(tout = 100; tout; tout--) __nop();
andrewboyson 59:e0e556c8bd46 239
andrewboyson 59:e0e556c8bd46 240 // Set clock
andrewboyson 59:e0e556c8bd46 241 LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;
andrewboyson 59:e0e556c8bd46 242 LPC_EMAC->MCMD = 0;
andrewboyson 59:e0e556c8bd46 243
andrewboyson 59:e0e556c8bd46 244 // Reset Reduced MII Logic.
andrewboyson 59:e0e556c8bd46 245 LPC_EMAC->SUPP = SUPP_RES_RMII;
andrewboyson 59:e0e556c8bd46 246
andrewboyson 59:e0e556c8bd46 247 // A short delay
andrewboyson 61:aad055f1b0d1 248 for (tout = 100; tout; tout--) __nop();
andrewboyson 59:e0e556c8bd46 249
andrewboyson 59:e0e556c8bd46 250 LPC_EMAC->SUPP = 0;
andrewboyson 59:e0e556c8bd46 251
andrewboyson 59:e0e556c8bd46 252 //Reset the PHY
andrewboyson 59:e0e556c8bd46 253 if (phy_reset()) return -1;
andrewboyson 59:e0e556c8bd46 254
andrewboyson 59:e0e556c8bd46 255 //Set the link to auto negotiate
andrewboyson 59:e0e556c8bd46 256 NicLinkSetSpeedDuplex(-1, 0);
andrewboyson 59:e0e556c8bd46 257
andrewboyson 59:e0e556c8bd46 258 // Set the Ethernet MAC Address registers
andrewboyson 60:1d8c7a1e7483 259 NicMac(mac);
andrewboyson 59:e0e556c8bd46 260 LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4];
andrewboyson 59:e0e556c8bd46 261 LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2];
andrewboyson 59:e0e556c8bd46 262 LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0];
andrewboyson 59:e0e556c8bd46 263
andrewboyson 59:e0e556c8bd46 264 //Initialise DMA descriptors
andrewboyson 59:e0e556c8bd46 265 txdscr_init();
andrewboyson 59:e0e556c8bd46 266 rxdscr_init();
andrewboyson 59:e0e556c8bd46 267
andrewboyson 59:e0e556c8bd46 268 // Set filter
andrewboyson 59:e0e556c8bd46 269 LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
andrewboyson 59:e0e556c8bd46 270
andrewboyson 59:e0e556c8bd46 271 // Disable and clear EMAC interrupts
andrewboyson 59:e0e556c8bd46 272 LPC_EMAC->IntEnable = 0;
andrewboyson 59:e0e556c8bd46 273 LPC_EMAC->IntClear = 0xFFFF;
andrewboyson 59:e0e556c8bd46 274
andrewboyson 59:e0e556c8bd46 275 //Enable receive and transmit
andrewboyson 59:e0e556c8bd46 276 LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN);
andrewboyson 59:e0e556c8bd46 277 LPC_EMAC->MAC1 |= MAC1_REC_EN;
andrewboyson 59:e0e556c8bd46 278
andrewboyson 59:e0e556c8bd46 279 //Return success
andrewboyson 59:e0e556c8bd46 280 return 0;
andrewboyson 59:e0e556c8bd46 281 }