Diff: tick.c

Revision:

21:48fe75bcde84

Parent:

20:62e0760cae13

Child:

22:df0b906bda26

diff -r 62e0760cae13 -r 48fe75bcde84 tick.c
--- a/tick.c	Thu Jan 18 18:07:30 2018 +0000
+++ b/tick.c	Fri Jan 19 18:38:15 2018 +0000
@@ -44,7 +44,7 @@
 
 void TickSet(int64_t extClock)
 {
-    uint32_t       tc = LPC_TIM1->TC;
+    uint32_t       tc = LPC_TIM0->TC;
     uint32_t  seconds =       tc / TICK_COUNT_PER_SECOND; //0 to 44
     uint32_t     base =  seconds * TICK_COUNT_PER_SECOND; //0 to 2^32
     uint32_t fraction =       tc % TICK_COUNT_PER_SECOND; //0 to 96,000,000
@@ -62,7 +62,7 @@
 }
 void TickMain()
 {
-    uint32_t sincesecondsBaseCount = LPC_TIM1->TC - secondsBaseCount;
+    uint32_t sincesecondsBaseCount = LPC_TIM0->TC - secondsBaseCount;
     if (sincesecondsBaseCount > TICK_COUNT_PER_SECOND)
     { 
         __disable_irq();
@@ -86,7 +86,7 @@
 
 void TickSaveSnapshotI()
 {
-     timerSnapshot = LPC_TIM1->TC - secondsBaseCount;
+     timerSnapshot = LPC_TIM0->TC - secondsBaseCount;
     nsTickSnapshot = nsTickCount;
     nsFreqSnapshot = nsFreqCount;
     nsTimeSnapshot = nsTimeCount;
@@ -123,7 +123,7 @@
      int64_t freqNs;
      int64_t timeNs;
     
-    timerCount = LPC_TIM1->TC - secondsBaseCount;
+    timerCount = LPC_TIM0->TC - secondsBaseCount;
      tickNs    = nsTickCount;
      freqNs    = nsFreqCount;
      timeNs    = nsTimeCount;
@@ -141,26 +141,26 @@
     slew = 0;
     nsCountIsSet = false;
     
-    LPC_TIM1->TCR     =     2; // 21.6.2 Timer Control Register - Reset TC and PC.
-    LPC_TIM1->CTCR    =     0; // 21.6.3 Count Control Register - Timer mode
-    LPC_TIM1->PR      =     0; // 21.6.5 Prescale register      - Don't prescale 96MHz clock (divide by PR+1).
-    LPC_TIM1->MCR     =     0; // 21.6.8 Match Control Register - no interrupt or reset
-    LPC_TIM1->TCR     =     1; // 21.6.2 Timer Control Register - Enable TC and PC
+    LPC_TIM0->TCR     =     2; // 21.6.2 Timer Control Register - Reset TC and PC.
+    LPC_TIM0->CTCR    =     0; // 21.6.3 Count Control Register - Timer mode
+    LPC_TIM0->PR      =     0; // 21.6.5 Prescale register      - Don't prescale 96MHz clock (divide by PR+1).
+    LPC_TIM0->MCR     =     0; // 21.6.8 Match Control Register - no interrupt or reset
+    LPC_TIM0->TCR     =     1; // 21.6.2 Timer Control Register - Enable TC and PC
 }
 uint32_t TickElapsed(uint32_t* pLastTime)
 {
-    uint32_t thisTime = LPC_TIM1->TC;
+    uint32_t thisTime = LPC_TIM0->TC;
     uint32_t elapsed = thisTime - *pLastTime;    
     *pLastTime = thisTime;
     return elapsed;
 }
 uint32_t TickTimerStart()
 {
-    return LPC_TIM1->TC;
+    return LPC_TIM0->TC;
 }
 uint32_t TickTimerCount(uint32_t startCount)
 {
-    uint32_t thisCount = LPC_TIM1->TC;
+    uint32_t thisCount = LPC_TIM0->TC;
     return thisCount - startCount; 
 }
 uint32_t TickTimerMs(uint32_t startCount)