Diff: timer.c

Revision:

30:212ca42b8779

Parent:

29:9332cf906aad

Child:

31:f6ff7fdb9c67

diff -r 9332cf906aad -r 212ca42b8779 timer.c
--- a/timer.c	Sat Jan 27 12:17:09 2018 +0000
+++ b/timer.c	Fri Feb 16 17:30:46 2018 +0000
@@ -1,27 +1,32 @@
 #include <stdint.h>
 #include <stdbool.h>
 
-#include "defs.h"
 #include "timer.h"
 
+#define TCR  (*((volatile unsigned *) 0x40004004))
+#define TC   (*((volatile unsigned *) 0x40004008))
+#define PR   (*((volatile unsigned *) 0x4000400C))
+#define MCR  (*((volatile unsigned *) 0x40004014))
+#define CTCR (*((volatile unsigned *) 0x40004070))
+
 uint32_t TimerNowCount()
 {
-    return LPC_TIM0->TC;
+    return TC;
 }
 uint32_t TimerIntervalCount(uint32_t* pLastCount)
 {
-    uint32_t thisCount = LPC_TIM0->TC;
+    uint32_t thisCount = TC;
     uint32_t period = thisCount - *pLastCount;    
     *pLastCount = thisCount;
     return period;
 }
 uint32_t TimerSinceCount(uint32_t startCount)
 {
-    return LPC_TIM0->TC - startCount; 
+    return TC - startCount; 
 }
 uint32_t TimerSinceMs(uint32_t startCount)
 {
-    uint32_t count = LPC_TIM0->TC - startCount;
+    uint32_t count = TC - startCount;
     return count / TIMER_COUNT_PER_MS;
 }
 
@@ -29,7 +34,7 @@
 
 uint32_t TimerCountSinceLastSecond()
 {
-    return LPC_TIM0->TC - secondsBaseCount; 
+    return TC - secondsBaseCount; 
 }
 int32_t TimerMultiplyFractionalPart(int32_t value, uint32_t timerCountSinceLastSecond)
 {
@@ -52,9 +57,9 @@
 }
 void TimerInit()
 {    
-    LPC_TIM0->TCR     =     2; // 21.6.2 Timer Control Register - Reset TC and PC.
-    LPC_TIM0->CTCR    =     0; // 21.6.3 Count Control Register - Timer mode
-    LPC_TIM0->PR      =     0; // 21.6.5 Prescale register      - Don't prescale 96MHz clock (divide by PR+1).
-    LPC_TIM0->MCR     =     0; // 21.6.8 Match Control Register - no interrupt or reset
-    LPC_TIM0->TCR     =     1; // 21.6.2 Timer Control Register - Enable TC and PC
+    TCR     =     2; // 21.6.2 Timer Control Register - Reset TC and PC.
+    CTCR    =     0; // 21.6.3 Count Control Register - Timer mode
+    PR      =     0; // 21.6.5 Prescale register      - Don't prescale 96MHz clock (divide by PR+1).
+    MCR     =     0; // 21.6.8 Match Control Register - no interrupt or reset
+    TCR     =     1; // 21.6.2 Timer Control Register - Enable TC and PC
 }