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Dependents: oldheating gps motorhome heating
timer.c@34:aeb58975e61a, 2018-11-30 (annotated)
- Committer:
- andrewboyson
- Date:
- Fri Nov 30 19:23:48 2018 +0000
- Revision:
- 34:aeb58975e61a
- Parent:
- 33:b9e3c06e7dab
Corrected unsigned comparison in TimerIntervalHasElapsed.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| andrewboyson | 24:6c9833e2a049 | 1 | #include <stdint.h> |
| andrewboyson | 26:0421132e6eaf | 2 | #include <stdbool.h> |
| andrewboyson | 24:6c9833e2a049 | 3 | |
| andrewboyson | 25:81014a201736 | 4 | #include "timer.h" |
| andrewboyson | 33:b9e3c06e7dab | 5 | #include "tick.h" |
| andrewboyson | 24:6c9833e2a049 | 6 | |
| andrewboyson | 30:212ca42b8779 | 7 | #define TCR (*((volatile unsigned *) 0x40004004)) |
| andrewboyson | 30:212ca42b8779 | 8 | #define TC (*((volatile unsigned *) 0x40004008)) |
| andrewboyson | 30:212ca42b8779 | 9 | #define PR (*((volatile unsigned *) 0x4000400C)) |
| andrewboyson | 30:212ca42b8779 | 10 | #define MCR (*((volatile unsigned *) 0x40004014)) |
| andrewboyson | 30:212ca42b8779 | 11 | #define CTCR (*((volatile unsigned *) 0x40004070)) |
| andrewboyson | 30:212ca42b8779 | 12 | |
| andrewboyson | 26:0421132e6eaf | 13 | uint32_t TimerNowCount() |
| andrewboyson | 26:0421132e6eaf | 14 | { |
| andrewboyson | 30:212ca42b8779 | 15 | return TC; |
| andrewboyson | 24:6c9833e2a049 | 16 | } |
| andrewboyson | 26:0421132e6eaf | 17 | uint32_t TimerIntervalCount(uint32_t* pLastCount) |
| andrewboyson | 24:6c9833e2a049 | 18 | { |
| andrewboyson | 30:212ca42b8779 | 19 | uint32_t thisCount = TC; |
| andrewboyson | 24:6c9833e2a049 | 20 | uint32_t period = thisCount - *pLastCount; |
| andrewboyson | 24:6c9833e2a049 | 21 | *pLastCount = thisCount; |
| andrewboyson | 24:6c9833e2a049 | 22 | return period; |
| andrewboyson | 24:6c9833e2a049 | 23 | } |
| andrewboyson | 24:6c9833e2a049 | 24 | uint32_t TimerSinceCount(uint32_t startCount) |
| andrewboyson | 24:6c9833e2a049 | 25 | { |
| andrewboyson | 30:212ca42b8779 | 26 | return TC - startCount; |
| andrewboyson | 24:6c9833e2a049 | 27 | } |
| andrewboyson | 24:6c9833e2a049 | 28 | uint32_t TimerSinceMs(uint32_t startCount) |
| andrewboyson | 24:6c9833e2a049 | 29 | { |
| andrewboyson | 30:212ca42b8779 | 30 | uint32_t count = TC - startCount; |
| andrewboyson | 25:81014a201736 | 31 | return count / TIMER_COUNT_PER_MS; |
| andrewboyson | 24:6c9833e2a049 | 32 | } |
| andrewboyson | 26:0421132e6eaf | 33 | |
| andrewboyson | 33:b9e3c06e7dab | 34 | bool TimerIntervalHasElapsed(uint32_t* pBaseCount, uint32_t intervalCount) |
| andrewboyson | 26:0421132e6eaf | 35 | { |
| andrewboyson | 34:aeb58975e61a | 36 | if (TC - *pBaseCount > intervalCount) //All unsigned wrap around arithmetic |
| andrewboyson | 33:b9e3c06e7dab | 37 | { |
| andrewboyson | 33:b9e3c06e7dab | 38 | *pBaseCount += intervalCount; |
| andrewboyson | 33:b9e3c06e7dab | 39 | return true; |
| andrewboyson | 33:b9e3c06e7dab | 40 | } |
| andrewboyson | 33:b9e3c06e7dab | 41 | return false; |
| andrewboyson | 26:0421132e6eaf | 42 | } |
| andrewboyson | 33:b9e3c06e7dab | 43 | |
| andrewboyson | 33:b9e3c06e7dab | 44 | int32_t TimerMultiplyFractionalPart(int32_t value, uint32_t timerCountSinceStart, uint32_t interval) |
| andrewboyson | 26:0421132e6eaf | 45 | { |
| andrewboyson | 26:0421132e6eaf | 46 | int64_t fraction; |
| andrewboyson | 26:0421132e6eaf | 47 | |
| andrewboyson | 33:b9e3c06e7dab | 48 | fraction = timerCountSinceStart; |
| andrewboyson | 26:0421132e6eaf | 49 | fraction <<= 32; |
| andrewboyson | 33:b9e3c06e7dab | 50 | fraction /= interval; |
| andrewboyson | 26:0421132e6eaf | 51 | |
| andrewboyson | 26:0421132e6eaf | 52 | return (value * fraction) >> 32; |
| andrewboyson | 26:0421132e6eaf | 53 | } |
| andrewboyson | 26:0421132e6eaf | 54 | |
| andrewboyson | 26:0421132e6eaf | 55 | void TimerInit() |
| andrewboyson | 26:0421132e6eaf | 56 | { |
| andrewboyson | 30:212ca42b8779 | 57 | TCR = 2; // 21.6.2 Timer Control Register - Reset TC and PC. |
| andrewboyson | 30:212ca42b8779 | 58 | CTCR = 0; // 21.6.3 Count Control Register - Timer mode |
| andrewboyson | 30:212ca42b8779 | 59 | PR = 0; // 21.6.5 Prescale register - Don't prescale 96MHz clock (divide by PR+1). |
| andrewboyson | 30:212ca42b8779 | 60 | MCR = 0; // 21.6.8 Match Control Register - no interrupt or reset |
| andrewboyson | 30:212ca42b8779 | 61 | TCR = 1; // 21.6.2 Timer Control Register - Enable TC and PC |
| andrewboyson | 26:0421132e6eaf | 62 | } |