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targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_stm32f4xx.c@167:e84263d55307, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:46:44 2017 +0100
Revision:
167:e84263d55307
Parent:
160:d5399cc887bb 
This updates the lib to the mbed lib v 145

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file system_stm32f4xx.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V2.6.1
AnnaBridge 167:e84263d55307 6 * @date 14-February-2017
<> 144:ef7eb2e8f9f7 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides two functions and one global variable to be called from
<> 144:ef7eb2e8f9f7 10 * user application:
<> 144:ef7eb2e8f9f7 11 * - SystemInit(): This function is called at startup just after reset and
<> 144:ef7eb2e8f9f7 12 * before branch to main program. This call is made inside
<> 144:ef7eb2e8f9f7 13 * the "startup_stm32f4xx.s" file.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
<> 144:ef7eb2e8f9f7 16 * by the user application to setup the SysTick
<> 144:ef7eb2e8f9f7 17 * timer or configure other parameters.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
<> 144:ef7eb2e8f9f7 20 * be called whenever the core clock is changed
<> 144:ef7eb2e8f9f7 21 * during program execution.
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * This file configures the system clock as follows:
<> 144:ef7eb2e8f9f7 24 *--------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25 * System clock source | PLL_HSE_XTAL | PLL_HSE_XTAL
<> 144:ef7eb2e8f9f7 26 * | (external 8 MHz clock) | (external 8 MHz clock)
<> 144:ef7eb2e8f9f7 27 *--------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28 * SYSCLK(MHz) | 168 | 180
<> 144:ef7eb2e8f9f7 29 *--------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30 * AHBCLK (MHz) | 168 | 180
<> 144:ef7eb2e8f9f7 31 *--------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 32 * APB1CLK (MHz) | 42 | 45
<> 144:ef7eb2e8f9f7 33 *--------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 34 * APB2CLK (MHz) | 84 | 90
<> 144:ef7eb2e8f9f7 35 *--------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 36 * USB capable (48 MHz precise clock) | YES | NO
<> 144:ef7eb2e8f9f7 37 *--------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 38 ******************************************************************************
<> 144:ef7eb2e8f9f7 39 * @attention
<> 144:ef7eb2e8f9f7 40 *
<> 160:d5399cc887bb 41 * <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 42 *
<> 144:ef7eb2e8f9f7 43 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 44 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 45 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 46 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 47 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 48 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 49 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 50 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 51 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 52 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 53 *
<> 144:ef7eb2e8f9f7 54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 55 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 57 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 60 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 61 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 64 *
<> 144:ef7eb2e8f9f7 65 ******************************************************************************
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 /** @addtogroup CMSIS
<> 144:ef7eb2e8f9f7 69 * @{
<> 144:ef7eb2e8f9f7 70 */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 /** @addtogroup stm32f4xx_system
<> 144:ef7eb2e8f9f7 73 * @{
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /** @addtogroup STM32F4xx_System_Private_Includes
<> 144:ef7eb2e8f9f7 77 * @{
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 #include "stm32f4xx.h"
<> 160:d5399cc887bb 82 #include "nvic_addr.h"
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 #if !defined (HSE_VALUE)
<> 144:ef7eb2e8f9f7 85 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
<> 144:ef7eb2e8f9f7 86 #endif /* HSE_VALUE */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 #if !defined (HSI_VALUE)
<> 144:ef7eb2e8f9f7 89 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
<> 144:ef7eb2e8f9f7 90 #endif /* HSI_VALUE */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /**
<> 144:ef7eb2e8f9f7 93 * @}
<> 144:ef7eb2e8f9f7 94 */
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
<> 144:ef7eb2e8f9f7 97 * @{
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /**
<> 144:ef7eb2e8f9f7 101 * @}
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 /** @addtogroup STM32F4xx_System_Private_Defines
<> 144:ef7eb2e8f9f7 105 * @{
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /************************* Miscellaneous Configuration ************************/
<> 144:ef7eb2e8f9f7 109 /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
<> 144:ef7eb2e8f9f7 110 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
<> 144:ef7eb2e8f9f7 111 || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
<> 144:ef7eb2e8f9f7 112 || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
<> 144:ef7eb2e8f9f7 113 /* #define DATA_IN_ExtSRAM */
<> 144:ef7eb2e8f9f7 114 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
<> 144:ef7eb2e8f9f7 115 STM32F412Zx || STM32F412Vx */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
<> 144:ef7eb2e8f9f7 118 || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 119 /* #define DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 120 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
<> 144:ef7eb2e8f9f7 121 STM32F479xx */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /*!< Uncomment the following line if you need to relocate your vector Table in
<> 144:ef7eb2e8f9f7 124 Internal SRAM. */
<> 144:ef7eb2e8f9f7 125 /* #define VECT_TAB_SRAM */
<> 144:ef7eb2e8f9f7 126 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
<> 144:ef7eb2e8f9f7 127 This value must be a multiple of 0x200. */
<> 144:ef7eb2e8f9f7 128 /******************************************************************************/
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /**
<> 144:ef7eb2e8f9f7 131 * @}
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /** @addtogroup STM32F4xx_System_Private_Macros
<> 144:ef7eb2e8f9f7 135 * @{
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /* Select the SYSCLOCK to start with (0=OFF, 1=ON) */
<> 144:ef7eb2e8f9f7 139 #define USE_SYSCLOCK_168 (1) /* Use external 8MHz xtal and sets SYSCLK to 168MHz */
<> 144:ef7eb2e8f9f7 140 #define USE_SYSCLOCK_180 (0) /* Use external 8MHz xtal and sets SYSCLK to 180MHz */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /**
<> 144:ef7eb2e8f9f7 143 * @}
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /** @addtogroup STM32F4xx_System_Private_Variables
<> 144:ef7eb2e8f9f7 147 * @{
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149 /* This variable is updated in three ways:
<> 144:ef7eb2e8f9f7 150 1) by calling CMSIS function SystemCoreClockUpdate()
<> 144:ef7eb2e8f9f7 151 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
<> 144:ef7eb2e8f9f7 152 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
<> 144:ef7eb2e8f9f7 153 Note: If you use this function to configure the system clock; then there
<> 144:ef7eb2e8f9f7 154 is no need to call the 2 first functions listed above, since SystemCoreClock
<> 144:ef7eb2e8f9f7 155 variable is updated automatically.
<> 144:ef7eb2e8f9f7 156 */
<> 144:ef7eb2e8f9f7 157 uint32_t SystemCoreClock = 168000000;
<> 144:ef7eb2e8f9f7 158 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
AnnaBridge 167:e84263d55307 159 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
<> 144:ef7eb2e8f9f7 160 /**
<> 144:ef7eb2e8f9f7 161 * @}
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
<> 144:ef7eb2e8f9f7 165 * @{
<> 144:ef7eb2e8f9f7 166 */
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 169 static void SystemInit_ExtMemCtl(void);
<> 144:ef7eb2e8f9f7 170 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 void SetSysClock(void);
<> 144:ef7eb2e8f9f7 173 /**
<> 144:ef7eb2e8f9f7 174 * @}
<> 144:ef7eb2e8f9f7 175 */
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /** @addtogroup STM32F4xx_System_Private_Functions
<> 144:ef7eb2e8f9f7 178 * @{
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /**
<> 144:ef7eb2e8f9f7 182 * @brief Setup the microcontroller system
<> 144:ef7eb2e8f9f7 183 * Initialize the FPU setting, vector table location and External memory
<> 144:ef7eb2e8f9f7 184 * configuration.
<> 144:ef7eb2e8f9f7 185 * @param None
<> 144:ef7eb2e8f9f7 186 * @retval None
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188 void SystemInit(void)
<> 144:ef7eb2e8f9f7 189 {
<> 144:ef7eb2e8f9f7 190 /* Reset the RCC clock configuration to the default reset state ------------*/
<> 144:ef7eb2e8f9f7 191 /* Set HSION bit */
<> 144:ef7eb2e8f9f7 192 RCC->CR |= (uint32_t)0x00000001;
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /* Reset CFGR register */
<> 144:ef7eb2e8f9f7 195 RCC->CFGR = 0x00000000;
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /* Reset HSEON, CSSON and PLLON bits */
<> 144:ef7eb2e8f9f7 198 RCC->CR &= (uint32_t)0xFEF6FFFF;
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /* Reset PLLCFGR register */
<> 144:ef7eb2e8f9f7 201 RCC->PLLCFGR = 0x24003010;
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /* Reset HSEBYP bit */
<> 144:ef7eb2e8f9f7 204 RCC->CR &= (uint32_t)0xFFFBFFFF;
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /* Disable all interrupts */
<> 144:ef7eb2e8f9f7 207 RCC->CIR = 0x00000000;
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 210 SystemInit_ExtMemCtl();
<> 144:ef7eb2e8f9f7 211 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 }
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /**
<> 144:ef7eb2e8f9f7 216 * @brief Update SystemCoreClock variable according to Clock Register Values.
<> 144:ef7eb2e8f9f7 217 * The SystemCoreClock variable contains the core clock (HCLK), it can
<> 144:ef7eb2e8f9f7 218 * be used by the user application to setup the SysTick timer or configure
<> 144:ef7eb2e8f9f7 219 * other parameters.
<> 144:ef7eb2e8f9f7 220 *
<> 144:ef7eb2e8f9f7 221 * @note Each time the core clock (HCLK) changes, this function must be called
<> 144:ef7eb2e8f9f7 222 * to update SystemCoreClock variable value. Otherwise, any configuration
<> 144:ef7eb2e8f9f7 223 * based on this variable will be incorrect.
<> 144:ef7eb2e8f9f7 224 *
<> 144:ef7eb2e8f9f7 225 * @note - The system frequency computed by this function is not the real
<> 144:ef7eb2e8f9f7 226 * frequency in the chip. It is calculated based on the predefined
<> 144:ef7eb2e8f9f7 227 * constant and the selected clock source:
<> 144:ef7eb2e8f9f7 228 *
<> 144:ef7eb2e8f9f7 229 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
<> 144:ef7eb2e8f9f7 230 *
<> 144:ef7eb2e8f9f7 231 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
<> 144:ef7eb2e8f9f7 232 *
<> 144:ef7eb2e8f9f7 233 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
<> 144:ef7eb2e8f9f7 234 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
<> 144:ef7eb2e8f9f7 235 *
<> 144:ef7eb2e8f9f7 236 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
<> 144:ef7eb2e8f9f7 237 * 16 MHz) but the real value may vary depending on the variations
<> 144:ef7eb2e8f9f7 238 * in voltage and temperature.
<> 144:ef7eb2e8f9f7 239 *
<> 144:ef7eb2e8f9f7 240 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
<> 144:ef7eb2e8f9f7 241 * depends on the application requirements), user has to ensure that HSE_VALUE
<> 144:ef7eb2e8f9f7 242 * is same as the real frequency of the crystal used. Otherwise, this function
<> 144:ef7eb2e8f9f7 243 * may have wrong result.
<> 144:ef7eb2e8f9f7 244 *
<> 144:ef7eb2e8f9f7 245 * - The result of this function could be not correct when using fractional
<> 144:ef7eb2e8f9f7 246 * value for HSE crystal.
<> 144:ef7eb2e8f9f7 247 *
<> 144:ef7eb2e8f9f7 248 * @param None
<> 144:ef7eb2e8f9f7 249 * @retval None
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251 void SystemCoreClockUpdate(void)
<> 144:ef7eb2e8f9f7 252 {
<> 144:ef7eb2e8f9f7 253 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /* Get SYSCLK source -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 256 tmp = RCC->CFGR & RCC_CFGR_SWS;
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 switch (tmp)
<> 144:ef7eb2e8f9f7 259 {
<> 144:ef7eb2e8f9f7 260 case 0x00: /* HSI used as system clock source */
<> 144:ef7eb2e8f9f7 261 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 262 break;
<> 144:ef7eb2e8f9f7 263 case 0x04: /* HSE used as system clock source */
<> 144:ef7eb2e8f9f7 264 SystemCoreClock = HSE_VALUE;
<> 144:ef7eb2e8f9f7 265 break;
<> 144:ef7eb2e8f9f7 266 case 0x08: /* PLL used as system clock source */
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
<> 144:ef7eb2e8f9f7 269 SYSCLK = PLL_VCO / PLL_P
<> 144:ef7eb2e8f9f7 270 */
<> 144:ef7eb2e8f9f7 271 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
<> 144:ef7eb2e8f9f7 272 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 if (pllsource != 0)
<> 144:ef7eb2e8f9f7 275 {
<> 144:ef7eb2e8f9f7 276 /* HSE used as PLL clock source */
<> 144:ef7eb2e8f9f7 277 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
<> 144:ef7eb2e8f9f7 278 }
<> 144:ef7eb2e8f9f7 279 else
<> 144:ef7eb2e8f9f7 280 {
<> 144:ef7eb2e8f9f7 281 /* HSI used as PLL clock source */
<> 144:ef7eb2e8f9f7 282 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
<> 144:ef7eb2e8f9f7 286 SystemCoreClock = pllvco/pllp;
<> 144:ef7eb2e8f9f7 287 break;
<> 144:ef7eb2e8f9f7 288 default:
<> 144:ef7eb2e8f9f7 289 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 290 break;
<> 144:ef7eb2e8f9f7 291 }
<> 144:ef7eb2e8f9f7 292 /* Compute HCLK frequency --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 293 /* Get HCLK prescaler */
<> 144:ef7eb2e8f9f7 294 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
<> 144:ef7eb2e8f9f7 295 /* HCLK frequency */
<> 144:ef7eb2e8f9f7 296 SystemCoreClock >>= tmp;
<> 144:ef7eb2e8f9f7 297 }
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 #if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
AnnaBridge 167:e84263d55307 300 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
AnnaBridge 167:e84263d55307 301 || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 302 /**
<> 144:ef7eb2e8f9f7 303 * @brief Setup the external memory controller.
<> 144:ef7eb2e8f9f7 304 * Called in startup_stm32f4xx.s before jump to main.
<> 144:ef7eb2e8f9f7 305 * This function configures the external memories (SRAM/SDRAM)
<> 144:ef7eb2e8f9f7 306 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
<> 144:ef7eb2e8f9f7 307 * @param None
<> 144:ef7eb2e8f9f7 308 * @retval None
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310 void SystemInit_ExtMemCtl(void)
<> 144:ef7eb2e8f9f7 311 {
<> 144:ef7eb2e8f9f7 312 __IO uint32_t tmp = 0x00;
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 register uint32_t tmpreg = 0, timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 315 register __IO uint32_t index;
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
<> 144:ef7eb2e8f9f7 318 RCC->AHB1ENR |= 0x000001F8;
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 321 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /* Connect PDx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 324 GPIOD->AFR[0] = 0x00CCC0CC;
<> 144:ef7eb2e8f9f7 325 GPIOD->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 326 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 327 GPIOD->MODER = 0xAAAA0A8A;
<> 144:ef7eb2e8f9f7 328 /* Configure PDx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 329 GPIOD->OSPEEDR = 0xFFFF0FCF;
<> 144:ef7eb2e8f9f7 330 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 331 GPIOD->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 332 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 333 GPIOD->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /* Connect PEx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 336 GPIOE->AFR[0] = 0xC00CC0CC;
<> 144:ef7eb2e8f9f7 337 GPIOE->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 338 /* Configure PEx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 339 GPIOE->MODER = 0xAAAA828A;
<> 144:ef7eb2e8f9f7 340 /* Configure PEx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 341 GPIOE->OSPEEDR = 0xFFFFC3CF;
<> 144:ef7eb2e8f9f7 342 /* Configure PEx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 343 GPIOE->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 344 /* No pull-up, pull-down for PEx pins */
<> 144:ef7eb2e8f9f7 345 GPIOE->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /* Connect PFx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 348 GPIOF->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 349 GPIOF->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 350 /* Configure PFx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 351 GPIOF->MODER = 0xAA800AAA;
<> 144:ef7eb2e8f9f7 352 /* Configure PFx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 353 GPIOF->OSPEEDR = 0xAA800AAA;
<> 144:ef7eb2e8f9f7 354 /* Configure PFx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 355 GPIOF->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 356 /* No pull-up, pull-down for PFx pins */
<> 144:ef7eb2e8f9f7 357 GPIOF->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /* Connect PGx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 360 GPIOG->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 361 GPIOG->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 362 /* Configure PGx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 363 GPIOG->MODER = 0xAAAAAAAA;
<> 144:ef7eb2e8f9f7 364 /* Configure PGx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 365 GPIOG->OSPEEDR = 0xAAAAAAAA;
<> 144:ef7eb2e8f9f7 366 /* Configure PGx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 367 GPIOG->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 368 /* No pull-up, pull-down for PGx pins */
<> 144:ef7eb2e8f9f7 369 GPIOG->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /* Connect PHx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 372 GPIOH->AFR[0] = 0x00C0CC00;
<> 144:ef7eb2e8f9f7 373 GPIOH->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 374 /* Configure PHx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 375 GPIOH->MODER = 0xAAAA08A0;
<> 144:ef7eb2e8f9f7 376 /* Configure PHx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 377 GPIOH->OSPEEDR = 0xAAAA08A0;
<> 144:ef7eb2e8f9f7 378 /* Configure PHx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 379 GPIOH->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 380 /* No pull-up, pull-down for PHx pins */
<> 144:ef7eb2e8f9f7 381 GPIOH->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /* Connect PIx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 384 GPIOI->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 385 GPIOI->AFR[1] = 0x00000CC0;
<> 144:ef7eb2e8f9f7 386 /* Configure PIx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 387 GPIOI->MODER = 0x0028AAAA;
<> 144:ef7eb2e8f9f7 388 /* Configure PIx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 389 GPIOI->OSPEEDR = 0x0028AAAA;
<> 144:ef7eb2e8f9f7 390 /* Configure PIx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 391 GPIOI->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 392 /* No pull-up, pull-down for PIx pins */
<> 144:ef7eb2e8f9f7 393 GPIOI->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /*-- FMC Configuration -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 396 /* Enable the FMC interface clock */
<> 144:ef7eb2e8f9f7 397 RCC->AHB3ENR |= 0x00000001;
<> 144:ef7eb2e8f9f7 398 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 399 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 FMC_Bank5_6->SDCR[0] = 0x000019E4;
<> 144:ef7eb2e8f9f7 402 FMC_Bank5_6->SDTR[0] = 0x01115351;
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /* SDRAM initialization sequence */
<> 144:ef7eb2e8f9f7 405 /* Clock enable command */
<> 144:ef7eb2e8f9f7 406 FMC_Bank5_6->SDCMR = 0x00000011;
<> 144:ef7eb2e8f9f7 407 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 408 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 409 {
<> 144:ef7eb2e8f9f7 410 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 411 }
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /* Delay */
<> 144:ef7eb2e8f9f7 414 for (index = 0; index<1000; index++);
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /* PALL command */
<> 144:ef7eb2e8f9f7 417 FMC_Bank5_6->SDCMR = 0x00000012;
<> 144:ef7eb2e8f9f7 418 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 419 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 420 {
<> 144:ef7eb2e8f9f7 421 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 422 }
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /* Auto refresh command */
<> 144:ef7eb2e8f9f7 425 FMC_Bank5_6->SDCMR = 0x00000073;
<> 144:ef7eb2e8f9f7 426 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 427 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 428 {
<> 144:ef7eb2e8f9f7 429 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 430 }
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /* MRD register program */
<> 144:ef7eb2e8f9f7 433 FMC_Bank5_6->SDCMR = 0x00046014;
<> 144:ef7eb2e8f9f7 434 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 435 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 436 {
<> 144:ef7eb2e8f9f7 437 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 438 }
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 /* Set refresh count */
<> 144:ef7eb2e8f9f7 441 tmpreg = FMC_Bank5_6->SDRTR;
<> 144:ef7eb2e8f9f7 442 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /* Disable write protection */
<> 144:ef7eb2e8f9f7 445 tmpreg = FMC_Bank5_6->SDCR[0];
<> 144:ef7eb2e8f9f7 446 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
<> 144:ef7eb2e8f9f7 449 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 450 FMC_Bank1->BTCR[2] = 0x00001011;
<> 144:ef7eb2e8f9f7 451 FMC_Bank1->BTCR[3] = 0x00000201;
<> 144:ef7eb2e8f9f7 452 FMC_Bank1E->BWTR[2] = 0x0fffffff;
<> 144:ef7eb2e8f9f7 453 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
<> 144:ef7eb2e8f9f7 454 #if defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 455 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 456 FMC_Bank1->BTCR[2] = 0x00001091;
<> 144:ef7eb2e8f9f7 457 FMC_Bank1->BTCR[3] = 0x00110212;
<> 144:ef7eb2e8f9f7 458 FMC_Bank1E->BWTR[2] = 0x0fffffff;
<> 144:ef7eb2e8f9f7 459 #endif /* STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 (void)(tmp);
<> 144:ef7eb2e8f9f7 462 }
<> 144:ef7eb2e8f9f7 463 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 464 #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 465 /**
<> 144:ef7eb2e8f9f7 466 * @brief Setup the external memory controller.
<> 144:ef7eb2e8f9f7 467 * Called in startup_stm32f4xx.s before jump to main.
<> 144:ef7eb2e8f9f7 468 * This function configures the external memories (SRAM/SDRAM)
<> 144:ef7eb2e8f9f7 469 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
<> 144:ef7eb2e8f9f7 470 * @param None
<> 144:ef7eb2e8f9f7 471 * @retval None
<> 144:ef7eb2e8f9f7 472 */
<> 144:ef7eb2e8f9f7 473 void SystemInit_ExtMemCtl(void)
<> 144:ef7eb2e8f9f7 474 {
<> 144:ef7eb2e8f9f7 475 __IO uint32_t tmp = 0x00;
<> 144:ef7eb2e8f9f7 476 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
<> 144:ef7eb2e8f9f7 477 || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 478 #if defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 479 register uint32_t tmpreg = 0, timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 480 register __IO uint32_t index;
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 483 /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
<> 144:ef7eb2e8f9f7 484 clock */
<> 144:ef7eb2e8f9f7 485 RCC->AHB1ENR |= 0x0000007D;
<> 144:ef7eb2e8f9f7 486 #else
<> 144:ef7eb2e8f9f7 487 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
<> 144:ef7eb2e8f9f7 488 clock */
<> 144:ef7eb2e8f9f7 489 RCC->AHB1ENR |= 0x000001F8;
<> 144:ef7eb2e8f9f7 490 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 491 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 492 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 495 /* Connect PAx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 496 GPIOA->AFR[0] |= 0xC0000000;
<> 144:ef7eb2e8f9f7 497 GPIOA->AFR[1] |= 0x00000000;
<> 144:ef7eb2e8f9f7 498 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 499 GPIOA->MODER |= 0x00008000;
<> 144:ef7eb2e8f9f7 500 /* Configure PDx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 501 GPIOA->OSPEEDR |= 0x00008000;
<> 144:ef7eb2e8f9f7 502 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 503 GPIOA->OTYPER |= 0x00000000;
<> 144:ef7eb2e8f9f7 504 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 505 GPIOA->PUPDR |= 0x00000000;
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /* Connect PCx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 508 GPIOC->AFR[0] |= 0x00CC0000;
<> 144:ef7eb2e8f9f7 509 GPIOC->AFR[1] |= 0x00000000;
<> 144:ef7eb2e8f9f7 510 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 511 GPIOC->MODER |= 0x00000A00;
<> 144:ef7eb2e8f9f7 512 /* Configure PDx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 513 GPIOC->OSPEEDR |= 0x00000A00;
<> 144:ef7eb2e8f9f7 514 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 515 GPIOC->OTYPER |= 0x00000000;
<> 144:ef7eb2e8f9f7 516 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 517 GPIOC->PUPDR |= 0x00000000;
<> 144:ef7eb2e8f9f7 518 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /* Connect PDx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 521 GPIOD->AFR[0] = 0x000000CC;
<> 144:ef7eb2e8f9f7 522 GPIOD->AFR[1] = 0xCC000CCC;
<> 144:ef7eb2e8f9f7 523 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 524 GPIOD->MODER = 0xA02A000A;
<> 144:ef7eb2e8f9f7 525 /* Configure PDx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 526 GPIOD->OSPEEDR = 0xA02A000A;
<> 144:ef7eb2e8f9f7 527 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 528 GPIOD->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 529 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 530 GPIOD->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /* Connect PEx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 533 GPIOE->AFR[0] = 0xC00000CC;
<> 144:ef7eb2e8f9f7 534 GPIOE->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 535 /* Configure PEx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 536 GPIOE->MODER = 0xAAAA800A;
<> 144:ef7eb2e8f9f7 537 /* Configure PEx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 538 GPIOE->OSPEEDR = 0xAAAA800A;
<> 144:ef7eb2e8f9f7 539 /* Configure PEx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 540 GPIOE->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 541 /* No pull-up, pull-down for PEx pins */
<> 144:ef7eb2e8f9f7 542 GPIOE->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /* Connect PFx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 545 GPIOF->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 546 GPIOF->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 547 /* Configure PFx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 548 GPIOF->MODER = 0xAA800AAA;
<> 144:ef7eb2e8f9f7 549 /* Configure PFx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 550 GPIOF->OSPEEDR = 0xAA800AAA;
<> 144:ef7eb2e8f9f7 551 /* Configure PFx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 552 GPIOF->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 553 /* No pull-up, pull-down for PFx pins */
<> 144:ef7eb2e8f9f7 554 GPIOF->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 /* Connect PGx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 557 GPIOG->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 558 GPIOG->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 559 /* Configure PGx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 560 GPIOG->MODER = 0xAAAAAAAA;
<> 144:ef7eb2e8f9f7 561 /* Configure PGx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 562 GPIOG->OSPEEDR = 0xAAAAAAAA;
<> 144:ef7eb2e8f9f7 563 /* Configure PGx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 564 GPIOG->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 565 /* No pull-up, pull-down for PGx pins */
<> 144:ef7eb2e8f9f7 566 GPIOG->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
<> 144:ef7eb2e8f9f7 569 || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 570 /* Connect PHx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 571 GPIOH->AFR[0] = 0x00C0CC00;
<> 144:ef7eb2e8f9f7 572 GPIOH->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 573 /* Configure PHx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 574 GPIOH->MODER = 0xAAAA08A0;
<> 144:ef7eb2e8f9f7 575 /* Configure PHx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 576 GPIOH->OSPEEDR = 0xAAAA08A0;
<> 144:ef7eb2e8f9f7 577 /* Configure PHx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 578 GPIOH->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 579 /* No pull-up, pull-down for PHx pins */
<> 144:ef7eb2e8f9f7 580 GPIOH->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 /* Connect PIx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 583 GPIOI->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 584 GPIOI->AFR[1] = 0x00000CC0;
<> 144:ef7eb2e8f9f7 585 /* Configure PIx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 586 GPIOI->MODER = 0x0028AAAA;
<> 144:ef7eb2e8f9f7 587 /* Configure PIx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 588 GPIOI->OSPEEDR = 0x0028AAAA;
<> 144:ef7eb2e8f9f7 589 /* Configure PIx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 590 GPIOI->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 591 /* No pull-up, pull-down for PIx pins */
<> 144:ef7eb2e8f9f7 592 GPIOI->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 593 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /*-- FMC Configuration -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 596 /* Enable the FMC interface clock */
<> 144:ef7eb2e8f9f7 597 RCC->AHB3ENR |= 0x00000001;
<> 144:ef7eb2e8f9f7 598 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 599 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /* Configure and enable SDRAM bank1 */
<> 144:ef7eb2e8f9f7 602 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 603 FMC_Bank5_6->SDCR[0] = 0x00001954;
<> 144:ef7eb2e8f9f7 604 #else
<> 144:ef7eb2e8f9f7 605 FMC_Bank5_6->SDCR[0] = 0x000019E4;
<> 144:ef7eb2e8f9f7 606 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 607 FMC_Bank5_6->SDTR[0] = 0x01115351;
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /* SDRAM initialization sequence */
<> 144:ef7eb2e8f9f7 610 /* Clock enable command */
<> 144:ef7eb2e8f9f7 611 FMC_Bank5_6->SDCMR = 0x00000011;
<> 144:ef7eb2e8f9f7 612 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 613 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 614 {
<> 144:ef7eb2e8f9f7 615 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 616 }
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /* Delay */
<> 144:ef7eb2e8f9f7 619 for (index = 0; index<1000; index++);
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /* PALL command */
<> 144:ef7eb2e8f9f7 622 FMC_Bank5_6->SDCMR = 0x00000012;
<> 144:ef7eb2e8f9f7 623 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 624 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 625 {
<> 144:ef7eb2e8f9f7 626 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 627 }
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /* Auto refresh command */
<> 144:ef7eb2e8f9f7 630 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 631 FMC_Bank5_6->SDCMR = 0x000000F3;
<> 144:ef7eb2e8f9f7 632 #else
<> 144:ef7eb2e8f9f7 633 FMC_Bank5_6->SDCMR = 0x00000073;
<> 144:ef7eb2e8f9f7 634 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 635 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 636 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 637 {
<> 144:ef7eb2e8f9f7 638 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 639 }
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 /* MRD register program */
<> 144:ef7eb2e8f9f7 642 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 643 FMC_Bank5_6->SDCMR = 0x00044014;
<> 144:ef7eb2e8f9f7 644 #else
<> 144:ef7eb2e8f9f7 645 FMC_Bank5_6->SDCMR = 0x00046014;
<> 144:ef7eb2e8f9f7 646 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 647 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 648 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 649 {
<> 144:ef7eb2e8f9f7 650 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 651 }
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 /* Set refresh count */
<> 144:ef7eb2e8f9f7 654 tmpreg = FMC_Bank5_6->SDRTR;
<> 144:ef7eb2e8f9f7 655 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 656 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
<> 144:ef7eb2e8f9f7 657 #else
<> 144:ef7eb2e8f9f7 658 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
<> 144:ef7eb2e8f9f7 659 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 /* Disable write protection */
<> 144:ef7eb2e8f9f7 662 tmpreg = FMC_Bank5_6->SDCR[0];
<> 144:ef7eb2e8f9f7 663 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
<> 144:ef7eb2e8f9f7 664 #endif /* DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 665 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
<> 144:ef7eb2e8f9f7 668 || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
<> 144:ef7eb2e8f9f7 669 || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 #if defined(DATA_IN_ExtSRAM)
<> 144:ef7eb2e8f9f7 672 /*-- GPIOs Configuration -----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 673 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
<> 144:ef7eb2e8f9f7 674 RCC->AHB1ENR |= 0x00000078;
<> 144:ef7eb2e8f9f7 675 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 676 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 /* Connect PDx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 679 GPIOD->AFR[0] = 0x00CCC0CC;
<> 144:ef7eb2e8f9f7 680 GPIOD->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 681 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 682 GPIOD->MODER = 0xAAAA0A8A;
<> 144:ef7eb2e8f9f7 683 /* Configure PDx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 684 GPIOD->OSPEEDR = 0xFFFF0FCF;
<> 144:ef7eb2e8f9f7 685 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 686 GPIOD->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 687 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 688 GPIOD->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /* Connect PEx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 691 GPIOE->AFR[0] = 0xC00CC0CC;
<> 144:ef7eb2e8f9f7 692 GPIOE->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 693 /* Configure PEx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 694 GPIOE->MODER = 0xAAAA828A;
<> 144:ef7eb2e8f9f7 695 /* Configure PEx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 696 GPIOE->OSPEEDR = 0xFFFFC3CF;
<> 144:ef7eb2e8f9f7 697 /* Configure PEx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 698 GPIOE->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 699 /* No pull-up, pull-down for PEx pins */
<> 144:ef7eb2e8f9f7 700 GPIOE->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 /* Connect PFx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 703 GPIOF->AFR[0] = 0x00CCCCCC;
<> 144:ef7eb2e8f9f7 704 GPIOF->AFR[1] = 0xCCCC0000;
<> 144:ef7eb2e8f9f7 705 /* Configure PFx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 706 GPIOF->MODER = 0xAA000AAA;
<> 144:ef7eb2e8f9f7 707 /* Configure PFx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 708 GPIOF->OSPEEDR = 0xFF000FFF;
<> 144:ef7eb2e8f9f7 709 /* Configure PFx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 710 GPIOF->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 711 /* No pull-up, pull-down for PFx pins */
<> 144:ef7eb2e8f9f7 712 GPIOF->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 /* Connect PGx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 715 GPIOG->AFR[0] = 0x00CCCCCC;
<> 144:ef7eb2e8f9f7 716 GPIOG->AFR[1] = 0x000000C0;
<> 144:ef7eb2e8f9f7 717 /* Configure PGx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 718 GPIOG->MODER = 0x00085AAA;
<> 144:ef7eb2e8f9f7 719 /* Configure PGx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 720 GPIOG->OSPEEDR = 0x000CAFFF;
<> 144:ef7eb2e8f9f7 721 /* Configure PGx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 722 GPIOG->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 723 /* No pull-up, pull-down for PGx pins */
<> 144:ef7eb2e8f9f7 724 GPIOG->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 /*-- FMC/FSMC Configuration --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 727 /* Enable the FMC/FSMC interface clock */
<> 144:ef7eb2e8f9f7 728 RCC->AHB3ENR |= 0x00000001;
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
<> 144:ef7eb2e8f9f7 731 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 732 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
<> 144:ef7eb2e8f9f7 733 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 734 FMC_Bank1->BTCR[2] = 0x00001011;
<> 144:ef7eb2e8f9f7 735 FMC_Bank1->BTCR[3] = 0x00000201;
<> 144:ef7eb2e8f9f7 736 FMC_Bank1E->BWTR[2] = 0x0fffffff;
<> 144:ef7eb2e8f9f7 737 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
<> 144:ef7eb2e8f9f7 738 #if defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 739 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 740 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
<> 144:ef7eb2e8f9f7 741 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 742 FMC_Bank1->BTCR[2] = 0x00001091;
<> 144:ef7eb2e8f9f7 743 FMC_Bank1->BTCR[3] = 0x00110212;
<> 144:ef7eb2e8f9f7 744 FMC_Bank1E->BWTR[2] = 0x0fffffff;
<> 144:ef7eb2e8f9f7 745 #endif /* STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 746 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
<> 144:ef7eb2e8f9f7 747 || defined(STM32F412Zx) || defined(STM32F412Vx)
<> 144:ef7eb2e8f9f7 748 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 749 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
<> 144:ef7eb2e8f9f7 750 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 751 FSMC_Bank1->BTCR[2] = 0x00001011;
<> 144:ef7eb2e8f9f7 752 FSMC_Bank1->BTCR[3] = 0x00000201;
<> 144:ef7eb2e8f9f7 753 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
<> 144:ef7eb2e8f9f7 754 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 #endif /* DATA_IN_ExtSRAM */
<> 144:ef7eb2e8f9f7 757 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
<> 144:ef7eb2e8f9f7 758 STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */
<> 144:ef7eb2e8f9f7 759 (void)(tmp);
<> 144:ef7eb2e8f9f7 760 }
<> 144:ef7eb2e8f9f7 761 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 /** System Clock Configuration
<> 144:ef7eb2e8f9f7 764 */
<> 144:ef7eb2e8f9f7 765 #if USE_SYSCLOCK_168 != 0
<> 144:ef7eb2e8f9f7 766 /*
<> 144:ef7eb2e8f9f7 767 * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery
<> 144:ef7eb2e8f9f7 768 * and SYSCLK=168MHZ
<> 144:ef7eb2e8f9f7 769 */
<> 144:ef7eb2e8f9f7 770 void SetSysClock(void)
<> 144:ef7eb2e8f9f7 771 {
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 RCC_OscInitTypeDef RCC_OscInitStruct;
<> 144:ef7eb2e8f9f7 774 RCC_ClkInitTypeDef RCC_ClkInitStruct;
<> 144:ef7eb2e8f9f7 775
AnnaBridge 167:e84263d55307 776 __HAL_RCC_PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
<> 144:ef7eb2e8f9f7 781 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
<> 144:ef7eb2e8f9f7 782 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 783 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
<> 144:ef7eb2e8f9f7 784 RCC_OscInitStruct.PLL.PLLM = 8;
<> 144:ef7eb2e8f9f7 785 RCC_OscInitStruct.PLL.PLLN = 336;
<> 144:ef7eb2e8f9f7 786 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
<> 144:ef7eb2e8f9f7 787 RCC_OscInitStruct.PLL.PLLQ = 7;
<> 144:ef7eb2e8f9f7 788 HAL_RCC_OscConfig(&RCC_OscInitStruct);
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
<> 144:ef7eb2e8f9f7 791 |RCC_CLOCKTYPE_PCLK2;
<> 144:ef7eb2e8f9f7 792 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
<> 144:ef7eb2e8f9f7 793 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
<> 144:ef7eb2e8f9f7 794 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
<> 144:ef7eb2e8f9f7 795 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
<> 144:ef7eb2e8f9f7 796 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
<> 144:ef7eb2e8f9f7 797
<> 144:ef7eb2e8f9f7 798 // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 }
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 #elif USE_SYSCLOCK_180 != 0
<> 144:ef7eb2e8f9f7 804 /*
<> 144:ef7eb2e8f9f7 805 * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery
<> 144:ef7eb2e8f9f7 806 * and SYSCLK=180MHZ
<> 144:ef7eb2e8f9f7 807 */
<> 144:ef7eb2e8f9f7 808 void SetSysClock(void)
<> 144:ef7eb2e8f9f7 809 {
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 RCC_OscInitTypeDef RCC_OscInitStruct;
<> 144:ef7eb2e8f9f7 812 RCC_ClkInitTypeDef RCC_ClkInitStruct;
<> 144:ef7eb2e8f9f7 813
AnnaBridge 167:e84263d55307 814 __HAL_RCC_PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
<> 144:ef7eb2e8f9f7 819 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
<> 144:ef7eb2e8f9f7 820 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 821 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
<> 144:ef7eb2e8f9f7 822 RCC_OscInitStruct.PLL.PLLM = 8;
<> 144:ef7eb2e8f9f7 823 RCC_OscInitStruct.PLL.PLLN = 360;
<> 144:ef7eb2e8f9f7 824 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
<> 144:ef7eb2e8f9f7 825 RCC_OscInitStruct.PLL.PLLQ = 7;
<> 144:ef7eb2e8f9f7 826 HAL_RCC_OscConfig(&RCC_OscInitStruct);
<> 144:ef7eb2e8f9f7 827
AnnaBridge 167:e84263d55307 828 HAL_PWREx_EnableOverDrive();
<> 144:ef7eb2e8f9f7 829
<> 144:ef7eb2e8f9f7 830 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
<> 144:ef7eb2e8f9f7 831 |RCC_CLOCKTYPE_PCLK2;
<> 144:ef7eb2e8f9f7 832 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
<> 144:ef7eb2e8f9f7 833 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
<> 144:ef7eb2e8f9f7 834 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
<> 144:ef7eb2e8f9f7 835 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
<> 144:ef7eb2e8f9f7 836 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
<> 144:ef7eb2e8f9f7 839
<> 144:ef7eb2e8f9f7 840 }
<> 144:ef7eb2e8f9f7 841 #endif
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 /**
<> 144:ef7eb2e8f9f7 844 * @}
<> 144:ef7eb2e8f9f7 845 */
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /**
<> 144:ef7eb2e8f9f7 848 * @}
<> 144:ef7eb2e8f9f7 849 */
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 /**
<> 144:ef7eb2e8f9f7 852 * @}
<> 144:ef7eb2e8f9f7 853 */
<> 144:ef7eb2e8f9f7 854 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/