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targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_stm32f4xx.c@167:e84263d55307, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:46:44 2017 +0100
Revision:
167:e84263d55307
Parent:
149:156823d33999 
This updates the lib to the mbed lib v 145

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file system_stm32f4xx.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V2.5.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides two functions and one global variable to be called from
<> 144:ef7eb2e8f9f7 10 * user application:
<> 144:ef7eb2e8f9f7 11 * - SystemInit(): This function is called at startup just after reset and
<> 144:ef7eb2e8f9f7 12 * before branch to main program. This call is made inside
<> 144:ef7eb2e8f9f7 13 * the "startup_stm32f4xx.s" file.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
<> 144:ef7eb2e8f9f7 16 * by the user application to setup the SysTick
<> 144:ef7eb2e8f9f7 17 * timer or configure other parameters.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
<> 144:ef7eb2e8f9f7 20 * be called whenever the core clock is changed
<> 144:ef7eb2e8f9f7 21 * during program execution.
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * This file configures the system clock as follows:
<> 144:ef7eb2e8f9f7 24 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
<> 144:ef7eb2e8f9f7 26 * | (external 8 MHz clock) | (internal 16 MHz)
<> 144:ef7eb2e8f9f7 27 * | 2- PLL_HSE_XTAL |
<> 144:ef7eb2e8f9f7 28 * | (external 8 MHz xtal) |
<> 144:ef7eb2e8f9f7 29 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30 * SYSCLK(MHz) | 96 | 96
<> 144:ef7eb2e8f9f7 31 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 32 * AHBCLK (MHz) | 96 | 96
<> 144:ef7eb2e8f9f7 33 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 34 * APB1CLK (MHz) | 48 | 48
<> 144:ef7eb2e8f9f7 35 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 36 * APB2CLK (MHz) | 96 | 96
<> 144:ef7eb2e8f9f7 37 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 38 * USB capable (48 MHz precise clock) | YES | NO
<> 144:ef7eb2e8f9f7 39 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 40 ******************************************************************************
<> 144:ef7eb2e8f9f7 41 * @attention
<> 144:ef7eb2e8f9f7 42 *
<> 144:ef7eb2e8f9f7 43 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 44 *
<> 144:ef7eb2e8f9f7 45 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 46 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 47 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 48 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 49 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 50 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 51 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 52 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 53 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 54 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 55 *
<> 144:ef7eb2e8f9f7 56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 57 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 59 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 63 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 65 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 66 *
<> 144:ef7eb2e8f9f7 67 ******************************************************************************
<> 144:ef7eb2e8f9f7 68 */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /** @addtogroup CMSIS
<> 144:ef7eb2e8f9f7 71 * @{
<> 144:ef7eb2e8f9f7 72 */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /** @addtogroup stm32f4xx_system
<> 144:ef7eb2e8f9f7 75 * @{
<> 144:ef7eb2e8f9f7 76 */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /** @addtogroup STM32F4xx_System_Private_Includes
<> 144:ef7eb2e8f9f7 79 * @{
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 #include "stm32f4xx.h"
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 #if !defined (HSE_VALUE)
<> 144:ef7eb2e8f9f7 86 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
<> 144:ef7eb2e8f9f7 87 #endif /* HSE_VALUE */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 #if !defined (HSI_VALUE)
<> 144:ef7eb2e8f9f7 90 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
<> 144:ef7eb2e8f9f7 91 #endif /* HSI_VALUE */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /**
<> 144:ef7eb2e8f9f7 94 * @}
<> 144:ef7eb2e8f9f7 95 */
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
<> 144:ef7eb2e8f9f7 98 * @{
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /**
<> 144:ef7eb2e8f9f7 102 * @}
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /** @addtogroup STM32F4xx_System_Private_Defines
<> 144:ef7eb2e8f9f7 106 * @{
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /************************* Miscellaneous Configuration ************************/
<> 144:ef7eb2e8f9f7 110 /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
<> 144:ef7eb2e8f9f7 111 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
<> 144:ef7eb2e8f9f7 112 || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
<> 144:ef7eb2e8f9f7 113 || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
<> 144:ef7eb2e8f9f7 114 /* #define DATA_IN_ExtSRAM */
<> 144:ef7eb2e8f9f7 115 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
<> 144:ef7eb2e8f9f7 116 STM32F412Zx || STM32F412Vx */
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
<> 144:ef7eb2e8f9f7 119 || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 120 /* #define DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 121 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
<> 144:ef7eb2e8f9f7 122 STM32F479xx */
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /*!< Uncomment the following line if you need to relocate your vector Table in
<> 144:ef7eb2e8f9f7 125 Internal SRAM. */
<> 144:ef7eb2e8f9f7 126 /* #define VECT_TAB_SRAM */
<> 144:ef7eb2e8f9f7 127 #ifndef VECT_TAB_OFFSET
<> 144:ef7eb2e8f9f7 128 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
<> 144:ef7eb2e8f9f7 129 This value must be a multiple of 0x200. */
<> 144:ef7eb2e8f9f7 130 #endif
<> 144:ef7eb2e8f9f7 131 /******************************************************************************/
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /**
<> 144:ef7eb2e8f9f7 134 * @}
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /** @addtogroup STM32F4xx_System_Private_Macros
<> 144:ef7eb2e8f9f7 138 * @{
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
<> 144:ef7eb2e8f9f7 142 #if !defined (USE_PLL_HSE_EXTC)
<> 144:ef7eb2e8f9f7 143 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
<> 144:ef7eb2e8f9f7 144 #endif
<> 144:ef7eb2e8f9f7 145 #if !defined (USE_PLL_HSE_XTAL)
<> 144:ef7eb2e8f9f7 146 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
<> 144:ef7eb2e8f9f7 147 #endif
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /**
<> 144:ef7eb2e8f9f7 150 * @}
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /** @addtogroup STM32F4xx_System_Private_Variables
<> 144:ef7eb2e8f9f7 154 * @{
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156 /* This variable is updated in three ways:
<> 144:ef7eb2e8f9f7 157 1) by calling CMSIS function SystemCoreClockUpdate()
<> 144:ef7eb2e8f9f7 158 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
<> 144:ef7eb2e8f9f7 159 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
<> 144:ef7eb2e8f9f7 160 Note: If you use this function to configure the system clock; then there
<> 144:ef7eb2e8f9f7 161 is no need to call the 2 first functions listed above, since SystemCoreClock
<> 144:ef7eb2e8f9f7 162 variable is updated automatically.
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164 uint32_t SystemCoreClock = 16000000;
<> 144:ef7eb2e8f9f7 165 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
AnnaBridge 167:e84263d55307 166 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
<> 144:ef7eb2e8f9f7 167 /**
<> 144:ef7eb2e8f9f7 168 * @}
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
<> 144:ef7eb2e8f9f7 172 * @{
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 176 static void SystemInit_ExtMemCtl(void);
<> 144:ef7eb2e8f9f7 177 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
<> 144:ef7eb2e8f9f7 180 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
<> 144:ef7eb2e8f9f7 181 #endif
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 uint8_t SetSysClock_PLL_HSI(void);
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /**
<> 144:ef7eb2e8f9f7 186 * @}
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /** @addtogroup STM32F4xx_System_Private_Functions
<> 144:ef7eb2e8f9f7 190 * @{
<> 144:ef7eb2e8f9f7 191 */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /**
<> 144:ef7eb2e8f9f7 194 * @brief Setup the microcontroller system
<> 144:ef7eb2e8f9f7 195 * Initialize the FPU setting, vector table location and External memory
<> 144:ef7eb2e8f9f7 196 * configuration.
<> 144:ef7eb2e8f9f7 197 * @param None
<> 144:ef7eb2e8f9f7 198 * @retval None
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200 void SystemInit(void)
<> 144:ef7eb2e8f9f7 201 {
<> 144:ef7eb2e8f9f7 202 /* FPU settings ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 203 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 144:ef7eb2e8f9f7 204 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
<> 144:ef7eb2e8f9f7 205 #endif
<> 144:ef7eb2e8f9f7 206 /* Reset the RCC clock configuration to the default reset state ------------*/
<> 144:ef7eb2e8f9f7 207 /* Set HSION bit */
<> 144:ef7eb2e8f9f7 208 RCC->CR |= (uint32_t)0x00000001;
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /* Reset CFGR register */
<> 144:ef7eb2e8f9f7 211 RCC->CFGR = 0x00000000;
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /* Reset HSEON, CSSON and PLLON bits */
<> 144:ef7eb2e8f9f7 214 RCC->CR &= (uint32_t)0xFEF6FFFF;
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /* Reset PLLCFGR register */
<> 144:ef7eb2e8f9f7 217 RCC->PLLCFGR = 0x24003010;
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /* Reset HSEBYP bit */
<> 144:ef7eb2e8f9f7 220 RCC->CR &= (uint32_t)0xFFFBFFFF;
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /* Disable all interrupts */
<> 144:ef7eb2e8f9f7 223 RCC->CIR = 0x00000000;
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 226 SystemInit_ExtMemCtl();
<> 144:ef7eb2e8f9f7 227 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Configure the Vector Table location add offset address ------------------*/
<> 144:ef7eb2e8f9f7 230 #ifdef VECT_TAB_SRAM
<> 144:ef7eb2e8f9f7 231 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
<> 144:ef7eb2e8f9f7 232 #else
<> 144:ef7eb2e8f9f7 233 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
<> 144:ef7eb2e8f9f7 234 #endif
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /**
<> 144:ef7eb2e8f9f7 239 * @brief Update SystemCoreClock variable according to Clock Register Values.
<> 144:ef7eb2e8f9f7 240 * The SystemCoreClock variable contains the core clock (HCLK), it can
<> 144:ef7eb2e8f9f7 241 * be used by the user application to setup the SysTick timer or configure
<> 144:ef7eb2e8f9f7 242 * other parameters.
<> 144:ef7eb2e8f9f7 243 *
<> 144:ef7eb2e8f9f7 244 * @note Each time the core clock (HCLK) changes, this function must be called
<> 144:ef7eb2e8f9f7 245 * to update SystemCoreClock variable value. Otherwise, any configuration
<> 144:ef7eb2e8f9f7 246 * based on this variable will be incorrect.
<> 144:ef7eb2e8f9f7 247 *
<> 144:ef7eb2e8f9f7 248 * @note - The system frequency computed by this function is not the real
<> 144:ef7eb2e8f9f7 249 * frequency in the chip. It is calculated based on the predefined
<> 144:ef7eb2e8f9f7 250 * constant and the selected clock source:
<> 144:ef7eb2e8f9f7 251 *
<> 144:ef7eb2e8f9f7 252 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
<> 144:ef7eb2e8f9f7 253 *
<> 144:ef7eb2e8f9f7 254 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
<> 144:ef7eb2e8f9f7 255 *
<> 144:ef7eb2e8f9f7 256 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
<> 144:ef7eb2e8f9f7 257 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
<> 144:ef7eb2e8f9f7 258 *
<> 144:ef7eb2e8f9f7 259 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
<> 144:ef7eb2e8f9f7 260 * 16 MHz) but the real value may vary depending on the variations
<> 144:ef7eb2e8f9f7 261 * in voltage and temperature.
<> 144:ef7eb2e8f9f7 262 *
<> 144:ef7eb2e8f9f7 263 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
<> 144:ef7eb2e8f9f7 264 * depends on the application requirements), user has to ensure that HSE_VALUE
<> 144:ef7eb2e8f9f7 265 * is same as the real frequency of the crystal used. Otherwise, this function
<> 144:ef7eb2e8f9f7 266 * may have wrong result.
<> 144:ef7eb2e8f9f7 267 *
<> 144:ef7eb2e8f9f7 268 * - The result of this function could be not correct when using fractional
<> 144:ef7eb2e8f9f7 269 * value for HSE crystal.
<> 144:ef7eb2e8f9f7 270 *
<> 144:ef7eb2e8f9f7 271 * @param None
<> 144:ef7eb2e8f9f7 272 * @retval None
<> 144:ef7eb2e8f9f7 273 */
<> 144:ef7eb2e8f9f7 274 void SystemCoreClockUpdate(void)
<> 144:ef7eb2e8f9f7 275 {
<> 144:ef7eb2e8f9f7 276 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /* Get SYSCLK source -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 279 tmp = RCC->CFGR & RCC_CFGR_SWS;
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 switch (tmp)
<> 144:ef7eb2e8f9f7 282 {
<> 144:ef7eb2e8f9f7 283 case 0x00: /* HSI used as system clock source */
<> 144:ef7eb2e8f9f7 284 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 285 break;
<> 144:ef7eb2e8f9f7 286 case 0x04: /* HSE used as system clock source */
<> 144:ef7eb2e8f9f7 287 SystemCoreClock = HSE_VALUE;
<> 144:ef7eb2e8f9f7 288 break;
<> 144:ef7eb2e8f9f7 289 case 0x08: /* PLL used as system clock source */
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
<> 144:ef7eb2e8f9f7 292 SYSCLK = PLL_VCO / PLL_P
<> 144:ef7eb2e8f9f7 293 */
<> 144:ef7eb2e8f9f7 294 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
<> 144:ef7eb2e8f9f7 295 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 if (pllsource != 0)
<> 144:ef7eb2e8f9f7 298 {
<> 144:ef7eb2e8f9f7 299 /* HSE used as PLL clock source */
<> 144:ef7eb2e8f9f7 300 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
<> 144:ef7eb2e8f9f7 301 }
<> 144:ef7eb2e8f9f7 302 else
<> 144:ef7eb2e8f9f7 303 {
<> 144:ef7eb2e8f9f7 304 /* HSI used as PLL clock source */
<> 144:ef7eb2e8f9f7 305 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
<> 144:ef7eb2e8f9f7 306 }
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
<> 144:ef7eb2e8f9f7 309 SystemCoreClock = pllvco/pllp;
<> 144:ef7eb2e8f9f7 310 break;
<> 144:ef7eb2e8f9f7 311 default:
<> 144:ef7eb2e8f9f7 312 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 313 break;
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315 /* Compute HCLK frequency --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 316 /* Get HCLK prescaler */
<> 144:ef7eb2e8f9f7 317 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
<> 144:ef7eb2e8f9f7 318 /* HCLK frequency */
<> 144:ef7eb2e8f9f7 319 SystemCoreClock >>= tmp;
<> 144:ef7eb2e8f9f7 320 }
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 #if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 323 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
<> 144:ef7eb2e8f9f7 324 defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 325 /**
<> 144:ef7eb2e8f9f7 326 * @brief Setup the external memory controller.
<> 144:ef7eb2e8f9f7 327 * Called in startup_stm32f4xx.s before jump to main.
<> 144:ef7eb2e8f9f7 328 * This function configures the external memories (SRAM/SDRAM)
<> 144:ef7eb2e8f9f7 329 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
<> 144:ef7eb2e8f9f7 330 * @param None
<> 144:ef7eb2e8f9f7 331 * @retval None
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333 void SystemInit_ExtMemCtl(void)
<> 144:ef7eb2e8f9f7 334 {
<> 144:ef7eb2e8f9f7 335 __IO uint32_t tmp = 0x00;
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 register uint32_t tmpreg = 0, timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 338 register __IO uint32_t index;
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
<> 144:ef7eb2e8f9f7 341 RCC->AHB1ENR |= 0x000001F8;
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 344 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /* Connect PDx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 347 GPIOD->AFR[0] = 0x00CCC0CC;
<> 144:ef7eb2e8f9f7 348 GPIOD->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 349 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 350 GPIOD->MODER = 0xAAAA0A8A;
<> 144:ef7eb2e8f9f7 351 /* Configure PDx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 352 GPIOD->OSPEEDR = 0xFFFF0FCF;
<> 144:ef7eb2e8f9f7 353 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 354 GPIOD->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 355 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 356 GPIOD->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /* Connect PEx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 359 GPIOE->AFR[0] = 0xC00CC0CC;
<> 144:ef7eb2e8f9f7 360 GPIOE->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 361 /* Configure PEx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 362 GPIOE->MODER = 0xAAAA828A;
<> 144:ef7eb2e8f9f7 363 /* Configure PEx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 364 GPIOE->OSPEEDR = 0xFFFFC3CF;
<> 144:ef7eb2e8f9f7 365 /* Configure PEx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 366 GPIOE->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 367 /* No pull-up, pull-down for PEx pins */
<> 144:ef7eb2e8f9f7 368 GPIOE->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /* Connect PFx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 371 GPIOF->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 372 GPIOF->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 373 /* Configure PFx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 374 GPIOF->MODER = 0xAA800AAA;
<> 144:ef7eb2e8f9f7 375 /* Configure PFx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 376 GPIOF->OSPEEDR = 0xAA800AAA;
<> 144:ef7eb2e8f9f7 377 /* Configure PFx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 378 GPIOF->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 379 /* No pull-up, pull-down for PFx pins */
<> 144:ef7eb2e8f9f7 380 GPIOF->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /* Connect PGx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 383 GPIOG->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 384 GPIOG->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 385 /* Configure PGx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 386 GPIOG->MODER = 0xAAAAAAAA;
<> 144:ef7eb2e8f9f7 387 /* Configure PGx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 388 GPIOG->OSPEEDR = 0xAAAAAAAA;
<> 144:ef7eb2e8f9f7 389 /* Configure PGx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 390 GPIOG->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 391 /* No pull-up, pull-down for PGx pins */
<> 144:ef7eb2e8f9f7 392 GPIOG->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /* Connect PHx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 395 GPIOH->AFR[0] = 0x00C0CC00;
<> 144:ef7eb2e8f9f7 396 GPIOH->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 397 /* Configure PHx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 398 GPIOH->MODER = 0xAAAA08A0;
<> 144:ef7eb2e8f9f7 399 /* Configure PHx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 400 GPIOH->OSPEEDR = 0xAAAA08A0;
<> 144:ef7eb2e8f9f7 401 /* Configure PHx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 402 GPIOH->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 403 /* No pull-up, pull-down for PHx pins */
<> 144:ef7eb2e8f9f7 404 GPIOH->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /* Connect PIx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 407 GPIOI->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 408 GPIOI->AFR[1] = 0x00000CC0;
<> 144:ef7eb2e8f9f7 409 /* Configure PIx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 410 GPIOI->MODER = 0x0028AAAA;
<> 144:ef7eb2e8f9f7 411 /* Configure PIx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 412 GPIOI->OSPEEDR = 0x0028AAAA;
<> 144:ef7eb2e8f9f7 413 /* Configure PIx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 414 GPIOI->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 415 /* No pull-up, pull-down for PIx pins */
<> 144:ef7eb2e8f9f7 416 GPIOI->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /*-- FMC Configuration -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 419 /* Enable the FMC interface clock */
<> 144:ef7eb2e8f9f7 420 RCC->AHB3ENR |= 0x00000001;
<> 144:ef7eb2e8f9f7 421 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 422 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 FMC_Bank5_6->SDCR[0] = 0x000019E4;
<> 144:ef7eb2e8f9f7 425 FMC_Bank5_6->SDTR[0] = 0x01115351;
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /* SDRAM initialization sequence */
<> 144:ef7eb2e8f9f7 428 /* Clock enable command */
<> 144:ef7eb2e8f9f7 429 FMC_Bank5_6->SDCMR = 0x00000011;
<> 144:ef7eb2e8f9f7 430 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 431 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 432 {
<> 144:ef7eb2e8f9f7 433 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 434 }
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 /* Delay */
<> 144:ef7eb2e8f9f7 437 for (index = 0; index<1000; index++);
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /* PALL command */
<> 144:ef7eb2e8f9f7 440 FMC_Bank5_6->SDCMR = 0x00000012;
<> 144:ef7eb2e8f9f7 441 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 442 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 443 {
<> 144:ef7eb2e8f9f7 444 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 445 }
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /* Auto refresh command */
<> 144:ef7eb2e8f9f7 448 FMC_Bank5_6->SDCMR = 0x00000073;
<> 144:ef7eb2e8f9f7 449 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 450 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 451 {
<> 144:ef7eb2e8f9f7 452 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 453 }
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /* MRD register program */
<> 144:ef7eb2e8f9f7 456 FMC_Bank5_6->SDCMR = 0x00046014;
<> 144:ef7eb2e8f9f7 457 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 458 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 459 {
<> 144:ef7eb2e8f9f7 460 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 461 }
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /* Set refresh count */
<> 144:ef7eb2e8f9f7 464 tmpreg = FMC_Bank5_6->SDRTR;
<> 144:ef7eb2e8f9f7 465 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /* Disable write protection */
<> 144:ef7eb2e8f9f7 468 tmpreg = FMC_Bank5_6->SDCR[0];
<> 144:ef7eb2e8f9f7 469 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
<> 144:ef7eb2e8f9f7 472 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 473 FMC_Bank1->BTCR[2] = 0x00001011;
<> 144:ef7eb2e8f9f7 474 FMC_Bank1->BTCR[3] = 0x00000201;
<> 144:ef7eb2e8f9f7 475 FMC_Bank1E->BWTR[2] = 0x0fffffff;
<> 144:ef7eb2e8f9f7 476 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
<> 144:ef7eb2e8f9f7 477 #if defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 478 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 479 FMC_Bank1->BTCR[2] = 0x00001091;
<> 144:ef7eb2e8f9f7 480 FMC_Bank1->BTCR[3] = 0x00110212;
<> 144:ef7eb2e8f9f7 481 FMC_Bank1E->BWTR[2] = 0x0fffffff;
<> 144:ef7eb2e8f9f7 482 #endif /* STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 (void)(tmp);
<> 144:ef7eb2e8f9f7 485 }
<> 144:ef7eb2e8f9f7 486 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 487 #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 488 /**
<> 144:ef7eb2e8f9f7 489 * @brief Setup the external memory controller.
<> 144:ef7eb2e8f9f7 490 * Called in startup_stm32f4xx.s before jump to main.
<> 144:ef7eb2e8f9f7 491 * This function configures the external memories (SRAM/SDRAM)
<> 144:ef7eb2e8f9f7 492 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
<> 144:ef7eb2e8f9f7 493 * @param None
<> 144:ef7eb2e8f9f7 494 * @retval None
<> 144:ef7eb2e8f9f7 495 */
<> 144:ef7eb2e8f9f7 496 void SystemInit_ExtMemCtl(void)
<> 144:ef7eb2e8f9f7 497 {
<> 144:ef7eb2e8f9f7 498 __IO uint32_t tmp = 0x00;
<> 144:ef7eb2e8f9f7 499 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
<> 144:ef7eb2e8f9f7 500 || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 501 #if defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 502 register uint32_t tmpreg = 0, timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 503 register __IO uint32_t index;
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 506 /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
<> 144:ef7eb2e8f9f7 507 clock */
<> 144:ef7eb2e8f9f7 508 RCC->AHB1ENR |= 0x0000007D;
<> 144:ef7eb2e8f9f7 509 #else
<> 144:ef7eb2e8f9f7 510 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
<> 144:ef7eb2e8f9f7 511 clock */
<> 144:ef7eb2e8f9f7 512 RCC->AHB1ENR |= 0x000001F8;
<> 144:ef7eb2e8f9f7 513 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 514 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 515 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 518 /* Connect PAx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 519 GPIOA->AFR[0] |= 0xC0000000;
<> 144:ef7eb2e8f9f7 520 GPIOA->AFR[1] |= 0x00000000;
<> 144:ef7eb2e8f9f7 521 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 522 GPIOA->MODER |= 0x00008000;
<> 144:ef7eb2e8f9f7 523 /* Configure PDx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 524 GPIOA->OSPEEDR |= 0x00008000;
<> 144:ef7eb2e8f9f7 525 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 526 GPIOA->OTYPER |= 0x00000000;
<> 144:ef7eb2e8f9f7 527 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 528 GPIOA->PUPDR |= 0x00000000;
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /* Connect PCx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 531 GPIOC->AFR[0] |= 0x00CC0000;
<> 144:ef7eb2e8f9f7 532 GPIOC->AFR[1] |= 0x00000000;
<> 144:ef7eb2e8f9f7 533 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 534 GPIOC->MODER |= 0x00000A00;
<> 144:ef7eb2e8f9f7 535 /* Configure PDx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 536 GPIOC->OSPEEDR |= 0x00000A00;
<> 144:ef7eb2e8f9f7 537 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 538 GPIOC->OTYPER |= 0x00000000;
<> 144:ef7eb2e8f9f7 539 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 540 GPIOC->PUPDR |= 0x00000000;
<> 144:ef7eb2e8f9f7 541 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /* Connect PDx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 544 GPIOD->AFR[0] = 0x000000CC;
<> 144:ef7eb2e8f9f7 545 GPIOD->AFR[1] = 0xCC000CCC;
<> 144:ef7eb2e8f9f7 546 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 547 GPIOD->MODER = 0xA02A000A;
<> 144:ef7eb2e8f9f7 548 /* Configure PDx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 549 GPIOD->OSPEEDR = 0xA02A000A;
<> 144:ef7eb2e8f9f7 550 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 551 GPIOD->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 552 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 553 GPIOD->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /* Connect PEx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 556 GPIOE->AFR[0] = 0xC00000CC;
<> 144:ef7eb2e8f9f7 557 GPIOE->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 558 /* Configure PEx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 559 GPIOE->MODER = 0xAAAA800A;
<> 144:ef7eb2e8f9f7 560 /* Configure PEx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 561 GPIOE->OSPEEDR = 0xAAAA800A;
<> 144:ef7eb2e8f9f7 562 /* Configure PEx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 563 GPIOE->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 564 /* No pull-up, pull-down for PEx pins */
<> 144:ef7eb2e8f9f7 565 GPIOE->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 /* Connect PFx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 568 GPIOF->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 569 GPIOF->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 570 /* Configure PFx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 571 GPIOF->MODER = 0xAA800AAA;
<> 144:ef7eb2e8f9f7 572 /* Configure PFx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 573 GPIOF->OSPEEDR = 0xAA800AAA;
<> 144:ef7eb2e8f9f7 574 /* Configure PFx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 575 GPIOF->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 576 /* No pull-up, pull-down for PFx pins */
<> 144:ef7eb2e8f9f7 577 GPIOF->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 /* Connect PGx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 580 GPIOG->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 581 GPIOG->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 582 /* Configure PGx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 583 GPIOG->MODER = 0xAAAAAAAA;
<> 144:ef7eb2e8f9f7 584 /* Configure PGx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 585 GPIOG->OSPEEDR = 0xAAAAAAAA;
<> 144:ef7eb2e8f9f7 586 /* Configure PGx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 587 GPIOG->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 588 /* No pull-up, pull-down for PGx pins */
<> 144:ef7eb2e8f9f7 589 GPIOG->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
<> 144:ef7eb2e8f9f7 592 || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 593 /* Connect PHx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 594 GPIOH->AFR[0] = 0x00C0CC00;
<> 144:ef7eb2e8f9f7 595 GPIOH->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 596 /* Configure PHx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 597 GPIOH->MODER = 0xAAAA08A0;
<> 144:ef7eb2e8f9f7 598 /* Configure PHx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 599 GPIOH->OSPEEDR = 0xAAAA08A0;
<> 144:ef7eb2e8f9f7 600 /* Configure PHx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 601 GPIOH->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 602 /* No pull-up, pull-down for PHx pins */
<> 144:ef7eb2e8f9f7 603 GPIOH->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /* Connect PIx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 606 GPIOI->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 607 GPIOI->AFR[1] = 0x00000CC0;
<> 144:ef7eb2e8f9f7 608 /* Configure PIx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 609 GPIOI->MODER = 0x0028AAAA;
<> 144:ef7eb2e8f9f7 610 /* Configure PIx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 611 GPIOI->OSPEEDR = 0x0028AAAA;
<> 144:ef7eb2e8f9f7 612 /* Configure PIx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 613 GPIOI->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 614 /* No pull-up, pull-down for PIx pins */
<> 144:ef7eb2e8f9f7 615 GPIOI->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 616 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /*-- FMC Configuration -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 619 /* Enable the FMC interface clock */
<> 144:ef7eb2e8f9f7 620 RCC->AHB3ENR |= 0x00000001;
<> 144:ef7eb2e8f9f7 621 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 622 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /* Configure and enable SDRAM bank1 */
<> 144:ef7eb2e8f9f7 625 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 626 FMC_Bank5_6->SDCR[0] = 0x00001954;
<> 144:ef7eb2e8f9f7 627 #else
<> 144:ef7eb2e8f9f7 628 FMC_Bank5_6->SDCR[0] = 0x000019E4;
<> 144:ef7eb2e8f9f7 629 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 630 FMC_Bank5_6->SDTR[0] = 0x01115351;
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /* SDRAM initialization sequence */
<> 144:ef7eb2e8f9f7 633 /* Clock enable command */
<> 144:ef7eb2e8f9f7 634 FMC_Bank5_6->SDCMR = 0x00000011;
<> 144:ef7eb2e8f9f7 635 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 636 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 637 {
<> 144:ef7eb2e8f9f7 638 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 639 }
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 /* Delay */
<> 144:ef7eb2e8f9f7 642 for (index = 0; index<1000; index++);
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 /* PALL command */
<> 144:ef7eb2e8f9f7 645 FMC_Bank5_6->SDCMR = 0x00000012;
<> 144:ef7eb2e8f9f7 646 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 647 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 648 {
<> 144:ef7eb2e8f9f7 649 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 650 }
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 /* Auto refresh command */
<> 144:ef7eb2e8f9f7 653 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 654 FMC_Bank5_6->SDCMR = 0x000000F3;
<> 144:ef7eb2e8f9f7 655 #else
<> 144:ef7eb2e8f9f7 656 FMC_Bank5_6->SDCMR = 0x00000073;
<> 144:ef7eb2e8f9f7 657 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 658 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 659 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 660 {
<> 144:ef7eb2e8f9f7 661 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 662 }
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /* MRD register program */
<> 144:ef7eb2e8f9f7 665 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 666 FMC_Bank5_6->SDCMR = 0x00044014;
<> 144:ef7eb2e8f9f7 667 #else
<> 144:ef7eb2e8f9f7 668 FMC_Bank5_6->SDCMR = 0x00046014;
<> 144:ef7eb2e8f9f7 669 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 670 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 671 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 672 {
<> 144:ef7eb2e8f9f7 673 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 674 }
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /* Set refresh count */
<> 144:ef7eb2e8f9f7 677 tmpreg = FMC_Bank5_6->SDRTR;
<> 144:ef7eb2e8f9f7 678 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 679 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
<> 144:ef7eb2e8f9f7 680 #else
<> 144:ef7eb2e8f9f7 681 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
<> 144:ef7eb2e8f9f7 682 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 /* Disable write protection */
<> 144:ef7eb2e8f9f7 685 tmpreg = FMC_Bank5_6->SDCR[0];
<> 144:ef7eb2e8f9f7 686 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
<> 144:ef7eb2e8f9f7 687 #endif /* DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 688 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
<> 144:ef7eb2e8f9f7 691 || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
<> 144:ef7eb2e8f9f7 692 || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 #if defined(DATA_IN_ExtSRAM)
<> 144:ef7eb2e8f9f7 695 /*-- GPIOs Configuration -----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 696 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
<> 144:ef7eb2e8f9f7 697 RCC->AHB1ENR |= 0x00000078;
<> 144:ef7eb2e8f9f7 698 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 699 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 /* Connect PDx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 702 GPIOD->AFR[0] = 0x00CCC0CC;
<> 144:ef7eb2e8f9f7 703 GPIOD->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 704 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 705 GPIOD->MODER = 0xAAAA0A8A;
<> 144:ef7eb2e8f9f7 706 /* Configure PDx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 707 GPIOD->OSPEEDR = 0xFFFF0FCF;
<> 144:ef7eb2e8f9f7 708 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 709 GPIOD->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 710 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 711 GPIOD->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 /* Connect PEx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 714 GPIOE->AFR[0] = 0xC00CC0CC;
<> 144:ef7eb2e8f9f7 715 GPIOE->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 716 /* Configure PEx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 717 GPIOE->MODER = 0xAAAA828A;
<> 144:ef7eb2e8f9f7 718 /* Configure PEx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 719 GPIOE->OSPEEDR = 0xFFFFC3CF;
<> 144:ef7eb2e8f9f7 720 /* Configure PEx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 721 GPIOE->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 722 /* No pull-up, pull-down for PEx pins */
<> 144:ef7eb2e8f9f7 723 GPIOE->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 /* Connect PFx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 726 GPIOF->AFR[0] = 0x00CCCCCC;
<> 144:ef7eb2e8f9f7 727 GPIOF->AFR[1] = 0xCCCC0000;
<> 144:ef7eb2e8f9f7 728 /* Configure PFx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 729 GPIOF->MODER = 0xAA000AAA;
<> 144:ef7eb2e8f9f7 730 /* Configure PFx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 731 GPIOF->OSPEEDR = 0xFF000FFF;
<> 144:ef7eb2e8f9f7 732 /* Configure PFx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 733 GPIOF->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 734 /* No pull-up, pull-down for PFx pins */
<> 144:ef7eb2e8f9f7 735 GPIOF->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /* Connect PGx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 738 GPIOG->AFR[0] = 0x00CCCCCC;
<> 144:ef7eb2e8f9f7 739 GPIOG->AFR[1] = 0x000000C0;
<> 144:ef7eb2e8f9f7 740 /* Configure PGx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 741 GPIOG->MODER = 0x00085AAA;
<> 144:ef7eb2e8f9f7 742 /* Configure PGx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 743 GPIOG->OSPEEDR = 0x000CAFFF;
<> 144:ef7eb2e8f9f7 744 /* Configure PGx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 745 GPIOG->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 746 /* No pull-up, pull-down for PGx pins */
<> 144:ef7eb2e8f9f7 747 GPIOG->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 /*-- FMC/FSMC Configuration --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 750 /* Enable the FMC/FSMC interface clock */
<> 144:ef7eb2e8f9f7 751 RCC->AHB3ENR |= 0x00000001;
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
<> 144:ef7eb2e8f9f7 754 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 755 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
<> 144:ef7eb2e8f9f7 756 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 757 FMC_Bank1->BTCR[2] = 0x00001011;
<> 144:ef7eb2e8f9f7 758 FMC_Bank1->BTCR[3] = 0x00000201;
<> 144:ef7eb2e8f9f7 759 FMC_Bank1E->BWTR[2] = 0x0fffffff;
<> 144:ef7eb2e8f9f7 760 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
<> 144:ef7eb2e8f9f7 761 #if defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 762 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 763 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
<> 144:ef7eb2e8f9f7 764 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 765 FMC_Bank1->BTCR[2] = 0x00001091;
<> 144:ef7eb2e8f9f7 766 FMC_Bank1->BTCR[3] = 0x00110212;
<> 144:ef7eb2e8f9f7 767 FMC_Bank1E->BWTR[2] = 0x0fffffff;
<> 144:ef7eb2e8f9f7 768 #endif /* STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 769 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
<> 144:ef7eb2e8f9f7 770 || defined(STM32F412Zx) || defined(STM32F412Vx)
<> 144:ef7eb2e8f9f7 771 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 772 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
<> 144:ef7eb2e8f9f7 773 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 774 FSMC_Bank1->BTCR[2] = 0x00001011;
<> 144:ef7eb2e8f9f7 775 FSMC_Bank1->BTCR[3] = 0x00000201;
<> 144:ef7eb2e8f9f7 776 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
<> 144:ef7eb2e8f9f7 777 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 #endif /* DATA_IN_ExtSRAM */
<> 144:ef7eb2e8f9f7 780 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
<> 144:ef7eb2e8f9f7 781 STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */
<> 144:ef7eb2e8f9f7 782 (void)(tmp);
<> 144:ef7eb2e8f9f7 783 }
<> 144:ef7eb2e8f9f7 784 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786 /**
<> 144:ef7eb2e8f9f7 787 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
<> 144:ef7eb2e8f9f7 788 * AHB/APBx prescalers and Flash settings
<> 144:ef7eb2e8f9f7 789 * @note This function should be called only once the RCC clock configuration
<> 144:ef7eb2e8f9f7 790 * is reset to the default reset state (done in SystemInit() function).
<> 144:ef7eb2e8f9f7 791 * @param None
<> 144:ef7eb2e8f9f7 792 * @retval None
<> 144:ef7eb2e8f9f7 793 */
<> 144:ef7eb2e8f9f7 794 void SetSysClock(void)
<> 144:ef7eb2e8f9f7 795 {
<> 144:ef7eb2e8f9f7 796 /* 1- Try to start with HSE and external clock */
<> 144:ef7eb2e8f9f7 797 #if USE_PLL_HSE_EXTC != 0
<> 144:ef7eb2e8f9f7 798 if (SetSysClock_PLL_HSE(1) == 0)
<> 144:ef7eb2e8f9f7 799 #endif
<> 144:ef7eb2e8f9f7 800 {
<> 144:ef7eb2e8f9f7 801 /* 2- If fail try to start with HSE and external xtal */
<> 144:ef7eb2e8f9f7 802 #if USE_PLL_HSE_XTAL != 0
<> 144:ef7eb2e8f9f7 803 if (SetSysClock_PLL_HSE(0) == 0)
<> 144:ef7eb2e8f9f7 804 #endif
<> 144:ef7eb2e8f9f7 805 {
<> 144:ef7eb2e8f9f7 806 /* 3- If fail start with HSI clock */
<> 144:ef7eb2e8f9f7 807 if (SetSysClock_PLL_HSI() == 0)
<> 144:ef7eb2e8f9f7 808 {
<> 144:ef7eb2e8f9f7 809 while(1)
<> 144:ef7eb2e8f9f7 810 {
<> 144:ef7eb2e8f9f7 811 // [TODO] Put something here to tell the user that a problem occured...
<> 144:ef7eb2e8f9f7 812 }
<> 144:ef7eb2e8f9f7 813 }
<> 144:ef7eb2e8f9f7 814 }
<> 144:ef7eb2e8f9f7 815 }
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 /* Output clock on MCO2 pin(PC9) for debugging purpose */
<> 144:ef7eb2e8f9f7 818 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz
<> 144:ef7eb2e8f9f7 819 }
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
<> 144:ef7eb2e8f9f7 822 /******************************************************************************/
<> 144:ef7eb2e8f9f7 823 /* PLL (clocked by HSE) used as System clock source */
<> 144:ef7eb2e8f9f7 824 /******************************************************************************/
<> 144:ef7eb2e8f9f7 825 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
<> 144:ef7eb2e8f9f7 826 {
<> 144:ef7eb2e8f9f7 827 RCC_ClkInitTypeDef RCC_ClkInitStruct;
<> 144:ef7eb2e8f9f7 828 RCC_OscInitTypeDef RCC_OscInitStruct;
<> 144:ef7eb2e8f9f7 829
<> 144:ef7eb2e8f9f7 830 /* The voltage scaling allows optimizing the power consumption when the device is
<> 144:ef7eb2e8f9f7 831 clocked below the maximum system frequency, to update the voltage scaling value
<> 144:ef7eb2e8f9f7 832 regarding system frequency refer to product datasheet. */
AnnaBridge 167:e84263d55307 833 __HAL_RCC_PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 834 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 /* Enable HSE oscillator and activate PLL with HSE as source */
<> 144:ef7eb2e8f9f7 837 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
<> 144:ef7eb2e8f9f7 838 if (bypass == 0)
<> 144:ef7eb2e8f9f7 839 {
<> 144:ef7eb2e8f9f7 840 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
<> 144:ef7eb2e8f9f7 841 }
<> 144:ef7eb2e8f9f7 842 else
<> 144:ef7eb2e8f9f7 843 {
<> 144:ef7eb2e8f9f7 844 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
<> 144:ef7eb2e8f9f7 845 }
<> 144:ef7eb2e8f9f7 846 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 847 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
<> 144:ef7eb2e8f9f7 848 RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000; // VCO input clock = 1 MHz
<> 144:ef7eb2e8f9f7 849 RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 192 MHz (1 MHz * 192)
<> 144:ef7eb2e8f9f7 850 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 96 MHz (192 MHz / 2)
<> 144:ef7eb2e8f9f7 851 RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock = 48 MHz (192 MHz / 4)
<> 144:ef7eb2e8f9f7 852 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
<> 144:ef7eb2e8f9f7 853 {
<> 144:ef7eb2e8f9f7 854 return 0; // FAIL
<> 144:ef7eb2e8f9f7 855 }
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
<> 144:ef7eb2e8f9f7 858 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
<> 144:ef7eb2e8f9f7 859 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
<> 144:ef7eb2e8f9f7 860 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
<> 144:ef7eb2e8f9f7 861 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
<> 144:ef7eb2e8f9f7 862 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
<> 144:ef7eb2e8f9f7 863 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
<> 144:ef7eb2e8f9f7 864 {
<> 144:ef7eb2e8f9f7 865 return 0; // FAIL
<> 144:ef7eb2e8f9f7 866 }
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 /* Output clock on MCO1 pin(PA8) for debugging purpose */
<> 144:ef7eb2e8f9f7 869
<> 144:ef7eb2e8f9f7 870 //if (bypass == 0)
<> 144:ef7eb2e8f9f7 871 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
<> 144:ef7eb2e8f9f7 872 //else
<> 144:ef7eb2e8f9f7 873 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
<> 144:ef7eb2e8f9f7 874
<> 144:ef7eb2e8f9f7 875 return 1; // OK
<> 144:ef7eb2e8f9f7 876 }
<> 144:ef7eb2e8f9f7 877 #endif
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 /******************************************************************************/
<> 144:ef7eb2e8f9f7 880 /* PLL (clocked by HSI) used as System clock source */
<> 144:ef7eb2e8f9f7 881 /******************************************************************************/
<> 144:ef7eb2e8f9f7 882 uint8_t SetSysClock_PLL_HSI(void)
<> 144:ef7eb2e8f9f7 883 {
<> 144:ef7eb2e8f9f7 884 RCC_ClkInitTypeDef RCC_ClkInitStruct;
<> 144:ef7eb2e8f9f7 885 RCC_OscInitTypeDef RCC_OscInitStruct;
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 /* The voltage scaling allows optimizing the power consumption when the device is
<> 144:ef7eb2e8f9f7 888 clocked below the maximum system frequency, to update the voltage scaling value
<> 144:ef7eb2e8f9f7 889 regarding system frequency refer to product datasheet. */
AnnaBridge 167:e84263d55307 890 __HAL_RCC_PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 891 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 /* Enable HSI oscillator and activate PLL with HSI as source */
<> 144:ef7eb2e8f9f7 894 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
<> 144:ef7eb2e8f9f7 895 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
<> 144:ef7eb2e8f9f7 896 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
<> 144:ef7eb2e8f9f7 897 RCC_OscInitStruct.HSICalibrationValue = 16;
<> 144:ef7eb2e8f9f7 898 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 899 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
<> 144:ef7eb2e8f9f7 900 RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
<> 144:ef7eb2e8f9f7 901 RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 192 MHz (1 MHz * 192)
<> 144:ef7eb2e8f9f7 902 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 96 MHz (192 MHz / 2)
<> 144:ef7eb2e8f9f7 903 RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock = 48 MHz (192 MHz / 4) --> Not stable for USB
<> 144:ef7eb2e8f9f7 904 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
<> 144:ef7eb2e8f9f7 905 {
<> 144:ef7eb2e8f9f7 906 return 0; // FAIL
<> 144:ef7eb2e8f9f7 907 }
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
<> 144:ef7eb2e8f9f7 910 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
<> 144:ef7eb2e8f9f7 911 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
<> 144:ef7eb2e8f9f7 912 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
<> 144:ef7eb2e8f9f7 913 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
<> 144:ef7eb2e8f9f7 914 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
<> 144:ef7eb2e8f9f7 915 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
<> 144:ef7eb2e8f9f7 916 {
<> 144:ef7eb2e8f9f7 917 return 0; // FAIL
<> 144:ef7eb2e8f9f7 918 }
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 /* Output clock on MCO1 pin(PA8) for debugging purpose */
<> 144:ef7eb2e8f9f7 921 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
<> 144:ef7eb2e8f9f7 922
<> 144:ef7eb2e8f9f7 923 return 1; // OK
<> 144:ef7eb2e8f9f7 924 }
<> 144:ef7eb2e8f9f7 925
<> 144:ef7eb2e8f9f7 926 /******************************************************************************/
<> 144:ef7eb2e8f9f7 927 /* Hard Fault Handler */
<> 144:ef7eb2e8f9f7 928 /******************************************************************************/
<> 144:ef7eb2e8f9f7 929 void HardFault_Handler(void)
<> 144:ef7eb2e8f9f7 930 {
<> 144:ef7eb2e8f9f7 931 printf("Hard Fault\n");
<> 144:ef7eb2e8f9f7 932 NVIC_SystemReset();
<> 144:ef7eb2e8f9f7 933 }
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 /**
<> 144:ef7eb2e8f9f7 936 * @}
<> 144:ef7eb2e8f9f7 937 */
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 /**
<> 144:ef7eb2e8f9f7 940 * @}
<> 144:ef7eb2e8f9f7 941 */
<> 144:ef7eb2e8f9f7 942
<> 144:ef7eb2e8f9f7 943 /**
<> 144:ef7eb2e8f9f7 944 * @}
<> 144:ef7eb2e8f9f7 945 */
<> 144:ef7eb2e8f9f7 946 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/