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Diff: targets/hal/TARGET_Freescale/TARGET_KLXX/rtc_api.c
- Revision:
- 56:05912f50f004
- Parent:
- 0:9b334a45a8ff
- Child:
- 144:ef7eb2e8f9f7
--- a/targets/hal/TARGET_Freescale/TARGET_KLXX/rtc_api.c Fri Jan 29 13:30:11 2016 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_KLXX/rtc_api.c Fri Jan 29 14:15:09 2016 +0000 @@ -38,14 +38,32 @@ void rtc_init(void) { init(); - //Configure the TSR. default value: 1 + // Configure the TSR. default value: 1 RTC->TSR = 1; - - if (PinMap_RTC[0].pin == NC) { //Use OSC32K - RTC->CR |= RTC_CR_OSCE_MASK; - //delay for OSCE stabilization - for(int i=0; i<0x1000; i++) __NOP(); - } + + // Configure Time Compensation Register to calibrate RTC accuracy + + // dissable LRL lock + RTC->LR &= ~RTC_LR_LRL_MASK; + // RTC->TCR: RTC_TCR_CIR_MASK,RTC_TCR_CIR(x)=0,RTC_TCR_TCR(x)=0 Default no correction + RTC->TCR = RTC_TCR_CIR(0) | RTC_TCR_TCR(0); + /* + RTC_TCR_CIR(x) sets the compensation interval in seconds from 1 to 256. + 0x05 will apply the compensation once every 4 seconds. + + RTC_TCR_TCR(x) sets the Register Overflow + 0x80 Time Prescaler Register overflows every 32896 clock cycles. (+128) + ... ... RTC runs slower + 0xFF Time Prescaler Register overflows every 32769 clock cycles. + 0x00 Time Prescaler Register overflows every 32768 clock cycles, Default. + 0x01 Time Prescaler Register overflows every 32767 clock cycles. + ... ... RTC runs faster + 0x7F Time Prescaler Register overflows every 32641 clock cycles. (-128) + */ + // enable TCL lock + RTC->LR |= RTC_LR_TCL_MASK; + // enable LRL lock + RTC->LR |= RTC_LR_LRL_MASK; // enable counter RTC->SR |= RTC_SR_TCE_MASK;