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targets/hal/TARGET_Freescale/TARGET_KLXX/rtc_api.c@56:05912f50f004, 2016-01-29 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jan 29 14:15:09 2016 +0000
- Revision:
- 56:05912f50f004
- Parent:
- 0:9b334a45a8ff
- Child:
- 144:ef7eb2e8f9f7
Synchronized with git revision d465cb53a3a479b9456cb456ded8d71a53f2bdee
Full URL: https://github.com/mbedmicro/mbed/commit/d465cb53a3a479b9456cb456ded8d71a53f2bdee/
Update rtc_api.c
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 0:9b334a45a8ff | 1 | /* mbed Microcontroller Library |
bogdanm | 0:9b334a45a8ff | 2 | * Copyright (c) 2006-2013 ARM Limited |
bogdanm | 0:9b334a45a8ff | 3 | * |
bogdanm | 0:9b334a45a8ff | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
bogdanm | 0:9b334a45a8ff | 5 | * you may not use this file except in compliance with the License. |
bogdanm | 0:9b334a45a8ff | 6 | * You may obtain a copy of the License at |
bogdanm | 0:9b334a45a8ff | 7 | * |
bogdanm | 0:9b334a45a8ff | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
bogdanm | 0:9b334a45a8ff | 9 | * |
bogdanm | 0:9b334a45a8ff | 10 | * Unless required by applicable law or agreed to in writing, software |
bogdanm | 0:9b334a45a8ff | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
bogdanm | 0:9b334a45a8ff | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
bogdanm | 0:9b334a45a8ff | 13 | * See the License for the specific language governing permissions and |
bogdanm | 0:9b334a45a8ff | 14 | * limitations under the License. |
bogdanm | 0:9b334a45a8ff | 15 | */ |
bogdanm | 0:9b334a45a8ff | 16 | #include "rtc_api.h" |
bogdanm | 0:9b334a45a8ff | 17 | #include "PeripheralPins.h" |
bogdanm | 0:9b334a45a8ff | 18 | #include "clk_freqs.h" |
bogdanm | 0:9b334a45a8ff | 19 | |
bogdanm | 0:9b334a45a8ff | 20 | static void init(void) { |
bogdanm | 0:9b334a45a8ff | 21 | // enable RTC clock |
bogdanm | 0:9b334a45a8ff | 22 | SIM->SCGC6 |= SIM_SCGC6_RTC_MASK; |
bogdanm | 0:9b334a45a8ff | 23 | |
bogdanm | 0:9b334a45a8ff | 24 | // select RTC clock source |
bogdanm | 0:9b334a45a8ff | 25 | SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK; |
bogdanm | 0:9b334a45a8ff | 26 | |
bogdanm | 0:9b334a45a8ff | 27 | // Enable external crystal source if clock source is 32KHz |
bogdanm | 0:9b334a45a8ff | 28 | if (extosc_frequency()==32768) { |
bogdanm | 0:9b334a45a8ff | 29 | SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(OSC32KCLK); |
bogdanm | 0:9b334a45a8ff | 30 | } |
bogdanm | 0:9b334a45a8ff | 31 | else{ |
bogdanm | 0:9b334a45a8ff | 32 | // If main clock is NOT 32KHz crystal, use external 32KHz clock source defined in PeripheralPins.c |
bogdanm | 0:9b334a45a8ff | 33 | SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(PinMap_RTC[0].peripheral); |
bogdanm | 0:9b334a45a8ff | 34 | pinmap_pinout(PinMap_RTC[0].pin, PinMap_RTC); //Map RTC clk input (if not NC) |
bogdanm | 0:9b334a45a8ff | 35 | } |
bogdanm | 0:9b334a45a8ff | 36 | } |
bogdanm | 0:9b334a45a8ff | 37 | |
bogdanm | 0:9b334a45a8ff | 38 | void rtc_init(void) { |
bogdanm | 0:9b334a45a8ff | 39 | init(); |
bogdanm | 0:9b334a45a8ff | 40 | |
mbed_official | 56:05912f50f004 | 41 | // Configure the TSR. default value: 1 |
bogdanm | 0:9b334a45a8ff | 42 | RTC->TSR = 1; |
mbed_official | 56:05912f50f004 | 43 | |
mbed_official | 56:05912f50f004 | 44 | // Configure Time Compensation Register to calibrate RTC accuracy |
mbed_official | 56:05912f50f004 | 45 | |
mbed_official | 56:05912f50f004 | 46 | // dissable LRL lock |
mbed_official | 56:05912f50f004 | 47 | RTC->LR &= ~RTC_LR_LRL_MASK; |
mbed_official | 56:05912f50f004 | 48 | // RTC->TCR: RTC_TCR_CIR_MASK,RTC_TCR_CIR(x)=0,RTC_TCR_TCR(x)=0 Default no correction |
mbed_official | 56:05912f50f004 | 49 | RTC->TCR = RTC_TCR_CIR(0) | RTC_TCR_TCR(0); |
mbed_official | 56:05912f50f004 | 50 | /* |
mbed_official | 56:05912f50f004 | 51 | RTC_TCR_CIR(x) sets the compensation interval in seconds from 1 to 256. |
mbed_official | 56:05912f50f004 | 52 | 0x05 will apply the compensation once every 4 seconds. |
mbed_official | 56:05912f50f004 | 53 | |
mbed_official | 56:05912f50f004 | 54 | RTC_TCR_TCR(x) sets the Register Overflow |
mbed_official | 56:05912f50f004 | 55 | 0x80 Time Prescaler Register overflows every 32896 clock cycles. (+128) |
mbed_official | 56:05912f50f004 | 56 | ... ... RTC runs slower |
mbed_official | 56:05912f50f004 | 57 | 0xFF Time Prescaler Register overflows every 32769 clock cycles. |
mbed_official | 56:05912f50f004 | 58 | 0x00 Time Prescaler Register overflows every 32768 clock cycles, Default. |
mbed_official | 56:05912f50f004 | 59 | 0x01 Time Prescaler Register overflows every 32767 clock cycles. |
mbed_official | 56:05912f50f004 | 60 | ... ... RTC runs faster |
mbed_official | 56:05912f50f004 | 61 | 0x7F Time Prescaler Register overflows every 32641 clock cycles. (-128) |
mbed_official | 56:05912f50f004 | 62 | */ |
mbed_official | 56:05912f50f004 | 63 | // enable TCL lock |
mbed_official | 56:05912f50f004 | 64 | RTC->LR |= RTC_LR_TCL_MASK; |
mbed_official | 56:05912f50f004 | 65 | // enable LRL lock |
mbed_official | 56:05912f50f004 | 66 | RTC->LR |= RTC_LR_LRL_MASK; |
bogdanm | 0:9b334a45a8ff | 67 | |
bogdanm | 0:9b334a45a8ff | 68 | // enable counter |
bogdanm | 0:9b334a45a8ff | 69 | RTC->SR |= RTC_SR_TCE_MASK; |
bogdanm | 0:9b334a45a8ff | 70 | } |
bogdanm | 0:9b334a45a8ff | 71 | |
bogdanm | 0:9b334a45a8ff | 72 | void rtc_free(void) { |
bogdanm | 0:9b334a45a8ff | 73 | // [TODO] |
bogdanm | 0:9b334a45a8ff | 74 | } |
bogdanm | 0:9b334a45a8ff | 75 | |
bogdanm | 0:9b334a45a8ff | 76 | /* |
bogdanm | 0:9b334a45a8ff | 77 | * Little check routine to see if the RTC has been enabled |
bogdanm | 0:9b334a45a8ff | 78 | * 0 = Disabled, 1 = Enabled |
bogdanm | 0:9b334a45a8ff | 79 | */ |
bogdanm | 0:9b334a45a8ff | 80 | int rtc_isenabled(void) { |
bogdanm | 0:9b334a45a8ff | 81 | // even if the RTC module is enabled, |
bogdanm | 0:9b334a45a8ff | 82 | // as we use RTC_CLKIN and an external clock, |
bogdanm | 0:9b334a45a8ff | 83 | // we need to reconfigure the pins. That is why we |
bogdanm | 0:9b334a45a8ff | 84 | // call init() if the rtc is enabled |
bogdanm | 0:9b334a45a8ff | 85 | |
bogdanm | 0:9b334a45a8ff | 86 | // if RTC not enabled return 0 |
bogdanm | 0:9b334a45a8ff | 87 | SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; |
bogdanm | 0:9b334a45a8ff | 88 | SIM->SCGC6 |= SIM_SCGC6_RTC_MASK; |
bogdanm | 0:9b334a45a8ff | 89 | if ((RTC->SR & RTC_SR_TCE_MASK) == 0) |
bogdanm | 0:9b334a45a8ff | 90 | return 0; |
bogdanm | 0:9b334a45a8ff | 91 | |
bogdanm | 0:9b334a45a8ff | 92 | init(); |
bogdanm | 0:9b334a45a8ff | 93 | return 1; |
bogdanm | 0:9b334a45a8ff | 94 | } |
bogdanm | 0:9b334a45a8ff | 95 | |
bogdanm | 0:9b334a45a8ff | 96 | time_t rtc_read(void) { |
bogdanm | 0:9b334a45a8ff | 97 | return RTC->TSR; |
bogdanm | 0:9b334a45a8ff | 98 | } |
bogdanm | 0:9b334a45a8ff | 99 | |
bogdanm | 0:9b334a45a8ff | 100 | void rtc_write(time_t t) { |
bogdanm | 0:9b334a45a8ff | 101 | // disable counter |
bogdanm | 0:9b334a45a8ff | 102 | RTC->SR &= ~RTC_SR_TCE_MASK; |
bogdanm | 0:9b334a45a8ff | 103 | |
bogdanm | 0:9b334a45a8ff | 104 | // we do not write 0 into TSR |
bogdanm | 0:9b334a45a8ff | 105 | // to avoid invalid time |
bogdanm | 0:9b334a45a8ff | 106 | if (t == 0) |
bogdanm | 0:9b334a45a8ff | 107 | t = 1; |
bogdanm | 0:9b334a45a8ff | 108 | |
bogdanm | 0:9b334a45a8ff | 109 | // write seconds |
bogdanm | 0:9b334a45a8ff | 110 | RTC->TSR = t; |
bogdanm | 0:9b334a45a8ff | 111 | |
bogdanm | 0:9b334a45a8ff | 112 | // re-enable counter |
bogdanm | 0:9b334a45a8ff | 113 | RTC->SR |= RTC_SR_TCE_MASK; |
bogdanm | 0:9b334a45a8ff | 114 | } |