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Dependencies:   C027_Support IBMIoTClientCellularExample MQTT mbed

Fork of MQTT-GSM-GPS-CAN-SMS by Babu Alikapati

mbed-rtos/rtx/rt_HAL_CM.h@6:37b6d0d56190, 2014-08-20 (annotated)

Committer:
samdanbury
Date:
Wed Aug 20 12:45:14 2014 +0000
Revision:
6:37b6d0d56190
Code completely changed to improve the structure, flow and memory usage of the application

Who changed what in which revision?

UserRevisionLine numberNew contents of line
samdanbury 6:37b6d0d56190 1 /*----------------------------------------------------------------------------
samdanbury 6:37b6d0d56190 2 * RL-ARM - RTX
samdanbury 6:37b6d0d56190 3 *----------------------------------------------------------------------------
samdanbury 6:37b6d0d56190 4 * Name: RT_HAL_CM.H
samdanbury 6:37b6d0d56190 5 * Purpose: Hardware Abstraction Layer for Cortex-M definitions
samdanbury 6:37b6d0d56190 6 * Rev.: V4.60
samdanbury 6:37b6d0d56190 7 *----------------------------------------------------------------------------
samdanbury 6:37b6d0d56190 8 *
samdanbury 6:37b6d0d56190 9 * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
samdanbury 6:37b6d0d56190 10 * All rights reserved.
samdanbury 6:37b6d0d56190 11 * Redistribution and use in source and binary forms, with or without
samdanbury 6:37b6d0d56190 12 * modification, are permitted provided that the following conditions are met:
samdanbury 6:37b6d0d56190 13 * - Redistributions of source code must retain the above copyright
samdanbury 6:37b6d0d56190 14 * notice, this list of conditions and the following disclaimer.
samdanbury 6:37b6d0d56190 15 * - Redistributions in binary form must reproduce the above copyright
samdanbury 6:37b6d0d56190 16 * notice, this list of conditions and the following disclaimer in the
samdanbury 6:37b6d0d56190 17 * documentation and/or other materials provided with the distribution.
samdanbury 6:37b6d0d56190 18 * - Neither the name of ARM nor the names of its contributors may be used
samdanbury 6:37b6d0d56190 19 * to endorse or promote products derived from this software without
samdanbury 6:37b6d0d56190 20 * specific prior written permission.
samdanbury 6:37b6d0d56190 21 *
samdanbury 6:37b6d0d56190 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
samdanbury 6:37b6d0d56190 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
samdanbury 6:37b6d0d56190 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
samdanbury 6:37b6d0d56190 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
samdanbury 6:37b6d0d56190 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
samdanbury 6:37b6d0d56190 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
samdanbury 6:37b6d0d56190 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
samdanbury 6:37b6d0d56190 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
samdanbury 6:37b6d0d56190 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
samdanbury 6:37b6d0d56190 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
samdanbury 6:37b6d0d56190 32 * POSSIBILITY OF SUCH DAMAGE.
samdanbury 6:37b6d0d56190 33 *---------------------------------------------------------------------------*/
samdanbury 6:37b6d0d56190 34
samdanbury 6:37b6d0d56190 35 /* Definitions */
samdanbury 6:37b6d0d56190 36 #define INITIAL_xPSR 0x01000000
samdanbury 6:37b6d0d56190 37 #define DEMCR_TRCENA 0x01000000
samdanbury 6:37b6d0d56190 38 #define ITM_ITMENA 0x00000001
samdanbury 6:37b6d0d56190 39 #define MAGIC_WORD 0xE25A2EA5
samdanbury 6:37b6d0d56190 40
samdanbury 6:37b6d0d56190 41 #if defined (__CC_ARM) /* ARM Compiler */
samdanbury 6:37b6d0d56190 42
samdanbury 6:37b6d0d56190 43 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !NO_EXCLUSIVE_ACCESS)
samdanbury 6:37b6d0d56190 44 #define __USE_EXCLUSIVE_ACCESS
samdanbury 6:37b6d0d56190 45 #else
samdanbury 6:37b6d0d56190 46 #undef __USE_EXCLUSIVE_ACCESS
samdanbury 6:37b6d0d56190 47 #endif
samdanbury 6:37b6d0d56190 48
samdanbury 6:37b6d0d56190 49 #elif defined (__GNUC__) /* GNU Compiler */
samdanbury 6:37b6d0d56190 50
samdanbury 6:37b6d0d56190 51 #undef __USE_EXCLUSIVE_ACCESS
samdanbury 6:37b6d0d56190 52
samdanbury 6:37b6d0d56190 53 #if defined (__CORTEX_M0) || defined (__CORTEX_M0PLUS)
samdanbury 6:37b6d0d56190 54 #define __TARGET_ARCH_6S_M 1
samdanbury 6:37b6d0d56190 55 #else
samdanbury 6:37b6d0d56190 56 #define __TARGET_ARCH_6S_M 0
samdanbury 6:37b6d0d56190 57 #endif
samdanbury 6:37b6d0d56190 58
samdanbury 6:37b6d0d56190 59 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
samdanbury 6:37b6d0d56190 60 #define __TARGET_FPU_VFP 1
samdanbury 6:37b6d0d56190 61 #else
samdanbury 6:37b6d0d56190 62 #define __TARGET_FPU_VFP 0
samdanbury 6:37b6d0d56190 63 #endif
samdanbury 6:37b6d0d56190 64
samdanbury 6:37b6d0d56190 65 #define __inline inline
samdanbury 6:37b6d0d56190 66 #define __weak __attribute__((weak))
samdanbury 6:37b6d0d56190 67
samdanbury 6:37b6d0d56190 68 #ifndef __CMSIS_GENERIC
samdanbury 6:37b6d0d56190 69
samdanbury 6:37b6d0d56190 70 __attribute__((always_inline)) static inline void __enable_irq(void)
samdanbury 6:37b6d0d56190 71 {
samdanbury 6:37b6d0d56190 72 __asm volatile ("cpsie i");
samdanbury 6:37b6d0d56190 73 }
samdanbury 6:37b6d0d56190 74
samdanbury 6:37b6d0d56190 75 __attribute__((always_inline)) static inline U32 __disable_irq(void)
samdanbury 6:37b6d0d56190 76 {
samdanbury 6:37b6d0d56190 77 U32 result;
samdanbury 6:37b6d0d56190 78
samdanbury 6:37b6d0d56190 79 __asm volatile ("mrs %0, primask" : "=r" (result));
samdanbury 6:37b6d0d56190 80 __asm volatile ("cpsid i");
samdanbury 6:37b6d0d56190 81 return(result & 1);
samdanbury 6:37b6d0d56190 82 }
samdanbury 6:37b6d0d56190 83
samdanbury 6:37b6d0d56190 84 #endif
samdanbury 6:37b6d0d56190 85
samdanbury 6:37b6d0d56190 86 __attribute__(( always_inline)) static inline U8 __clz(U32 value)
samdanbury 6:37b6d0d56190 87 {
samdanbury 6:37b6d0d56190 88 U8 result;
samdanbury 6:37b6d0d56190 89
samdanbury 6:37b6d0d56190 90 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
samdanbury 6:37b6d0d56190 91 return(result);
samdanbury 6:37b6d0d56190 92 }
samdanbury 6:37b6d0d56190 93
samdanbury 6:37b6d0d56190 94 #elif defined (__ICCARM__) /* IAR Compiler */
samdanbury 6:37b6d0d56190 95
samdanbury 6:37b6d0d56190 96 #undef __USE_EXCLUSIVE_ACCESS
samdanbury 6:37b6d0d56190 97
samdanbury 6:37b6d0d56190 98 #if (__CORE__ == __ARM6M__)
samdanbury 6:37b6d0d56190 99 #define __TARGET_ARCH_6S_M 1
samdanbury 6:37b6d0d56190 100 #else
samdanbury 6:37b6d0d56190 101 #define __TARGET_ARCH_6S_M 0
samdanbury 6:37b6d0d56190 102 #endif
samdanbury 6:37b6d0d56190 103
samdanbury 6:37b6d0d56190 104 #if defined __ARMVFP__
samdanbury 6:37b6d0d56190 105 #define __TARGET_FPU_VFP 1
samdanbury 6:37b6d0d56190 106 #else
samdanbury 6:37b6d0d56190 107 #define __TARGET_FPU_VFP 0
samdanbury 6:37b6d0d56190 108 #endif
samdanbury 6:37b6d0d56190 109
samdanbury 6:37b6d0d56190 110 #define __inline inline
samdanbury 6:37b6d0d56190 111
samdanbury 6:37b6d0d56190 112 #ifndef __CMSIS_GENERIC
samdanbury 6:37b6d0d56190 113
samdanbury 6:37b6d0d56190 114 static inline void __enable_irq(void)
samdanbury 6:37b6d0d56190 115 {
samdanbury 6:37b6d0d56190 116 __asm volatile ("cpsie i");
samdanbury 6:37b6d0d56190 117 }
samdanbury 6:37b6d0d56190 118
samdanbury 6:37b6d0d56190 119 static inline U32 __disable_irq(void)
samdanbury 6:37b6d0d56190 120 {
samdanbury 6:37b6d0d56190 121 U32 result;
samdanbury 6:37b6d0d56190 122
samdanbury 6:37b6d0d56190 123 __asm volatile ("mrs %0, primask" : "=r" (result));
samdanbury 6:37b6d0d56190 124 __asm volatile ("cpsid i");
samdanbury 6:37b6d0d56190 125 return(result & 1);
samdanbury 6:37b6d0d56190 126 }
samdanbury 6:37b6d0d56190 127
samdanbury 6:37b6d0d56190 128 #endif
samdanbury 6:37b6d0d56190 129
samdanbury 6:37b6d0d56190 130 static inline U8 __clz(U32 value)
samdanbury 6:37b6d0d56190 131 {
samdanbury 6:37b6d0d56190 132 U8 result;
samdanbury 6:37b6d0d56190 133
samdanbury 6:37b6d0d56190 134 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
samdanbury 6:37b6d0d56190 135 return(result);
samdanbury 6:37b6d0d56190 136 }
samdanbury 6:37b6d0d56190 137
samdanbury 6:37b6d0d56190 138 #endif
samdanbury 6:37b6d0d56190 139
samdanbury 6:37b6d0d56190 140 /* NVIC registers */
samdanbury 6:37b6d0d56190 141 #define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010))
samdanbury 6:37b6d0d56190 142 #define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014))
samdanbury 6:37b6d0d56190 143 #define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018))
samdanbury 6:37b6d0d56190 144 #define NVIC_ISER ((volatile U32 *)0xE000E100)
samdanbury 6:37b6d0d56190 145 #define NVIC_ICER ((volatile U32 *)0xE000E180)
samdanbury 6:37b6d0d56190 146 #if (__TARGET_ARCH_6S_M)
samdanbury 6:37b6d0d56190 147 #define NVIC_IP ((volatile U32 *)0xE000E400)
samdanbury 6:37b6d0d56190 148 #else
samdanbury 6:37b6d0d56190 149 #define NVIC_IP ((volatile U8 *)0xE000E400)
samdanbury 6:37b6d0d56190 150 #endif
samdanbury 6:37b6d0d56190 151 #define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04))
samdanbury 6:37b6d0d56190 152 #define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0C))
samdanbury 6:37b6d0d56190 153 #define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1C))
samdanbury 6:37b6d0d56190 154 #define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20))
samdanbury 6:37b6d0d56190 155
samdanbury 6:37b6d0d56190 156 #define OS_PEND_IRQ() NVIC_INT_CTRL = (1<<28)
samdanbury 6:37b6d0d56190 157 #define OS_PENDING ((NVIC_INT_CTRL >> 26) & (1<<2 | 1))
samdanbury 6:37b6d0d56190 158 #define OS_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_PENDING) << 25
samdanbury 6:37b6d0d56190 159 #define OS_PEND(fl,p) NVIC_INT_CTRL = (fl | p<<2) << 26
samdanbury 6:37b6d0d56190 160 #define OS_LOCK() NVIC_ST_CTRL = 0x0005
samdanbury 6:37b6d0d56190 161 #define OS_UNLOCK() NVIC_ST_CTRL = 0x0007
samdanbury 6:37b6d0d56190 162
samdanbury 6:37b6d0d56190 163 #define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1)
samdanbury 6:37b6d0d56190 164 #define OS_X_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_X_PENDING) << 27
samdanbury 6:37b6d0d56190 165 #define OS_X_PEND(fl,p) NVIC_INT_CTRL = (fl | p) << 28
samdanbury 6:37b6d0d56190 166 #if (__TARGET_ARCH_6S_M)
samdanbury 6:37b6d0d56190 167 #define OS_X_INIT(n) NVIC_IP[n>>2] |= 0xFF << (8*(n & 0x03)); \
samdanbury 6:37b6d0d56190 168 NVIC_ISER[n>>5] = 1 << (n & 0x1F)
samdanbury 6:37b6d0d56190 169 #else
samdanbury 6:37b6d0d56190 170 #define OS_X_INIT(n) NVIC_IP[n] = 0xFF; \
samdanbury 6:37b6d0d56190 171 NVIC_ISER[n>>5] = 1 << (n & 0x1F)
samdanbury 6:37b6d0d56190 172 #endif
samdanbury 6:37b6d0d56190 173 #define OS_X_LOCK(n) NVIC_ICER[n>>5] = 1 << (n & 0x1F)
samdanbury 6:37b6d0d56190 174 #define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = 1 << (n & 0x1F)
samdanbury 6:37b6d0d56190 175
samdanbury 6:37b6d0d56190 176 /* Core Debug registers */
samdanbury 6:37b6d0d56190 177 #define DEMCR (*((volatile U32 *)0xE000EDFC))
samdanbury 6:37b6d0d56190 178
samdanbury 6:37b6d0d56190 179 /* ITM registers */
samdanbury 6:37b6d0d56190 180 #define ITM_CONTROL (*((volatile U32 *)0xE0000E80))
samdanbury 6:37b6d0d56190 181 #define ITM_ENABLE (*((volatile U32 *)0xE0000E00))
samdanbury 6:37b6d0d56190 182 #define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078))
samdanbury 6:37b6d0d56190 183 #define ITM_PORT31_U32 (*((volatile U32 *)0xE000007C))
samdanbury 6:37b6d0d56190 184 #define ITM_PORT31_U16 (*((volatile U16 *)0xE000007C))
samdanbury 6:37b6d0d56190 185 #define ITM_PORT31_U8 (*((volatile U8 *)0xE000007C))
samdanbury 6:37b6d0d56190 186
samdanbury 6:37b6d0d56190 187 /* Variables */
samdanbury 6:37b6d0d56190 188 extern BIT dbg_msg;
samdanbury 6:37b6d0d56190 189
samdanbury 6:37b6d0d56190 190 /* Functions */
samdanbury 6:37b6d0d56190 191 #ifdef __USE_EXCLUSIVE_ACCESS
samdanbury 6:37b6d0d56190 192 #define rt_inc(p) while(__strex((__ldrex(p)+1),p))
samdanbury 6:37b6d0d56190 193 #define rt_dec(p) while(__strex((__ldrex(p)-1),p))
samdanbury 6:37b6d0d56190 194 #else
samdanbury 6:37b6d0d56190 195 #define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
samdanbury 6:37b6d0d56190 196 #define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
samdanbury 6:37b6d0d56190 197 #endif
samdanbury 6:37b6d0d56190 198
samdanbury 6:37b6d0d56190 199 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
samdanbury 6:37b6d0d56190 200 U32 cnt,c2;
samdanbury 6:37b6d0d56190 201 #ifdef __USE_EXCLUSIVE_ACCESS
samdanbury 6:37b6d0d56190 202 do {
samdanbury 6:37b6d0d56190 203 if ((cnt = __ldrex(count)) == size) {
samdanbury 6:37b6d0d56190 204 __clrex();
samdanbury 6:37b6d0d56190 205 return (cnt); }
samdanbury 6:37b6d0d56190 206 } while (__strex(cnt+1, count));
samdanbury 6:37b6d0d56190 207 do {
samdanbury 6:37b6d0d56190 208 c2 = (cnt = __ldrex(first)) + 1;
samdanbury 6:37b6d0d56190 209 if (c2 == size) c2 = 0;
samdanbury 6:37b6d0d56190 210 } while (__strex(c2, first));
samdanbury 6:37b6d0d56190 211 #else
samdanbury 6:37b6d0d56190 212 __disable_irq();
samdanbury 6:37b6d0d56190 213 if ((cnt = *count) < size) {
samdanbury 6:37b6d0d56190 214 *count = cnt+1;
samdanbury 6:37b6d0d56190 215 c2 = (cnt = *first) + 1;
samdanbury 6:37b6d0d56190 216 if (c2 == size) c2 = 0;
samdanbury 6:37b6d0d56190 217 *first = c2;
samdanbury 6:37b6d0d56190 218 }
samdanbury 6:37b6d0d56190 219 __enable_irq ();
samdanbury 6:37b6d0d56190 220 #endif
samdanbury 6:37b6d0d56190 221 return (cnt);
samdanbury 6:37b6d0d56190 222 }
samdanbury 6:37b6d0d56190 223
samdanbury 6:37b6d0d56190 224 __inline static void rt_systick_init (void) {
samdanbury 6:37b6d0d56190 225 NVIC_ST_RELOAD = os_trv;
samdanbury 6:37b6d0d56190 226 NVIC_ST_CURRENT = 0;
samdanbury 6:37b6d0d56190 227 NVIC_ST_CTRL = 0x0007;
samdanbury 6:37b6d0d56190 228 NVIC_SYS_PRI3 |= 0xFF000000;
samdanbury 6:37b6d0d56190 229 }
samdanbury 6:37b6d0d56190 230
samdanbury 6:37b6d0d56190 231 __inline static void rt_svc_init (void) {
samdanbury 6:37b6d0d56190 232 #if !(__TARGET_ARCH_6S_M)
samdanbury 6:37b6d0d56190 233 int sh,prigroup;
samdanbury 6:37b6d0d56190 234 #endif
samdanbury 6:37b6d0d56190 235 NVIC_SYS_PRI3 |= 0x00FF0000;
samdanbury 6:37b6d0d56190 236 #if (__TARGET_ARCH_6S_M)
samdanbury 6:37b6d0d56190 237 NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000;
samdanbury 6:37b6d0d56190 238 #else
samdanbury 6:37b6d0d56190 239 sh = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000));
samdanbury 6:37b6d0d56190 240 prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07);
samdanbury 6:37b6d0d56190 241 if (prigroup >= sh) {
samdanbury 6:37b6d0d56190 242 sh = prigroup + 1;
samdanbury 6:37b6d0d56190 243 }
samdanbury 6:37b6d0d56190 244 NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF);
samdanbury 6:37b6d0d56190 245 #endif
samdanbury 6:37b6d0d56190 246 }
samdanbury 6:37b6d0d56190 247
samdanbury 6:37b6d0d56190 248 extern void rt_set_PSP (U32 stack);
samdanbury 6:37b6d0d56190 249 extern U32 rt_get_PSP (void);
samdanbury 6:37b6d0d56190 250 extern void os_set_env (void);
samdanbury 6:37b6d0d56190 251 extern void *_alloc_box (void *box_mem);
samdanbury 6:37b6d0d56190 252 extern int _free_box (void *box_mem, void *box);
samdanbury 6:37b6d0d56190 253
samdanbury 6:37b6d0d56190 254 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
samdanbury 6:37b6d0d56190 255 extern void rt_ret_val (P_TCB p_TCB, U32 v0);
samdanbury 6:37b6d0d56190 256 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
samdanbury 6:37b6d0d56190 257
samdanbury 6:37b6d0d56190 258 extern void dbg_init (void);
samdanbury 6:37b6d0d56190 259 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
samdanbury 6:37b6d0d56190 260 extern void dbg_task_switch (U32 task_id);
samdanbury 6:37b6d0d56190 261
samdanbury 6:37b6d0d56190 262 #ifdef DBG_MSG
samdanbury 6:37b6d0d56190 263 #define DBG_INIT() dbg_init()
samdanbury 6:37b6d0d56190 264 #define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
samdanbury 6:37b6d0d56190 265 #define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk != os_tsk.run)) \
samdanbury 6:37b6d0d56190 266 dbg_task_switch(task_id)
samdanbury 6:37b6d0d56190 267 #else
samdanbury 6:37b6d0d56190 268 #define DBG_INIT()
samdanbury 6:37b6d0d56190 269 #define DBG_TASK_NOTIFY(p_tcb,create)
samdanbury 6:37b6d0d56190 270 #define DBG_TASK_SWITCH(task_id)
samdanbury 6:37b6d0d56190 271 #endif
samdanbury 6:37b6d0d56190 272
samdanbury 6:37b6d0d56190 273 /*----------------------------------------------------------------------------
samdanbury 6:37b6d0d56190 274 * end of file
samdanbury 6:37b6d0d56190 275 *---------------------------------------------------------------------------*/
samdanbury 6:37b6d0d56190 276