registers.h

00001 //registers ripped from sparkfun github 
00002 
00003 /* ============================================
00004 I2Cdev device library code is placed under the MIT license
00005 Copyright (c) 2012 Jeff Rowberg
00006 
00007 Permission is hereby granted, free of charge, to any person obtaining a copy
00008 of this software and associated documentation files (the "Software"), to deal
00009 in the Software without restriction, including without limitation the rights
00010 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
00011 copies of the Software, and to permit persons to whom the Software is
00012 furnished to do so, subject to the following conditions:
00013 
00014 The above copyright notice and this permission notice shall be included in
00015 all copies or substantial portions of the Software.
00016 
00017 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
00018 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
00019 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
00020 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
00021 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
00022 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
00023 THE SOFTWARE.
00024 ===============================================
00025 */
00026 
00027 //Magnetometer Registers
00028 #define MPU9150_RA_MAG_ADDRESS      0x0C
00029 #define MPU9150_RA_MAG_XOUT_L       0x03
00030 #define MPU9150_RA_MAG_XOUT_H       0x04
00031 #define MPU9150_RA_MAG_YOUT_L       0x05
00032 #define MPU9150_RA_MAG_YOUT_H       0x06
00033 #define MPU9150_RA_MAG_ZOUT_L       0x07
00034 #define MPU9150_RA_MAG_ZOUT_H       0x08
00035 #define MPU9150_RA_MAG_CTRL         0x0A
00036 
00037 #define MPU6050_ADDRESS_AD0_LOW     0x68 // address pin low (GND), default for InvenSense evaluation board
00038 #define MPU6050_ADDRESS_AD0_HIGH    0x69 // address pin high (VCC)
00039 #define MPU6050_DEFAULT_ADDRESS     MPU6050_ADDRESS_AD0_LOW
00040 
00041 #define MPU6050_RA_XG_OFFS_TC       0x00 //[7] PWR_MODE, [6:1] XG_OFFS_TC, [0] OTP_BNK_VLD
00042 #define MPU6050_RA_YG_OFFS_TC       0x01 //[7] PWR_MODE, [6:1] YG_OFFS_TC, [0] OTP_BNK_VLD
00043 #define MPU6050_RA_ZG_OFFS_TC       0x02 //[7] PWR_MODE, [6:1] ZG_OFFS_TC, [0] OTP_BNK_VLD
00044 #define MPU6050_RA_X_FINE_GAIN      0x03 //[7:0] X_FINE_GAIN
00045 #define MPU6050_RA_Y_FINE_GAIN      0x04 //[7:0] Y_FINE_GAIN
00046 #define MPU6050_RA_Z_FINE_GAIN      0x05 //[7:0] Z_FINE_GAIN
00047 #define MPU6050_RA_XA_OFFS_H        0x06 //[15:0] XA_OFFS
00048 #define MPU6050_RA_XA_OFFS_L_TC     0x07
00049 #define MPU6050_RA_YA_OFFS_H        0x08 //[15:0] YA_OFFS
00050 #define MPU6050_RA_YA_OFFS_L_TC     0x09
00051 #define MPU6050_RA_ZA_OFFS_H        0x0A //[15:0] ZA_OFFS
00052 #define MPU6050_RA_ZA_OFFS_L_TC     0x0B
00053 #define MPU6050_RA_XG_OFFS_USRH     0x13 //[15:0] XG_OFFS_USR
00054 #define MPU6050_RA_XG_OFFS_USRL     0x14
00055 #define MPU6050_RA_YG_OFFS_USRH     0x15 //[15:0] YG_OFFS_USR
00056 #define MPU6050_RA_YG_OFFS_USRL     0x16
00057 #define MPU6050_RA_ZG_OFFS_USRH     0x17 //[15:0] ZG_OFFS_USR
00058 #define MPU6050_RA_ZG_OFFS_USRL     0x18
00059 #define MPU6050_RA_SMPLRT_DIV       0x19
00060 #define MPU6050_RA_CONFIG           0x1A
00061 #define MPU6050_RA_GYRO_CONFIG      0x1B
00062 #define MPU6050_RA_ACCEL_CONFIG     0x1C
00063 #define MPU6050_RA_FF_THR           0x1D
00064 #define MPU6050_RA_FF_DUR           0x1E
00065 #define MPU6050_RA_MOT_THR          0x1F
00066 #define MPU6050_RA_MOT_DUR          0x20
00067 #define MPU6050_RA_ZRMOT_THR        0x21
00068 #define MPU6050_RA_ZRMOT_DUR        0x22
00069 #define MPU6050_RA_FIFO_EN          0x23
00070 #define MPU6050_RA_I2C_MST_CTRL     0x24
00071 #define MPU6050_RA_I2C_SLV0_ADDR    0x25
00072 #define MPU6050_RA_I2C_SLV0_REG     0x26
00073 #define MPU6050_RA_I2C_SLV0_CTRL    0x27
00074 #define MPU6050_RA_I2C_SLV1_ADDR    0x28
00075 #define MPU6050_RA_I2C_SLV1_REG     0x29
00076 #define MPU6050_RA_I2C_SLV1_CTRL    0x2A
00077 #define MPU6050_RA_I2C_SLV2_ADDR    0x2B
00078 #define MPU6050_RA_I2C_SLV2_REG     0x2C
00079 #define MPU6050_RA_I2C_SLV2_CTRL    0x2D
00080 #define MPU6050_RA_I2C_SLV3_ADDR    0x2E
00081 #define MPU6050_RA_I2C_SLV3_REG     0x2F
00082 #define MPU6050_RA_I2C_SLV3_CTRL    0x30
00083 #define MPU6050_RA_I2C_SLV4_ADDR    0x31
00084 #define MPU6050_RA_I2C_SLV4_REG     0x32
00085 #define MPU6050_RA_I2C_SLV4_DO      0x33
00086 #define MPU6050_RA_I2C_SLV4_CTRL    0x34
00087 #define MPU6050_RA_I2C_SLV4_DI      0x35
00088 #define MPU6050_RA_I2C_MST_STATUS   0x36
00089 #define MPU6050_RA_INT_PIN_CFG      0x37
00090 #define MPU6050_RA_INT_ENABLE       0x38
00091 #define MPU6050_RA_DMP_INT_STATUS   0x39
00092 #define MPU6050_RA_INT_STATUS       0x3A
00093 #define MPU6050_RA_ACCEL_XOUT_H     0x3B
00094 #define MPU6050_RA_ACCEL_XOUT_L     0x3C
00095 #define MPU6050_RA_ACCEL_YOUT_H     0x3D
00096 #define MPU6050_RA_ACCEL_YOUT_L     0x3E
00097 #define MPU6050_RA_ACCEL_ZOUT_H     0x3F
00098 #define MPU6050_RA_ACCEL_ZOUT_L     0x40
00099 #define MPU6050_RA_TEMP_OUT_H       0x41
00100 #define MPU6050_RA_TEMP_OUT_L       0x42
00101 #define MPU6050_RA_GYRO_XOUT_H      0x43
00102 #define MPU6050_RA_GYRO_XOUT_L      0x44
00103 #define MPU6050_RA_GYRO_YOUT_H      0x45
00104 #define MPU6050_RA_GYRO_YOUT_L      0x46
00105 #define MPU6050_RA_GYRO_ZOUT_H      0x47
00106 #define MPU6050_RA_GYRO_ZOUT_L      0x48
00107 #define MPU6050_RA_EXT_SENS_DATA_00 0x49
00108 #define MPU6050_RA_EXT_SENS_DATA_01 0x4A
00109 #define MPU6050_RA_EXT_SENS_DATA_02 0x4B
00110 #define MPU6050_RA_EXT_SENS_DATA_03 0x4C
00111 #define MPU6050_RA_EXT_SENS_DATA_04 0x4D
00112 #define MPU6050_RA_EXT_SENS_DATA_05 0x4E
00113 #define MPU6050_RA_EXT_SENS_DATA_06 0x4F
00114 #define MPU6050_RA_EXT_SENS_DATA_07 0x50
00115 #define MPU6050_RA_EXT_SENS_DATA_08 0x51
00116 #define MPU6050_RA_EXT_SENS_DATA_09 0x52
00117 #define MPU6050_RA_EXT_SENS_DATA_10 0x53
00118 #define MPU6050_RA_EXT_SENS_DATA_11 0x54
00119 #define MPU6050_RA_EXT_SENS_DATA_12 0x55
00120 #define MPU6050_RA_EXT_SENS_DATA_13 0x56
00121 #define MPU6050_RA_EXT_SENS_DATA_14 0x57
00122 #define MPU6050_RA_EXT_SENS_DATA_15 0x58
00123 #define MPU6050_RA_EXT_SENS_DATA_16 0x59
00124 #define MPU6050_RA_EXT_SENS_DATA_17 0x5A
00125 #define MPU6050_RA_EXT_SENS_DATA_18 0x5B
00126 #define MPU6050_RA_EXT_SENS_DATA_19 0x5C
00127 #define MPU6050_RA_EXT_SENS_DATA_20 0x5D
00128 #define MPU6050_RA_EXT_SENS_DATA_21 0x5E
00129 #define MPU6050_RA_EXT_SENS_DATA_22 0x5F
00130 #define MPU6050_RA_EXT_SENS_DATA_23 0x60
00131 #define MPU6050_RA_MOT_DETECT_STATUS    0x61
00132 #define MPU6050_RA_I2C_SLV0_DO      0x63
00133 #define MPU6050_RA_I2C_SLV1_DO      0x64
00134 #define MPU6050_RA_I2C_SLV2_DO      0x65
00135 #define MPU6050_RA_I2C_SLV3_DO      0x66
00136 #define MPU6050_RA_I2C_MST_DELAY_CTRL   0x67
00137 #define MPU6050_RA_SIGNAL_PATH_RESET    0x68
00138 #define MPU6050_RA_MOT_DETECT_CTRL      0x69
00139 #define MPU6050_RA_USER_CTRL        0x6A
00140 #define MPU6050_RA_PWR_MGMT_1       0x6B
00141 #define MPU6050_RA_PWR_MGMT_2       0x6C
00142 #define MPU6050_RA_BANK_SEL         0x6D
00143 #define MPU6050_RA_MEM_START_ADDR   0x6E
00144 #define MPU6050_RA_MEM_R_W          0x6F
00145 #define MPU6050_RA_DMP_CFG_1        0x70
00146 #define MPU6050_RA_DMP_CFG_2        0x71
00147 #define MPU6050_RA_FIFO_COUNTH      0x72
00148 #define MPU6050_RA_FIFO_COUNTL      0x73
00149 #define MPU6050_RA_FIFO_R_W         0x74
00150 #define MPU6050_RA_WHO_AM_I         0x75
00151 
00152 #define MPU6050_TC_PWR_MODE_BIT     7
00153 #define MPU6050_TC_OFFSET_BIT       6
00154 #define MPU6050_TC_OFFSET_LENGTH    6
00155 #define MPU6050_TC_OTP_BNK_VLD_BIT  0
00156 
00157 #define MPU6050_VDDIO_LEVEL_VLOGIC  0
00158 #define MPU6050_VDDIO_LEVEL_VDD     1
00159 
00160 #define MPU6050_CFG_EXT_SYNC_SET_BIT    5
00161 #define MPU6050_CFG_EXT_SYNC_SET_LENGTH 3
00162 #define MPU6050_CFG_DLPF_CFG_BIT    2
00163 #define MPU6050_CFG_DLPF_CFG_LENGTH 3
00164 
00165 #define MPU6050_EXT_SYNC_DISABLED       0x0
00166 #define MPU6050_EXT_SYNC_TEMP_OUT_L     0x1
00167 #define MPU6050_EXT_SYNC_GYRO_XOUT_L    0x2
00168 #define MPU6050_EXT_SYNC_GYRO_YOUT_L    0x3
00169 #define MPU6050_EXT_SYNC_GYRO_ZOUT_L    0x4
00170 #define MPU6050_EXT_SYNC_ACCEL_XOUT_L   0x5
00171 #define MPU6050_EXT_SYNC_ACCEL_YOUT_L   0x6
00172 #define MPU6050_EXT_SYNC_ACCEL_ZOUT_L   0x7
00173 
00174 #define MPU6050_DLPF_BW_256         0x00
00175 #define MPU6050_DLPF_BW_188         0x01
00176 #define MPU6050_DLPF_BW_98          0x02
00177 #define MPU6050_DLPF_BW_42          0x03
00178 #define MPU6050_DLPF_BW_20          0x04
00179 #define MPU6050_DLPF_BW_10          0x05
00180 #define MPU6050_DLPF_BW_5           0x06
00181 
00182 #define MPU6050_GCONFIG_FS_SEL_BIT      4
00183 #define MPU6050_GCONFIG_FS_SEL_LENGTH   2
00184 
00185 #define MPU6050_GYRO_FS_250         0x00
00186 #define MPU6050_GYRO_FS_500         0x01
00187 #define MPU6050_GYRO_FS_1000        0x02
00188 #define MPU6050_GYRO_FS_2000        0x03
00189 
00190 #define MPU6050_ACONFIG_XA_ST_BIT           7
00191 #define MPU6050_ACONFIG_YA_ST_BIT           6
00192 #define MPU6050_ACONFIG_ZA_ST_BIT           5
00193 #define MPU6050_ACONFIG_AFS_SEL_BIT         4
00194 #define MPU6050_ACONFIG_AFS_SEL_LENGTH      2
00195 #define MPU6050_ACONFIG_ACCEL_HPF_BIT       2
00196 #define MPU6050_ACONFIG_ACCEL_HPF_LENGTH    3
00197 
00198 #define MPU6050_ACCEL_FS_2          0x00
00199 #define MPU6050_ACCEL_FS_4          0x01
00200 #define MPU6050_ACCEL_FS_8          0x02
00201 #define MPU6050_ACCEL_FS_16         0x03
00202 
00203 #define MPU6050_DHPF_RESET          0x00
00204 #define MPU6050_DHPF_5              0x01
00205 #define MPU6050_DHPF_2P5            0x02
00206 #define MPU6050_DHPF_1P25           0x03
00207 #define MPU6050_DHPF_0P63           0x04
00208 #define MPU6050_DHPF_HOLD           0x07
00209 
00210 #define MPU6050_TEMP_FIFO_EN_BIT    7
00211 #define MPU6050_XG_FIFO_EN_BIT      6
00212 #define MPU6050_YG_FIFO_EN_BIT      5
00213 #define MPU6050_ZG_FIFO_EN_BIT      4
00214 #define MPU6050_ACCEL_FIFO_EN_BIT   3
00215 #define MPU6050_SLV2_FIFO_EN_BIT    2
00216 #define MPU6050_SLV1_FIFO_EN_BIT    1
00217 #define MPU6050_SLV0_FIFO_EN_BIT    0
00218 
00219 #define MPU6050_MULT_MST_EN_BIT     7
00220 #define MPU6050_WAIT_FOR_ES_BIT     6
00221 #define MPU6050_SLV_3_FIFO_EN_BIT   5
00222 #define MPU6050_I2C_MST_P_NSR_BIT   4
00223 #define MPU6050_I2C_MST_CLK_BIT     3
00224 #define MPU6050_I2C_MST_CLK_LENGTH  4
00225 
00226 #define MPU6050_CLOCK_DIV_348       0x0
00227 #define MPU6050_CLOCK_DIV_333       0x1
00228 #define MPU6050_CLOCK_DIV_320       0x2
00229 #define MPU6050_CLOCK_DIV_308       0x3
00230 #define MPU6050_CLOCK_DIV_296       0x4
00231 #define MPU6050_CLOCK_DIV_286       0x5
00232 #define MPU6050_CLOCK_DIV_276       0x6
00233 #define MPU6050_CLOCK_DIV_267       0x7
00234 #define MPU6050_CLOCK_DIV_258       0x8
00235 #define MPU6050_CLOCK_DIV_500       0x9
00236 #define MPU6050_CLOCK_DIV_471       0xA
00237 #define MPU6050_CLOCK_DIV_444       0xB
00238 #define MPU6050_CLOCK_DIV_421       0xC
00239 #define MPU6050_CLOCK_DIV_400       0xD
00240 #define MPU6050_CLOCK_DIV_381       0xE
00241 #define MPU6050_CLOCK_DIV_364       0xF
00242 
00243 #define MPU6050_I2C_SLV_RW_BIT      7
00244 #define MPU6050_I2C_SLV_ADDR_BIT    6
00245 #define MPU6050_I2C_SLV_ADDR_LENGTH 7
00246 #define MPU6050_I2C_SLV_EN_BIT      7
00247 #define MPU6050_I2C_SLV_BYTE_SW_BIT 6
00248 #define MPU6050_I2C_SLV_REG_DIS_BIT 5
00249 #define MPU6050_I2C_SLV_GRP_BIT     4
00250 #define MPU6050_I2C_SLV_LEN_BIT     3
00251 #define MPU6050_I2C_SLV_LEN_LENGTH  4
00252 
00253 #define MPU6050_I2C_SLV4_RW_BIT         7
00254 #define MPU6050_I2C_SLV4_ADDR_BIT       6
00255 #define MPU6050_I2C_SLV4_ADDR_LENGTH    7
00256 #define MPU6050_I2C_SLV4_EN_BIT         7
00257 #define MPU6050_I2C_SLV4_INT_EN_BIT     6
00258 #define MPU6050_I2C_SLV4_REG_DIS_BIT    5
00259 #define MPU6050_I2C_SLV4_MST_DLY_BIT    4
00260 #define MPU6050_I2C_SLV4_MST_DLY_LENGTH 5
00261 
00262 #define MPU6050_MST_PASS_THROUGH_BIT    7
00263 #define MPU6050_MST_I2C_SLV4_DONE_BIT   6
00264 #define MPU6050_MST_I2C_LOST_ARB_BIT    5
00265 #define MPU6050_MST_I2C_SLV4_NACK_BIT   4
00266 #define MPU6050_MST_I2C_SLV3_NACK_BIT   3
00267 #define MPU6050_MST_I2C_SLV2_NACK_BIT   2
00268 #define MPU6050_MST_I2C_SLV1_NACK_BIT   1
00269 #define MPU6050_MST_I2C_SLV0_NACK_BIT   0
00270 
00271 #define MPU6050_INTCFG_INT_LEVEL_BIT        7
00272 #define MPU6050_INTCFG_INT_OPEN_BIT         6
00273 #define MPU6050_INTCFG_LATCH_INT_EN_BIT     5
00274 #define MPU6050_INTCFG_INT_RD_CLEAR_BIT     4
00275 #define MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT  3
00276 #define MPU6050_INTCFG_FSYNC_INT_EN_BIT     2
00277 #define MPU6050_INTCFG_I2C_BYPASS_EN_BIT    1
00278 #define MPU6050_INTCFG_CLKOUT_EN_BIT        0
00279 
00280 #define MPU6050_INTMODE_ACTIVEHIGH  0x00
00281 #define MPU6050_INTMODE_ACTIVELOW   0x01
00282 
00283 #define MPU6050_INTDRV_PUSHPULL     0x00
00284 #define MPU6050_INTDRV_OPENDRAIN    0x01
00285 
00286 #define MPU6050_INTLATCH_50USPULSE  0x00
00287 #define MPU6050_INTLATCH_WAITCLEAR  0x01
00288 
00289 #define MPU6050_INTCLEAR_STATUSREAD 0x00
00290 #define MPU6050_INTCLEAR_ANYREAD    0x01
00291 
00292 #define MPU6050_INTERRUPT_FF_BIT            7
00293 #define MPU6050_INTERRUPT_MOT_BIT           6
00294 #define MPU6050_INTERRUPT_ZMOT_BIT          5
00295 #define MPU6050_INTERRUPT_FIFO_OFLOW_BIT    4
00296 #define MPU6050_INTERRUPT_I2C_MST_INT_BIT   3
00297 #define MPU6050_INTERRUPT_PLL_RDY_INT_BIT   2
00298 #define MPU6050_INTERRUPT_DMP_INT_BIT       1
00299 #define MPU6050_INTERRUPT_DATA_RDY_BIT      0
00300 
00301 // TODO: figure out what these actually do
00302 // UMPL source code is not very obivous
00303 #define MPU6050_DMPINT_5_BIT            5
00304 #define MPU6050_DMPINT_4_BIT            4
00305 #define MPU6050_DMPINT_3_BIT            3
00306 #define MPU6050_DMPINT_2_BIT            2
00307 #define MPU6050_DMPINT_1_BIT            1
00308 #define MPU6050_DMPINT_0_BIT            0
00309 
00310 #define MPU6050_MOTION_MOT_XNEG_BIT     7
00311 #define MPU6050_MOTION_MOT_XPOS_BIT     6
00312 #define MPU6050_MOTION_MOT_YNEG_BIT     5
00313 #define MPU6050_MOTION_MOT_YPOS_BIT     4
00314 #define MPU6050_MOTION_MOT_ZNEG_BIT     3
00315 #define MPU6050_MOTION_MOT_ZPOS_BIT     2
00316 #define MPU6050_MOTION_MOT_ZRMOT_BIT    0
00317 
00318 #define MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT   7
00319 #define MPU6050_DELAYCTRL_I2C_SLV4_DLY_EN_BIT   4
00320 #define MPU6050_DELAYCTRL_I2C_SLV3_DLY_EN_BIT   3
00321 #define MPU6050_DELAYCTRL_I2C_SLV2_DLY_EN_BIT   2
00322 #define MPU6050_DELAYCTRL_I2C_SLV1_DLY_EN_BIT   1
00323 #define MPU6050_DELAYCTRL_I2C_SLV0_DLY_EN_BIT   0
00324 
00325 #define MPU6050_PATHRESET_GYRO_RESET_BIT    2
00326 #define MPU6050_PATHRESET_ACCEL_RESET_BIT   1
00327 #define MPU6050_PATHRESET_TEMP_RESET_BIT    0
00328 
00329 #define MPU6050_DETECT_ACCEL_ON_DELAY_BIT       5
00330 #define MPU6050_DETECT_ACCEL_ON_DELAY_LENGTH    2
00331 #define MPU6050_DETECT_FF_COUNT_BIT             3
00332 #define MPU6050_DETECT_FF_COUNT_LENGTH          2
00333 #define MPU6050_DETECT_MOT_COUNT_BIT            1
00334 #define MPU6050_DETECT_MOT_COUNT_LENGTH         2
00335 
00336 #define MPU6050_DETECT_DECREMENT_RESET  0x0
00337 #define MPU6050_DETECT_DECREMENT_1      0x1
00338 #define MPU6050_DETECT_DECREMENT_2      0x2
00339 #define MPU6050_DETECT_DECREMENT_4      0x3
00340 
00341 #define MPU6050_USERCTRL_DMP_EN_BIT             7
00342 #define MPU6050_USERCTRL_FIFO_EN_BIT            6
00343 #define MPU6050_USERCTRL_I2C_MST_EN_BIT         5
00344 #define MPU6050_USERCTRL_I2C_IF_DIS_BIT         4
00345 #define MPU6050_USERCTRL_DMP_RESET_BIT          3
00346 #define MPU6050_USERCTRL_FIFO_RESET_BIT         2
00347 #define MPU6050_USERCTRL_I2C_MST_RESET_BIT      1
00348 #define MPU6050_USERCTRL_SIG_COND_RESET_BIT     0
00349 
00350 #define MPU6050_PWR1_DEVICE_RESET_BIT   7
00351 #define MPU6050_PWR1_SLEEP_BIT          6
00352 #define MPU6050_PWR1_CYCLE_BIT          5
00353 #define MPU6050_PWR1_TEMP_DIS_BIT       3
00354 #define MPU6050_PWR1_CLKSEL_BIT         2
00355 #define MPU6050_PWR1_CLKSEL_LENGTH      3
00356 
00357 #define MPU6050_CLOCK_INTERNAL          0x00
00358 #define MPU6050_CLOCK_PLL_XGYRO         0x01
00359 #define MPU6050_CLOCK_PLL_YGYRO         0x02
00360 #define MPU6050_CLOCK_PLL_ZGYRO         0x03
00361 #define MPU6050_CLOCK_PLL_EXT32K        0x04
00362 #define MPU6050_CLOCK_PLL_EXT19M        0x05
00363 #define MPU6050_CLOCK_KEEP_RESET        0x07
00364 
00365 #define MPU6050_PWR2_LP_WAKE_CTRL_BIT       7
00366 #define MPU6050_PWR2_LP_WAKE_CTRL_LENGTH    2
00367 #define MPU6050_PWR2_STBY_XA_BIT            5
00368 #define MPU6050_PWR2_STBY_YA_BIT            4
00369 #define MPU6050_PWR2_STBY_ZA_BIT            3
00370 #define MPU6050_PWR2_STBY_XG_BIT            2
00371 #define MPU6050_PWR2_STBY_YG_BIT            1
00372 #define MPU6050_PWR2_STBY_ZG_BIT            0
00373 
00374 #define MPU6050_WAKE_FREQ_1P25      0x0
00375 #define MPU6050_WAKE_FREQ_2P5       0x1
00376 #define MPU6050_WAKE_FREQ_5         0x2
00377 #define MPU6050_WAKE_FREQ_10        0x3
00378 
00379 #define MPU6050_BANKSEL_PRFTCH_EN_BIT       6
00380 #define MPU6050_BANKSEL_CFG_USER_BANK_BIT   5
00381 #define MPU6050_BANKSEL_MEM_SEL_BIT         4
00382 #define MPU6050_BANKSEL_MEM_SEL_LENGTH      5
00383 
00384 #define MPU6050_WHO_AM_I_BIT        6
00385 #define MPU6050_WHO_AM_I_LENGTH     6
00386 
00387 #define MPU6050_DMP_MEMORY_BANKS        8
00388 #define MPU6050_DMP_MEMORY_BANK_SIZE    256
00389 #define MPU6050_DMP_MEMORY_CHUNK_SIZE   16