Aidan Walton
Library to control and transfer data from NXP SGTL5000. As used on the Teensy Audio Shield. It uses DMA to transfer I2S FIFO data.
The Library now supports dual codecs. Allowing all 4 channels of the Teensy I2S interface to RX and TX data to separate SGTL5000 devices.
The ISR routines that handles pointer swaps for double buffering has been fully coded in assembler to reduce overhead and now takes < 800nS per FIFO transfer when using all 4 channels.
Support added for all typical sample rates and system Clock speeds of 96Mhz or 120Mhz.
Pause and Resume functions added to allow quick and simple suppression of IRQs and stream halting and restart. This required software triggered IRQ, in order to ensure accurate word sync control.
Diff: sgtl5000.h
- Revision:
- 4:91354c908416
- Parent:
- 3:62c03088f256
- Child:
- 6:4ab5aaeaa064
--- a/sgtl5000.h Fri Jun 16 12:57:54 2017 +0000
+++ b/sgtl5000.h Fri Jun 30 09:33:42 2017 +0000
@@ -168,8 +168,11 @@
@param BufTX_R_safe A pointer address to the TX Right channel data.
@param block_size 2 | 4 | 8 words of both Left and Right channels combined.
This defines the number of samples that are transferred to the TX FIFO each time a FIFO demand is detected.
+ @param packed_TX If true 2 * 16bit words for wire transmission are expected packed into a single 32bit word.
+ If False each 32bit word from the user should contain a single 16bit word for transmission.
@param TX_shift True = The MS16bits of TX buffer are sent to the TX FIFO. Default = true.
False = The LS16bits of TX buffer are sent to the TX FIFO.
+ If packed is true, then shift has no relevance.
@param tx_DMAch Defines the system DMA channel to assign to the TX transfer. Default is 15.
15 is used as default to avoid using channels 0 - 3 which are the only channels available for gated triggers.
Gated triggering is not needed, so these 4 channels are avoided.
@@ -178,7 +181,7 @@
Fails on variable sanity checks.
*/
int32_t start_TX(uint32_t BufTX_L_safe, uint32_t BufTX_R_safe,
- uint32_t block_size = 4, bool _TX_shift = true, uint32_t _TX_DMAch = 15, uint32_t DMA_irq_pri = 0);
+ uint32_t block_size = 4, bool _packed_TX = false, bool _TX_shift = true, uint32_t _TX_DMAch = 15, uint32_t DMA_irq_pri = 0);
/*!
@brief Attach a callback function to RX
@@ -221,9 +224,12 @@
@param BufRX_R_safe A pointer address to the RX Right channel data.
@param block_size 2 | 4 | 8 words of both Left and Right channels combined.
This defines the number of samples that are transferred to the RX FIFO each time a FIFO demand is detected.
+ @param packed_RX If true the 2 * 16bit words from the codec are packed into a single 32bit word towards the user. This allows user code to use SIMD operations on the data
+ If False a single 16bit word from the wire is placed into a single 32bit word towards the user.
@param RX_shift True = The 16bits of RX FIFO data are shifted to the MSBs of the RX buffer. Default = true
False = The 16bits of RX FIFO data are placed in the LSBs of the RX buffer
Note: If data is not shifted, the 32bit word delivered to the user will not be sign extended.
+ If packed is true, then shift has no relevance.
@param rx_DMAch Defines the system DMA channel to assign to the RX transfer. Default is 14.
14 is used as default to avoid using channels 0 - 3 which are the only channels available for gated triggers.
Gated triggering is not needed, so these 4 channels are avoided.
@@ -232,7 +238,7 @@
Fails on variable sanity checks.
*/
int32_t start_RX(uint32_t BufRX_L_safe, uint32_t BufRX_R_safe,
- uint32_t block_size = 4, bool _RX_shift = true, uint32_t _RX_DMAch = 14, uint32_t DMA_irq_pri = 0);
+ uint32_t block_size = 4, bool _packed_RX = false, bool _RX_shift = true, uint32_t _RX_DMAch = 14, uint32_t DMA_irq_pri = 0);
/*!
@brief Attach a callback function to DMA SYNC
@@ -273,11 +279,17 @@
@param BufRX_L_safe A pointer address to the TX Right channel data.
@param block_size 2 | 4 | 8 words of both Left and Right channels combined.
This defines the number of samples that are transferred to both FIFOs each time a FIFO demand is detected.
+ @param packed_TX If true the 2 * 16bit words for wire transmission are expected packed into a single 32bit word.
+ If False each 32bit word from the user should contain a single 16bit word for transmission.
+ @param packed_RX If true the 2 * 16bit words from the codec are packed into a single 32bit word towards the user. This allows user code to use SIMD operations on the data
+ If False a single 16bit word from the wire is placed into a single 32bit word towards the user.
@param _RX_shift True = The 16bits of RX FIFO data are shifted to the MSBs of the RX buffer. Default = true
False = The 16bits of RX FIFO data are placed in the LSBs of the RX buffer.
Note: If data is not shifted, the 32bit word delivered to the user will not be sign extended.
+ If RX packed is true, then shift has no relevance.
@param _TX_shift True = The MS16bits of TX buffer are sent to the TX FIFO. Default = true.
False = The LS16bits of TX buffer are sent to the TX FIFO.
+ If TX packed is true, then shift has no relevance.
@param _RX_DMAch Defines the system DMA channel to assign to the RX transfer. Default is 14.
@param _TX_DMAch Defines the system DMA channel to assign to the TX transfer. Default is 15.
14 & 15 are used as default to avoid using channels 0 - 3 which are the only channels available for gated triggers.
@@ -287,7 +299,7 @@
Fails on variable sanity checks.
*/
int32_t start_SYNC(uint32_t BufRX_L_safe, uint32_t BufRX_R_safe, uint32_t BufTX_L_safe, uint32_t BufTX_R_safe,
- uint32_t block_size = 4, bool _RX_shift = true, bool _TX_shift = true, uint32_t _RX_DMAch = 14, uint32_t _TX_DMAch = 15, uint32_t DMA_irq_pri = 0);
+ uint32_t block_size = 4, bool _packed_RX = false, bool _packed_TX = false, bool _RX_shift = true, bool _TX_shift = true, uint32_t _RX_DMAch = 14, uint32_t _TX_DMAch = 15, uint32_t DMA_irq_pri = 0);
/*!
@brief Stops i2s TX & RX channels but maintains clocking.
@@ -381,6 +393,9 @@
bool RX_attached;
bool TX_shift;
bool RX_shift;
+
+ bool packed_RX;
+ bool packed_TX;
};
}
#endif
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