Aidan Walton / SGTL5000 Featured

Library to control and transfer data from NXP SGTL5000. As used on the Teensy Audio Shield. It uses DMA to transfer I2S FIFO data.

The Library now supports dual codecs. Allowing all 4 channels of the Teensy I2S interface to RX and TX data to separate SGTL5000 devices.

The ISR routines that handles pointer swaps for double buffering has been fully coded in assembler to reduce overhead and now takes < 800nS per FIFO transfer when using all 4 channels.

Support added for all typical sample rates and system Clock speeds of 96Mhz or 120Mhz.

Pause and Resume functions added to allow quick and simple suppression of IRQs and stream halting and restart. This required software triggered IRQ, in order to ensure accurate word sync control.

Diff: sgtl5000_defs.h

Revision:
10:49bb33f71d32
Parent:
3:62c03088f256
--- a/sgtl5000_defs.h	Sat Jul 15 13:15:08 2017 +0000
+++ b/sgtl5000_defs.h	Tue Sep 26 23:03:32 2017 +0000
@@ -623,6 +623,43 @@
 
 #define SGTL5000_ANA_TEST1          0x0038 //  intended only for debug.
 #define SGTL5000_ANA_TEST2          0x003A //  intended only for debug.
+//14
+#define SGTL5000_ANA_TEST2_LINEOUT_TO_VDDA_MASK                 0x4000       //Changes the LINEOUT amplifier power supply from VDDIO to VDDA. Typically
+                                                                            //LINEOUT should be on the higher power supply. This bit is useful when VDDA is
+                                                                            //~3.3 V and VDDIO is ~1.8 V.
+//13
+#define SGTL5000_ANA_TEST2_SPARE_MASK                           0x2000       // Spare registers to analog
+//12
+#define SGTL5000_ANA_TEST2_MONOMODE_DAC_MASK                    0x1000       // Copy the left channel DAC data to the right channel. This allows both left and right to
+                                                                            //play from MONO dac data.
+//11
+#define SGTL5000_ANA_TEST2_VCO_TUNE_AGAIN_MASK                  0x800       //When toggled high then low forces the PLL VCO to retune the number of inverters in
+                                                                            //the ring oscillator loop.
+//10
+#define SGTL5000_ANA_TEST2_LO_PASS_MASTERVAG_MASK                  0x400    // Tie the main analog VAG to the LINEOUT VAG. This can improve SNR for the
+                                                                            //LINEOUT when both are the same voltage.
+//9
+#define SGTL5000_ANA_TEST2_INVERT_DAC_SAMPLE_CLOCK_MASK           0x200    // Change the clock edge used for the DAC output sampling.
+//8
+#define SGTL5000_ANA_TEST2_INVERT_DAC_DATA_TIMING_MASK           0x100      //Change the clock edge used for the digital to analog DAC data crossing.
+//7
+#define SGTL5000_ANA_TEST2_DAC_EXTEND_RTZ_MASK           0x80              // Extend the return-to-zero time for the DAC.
+//6
+#define SGTL5000_ANA_TEST2_DAC_DOUBLE_I_MASK           0x40                 //Double the output current of the DAC amplifier when it is in classA mode.
+//5
+#define SGTL5000_ANA_TEST2_DAC_DIS_RTZ_MASK           0x20                  // Turn off the return-to-zero in the DAC. In mode cases, this hurts the SNDR of the DAC.
+//4
+#define SGTL5000_ANA_TEST2_DAC_CLASSA_MASK           0x10                   //Turn off the classAB mode in the DAC amplifier. This mode should normally not be
+                                                                            //used. The output current is not high enough to support a full scale signal in this mode.
+//3
+#define SGTL5000_ANA_TEST2_INVERT_ADC_SAMPLE_CLOCK_MASK           0x8       //Change the clock edge used for the ADC sampling.
+//2
+#define SGTL5000_ANA_TEST2_INVERT_ADC_DATA_TIMING_MASK           0x4        // Change the clock edge used for the analog to digital ADC data crossing
+//1
+#define SGTL5000_ANA_TEST2_ADC_LESSI_MASK           0x2                         // Drops ADC bias currents by 20%
+//0
+#define SGTL5000_ANA_TEST2_ADC_DITHEROFF_MASK           0x1                 // Turns off the ADC dithering.
+               
 
 #define SGTL5000_SHORT_CTRL         0x003C
 // 14:12