Aidan Walton
Library to control and transfer data from NXP SGTL5000. As used on the Teensy Audio Shield. It uses DMA to transfer I2S FIFO data.
The Library now supports dual codecs. Allowing all 4 channels of the Teensy I2S interface to RX and TX data to separate SGTL5000 devices.
The ISR routines that handles pointer swaps for double buffering has been fully coded in assembler to reduce overhead and now takes < 800nS per FIFO transfer when using all 4 channels.
Support added for all typical sample rates and system Clock speeds of 96Mhz or 120Mhz.
Pause and Resume functions added to allow quick and simple suppression of IRQs and stream halting and restart. This required software triggered IRQ, in order to ensure accurate word sync control.
sgtl5000_defs.h@3:62c03088f256, 2017-06-16 (annotated)
- Committer:
- aidan1971
- Date:
- Fri Jun 16 12:57:54 2017 +0000
- Revision:
- 3:62c03088f256
- Parent:
- 0:8f28f25e3435
- Child:
- 10:49bb33f71d32
Documentation added and function types corrected to match accurate return types
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| aidan1971 | 3:62c03088f256 | 1 | /*! |
| aidan1971 | 0:8f28f25e3435 | 2 | @ author Aidan Walton, aidan.walton@gmail.com |
| aidan1971 | 0:8f28f25e3435 | 3 | |
| aidan1971 | 0:8f28f25e3435 | 4 | @section LICENSE |
| aidan1971 | 0:8f28f25e3435 | 5 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| aidan1971 | 0:8f28f25e3435 | 6 | * of this software and associated documentation files (the "Software"), to deal |
| aidan1971 | 0:8f28f25e3435 | 7 | * in the Software without restriction, including without limitation the rights |
| aidan1971 | 0:8f28f25e3435 | 8 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| aidan1971 | 0:8f28f25e3435 | 9 | * copies of the Software, and to permit persons to whom the Software is |
| aidan1971 | 0:8f28f25e3435 | 10 | * furnished to do so, subject to the following conditions: |
| aidan1971 | 0:8f28f25e3435 | 11 | * |
| aidan1971 | 0:8f28f25e3435 | 12 | * The above copyright notice, development funding notice, and this permission |
| aidan1971 | 0:8f28f25e3435 | 13 | * notice shall be included in all copies or substantial portions of the Software. |
| aidan1971 | 0:8f28f25e3435 | 14 | * |
| aidan1971 | 0:8f28f25e3435 | 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| aidan1971 | 0:8f28f25e3435 | 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| aidan1971 | 0:8f28f25e3435 | 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| aidan1971 | 0:8f28f25e3435 | 18 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| aidan1971 | 0:8f28f25e3435 | 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| aidan1971 | 0:8f28f25e3435 | 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| aidan1971 | 0:8f28f25e3435 | 21 | * THE SOFTWARE. |
| aidan1971 | 0:8f28f25e3435 | 22 | |
| aidan1971 | 0:8f28f25e3435 | 23 | @section DESCRIPTION |
| aidan1971 | 0:8f28f25e3435 | 24 | Library for NXP SGTL5000 Codec |
| aidan1971 | 0:8f28f25e3435 | 25 | */ |
| aidan1971 | 0:8f28f25e3435 | 26 | |
| aidan1971 | 0:8f28f25e3435 | 27 | #ifndef MBED_SGTL5000_DEFS_H |
| aidan1971 | 0:8f28f25e3435 | 28 | #define MBED_SGTL5000_DEFS_H |
| aidan1971 | 0:8f28f25e3435 | 29 | |
| aidan1971 | 0:8f28f25e3435 | 30 | #define SGTL5000_ID 0x0000 |
| aidan1971 | 0:8f28f25e3435 | 31 | // 15:8 |
| aidan1971 | 0:8f28f25e3435 | 32 | #define SGTL5000_ID_PARTID_MASK 0xFF00 //0xA0 - 8 bit identifier for SGTL5000 |
| aidan1971 | 0:8f28f25e3435 | 33 | #define SGTL5000_ID_PARTID_SHIFT 0x8 |
| aidan1971 | 0:8f28f25e3435 | 34 | // 7:0 |
| aidan1971 | 0:8f28f25e3435 | 35 | #define SGTL5000_ID_REVID_MASK 0xFF //0x00 - revision number for SGTL5000. |
| aidan1971 | 0:8f28f25e3435 | 36 | #define SGTL5000_ID_REVID_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 37 | |
| aidan1971 | 0:8f28f25e3435 | 38 | #define SGTL5000_I2C_ADDR_CS_LOW 0x0A // CTRL_ADR0_CS pin low (normal configuration) |
| aidan1971 | 0:8f28f25e3435 | 39 | #define SGTL5000_I2C_ADDR_CS_HIGH 0x2A // CTRL_ADR0_CS pin high |
| aidan1971 | 0:8f28f25e3435 | 40 | |
| aidan1971 | 0:8f28f25e3435 | 41 | #define SGTL5000_DIG_POWER 0x0002 |
| aidan1971 | 0:8f28f25e3435 | 42 | // 6 |
| aidan1971 | 0:8f28f25e3435 | 43 | #define SGTL5000_DIG_POWER_ADC_POWERUP_MASK 0x40 //1=Enable, 0=disable the ADC block, both digital & analog, |
| aidan1971 | 0:8f28f25e3435 | 44 | #define SGTL5000_DIG_POWER_ADC_POWERUP_SHIFT 0x6 |
| aidan1971 | 0:8f28f25e3435 | 45 | // 5 |
| aidan1971 | 0:8f28f25e3435 | 46 | #define SGTL5000_DIG_POWER_DAC_POWERUP_MASK 0x20 //1=Enable, 0=disable the DAC block, both analog and digital |
| aidan1971 | 0:8f28f25e3435 | 47 | #define SGTL5000_DIG_POWER_DAC_POWERUP_SHIFT 0x5 |
| aidan1971 | 0:8f28f25e3435 | 48 | // 4 |
| aidan1971 | 0:8f28f25e3435 | 49 | #define SGTL5000_DIG_POWER_DAP_POWERUP_MASK 0x10 //1=Enable, 0=disable the DAP block |
| aidan1971 | 0:8f28f25e3435 | 50 | #define SGTL5000_DIG_POWER_DAP_POWERUP_SHIFT 0x4 |
| aidan1971 | 0:8f28f25e3435 | 51 | // 1 |
| aidan1971 | 0:8f28f25e3435 | 52 | #define SGTL5000_DIG_POWER_I2S_OUT_POWERUP_MASK 0x2 //1=Enable, 0=disable the I2S data output |
| aidan1971 | 0:8f28f25e3435 | 53 | #define SGTL5000_DIG_POWER_I2S_OUT_POWERUP_SHIFT 0x1 |
| aidan1971 | 0:8f28f25e3435 | 54 | // 0 |
| aidan1971 | 0:8f28f25e3435 | 55 | #define SGTL5000_DIG_POWER_I2S_IN_POWERUP_MASK 0x1 //1=Enable, 0=disable the I2S data input |
| aidan1971 | 0:8f28f25e3435 | 56 | #define SGTL5000_DIG_POWER_I2S_IN_POWERUP_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 57 | |
| aidan1971 | 0:8f28f25e3435 | 58 | |
| aidan1971 | 0:8f28f25e3435 | 59 | #define SGTL5000_CLK_CTRL 0x0004 |
| aidan1971 | 0:8f28f25e3435 | 60 | // 5:4 |
| aidan1971 | 0:8f28f25e3435 | 61 | #define SGTL5000_CLK_CTRL_RATE_MODE_MASK 0x30 //Sets the sample rate mode. MCLK_FREQ is still specified |
| aidan1971 | 0:8f28f25e3435 | 62 | #define SGTL5000_CLK_CTRL_RATE_MODE_SHIFT 0x4 |
| aidan1971 | 0:8f28f25e3435 | 63 | // relative to the rate in SYS_FS |
| aidan1971 | 0:8f28f25e3435 | 64 | // 0x0 = SYS_FS specifies the rate |
| aidan1971 | 0:8f28f25e3435 | 65 | // 0x1 = Rate is 1/2 of the SYS_FS rate |
| aidan1971 | 0:8f28f25e3435 | 66 | // 0x2 = Rate is 1/4 of the SYS_FS rate |
| aidan1971 | 0:8f28f25e3435 | 67 | // 0x3 = Rate is 1/6 of the SYS_FS rate |
| aidan1971 | 0:8f28f25e3435 | 68 | // 3:2 |
| aidan1971 | 0:8f28f25e3435 | 69 | #define SGTL5000_CLK_CTRL_SYS_FS_MASK 0xC //Sets the internal system sample rate (default=2) |
| aidan1971 | 0:8f28f25e3435 | 70 | #define SGTL5000_CLK_CTRL_SYS_FS_SHIFT 0x2 |
| aidan1971 | 0:8f28f25e3435 | 71 | // 0x0 = 32 kHz |
| aidan1971 | 0:8f28f25e3435 | 72 | // 0x1 = 44.1 kHz |
| aidan1971 | 0:8f28f25e3435 | 73 | // 0x2 = 48 kHz |
| aidan1971 | 0:8f28f25e3435 | 74 | // 0x3 = 96 kHz |
| aidan1971 | 0:8f28f25e3435 | 75 | // 1:0 |
| aidan1971 | 0:8f28f25e3435 | 76 | #define SGTL5000_CLK_CTRL_MCLK_FREQ_MASK 0x3 //Identifies incoming SYS_MCLK frequency and if the PLL should be used |
| aidan1971 | 0:8f28f25e3435 | 77 | #define SGTL5000_CLK_CTRL_MCLK_FREQ_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 78 | // 0x0 = 256*Fs |
| aidan1971 | 0:8f28f25e3435 | 79 | // 0x1 = 384*Fs |
| aidan1971 | 0:8f28f25e3435 | 80 | // 0x2 = 512*Fs |
| aidan1971 | 0:8f28f25e3435 | 81 | // 0x3 = Use PLL |
| aidan1971 | 0:8f28f25e3435 | 82 | // The 0x3 (Use PLL) setting must be used if the SYS_MCLK is not |
| aidan1971 | 0:8f28f25e3435 | 83 | // a standard multiple of Fs (256, 384, or 512). This setting can |
| aidan1971 | 0:8f28f25e3435 | 84 | // also be used if SYS_MCLK is a standard multiple of Fs. |
| aidan1971 | 0:8f28f25e3435 | 85 | // Before this field is set to 0x3 (Use PLL), the PLL must be |
| aidan1971 | 0:8f28f25e3435 | 86 | // powered up by setting CHIP_ANA_POWER->PLL_POWERUP and |
| aidan1971 | 0:8f28f25e3435 | 87 | // CHIP_ANA_POWER->VCOAMP_POWERUP. Also, the PLL dividers must |
| aidan1971 | 0:8f28f25e3435 | 88 | // be calculated based on the external MCLK rate and |
| aidan1971 | 0:8f28f25e3435 | 89 | // CHIP_PLL_CTRL register must be set (see CHIP_PLL_CTRL register |
| aidan1971 | 0:8f28f25e3435 | 90 | // description details on how to calculate the divisors). |
| aidan1971 | 0:8f28f25e3435 | 91 | |
| aidan1971 | 0:8f28f25e3435 | 92 | |
| aidan1971 | 0:8f28f25e3435 | 93 | #define SGTL5000_I2S_CTRL 0x0006 |
| aidan1971 | 0:8f28f25e3435 | 94 | // 8 |
| aidan1971 | 0:8f28f25e3435 | 95 | #define SGTL5000_I2S_CTRL_SCLKFREQ_MASK 0x100 //Sets frequency of I2S_SCLK when in master mode (MS=1). When in slave |
| aidan1971 | 0:8f28f25e3435 | 96 | #define SGTL5000_I2S_CTRL_SCLKFREQ_SHIFT 0x8 |
| aidan1971 | 0:8f28f25e3435 | 97 | // mode (MS=0), this field must be set appropriately to match SCLK input |
| aidan1971 | 0:8f28f25e3435 | 98 | // rate. |
| aidan1971 | 0:8f28f25e3435 | 99 | // 0x0 = 64Fs |
| aidan1971 | 0:8f28f25e3435 | 100 | // 0x1 = 32Fs - Not supported for RJ mode (I2S_MODE = 1) |
| aidan1971 | 0:8f28f25e3435 | 101 | // 7 |
| aidan1971 | 0:8f28f25e3435 | 102 | #define SGTL5000_I2S_CTRL_MS_MASK 0x80 //Configures master or slave of I2S_LRCLK and I2S_SCLK. |
| aidan1971 | 0:8f28f25e3435 | 103 | #define SGTL5000_I2S_CTRL_MS_SHIFT 0x7 |
| aidan1971 | 0:8f28f25e3435 | 104 | // 0x0 = Slave: I2S_LRCLK an I2S_SCLK are inputs |
| aidan1971 | 0:8f28f25e3435 | 105 | // 0x1 = Master: I2S_LRCLK and I2S_SCLK are outputs |
| aidan1971 | 0:8f28f25e3435 | 106 | // NOTE: If the PLL is used (CHIP_CLK_CTRL->MCLK_FREQ==0x3), |
| aidan1971 | 0:8f28f25e3435 | 107 | // the SGTL5000 must be a master of the I2S port (MS==1) |
| aidan1971 | 0:8f28f25e3435 | 108 | // 6 |
| aidan1971 | 0:8f28f25e3435 | 109 | #define SGTL5000_I2S_CTRL_SCLK_INV_MASK 0x40 //Sets the edge that data (input and output) is clocked in on for I2S_SCLK |
| aidan1971 | 0:8f28f25e3435 | 110 | #define SGTL5000_I2S_CTRL_SCLK_INV_SHIFT 0x6 |
| aidan1971 | 0:8f28f25e3435 | 111 | // 0x0 = data is valid on rising edge of I2S_SCLK |
| aidan1971 | 0:8f28f25e3435 | 112 | // 0x1 = data is valid on falling edge of I2S_SCLK |
| aidan1971 | 0:8f28f25e3435 | 113 | // 5:4 |
| aidan1971 | 0:8f28f25e3435 | 114 | #define SGTL5000_I2S_CTRL_DLEN_MASK 0x30 //I2S data length (default=1) |
| aidan1971 | 0:8f28f25e3435 | 115 | #define SGTL5000_I2S_CTRL_DLEN_SHIFT 0x4 |
| aidan1971 | 0:8f28f25e3435 | 116 | // 0x0 = 32 bits (only valid when SCLKFREQ=0), |
| aidan1971 | 0:8f28f25e3435 | 117 | // not valid for Right Justified Mode |
| aidan1971 | 0:8f28f25e3435 | 118 | // 0x1 = 24 bits (only valid when SCLKFREQ=0) |
| aidan1971 | 0:8f28f25e3435 | 119 | // 0x2 = 20 bits |
| aidan1971 | 0:8f28f25e3435 | 120 | // 0x3 = 16 bits |
| aidan1971 | 0:8f28f25e3435 | 121 | // 3:2 |
| aidan1971 | 0:8f28f25e3435 | 122 | #define SGTL5000_I2S_CTRL_MODE_MASK 0x0C //Sets the mode for the I2S port |
| aidan1971 | 0:8f28f25e3435 | 123 | #define SGTL5000_I2S_CTRL_MODE_SHIFT 0x2 |
| aidan1971 | 0:8f28f25e3435 | 124 | // 0x0 = I2S mode or Left Justified (Use LRALIGN to select) |
| aidan1971 | 0:8f28f25e3435 | 125 | // 0x1 = Right Justified Mode |
| aidan1971 | 0:8f28f25e3435 | 126 | // 0x2 = PCM Format A/B |
| aidan1971 | 0:8f28f25e3435 | 127 | // 0x3 = RESERVED |
| aidan1971 | 0:8f28f25e3435 | 128 | // 1 |
| aidan1971 | 0:8f28f25e3435 | 129 | #define SGTL5000_I2S_CTRL_LRALIGN_MASK 0x02 //I2S_LRCLK Alignment to data word. Not used for Right Justified mode |
| aidan1971 | 0:8f28f25e3435 | 130 | #define SGTL5000_I2S_CTRL_LRALIGN_SHIFT 0x1 |
| aidan1971 | 0:8f28f25e3435 | 131 | // 0x0 = Data word starts 1 I2S_SCLK delay after I2S_LRCLK |
| aidan1971 | 0:8f28f25e3435 | 132 | // transition (I2S format, PCM format A) |
| aidan1971 | 0:8f28f25e3435 | 133 | // 0x1 = Data word starts after I2S_LRCLK transition (left |
| aidan1971 | 0:8f28f25e3435 | 134 | // justified format, PCM format B) |
| aidan1971 | 0:8f28f25e3435 | 135 | // 0 |
| aidan1971 | 0:8f28f25e3435 | 136 | #define SGTL5000_I2S_CTRL_LRPOL_MASK 0x01 //I2S_LRCLK Polarity when data is presented. |
| aidan1971 | 0:8f28f25e3435 | 137 | #define SGTL5000_I2S_CTRL_LRPOL_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 138 | // 0x0 = I2S_LRCLK = 0 - Left, 1 - Right |
| aidan1971 | 0:8f28f25e3435 | 139 | // 1x0 = I2S_LRCLK = 0 - Right, 1 - Left |
| aidan1971 | 0:8f28f25e3435 | 140 | // The left subframe should be presented first regardless of |
| aidan1971 | 0:8f28f25e3435 | 141 | // the setting of LRPOL. |
| aidan1971 | 0:8f28f25e3435 | 142 | |
| aidan1971 | 0:8f28f25e3435 | 143 | #define SGTL5000_SSS_CTRL 0x000A |
| aidan1971 | 0:8f28f25e3435 | 144 | // 14 |
| aidan1971 | 0:8f28f25e3435 | 145 | #define SGTL5000_SSS_CTRL_DAP_MIX_LRSWAP_MASK 0x4000 //DAP Mixer Input Swap |
| aidan1971 | 0:8f28f25e3435 | 146 | #define SGTL5000_SSS_CTRL_DAP_MIX_LRSWAP_SHIFT 0xE |
| aidan1971 | 0:8f28f25e3435 | 147 | // 0x0 = Normal Operation |
| aidan1971 | 0:8f28f25e3435 | 148 | // 0x1 = Left and Right channels for the DAP MIXER Input are swapped. |
| aidan1971 | 0:8f28f25e3435 | 149 | // 13 |
| aidan1971 | 0:8f28f25e3435 | 150 | #define SGTL5000_SSS_CTRL_DAP_LRSWAP_MASK 0x2000 //DAP Mixer Input Swap |
| aidan1971 | 0:8f28f25e3435 | 151 | #define SGTL5000_SSS_CTRL_DAP_LRSWAP_SHIFT 0xD |
| aidan1971 | 0:8f28f25e3435 | 152 | // 0x0 = Normal Operation |
| aidan1971 | 0:8f28f25e3435 | 153 | // 0x1 = Left and Right channels for the DAP Input are swapped |
| aidan1971 | 0:8f28f25e3435 | 154 | // 12 |
| aidan1971 | 0:8f28f25e3435 | 155 | #define SGTL5000_SSS_CTRL_DAC_LRSWAP_MASK 0x1000 //DAC Input Swap |
| aidan1971 | 0:8f28f25e3435 | 156 | #define SGTL5000_SSS_CTRL_DAC_LRSWAP_SHIFT 0xC |
| aidan1971 | 0:8f28f25e3435 | 157 | // 0x0 = Normal Operation |
| aidan1971 | 0:8f28f25e3435 | 158 | // 0x1 = Left and Right channels for the DAC are swapped |
| aidan1971 | 0:8f28f25e3435 | 159 | // 10 |
| aidan1971 | 0:8f28f25e3435 | 160 | #define SGTL5000_SSS_CTRL_I2S_LRSWAP_MASK 0x400 //I2S_DOUT Swap |
| aidan1971 | 0:8f28f25e3435 | 161 | #define SGTL5000_SSS_CTRL_I2S_LRSWAP_SHIFT 0xA |
| aidan1971 | 0:8f28f25e3435 | 162 | // 0x0 = Normal Operation |
| aidan1971 | 0:8f28f25e3435 | 163 | // 0x1 = Left and Right channels for the I2S_DOUT are swapped |
| aidan1971 | 0:8f28f25e3435 | 164 | // 9:8 |
| aidan1971 | 0:8f28f25e3435 | 165 | #define SGTL5000_SSS_CTRL_DAP_MIX_SELECT_MASK 0x300 //Select data source for DAP mixer |
| aidan1971 | 0:8f28f25e3435 | 166 | #define SGTL5000_SSS_CTRL_DAP_MIX_SELECT_SHIFT 0x8 |
| aidan1971 | 0:8f28f25e3435 | 167 | // 0x0 = ADC |
| aidan1971 | 0:8f28f25e3435 | 168 | // 0x1 = I2S_IN |
| aidan1971 | 0:8f28f25e3435 | 169 | // 0x2 = Reserved |
| aidan1971 | 0:8f28f25e3435 | 170 | // 0x3 = Reserved |
| aidan1971 | 0:8f28f25e3435 | 171 | // 7:6 |
| aidan1971 | 0:8f28f25e3435 | 172 | #define SGTL5000_SSS_CTRL_DAP_SELECT_MASK 0xC0 //Select data source for DAP |
| aidan1971 | 0:8f28f25e3435 | 173 | #define SGTL5000_SSS_CTRL_DAP_SELECT_SHIFT 0x6 |
| aidan1971 | 0:8f28f25e3435 | 174 | // 0x0 = ADC |
| aidan1971 | 0:8f28f25e3435 | 175 | // 0x1 = I2S_IN |
| aidan1971 | 0:8f28f25e3435 | 176 | // 0x2 = Reserved |
| aidan1971 | 0:8f28f25e3435 | 177 | // 0x3 = Reserved |
| aidan1971 | 0:8f28f25e3435 | 178 | // 5:4 |
| aidan1971 | 0:8f28f25e3435 | 179 | #define SGTL5000_SSS_CTRL_DAC_SELECT_MASK 0x30 //Select data source for DAC (default=1) |
| aidan1971 | 0:8f28f25e3435 | 180 | #define SGTL5000_SSS_CTRL_DAC_SELECT_SHIFT 0x4 |
| aidan1971 | 0:8f28f25e3435 | 181 | // 0x0 = ADC |
| aidan1971 | 0:8f28f25e3435 | 182 | // 0x1 = I2S_IN |
| aidan1971 | 0:8f28f25e3435 | 183 | // 0x2 = Reserved |
| aidan1971 | 0:8f28f25e3435 | 184 | // 0x3 = DAP |
| aidan1971 | 0:8f28f25e3435 | 185 | // 1:0 |
| aidan1971 | 0:8f28f25e3435 | 186 | #define SGTL5000_SSS_CTRL_I2S_SELECT_MASK 0x3 //Select data source for I2S_DOUT |
| aidan1971 | 0:8f28f25e3435 | 187 | #define SGTL5000_SSS_CTRL_I2S_SELECT_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 188 | // 0x0 = ADC |
| aidan1971 | 0:8f28f25e3435 | 189 | // 0x1 = I2S_IN |
| aidan1971 | 0:8f28f25e3435 | 190 | // 0x2 = Reserved |
| aidan1971 | 0:8f28f25e3435 | 191 | // 0x3 = DAP |
| aidan1971 | 0:8f28f25e3435 | 192 | |
| aidan1971 | 0:8f28f25e3435 | 193 | |
| aidan1971 | 0:8f28f25e3435 | 194 | #define SGTL5000_ADCDAC_CTRL 0x000E |
| aidan1971 | 0:8f28f25e3435 | 195 | // 13 |
| aidan1971 | 0:8f28f25e3435 | 196 | #define SGTL5000_ADCDAC_CTRL_VOL_BUSY_DAC_RIGHT_MASK 0x2000 //Volume Busy DAC Right |
| aidan1971 | 0:8f28f25e3435 | 197 | #define SGTL5000_ADCDAC_CTRL_VOL_BUSY_DAC_RIGHT_SHIFT 0xD |
| aidan1971 | 0:8f28f25e3435 | 198 | // 0x0 = Ready |
| aidan1971 | 0:8f28f25e3435 | 199 | // 0x1 = Busy - This indicates the channel has not reached its |
| aidan1971 | 0:8f28f25e3435 | 200 | // programmed volume/mute level |
| aidan1971 | 0:8f28f25e3435 | 201 | // 12 |
| aidan1971 | 0:8f28f25e3435 | 202 | #define SGTL5000_ADCDAC_CTRL_VOL_BUSY_DAC_LEFT_MASK 0x1000 //Volume Busy DAC Left |
| aidan1971 | 0:8f28f25e3435 | 203 | #define SGTL5000_ADCDAC_CTRL_VOL_BUSY_DAC_LEFT_SHIFT 0xC |
| aidan1971 | 0:8f28f25e3435 | 204 | // 0x0 = Ready |
| aidan1971 | 0:8f28f25e3435 | 205 | // 0x1 = Busy - This indicates the channel has not reached its |
| aidan1971 | 0:8f28f25e3435 | 206 | // programmed volume/mute level |
| aidan1971 | 0:8f28f25e3435 | 207 | // 9 |
| aidan1971 | 0:8f28f25e3435 | 208 | #define SGTL5000_ADCDAC_CTRL_VOL_RAMP_EN_MASK 0x200 //Volume Ramp Enable (default=1) |
| aidan1971 | 0:8f28f25e3435 | 209 | #define SGTL5000_ADCDAC_CTRL_VOL_RAMP_EN_SHIFT 0x9 |
| aidan1971 | 0:8f28f25e3435 | 210 | // 0x0 = Disables volume ramp. New volume settings take immediate |
| aidan1971 | 0:8f28f25e3435 | 211 | // effect without a ramp |
| aidan1971 | 0:8f28f25e3435 | 212 | // 0x1 = Enables volume ramp |
| aidan1971 | 0:8f28f25e3435 | 213 | // This field affects DAC_VOL. The volume ramp effects both |
| aidan1971 | 0:8f28f25e3435 | 214 | // volume settings and mute When set to 1 a soft mute is enabled. |
| aidan1971 | 0:8f28f25e3435 | 215 | // 8 |
| aidan1971 | 0:8f28f25e3435 | 216 | #define SGTL5000_ADCDAC_CTRL_VOL_EXPO_RAMP_MASK 0x100 //Exponential Volume Ramp Enable |
| aidan1971 | 0:8f28f25e3435 | 217 | #define SGTL5000_ADCDAC_CTRL_VOL_EXPO_RAMP_SHIFT 0x8 |
| aidan1971 | 0:8f28f25e3435 | 218 | // 0x0 = Linear ramp over top 4 volume octaves |
| aidan1971 | 0:8f28f25e3435 | 219 | // 0x1 = Exponential ramp over full volume range |
| aidan1971 | 0:8f28f25e3435 | 220 | // This bit only takes effect if VOL_RAMP_EN is 1. |
| aidan1971 | 0:8f28f25e3435 | 221 | // 3 |
| aidan1971 | 0:8f28f25e3435 | 222 | #define SGTL5000_ADCDAC_CTRL_DAC_MUTE_RIGHT_MASK 0x8 //DAC Right Mute (default=1) |
| aidan1971 | 0:8f28f25e3435 | 223 | #define SGTL5000_ADCDAC_CTRL_DAC_MUTE_RIGHT_SHIFT 0x3 |
| aidan1971 | 0:8f28f25e3435 | 224 | // 0x0 = Unmute |
| aidan1971 | 0:8f28f25e3435 | 225 | // 0x1 = Muted |
| aidan1971 | 0:8f28f25e3435 | 226 | // If VOL_RAMP_EN = 1, this is a soft mute. |
| aidan1971 | 0:8f28f25e3435 | 227 | // 2 |
| aidan1971 | 0:8f28f25e3435 | 228 | #define SGTL5000_ADCDAC_CTRL_DAC_MUTE_LEFT_MASK 0x4 //DAC Left Mute (default=1) |
| aidan1971 | 0:8f28f25e3435 | 229 | #define SGTL5000_ADCDAC_CTRL_DAC_MUTE_LEFT_SHIFT 0x2 |
| aidan1971 | 0:8f28f25e3435 | 230 | // 0x0 = Unmute |
| aidan1971 | 0:8f28f25e3435 | 231 | // 0x1 = Muted |
| aidan1971 | 0:8f28f25e3435 | 232 | // If VOL_RAMP_EN = 1, this is a soft mute. |
| aidan1971 | 0:8f28f25e3435 | 233 | // 1 |
| aidan1971 | 0:8f28f25e3435 | 234 | #define SGTL5000_ADCDAC_CTRL_ADC_HPF_FREEZE_MASK 0x2 //ADC High Pass Filter Freeze |
| aidan1971 | 0:8f28f25e3435 | 235 | #define SGTL5000_ADCDAC_CTRL_ADC_HPF_FREEZE_SHIFT 0x1 |
| aidan1971 | 0:8f28f25e3435 | 236 | // 0x0 = Normal operation |
| aidan1971 | 0:8f28f25e3435 | 237 | // 0x1 = Freeze the ADC high-pass filter offset register. The |
| aidan1971 | 0:8f28f25e3435 | 238 | // offset continues to be subtracted from the ADC data stream. |
| aidan1971 | 0:8f28f25e3435 | 239 | // 0 |
| aidan1971 | 0:8f28f25e3435 | 240 | #define SGTL5000_ADCDAC_CTRL_ADC_HPF_BYPASS_MASK 0x1 //ADC High Pass Filter Bypass |
| aidan1971 | 0:8f28f25e3435 | 241 | #define SGTL5000_ADCDAC_CTRL_ADC_HPF_BYPASS_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 242 | // 0x0 = Normal operation |
| aidan1971 | 0:8f28f25e3435 | 243 | // 0x1 = Bypassed and offset not updated |
| aidan1971 | 0:8f28f25e3435 | 244 | |
| aidan1971 | 0:8f28f25e3435 | 245 | |
| aidan1971 | 0:8f28f25e3435 | 246 | #define SGTL5000_DAC_VOL 0x0010 |
| aidan1971 | 0:8f28f25e3435 | 247 | //15:8 |
| aidan1971 | 0:8f28f25e3435 | 248 | #define SGTL5000_DAC_VOL_DAC_VOL_RIGHT_MASK 0xFF00 //DAC Right Channel Volume. Set the Right channel DAC volume |
| aidan1971 | 0:8f28f25e3435 | 249 | #define SGTL5000_DAC_VOL_DAC_VOL_RIGHT_SHIFT 0x8 |
| aidan1971 | 0:8f28f25e3435 | 250 | // with 0.5017 dB steps from 0 to -90 dB |
| aidan1971 | 0:8f28f25e3435 | 251 | // 0x3B and less = Reserved |
| aidan1971 | 0:8f28f25e3435 | 252 | // 0x3C = 0 dB |
| aidan1971 | 0:8f28f25e3435 | 253 | // 0x3D = -0.5 dB |
| aidan1971 | 0:8f28f25e3435 | 254 | // 0xF0 = -90 dB |
| aidan1971 | 0:8f28f25e3435 | 255 | // 0xFC and greater = Muted |
| aidan1971 | 0:8f28f25e3435 | 256 | // If VOL_RAMP_EN = 1, there is an automatic ramp to the |
| aidan1971 | 0:8f28f25e3435 | 257 | // new volume setting. |
| aidan1971 | 0:8f28f25e3435 | 258 | // 7:0 |
| aidan1971 | 0:8f28f25e3435 | 259 | #define SGTL5000_DAC_VOL_DAC_VOL_LEFT_MASK 0x00FF //DAC Left Channel Volume. Set the Left channel DAC volume |
| aidan1971 | 0:8f28f25e3435 | 260 | #define SGTL5000_DAC_VOL_DAC_VOL_LEFT_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 261 | // with 0.5017 dB steps from 0 to -90 dB |
| aidan1971 | 0:8f28f25e3435 | 262 | // 0x3B and less = Reserved |
| aidan1971 | 0:8f28f25e3435 | 263 | // 0x3C = 0 dB |
| aidan1971 | 0:8f28f25e3435 | 264 | // 0x3D = -0.5 dB |
| aidan1971 | 0:8f28f25e3435 | 265 | // 0xF0 = -90 dB |
| aidan1971 | 0:8f28f25e3435 | 266 | // 0xFC and greater = Muted |
| aidan1971 | 0:8f28f25e3435 | 267 | // If VOL_RAMP_EN = 1, there is an automatic ramp to the |
| aidan1971 | 0:8f28f25e3435 | 268 | // new volume setting. |
| aidan1971 | 0:8f28f25e3435 | 269 | |
| aidan1971 | 0:8f28f25e3435 | 270 | |
| aidan1971 | 0:8f28f25e3435 | 271 | #define SGTL5000_PAD_STRENGTH 0x0014 |
| aidan1971 | 0:8f28f25e3435 | 272 | // 9:8 |
| aidan1971 | 0:8f28f25e3435 | 273 | #define SGTL5000_PAD_STRENGTH_I2S_LRCLK_MASK 0x300 //I2S LRCLK Pad Drive Strength (default=1) |
| aidan1971 | 0:8f28f25e3435 | 274 | #define SGTL5000_PAD_STRENGTH_I2S_LRCLK_SHIFT 0x8 |
| aidan1971 | 0:8f28f25e3435 | 275 | // Sets drive strength for output pads per the table below. |
| aidan1971 | 0:8f28f25e3435 | 276 | // VDDIO 1.8 V 2.5 V 3.3 V |
| aidan1971 | 0:8f28f25e3435 | 277 | // 0x0 = Disable |
| aidan1971 | 0:8f28f25e3435 | 278 | // 0x1 = 1.66 mA 2.87 mA 4.02 mA |
| aidan1971 | 0:8f28f25e3435 | 279 | // 0x2 = 3.33 mA 5.74 mA 8.03 mA |
| aidan1971 | 0:8f28f25e3435 | 280 | // 0x3 = 4.99 mA 8.61 mA 12.05 mA |
| aidan1971 | 0:8f28f25e3435 | 281 | // 7:6 |
| aidan1971 | 0:8f28f25e3435 | 282 | #define SGTL5000_PAD_STRENGTH_I2S_SCLK_MASK 0xC0 //I2S SCLK Pad Drive Strength (default=1) |
| aidan1971 | 0:8f28f25e3435 | 283 | #define SGTL5000_PAD_STRENGTH_I2S_SCLK_SHIFT 0x6 |
| aidan1971 | 0:8f28f25e3435 | 284 | // 5:4 |
| aidan1971 | 0:8f28f25e3435 | 285 | #define SGTL5000_PAD_STRENGTH_I2S_DOUT_MASK 0x30 //I2S DOUT Pad Drive Strength (default=1) |
| aidan1971 | 0:8f28f25e3435 | 286 | #define SGTL5000_PAD_STRENGTH_I2S_DOUT_SHIFT 0x4 |
| aidan1971 | 0:8f28f25e3435 | 287 | // 3:2 |
| aidan1971 | 0:8f28f25e3435 | 288 | #define SGTL5000_PAD_STRENGTH_CTRL_DATA_MASK 0xC //I2C DATA Pad Drive Strength (default=3) |
| aidan1971 | 0:8f28f25e3435 | 289 | #define SGTL5000_PAD_STRENGTH_CTRL_DATA_SHIFT 0x2 |
| aidan1971 | 0:8f28f25e3435 | 290 | // 1:0 |
| aidan1971 | 0:8f28f25e3435 | 291 | #define SGTL5000_PAD_STRENGTH_CTRL_CLK_MASK 0x3 //I2C CLK Pad Drive Strength (default=3) |
| aidan1971 | 0:8f28f25e3435 | 292 | #define SGTL5000_PAD_STRENGTH_CTRL_CLK_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 293 | // (all use same table as I2S_LRCLK) |
| aidan1971 | 0:8f28f25e3435 | 294 | |
| aidan1971 | 0:8f28f25e3435 | 295 | |
| aidan1971 | 0:8f28f25e3435 | 296 | #define SGTL5000_ANA_ADC_CTRL 0x0020 |
| aidan1971 | 0:8f28f25e3435 | 297 | // 8 |
| aidan1971 | 0:8f28f25e3435 | 298 | #define SGTL5000_ANA_ADC_CTRL_ADC_VOL_M6DB_MASK 0x100 //ADC Volume Range Reduction |
| aidan1971 | 0:8f28f25e3435 | 299 | #define SGTL5000_ANA_ADC_CTRL_ADC_VOL_M6DB_SHIFT 0x8 |
| aidan1971 | 0:8f28f25e3435 | 300 | // This bit shifts both right and left analog ADC volume |
| aidan1971 | 0:8f28f25e3435 | 301 | // range down by 6.0 dB. |
| aidan1971 | 0:8f28f25e3435 | 302 | // 0x0 = No change in ADC range |
| aidan1971 | 0:8f28f25e3435 | 303 | // 0x1 = ADC range reduced by 6.0 dB |
| aidan1971 | 0:8f28f25e3435 | 304 | // 7:4 |
| aidan1971 | 0:8f28f25e3435 | 305 | #define SGTL5000_ANA_ADC_CTRL_ADC_VOL_RIGHT_MASK 0xF0 //ADC Right Channel Volume |
| aidan1971 | 0:8f28f25e3435 | 306 | #define SGTL5000_ANA_ADC_CTRL_ADC_VOL_RIGHT_SHIFT 0x4 |
| aidan1971 | 0:8f28f25e3435 | 307 | // Right channel analog ADC volume control in 1.5 dB steps. |
| aidan1971 | 0:8f28f25e3435 | 308 | // 0x0 = 0 dB |
| aidan1971 | 0:8f28f25e3435 | 309 | // 0x1 = +1.5 dB |
| aidan1971 | 0:8f28f25e3435 | 310 | // ... |
| aidan1971 | 0:8f28f25e3435 | 311 | // 0xF = +22.5 dB |
| aidan1971 | 0:8f28f25e3435 | 312 | // This range is -6.0 dB to +16.5 dB if ADC_VOL_M6DB is set to 1. |
| aidan1971 | 0:8f28f25e3435 | 313 | // 3:0 |
| aidan1971 | 0:8f28f25e3435 | 314 | #define SGTL5000_ANA_ADC_CTRL_ADC_VOL_LEFT_MASK 0xF //ADC Left Channel Volume |
| aidan1971 | 0:8f28f25e3435 | 315 | #define SGTL5000_ANA_ADC_CTRL_ADC_VOL_LEFT_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 316 | // (same scale as ADC_VOL_RIGHT) |
| aidan1971 | 0:8f28f25e3435 | 317 | |
| aidan1971 | 0:8f28f25e3435 | 318 | |
| aidan1971 | 0:8f28f25e3435 | 319 | #define SGTL5000_ANA_HP_CTRL 0x0022 |
| aidan1971 | 0:8f28f25e3435 | 320 | // 14:8 |
| aidan1971 | 0:8f28f25e3435 | 321 | #define SGTL5000_ANA_HP_CTRL_HP_VOL_RIGHT_MASK 0x7F00 //Headphone Right Channel Volume (default 0x18) |
| aidan1971 | 0:8f28f25e3435 | 322 | #define SGTL5000_ANA_HP_CTRL_HP_VOL_RIGHT_SHIFT 0x8 |
| aidan1971 | 0:8f28f25e3435 | 323 | // Right channel headphone volume control with 0.5 dB steps. |
| aidan1971 | 0:8f28f25e3435 | 324 | // 0x00 = +12 dB |
| aidan1971 | 0:8f28f25e3435 | 325 | // 0x01 = +11.5 dB |
| aidan1971 | 0:8f28f25e3435 | 326 | // 0x18 = 0 dB |
| aidan1971 | 0:8f28f25e3435 | 327 | // ... |
| aidan1971 | 0:8f28f25e3435 | 328 | // 0x7F = -51.5 dB |
| aidan1971 | 0:8f28f25e3435 | 329 | // 6:0 |
| aidan1971 | 0:8f28f25e3435 | 330 | #define SGTL5000_ANA_HP_CTRL_HP_VOL_LEFT_MASK 0x7F //Headphone Left Channel Volume (default 0x18) |
| aidan1971 | 0:8f28f25e3435 | 331 | #define SGTL5000_ANA_HP_CTRL_HP_VOL_LEFT_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 332 | // (same scale as HP_VOL_RIGHT) |
| aidan1971 | 0:8f28f25e3435 | 333 | |
| aidan1971 | 0:8f28f25e3435 | 334 | |
| aidan1971 | 0:8f28f25e3435 | 335 | #define SGTL5000_ANA_CTRL 0x0024 |
| aidan1971 | 0:8f28f25e3435 | 336 | // 8 |
| aidan1971 | 0:8f28f25e3435 | 337 | #define SGTL5000_ANA_CTRL_MUTE_LO_MASK 0x100 //LINEOUT Mute, 0 = Unmute, 1 = Mute (default 1) |
| aidan1971 | 0:8f28f25e3435 | 338 | #define SGTL5000_ANA_CTRL_MUTE_LO_SHIFT 0x8 |
| aidan1971 | 0:8f28f25e3435 | 339 | // 6 |
| aidan1971 | 0:8f28f25e3435 | 340 | #define SGTL5000_ANA_CTRL_SELECT_HP_MASK 0x40 //Select the headphone input, 0 = DAC, 1 = LINEIN |
| aidan1971 | 0:8f28f25e3435 | 341 | #define SGTL5000_ANA_CTRL_SELECT_HP_SHIFT 0x6 |
| aidan1971 | 0:8f28f25e3435 | 342 | // 5 |
| aidan1971 | 0:8f28f25e3435 | 343 | #define SGTL5000_ANA_CTRL_EN_ZCD_HP_MASK 0x20 //Enable the headphone zero cross detector (ZCD) |
| aidan1971 | 0:8f28f25e3435 | 344 | #define SGTL5000_ANA_CTRL_EN_ZCD_HP_SHIFT 0x5 |
| aidan1971 | 0:8f28f25e3435 | 345 | // 0x0 = HP ZCD disabled |
| aidan1971 | 0:8f28f25e3435 | 346 | // 0x1 = HP ZCD enabled |
| aidan1971 | 0:8f28f25e3435 | 347 | // 4 |
| aidan1971 | 0:8f28f25e3435 | 348 | #define SGTL5000_ANA_CTRL_MUTE_HP_MASK 0x10 //Mute the headphone outputs, 0 = Unmute, 1 = Mute (default) |
| aidan1971 | 0:8f28f25e3435 | 349 | #define SGTL5000_ANA_CTRL_MUTE_HP_SHIFT 0x4 |
| aidan1971 | 0:8f28f25e3435 | 350 | // 2 |
| aidan1971 | 0:8f28f25e3435 | 351 | #define SGTL5000_ANA_CTRL_SELECT_ADC_MASK 0x4 //Select the ADC input, 0 = Microphone, 1 = LINEIN |
| aidan1971 | 0:8f28f25e3435 | 352 | #define SGTL5000_ANA_CTRL_SELECT_ADC_SHIFT 0x2 |
| aidan1971 | 0:8f28f25e3435 | 353 | // 1 |
| aidan1971 | 0:8f28f25e3435 | 354 | #define SGTL5000_ANA_CTRL_EN_ZCD_ADC_MASK 0x2 //Enable the ADC analog zero cross detector (ZCD) |
| aidan1971 | 0:8f28f25e3435 | 355 | #define SGTL5000_ANA_CTRL_EN_ZCD_ADC_SHIFT 0x1 |
| aidan1971 | 0:8f28f25e3435 | 356 | // 0x0 = ADC ZCD disabled |
| aidan1971 | 0:8f28f25e3435 | 357 | // 0x1 = ADC ZCD enabled |
| aidan1971 | 0:8f28f25e3435 | 358 | // 0 |
| aidan1971 | 0:8f28f25e3435 | 359 | #define SGTL5000_ANA_CTRL_MUTE_ADC_MASK 0x1 //Mute the ADC analog volume, 0 = Unmute, 1 = Mute (default) |
| aidan1971 | 0:8f28f25e3435 | 360 | #define SGTL5000_ANA_CTRL_MUTE_ADC_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 361 | |
| aidan1971 | 0:8f28f25e3435 | 362 | #define SGTL5000_LINREG_CTRL 0x0026 |
| aidan1971 | 0:8f28f25e3435 | 363 | // 6 |
| aidan1971 | 0:8f28f25e3435 | 364 | #define SGTL5000_LINREG_CTRL_VDDC_MAN_ASSN_MASK 0x40 //Determines chargepump source when VDDC_ASSN_OVRD is set. |
| aidan1971 | 0:8f28f25e3435 | 365 | #define SGTL5000_LINREG_CTRL_VDDC_MAN_ASSN_SHIFT 0x6 |
| aidan1971 | 0:8f28f25e3435 | 366 | // 0x0 = VDDA |
| aidan1971 | 0:8f28f25e3435 | 367 | // 0x1 = VDDIO |
| aidan1971 | 0:8f28f25e3435 | 368 | // 5 |
| aidan1971 | 0:8f28f25e3435 | 369 | #define SGTL5000_LINREG_CTRL_VDDC_ASSN_OVRD_MASK 0x20 //Charge pump Source Assignment Override |
| aidan1971 | 0:8f28f25e3435 | 370 | #define SGTL5000_LINREG_CTRL_VDDC_ASSN_OVRD_SHIFT 0x5 |
| aidan1971 | 0:8f28f25e3435 | 371 | // 0x0 = Charge pump source is automatically assigned based |
| aidan1971 | 0:8f28f25e3435 | 372 | // on higher of VDDA and VDDIO |
| aidan1971 | 0:8f28f25e3435 | 373 | // 0x1 = the source of charge pump is manually assigned by |
| aidan1971 | 0:8f28f25e3435 | 374 | // VDDC_MAN_ASSN If VDDIO and VDDA are both the same |
| aidan1971 | 0:8f28f25e3435 | 375 | // and greater than 3.1 V, VDDC_ASSN_OVRD and |
| aidan1971 | 0:8f28f25e3435 | 376 | // VDDC_MAN_ASSN should be used to manually assign |
| aidan1971 | 0:8f28f25e3435 | 377 | // VDDIO as the source for charge pump. |
| aidan1971 | 0:8f28f25e3435 | 378 | // 3:0 |
| aidan1971 | 0:8f28f25e3435 | 379 | #define SGTL5000_LINREG_CTRL_D_PROGRAMMING_MASK 0xF //Sets the VDDD linear regulator output voltage in 50 mV steps. |
| aidan1971 | 0:8f28f25e3435 | 380 | #define SGTL5000_LINREG_CTRL_D_PROGRAMMING_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 381 | // Must clear the LINREG_SIMPLE_POWERUP and STARTUP_POWERUP bits |
| aidan1971 | 0:8f28f25e3435 | 382 | // in the 0x0030 (CHIP_ANA_POWER) register after power-up, for |
| aidan1971 | 0:8f28f25e3435 | 383 | // this setting to produce the proper VDDD voltage. |
| aidan1971 | 0:8f28f25e3435 | 384 | // 0x0 = 1.60 |
| aidan1971 | 0:8f28f25e3435 | 385 | // 0xF = 0.85 |
| aidan1971 | 0:8f28f25e3435 | 386 | |
| aidan1971 | 0:8f28f25e3435 | 387 | |
| aidan1971 | 0:8f28f25e3435 | 388 | #define SGTL5000_REF_CTRL 0x0028 // bandgap reference bias voltage and currents |
| aidan1971 | 0:8f28f25e3435 | 389 | // 8:4 |
| aidan1971 | 0:8f28f25e3435 | 390 | #define SGTL5000_REF_CTRL_VAG_VAL_MASK 0x1F0 //Analog Ground Voltage Control |
| aidan1971 | 0:8f28f25e3435 | 391 | #define SGTL5000_REF_CTRL_VAG_VAL_SHIFT 0x4 |
| aidan1971 | 0:8f28f25e3435 | 392 | // These bits control the analog ground voltage in 25 mV steps. |
| aidan1971 | 0:8f28f25e3435 | 393 | // This should usually be set to VDDA/2 or lower for best |
| aidan1971 | 0:8f28f25e3435 | 394 | // performance (maximum output swing at minimum THD). This VAG |
| aidan1971 | 0:8f28f25e3435 | 395 | // reference is also used for the DAC and ADC voltage reference. |
| aidan1971 | 0:8f28f25e3435 | 396 | // So changing this voltage scales the output swing of the DAC |
| aidan1971 | 0:8f28f25e3435 | 397 | // and the output signal of the ADC. |
| aidan1971 | 0:8f28f25e3435 | 398 | // 0x00 = 0.800 V |
| aidan1971 | 0:8f28f25e3435 | 399 | // 0x1F = 1.575 V |
| aidan1971 | 0:8f28f25e3435 | 400 | // 3:1 |
| aidan1971 | 0:8f28f25e3435 | 401 | #define SGTL5000_REF_CTRL_BIAS_CTRL_MASK 0xE //Bias control |
| aidan1971 | 0:8f28f25e3435 | 402 | #define SGTL5000_REF_CTRL_BIAS_CTRL_SHIFT 0x1 |
| aidan1971 | 0:8f28f25e3435 | 403 | // These bits adjust the bias currents for all of the analog |
| aidan1971 | 0:8f28f25e3435 | 404 | // blocks. By lowering the bias current a lower quiescent power |
| aidan1971 | 0:8f28f25e3435 | 405 | // is achieved. It should be noted that this mode can affect |
| aidan1971 | 0:8f28f25e3435 | 406 | // performance by 3-4 dB. |
| aidan1971 | 0:8f28f25e3435 | 407 | // 0x0 = Nominal |
| aidan1971 | 0:8f28f25e3435 | 408 | // 0x1-0x3=+12.5% |
| aidan1971 | 0:8f28f25e3435 | 409 | // 0x4=-12.5% |
| aidan1971 | 0:8f28f25e3435 | 410 | // 0x5=-25% |
| aidan1971 | 0:8f28f25e3435 | 411 | // 0x6=-37.5% |
| aidan1971 | 0:8f28f25e3435 | 412 | // 0x7=-50% |
| aidan1971 | 0:8f28f25e3435 | 413 | // 0 |
| aidan1971 | 0:8f28f25e3435 | 414 | #define SGTL5000_REF_CTRL_SMALL_POP_MASK 0x1 //VAG Ramp Control |
| aidan1971 | 0:8f28f25e3435 | 415 | #define SGTL5000_REF_CTRL_SMALL_POP_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 416 | // Setting this bit slows down the VAG ramp from ~200 to ~400 ms |
| aidan1971 | 0:8f28f25e3435 | 417 | // to reduce the startup pop, but increases the turn on/off time. |
| aidan1971 | 0:8f28f25e3435 | 418 | // 0x0 = Normal VAG ramp |
| aidan1971 | 0:8f28f25e3435 | 419 | // 0x1 = Slow down VAG ramp |
| aidan1971 | 0:8f28f25e3435 | 420 | |
| aidan1971 | 0:8f28f25e3435 | 421 | |
| aidan1971 | 0:8f28f25e3435 | 422 | #define SGTL5000_MIC_CTRL 0x002A // microphone gain & internal microphone bias |
| aidan1971 | 0:8f28f25e3435 | 423 | // 9:8 |
| aidan1971 | 0:8f28f25e3435 | 424 | #define SGTL5000_MIC_CTRL_BIAS_RESISTOR_MASK 0x300 //MIC Bias Output Impedance Adjustment |
| aidan1971 | 0:8f28f25e3435 | 425 | #define SGTL5000_MIC_CTRL_BIAS_RESISTOR_SHIFT 0x8 |
| aidan1971 | 0:8f28f25e3435 | 426 | // Controls an adjustable output impedance for the microphone bias. |
| aidan1971 | 0:8f28f25e3435 | 427 | // If this is set to zero the micbias block is powered off and |
| aidan1971 | 0:8f28f25e3435 | 428 | // the output is highZ. |
| aidan1971 | 0:8f28f25e3435 | 429 | // 0x0 = Powered off |
| aidan1971 | 0:8f28f25e3435 | 430 | // 0x1 = 2.0 kohm |
| aidan1971 | 0:8f28f25e3435 | 431 | // 0x2 = 4.0 kohm |
| aidan1971 | 0:8f28f25e3435 | 432 | // 0x3 = 8.0 kohm |
| aidan1971 | 0:8f28f25e3435 | 433 | // 6:4 |
| aidan1971 | 0:8f28f25e3435 | 434 | #define SGTL5000_MIC_CTRL_BIAS_VOLT_MASK 0x70 //MIC Bias Voltage Adjustment |
| aidan1971 | 0:8f28f25e3435 | 435 | #define SGTL5000_MIC_CTRL_BIAS_VOLT_SHIFT 0x4 |
| aidan1971 | 0:8f28f25e3435 | 436 | // Controls an adjustable bias voltage for the microphone bias |
| aidan1971 | 0:8f28f25e3435 | 437 | // amp in 250 mV steps. This bias voltage setting should be no |
| aidan1971 | 0:8f28f25e3435 | 438 | // more than VDDA-200 mV for adequate power supply rejection. |
| aidan1971 | 0:8f28f25e3435 | 439 | // 0x0 = 1.25 V |
| aidan1971 | 0:8f28f25e3435 | 440 | // ... |
| aidan1971 | 0:8f28f25e3435 | 441 | // 0x7 = 3.00 V |
| aidan1971 | 0:8f28f25e3435 | 442 | // 1:0 |
| aidan1971 | 0:8f28f25e3435 | 443 | #define SGTL5000_MIC_CTRL_GAIN_MASK 0x3 //MIC Amplifier Gain |
| aidan1971 | 0:8f28f25e3435 | 444 | #define SGTL5000_MIC_CTRL_GAIN_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 445 | // Sets the microphone amplifier gain. At 0 dB setting the THD |
| aidan1971 | 0:8f28f25e3435 | 446 | // can be slightly higher than other paths- typically around |
| aidan1971 | 0:8f28f25e3435 | 447 | // ~65 dB. At other gain settings the THD are better. |
| aidan1971 | 0:8f28f25e3435 | 448 | // 0x0 = 0 dB |
| aidan1971 | 0:8f28f25e3435 | 449 | // 0x1 = +20 dB |
| aidan1971 | 0:8f28f25e3435 | 450 | // 0x2 = +30 dB |
| aidan1971 | 0:8f28f25e3435 | 451 | // 0x3 = +40 dB |
| aidan1971 | 0:8f28f25e3435 | 452 | |
| aidan1971 | 0:8f28f25e3435 | 453 | |
| aidan1971 | 0:8f28f25e3435 | 454 | #define SGTL5000_LINE_OUT_CTRL 0x002C |
| aidan1971 | 0:8f28f25e3435 | 455 | // 11:8 |
| aidan1971 | 0:8f28f25e3435 | 456 | #define SGTL5000_LINE_OUT_CTRL_OUT_CURRENT_MASK 0xF00 //Controls the output bias current for the LINEOUT amplifiers. The |
| aidan1971 | 0:8f28f25e3435 | 457 | #define SGTL5000_LINE_OUT_CTRL_OUT_CURRENT_SHIFT 0x8 |
| aidan1971 | 0:8f28f25e3435 | 458 | // nominal recommended setting for a 10 kohm load with 1.0 nF load cap |
| aidan1971 | 0:8f28f25e3435 | 459 | // is 0x3. There are only 5 valid settings. |
| aidan1971 | 0:8f28f25e3435 | 460 | // 0x0=0.18 mA |
| aidan1971 | 0:8f28f25e3435 | 461 | // 0x1=0.27 mA |
| aidan1971 | 0:8f28f25e3435 | 462 | // 0x3=0.36 mA |
| aidan1971 | 0:8f28f25e3435 | 463 | // 0x7=0.45 mA |
| aidan1971 | 0:8f28f25e3435 | 464 | // 0xF=0.54 mA |
| aidan1971 | 0:8f28f25e3435 | 465 | // 5:0 |
| aidan1971 | 0:8f28f25e3435 | 466 | #define SGTL5000_LINE_OUT_CTRL_LO_VAGCNTRL_MASK 0x3F //LINEOUT Amplifier Analog Ground Voltage |
| aidan1971 | 0:8f28f25e3435 | 467 | #define SGTL5000_LINE_OUT_CTRL_LO_VAGCNTRL_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 468 | // Controls the analog ground voltage for the LINEOUT amplifiers |
| aidan1971 | 0:8f28f25e3435 | 469 | // in 25 mV steps. This should usually be set to VDDIO/2. |
| aidan1971 | 0:8f28f25e3435 | 470 | // 0x00 = 0.800 V |
| aidan1971 | 0:8f28f25e3435 | 471 | // ... |
| aidan1971 | 0:8f28f25e3435 | 472 | // 0x1F = 1.575 V |
| aidan1971 | 0:8f28f25e3435 | 473 | // ... |
| aidan1971 | 0:8f28f25e3435 | 474 | // 0x23 = 1.675 V |
| aidan1971 | 0:8f28f25e3435 | 475 | // 0x24-0x3F are invalid |
| aidan1971 | 0:8f28f25e3435 | 476 | |
| aidan1971 | 0:8f28f25e3435 | 477 | |
| aidan1971 | 0:8f28f25e3435 | 478 | #define SGTL5000_LINE_OUT_VOL 0x002E |
| aidan1971 | 0:8f28f25e3435 | 479 | // 12:8 |
| aidan1971 | 0:8f28f25e3435 | 480 | #define SGTL5000_LINE_OUT_VOL_LO_VOL_RIGHT_MASK 0x1F00 //LINEOUT Right Channel Volume (default=4) |
| aidan1971 | 0:8f28f25e3435 | 481 | #define SGTL5000_LINE_OUT_VOL_LO_VOL_RIGHT_SHIFT 0x8 |
| aidan1971 | 0:8f28f25e3435 | 482 | // Controls the right channel LINEOUT volume in 0.5 dB steps. |
| aidan1971 | 0:8f28f25e3435 | 483 | // Higher codes have more attenuation. |
| aidan1971 | 0:8f28f25e3435 | 484 | // 4:0 |
| aidan1971 | 0:8f28f25e3435 | 485 | #define SGTL5000_LINE_OUT_VOL_LO_VOL_LEFT_MASK 0x001F //LINEOUT Left Channel Output Level (default=4) |
| aidan1971 | 0:8f28f25e3435 | 486 | #define SGTL5000_LINE_OUT_VOL_LO_VOL_LEFT_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 487 | // Used to normalize the output level of the left line output |
| aidan1971 | 0:8f28f25e3435 | 488 | // to full scale based on the values used to set |
| aidan1971 | 0:8f28f25e3435 | 489 | // LINE_OUT_CTRL->LO_VAGCNTRL and CHIP_REF_CTRL->VAG_VAL. |
| aidan1971 | 0:8f28f25e3435 | 490 | // In general this field should be set to: |
| aidan1971 | 0:8f28f25e3435 | 491 | // 40*log((VAG_VAL)/(LO_VAGCNTRL)) + 15 |
| aidan1971 | 0:8f28f25e3435 | 492 | // Suggested values based on typical VDDIO and VDDA voltages. |
| aidan1971 | 0:8f28f25e3435 | 493 | // VDDA VAG_VAL VDDIO LO_VAGCNTRL LO_VOL_* |
| aidan1971 | 0:8f28f25e3435 | 494 | // 1.8 V 0.9 3.3 V 1.55 0x06 |
| aidan1971 | 0:8f28f25e3435 | 495 | // 1.8 V 0.9 1.8 V 0.9 0x0F |
| aidan1971 | 0:8f28f25e3435 | 496 | // 3.3 V 1.55 1.8 V 0.9 0x19 |
| aidan1971 | 0:8f28f25e3435 | 497 | // 3.3 V 1.55 3.3 V 1.55 0x0F |
| aidan1971 | 0:8f28f25e3435 | 498 | // After setting to the nominal voltage, this field can be used |
| aidan1971 | 0:8f28f25e3435 | 499 | // to adjust the output level in +/-0.5 dB increments by using |
| aidan1971 | 0:8f28f25e3435 | 500 | // values higher or lower than the nominal setting. |
| aidan1971 | 0:8f28f25e3435 | 501 | |
| aidan1971 | 0:8f28f25e3435 | 502 | |
| aidan1971 | 0:8f28f25e3435 | 503 | #define SGTL5000_ANA_POWER 0x0030 // power down controls for the analog blocks. |
| aidan1971 | 0:8f28f25e3435 | 504 | // The only other power-down controls are BIAS_RESISTOR in the MIC_CTRL register |
| aidan1971 | 0:8f28f25e3435 | 505 | // and the EN_ZCD control bits in ANA_CTRL. |
| aidan1971 | 0:8f28f25e3435 | 506 | // 14 |
| aidan1971 | 0:8f28f25e3435 | 507 | #define SGTL5000_ANA_POWER_DAC_MONO_MASK 0x4000 //While DAC_POWERUP is set, this allows the DAC to be put into left only |
| aidan1971 | 0:8f28f25e3435 | 508 | #define SGTL5000_ANA_POWER_DAC_MONO_SHIFT 0xE |
| aidan1971 | 0:8f28f25e3435 | 509 | // mono operation for power savings. 0=mono, 1=stereo (default) |
| aidan1971 | 0:8f28f25e3435 | 510 | // 13 |
| aidan1971 | 0:8f28f25e3435 | 511 | #define SGTL5000_ANA_POWER_LINREG_SIMPLE_POWERUP_MASK 0x2000 //Power up the simple (low power) digital supply regulator. |
| aidan1971 | 0:8f28f25e3435 | 512 | #define SGTL5000_ANA_POWER_LINREG_SIMPLE_POWERUP_SHIFT 0xD |
| aidan1971 | 0:8f28f25e3435 | 513 | // After reset, this bit can be cleared IF VDDD is driven |
| aidan1971 | 0:8f28f25e3435 | 514 | // externally OR the primary digital linreg is enabled with |
| aidan1971 | 0:8f28f25e3435 | 515 | // LINREG_D_POWERUP |
| aidan1971 | 0:8f28f25e3435 | 516 | // 12 |
| aidan1971 | 0:8f28f25e3435 | 517 | #define SGTL5000_ANA_POWER_STARTUP_POWERUP_MASK 0x1000 //Power up the circuitry needed during the power up ramp and reset. |
| aidan1971 | 0:8f28f25e3435 | 518 | #define SGTL5000_ANA_POWER_STARTUP_POWERUP_SHIFT 0xC |
| aidan1971 | 0:8f28f25e3435 | 519 | // After reset this bit can be cleared if VDDD is coming from |
| aidan1971 | 0:8f28f25e3435 | 520 | // an external source. |
| aidan1971 | 0:8f28f25e3435 | 521 | // 11 |
| aidan1971 | 0:8f28f25e3435 | 522 | #define SGTL5000_ANA_POWER_VDDC_CHRGPMP_POWERUP_MASK 0x800 //Power up the VDDC charge pump block. If neither VDDA or VDDIO |
| aidan1971 | 0:8f28f25e3435 | 523 | #define SGTL5000_ANA_POWER_VDDC_CHRGPMP_POWERUP_SHIFT 0xB |
| aidan1971 | 0:8f28f25e3435 | 524 | // is 3.0 V or larger this bit should be cleared before analog |
| aidan1971 | 0:8f28f25e3435 | 525 | // blocks are powered up. |
| aidan1971 | 0:8f28f25e3435 | 526 | // 10 |
| aidan1971 | 0:8f28f25e3435 | 527 | #define SGTL5000_ANA_POWER_PLL_POWERUP_MASK 0x400 //PLL Power Up, 0 = Power down, 1 = Power up |
| aidan1971 | 0:8f28f25e3435 | 528 | #define SGTL5000_ANA_POWER_PLL_POWERUP_SHIFT 0xA |
| aidan1971 | 0:8f28f25e3435 | 529 | // When cleared, the PLL is turned off. This must be set before |
| aidan1971 | 0:8f28f25e3435 | 530 | // CHIP_CLK_CTRL->MCLK_FREQ is programmed to 0x3. The |
| aidan1971 | 0:8f28f25e3435 | 531 | // CHIP_PLL_CTRL register must be configured correctly before |
| aidan1971 | 0:8f28f25e3435 | 532 | // setting this bit. |
| aidan1971 | 0:8f28f25e3435 | 533 | // 9 |
| aidan1971 | 0:8f28f25e3435 | 534 | #define SGTL5000_ANA_POWER_LINREG_D_POWERUP_MASK 0x200 //Power up the primary VDDD linear regulator, 0 = Power down, 1 = Power up |
| aidan1971 | 0:8f28f25e3435 | 535 | #define SGTL5000_ANA_POWER_LINREG_D_POWERUP_SHIFT 0x9 |
| aidan1971 | 0:8f28f25e3435 | 536 | // 8 |
| aidan1971 | 0:8f28f25e3435 | 537 | #define SGTL5000_ANA_POWER_VCOAMP_POWERUP_MASK 0x100 //Power up the PLL VCO amplifier, 0 = Power down, 1 = Power up |
| aidan1971 | 0:8f28f25e3435 | 538 | #define SGTL5000_ANA_POWER_VCOAMP_POWERUP_SHIFT 0x8 |
| aidan1971 | 0:8f28f25e3435 | 539 | // 7 |
| aidan1971 | 0:8f28f25e3435 | 540 | #define SGTL5000_ANA_POWER_VAG_POWERUP_MASK 0x80 //Power up the VAG reference buffer. |
| aidan1971 | 0:8f28f25e3435 | 541 | #define SGTL5000_ANA_POWER_VAG_POWERUP_SHIFT 0x7 |
| aidan1971 | 0:8f28f25e3435 | 542 | // Setting this bit starts the power up ramp for the headphone |
| aidan1971 | 0:8f28f25e3435 | 543 | // and LINEOUT. The headphone (and/or LINEOUT) powerup should |
| aidan1971 | 0:8f28f25e3435 | 544 | // be set BEFORE clearing this bit. When this bit is cleared |
| aidan1971 | 0:8f28f25e3435 | 545 | // the power-down ramp is started. The headphone (and/or LINEOUT) |
| aidan1971 | 0:8f28f25e3435 | 546 | // powerup should stay set until the VAG is fully ramped down |
| aidan1971 | 0:8f28f25e3435 | 547 | // (200 to 400 ms after clearing this bit). |
| aidan1971 | 0:8f28f25e3435 | 548 | // 0x0 = Power down, 0x1 = Power up |
| aidan1971 | 0:8f28f25e3435 | 549 | // 6 |
| aidan1971 | 0:8f28f25e3435 | 550 | #define SGTL5000_ANA_POWER_ADC_MONO_MASK 0x40 //While ADC_POWERUP is set, this allows the ADC to be put into left only |
| aidan1971 | 0:8f28f25e3435 | 551 | #define SGTL5000_ANA_POWER_ADC_MONO_SHIFT 0x6 |
| aidan1971 | 0:8f28f25e3435 | 552 | // mono operation for power savings. This mode is useful when |
| aidan1971 | 0:8f28f25e3435 | 553 | // only using the microphone input. |
| aidan1971 | 0:8f28f25e3435 | 554 | // 0x0 = Mono (left only), 0x1 = Stereo |
| aidan1971 | 0:8f28f25e3435 | 555 | // 5 |
| aidan1971 | 0:8f28f25e3435 | 556 | #define SGTL5000_ANA_POWER_REFTOP_POWERUP_MASK 0x20 //Power up the reference bias currents |
| aidan1971 | 0:8f28f25e3435 | 557 | #define SGTL5000_ANA_POWER_REFTOP_POWERUP_SHIFT 0x5 |
| aidan1971 | 0:8f28f25e3435 | 558 | // 0x0 = Power down, 0x1 = Power up |
| aidan1971 | 0:8f28f25e3435 | 559 | // This bit can be cleared when the part is a sleep state |
| aidan1971 | 0:8f28f25e3435 | 560 | // to minimize analog power. |
| aidan1971 | 0:8f28f25e3435 | 561 | // 4 |
| aidan1971 | 0:8f28f25e3435 | 562 | #define SGTL5000_ANA_POWER_HEADPHONE_POWERUP_MASK 0x10 //Power up the headphone amplifiers |
| aidan1971 | 0:8f28f25e3435 | 563 | #define SGTL5000_ANA_POWER_HEADPHONE_POWERUP_SHIFT 0x4 |
| aidan1971 | 0:8f28f25e3435 | 564 | // 0x0 = Power down, 0x1 = Power up |
| aidan1971 | 0:8f28f25e3435 | 565 | // 3 |
| aidan1971 | 0:8f28f25e3435 | 566 | #define SGTL5000_ANA_POWER_DAC_POWERUP_MASK 0x8 //Power up the DACs |
| aidan1971 | 0:8f28f25e3435 | 567 | #define SGTL5000_ANA_POWER_DAC_POWERUP_SHIFT 0x3 |
| aidan1971 | 0:8f28f25e3435 | 568 | // 0x0 = Power down, 0x1 = Power up |
| aidan1971 | 0:8f28f25e3435 | 569 | // 2 |
| aidan1971 | 0:8f28f25e3435 | 570 | #define SGTL5000_ANA_POWER_CAPLESS_HEADPHONE_POWERUP_MASK 0x4 //Power up the capless headphone mode |
| aidan1971 | 0:8f28f25e3435 | 571 | #define SGTL5000_ANA_POWER_CAPLESS_HEADPHONE_POWERUP_SHIFT 0x2 |
| aidan1971 | 0:8f28f25e3435 | 572 | // 0x0 = Power down, 0x1 = Power up |
| aidan1971 | 0:8f28f25e3435 | 573 | // 1 |
| aidan1971 | 0:8f28f25e3435 | 574 | #define SGTL5000_ANA_POWER_ADC_POWERUP_MASK 0x2 //Power up the ADCs |
| aidan1971 | 0:8f28f25e3435 | 575 | #define SGTL5000_ANA_POWER_ADC_POWERUP_SHIFT 0x1 |
| aidan1971 | 0:8f28f25e3435 | 576 | // 0x0 = Power down, 0x1 = Power up |
| aidan1971 | 0:8f28f25e3435 | 577 | // 0 |
| aidan1971 | 0:8f28f25e3435 | 578 | #define SGTL5000_ANA_POWER_LINEOUT_POWERUP_MASK 0x1 //Power up the LINEOUT amplifiers |
| aidan1971 | 0:8f28f25e3435 | 579 | #define SGTL5000_ANA_POWER_LINEOUT_POWERUP_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 580 | // 0x0 = Power down, 0x1 = Power up |
| aidan1971 | 0:8f28f25e3435 | 581 | |
| aidan1971 | 0:8f28f25e3435 | 582 | |
| aidan1971 | 0:8f28f25e3435 | 583 | #define SGTL5000_PLL_CTRL 0x0032 |
| aidan1971 | 0:8f28f25e3435 | 584 | // 15:11 |
| aidan1971 | 0:8f28f25e3435 | 585 | #define SGTL5000_PLL_CTRL_INT_DIVISOR_MASK 0xF800 |
| aidan1971 | 0:8f28f25e3435 | 586 | #define SGTL5000_PLL_CTRL_INT_DIVISOR_SHIFT 0xB |
| aidan1971 | 0:8f28f25e3435 | 587 | // 10:0 |
| aidan1971 | 0:8f28f25e3435 | 588 | #define SGTL5000_PLL_CTRL_FRAC_DIVISOR_MASK 0x7FF |
| aidan1971 | 0:8f28f25e3435 | 589 | #define SGTL5000_PLL_CTRL_FRAC_DIVISOR_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 590 | |
| aidan1971 | 0:8f28f25e3435 | 591 | |
| aidan1971 | 0:8f28f25e3435 | 592 | #define SGTL5000_CLK_TOP_CTRL 0x0034 |
| aidan1971 | 0:8f28f25e3435 | 593 | // 11 |
| aidan1971 | 0:8f28f25e3435 | 594 | #define SGTL5000_CLK_TOP_CTRL_ENABLE_INT_OSC_MASK 0x800 //Setting this bit enables an internal oscillator to be used for the |
| aidan1971 | 0:8f28f25e3435 | 595 | #define SGTL5000_CLK_TOP_CTRL_ENABLE_INT_OSC_SHIFT 0xB |
| aidan1971 | 0:8f28f25e3435 | 596 | // zero cross detectors, the short detect recovery, and the |
| aidan1971 | 0:8f28f25e3435 | 597 | // charge pump. This allows the I2S clock to be shut off while |
| aidan1971 | 0:8f28f25e3435 | 598 | // still operating an analog signal path. This bit can be kept |
| aidan1971 | 0:8f28f25e3435 | 599 | // on when the I2S clock is enabled, but the I2S clock is more |
| aidan1971 | 0:8f28f25e3435 | 600 | // accurate so it is preferred to clear this bit when I2S is present. |
| aidan1971 | 0:8f28f25e3435 | 601 | // 3 |
| aidan1971 | 0:8f28f25e3435 | 602 | #define SGTL5000_CLK_TOP_CTRL_INPUT_FREQ_DIV2_MASK 0x8 //SYS_MCLK divider before PLL input |
| aidan1971 | 0:8f28f25e3435 | 603 | #define SGTL5000_CLK_TOP_CTRL_INPUT_FREQ_DIV2_SHIFT 0x3 |
| aidan1971 | 0:8f28f25e3435 | 604 | // 0x0 = pass through |
| aidan1971 | 0:8f28f25e3435 | 605 | // 0x1 = SYS_MCLK is divided by 2 before entering PLL |
| aidan1971 | 0:8f28f25e3435 | 606 | // This must be set when the input clock is above 17 Mhz. This |
| aidan1971 | 0:8f28f25e3435 | 607 | // has no effect when the PLL is powered down. |
| aidan1971 | 0:8f28f25e3435 | 608 | |
| aidan1971 | 0:8f28f25e3435 | 609 | |
| aidan1971 | 0:8f28f25e3435 | 610 | #define SGTL5000_ANA_STATUS 0x0036 |
| aidan1971 | 0:8f28f25e3435 | 611 | // 9 |
| aidan1971 | 0:8f28f25e3435 | 612 | #define SGTL5000_ANA_STATUS_LRSHORT_STS_MASK 0x200 //This bit is high whenever a short is detected on the left or right |
| aidan1971 | 0:8f28f25e3435 | 613 | #define SGTL5000_ANA_STATUS_LRSHORT_STS_SHIFT 0x9 |
| aidan1971 | 0:8f28f25e3435 | 614 | // channel headphone drivers. |
| aidan1971 | 0:8f28f25e3435 | 615 | // 8 |
| aidan1971 | 0:8f28f25e3435 | 616 | #define SGTL5000_ANA_STATUS_CSHORT_STS_MASK 0x100 //This bit is high whenever a short is detected on the capless headphone |
| aidan1971 | 0:8f28f25e3435 | 617 | #define SGTL5000_ANA_STATUS_CSHORT_STS_SHIFT 0x8 |
| aidan1971 | 0:8f28f25e3435 | 618 | // common/center channel driver. |
| aidan1971 | 0:8f28f25e3435 | 619 | // 4 |
| aidan1971 | 0:8f28f25e3435 | 620 | #define SGTL5000_ANA_STATUS_PLL_IS_LOCKED_MASK 0x10 //This bit goes high after the PLL is locked. |
| aidan1971 | 0:8f28f25e3435 | 621 | #define SGTL5000_ANA_STATUS_PLL_IS_LOCKED_SHIFT 0x4 |
| aidan1971 | 0:8f28f25e3435 | 622 | |
| aidan1971 | 0:8f28f25e3435 | 623 | |
| aidan1971 | 0:8f28f25e3435 | 624 | #define SGTL5000_ANA_TEST1 0x0038 // intended only for debug. |
| aidan1971 | 0:8f28f25e3435 | 625 | #define SGTL5000_ANA_TEST2 0x003A // intended only for debug. |
| aidan1971 | 0:8f28f25e3435 | 626 | |
| aidan1971 | 0:8f28f25e3435 | 627 | #define SGTL5000_SHORT_CTRL 0x003C |
| aidan1971 | 0:8f28f25e3435 | 628 | // 14:12 |
| aidan1971 | 0:8f28f25e3435 | 629 | #define SGTL5000_SHORT_CTRL_LVLADJR_MASK 0x7000 //Right channel headphone short detector in 25 mA steps. |
| aidan1971 | 0:8f28f25e3435 | 630 | #define SGTL5000_SHORT_CTRL_LVLADJR_SHIFT 0xC |
| aidan1971 | 0:8f28f25e3435 | 631 | // 0x3=25 mA |
| aidan1971 | 0:8f28f25e3435 | 632 | // 0x2=50 mA |
| aidan1971 | 0:8f28f25e3435 | 633 | // 0x1=75 mA |
| aidan1971 | 0:8f28f25e3435 | 634 | // 0x0=100 mA |
| aidan1971 | 0:8f28f25e3435 | 635 | // 0x4=125 mA |
| aidan1971 | 0:8f28f25e3435 | 636 | // 0x5=150 mA |
| aidan1971 | 0:8f28f25e3435 | 637 | // 0x6=175 mA |
| aidan1971 | 0:8f28f25e3435 | 638 | // 0x7=200 mA |
| aidan1971 | 0:8f28f25e3435 | 639 | // This trip point can vary by ~30% over process so leave plenty |
| aidan1971 | 0:8f28f25e3435 | 640 | // of guard band to avoid false trips. This short detect trip |
| aidan1971 | 0:8f28f25e3435 | 641 | // point is also effected by the bias current adjustments made |
| aidan1971 | 0:8f28f25e3435 | 642 | // by CHIP_REF_CTRL->BIAS_CTRL and by CHIP_ANA_TEST1->HP_IALL_ADJ. |
| aidan1971 | 0:8f28f25e3435 | 643 | // 10:8 |
| aidan1971 | 0:8f28f25e3435 | 644 | #define SGTL5000_SHORT_CTRL_LVLADJL_MASK 0x700 //Left channel headphone short detector in 25 mA steps. |
| aidan1971 | 0:8f28f25e3435 | 645 | #define SGTL5000_SHORT_CTRL_LVLADJL_SHIFT 0x8 |
| aidan1971 | 0:8f28f25e3435 | 646 | // (same scale as LVLADJR) |
| aidan1971 | 0:8f28f25e3435 | 647 | // 6:4 |
| aidan1971 | 0:8f28f25e3435 | 648 | #define SGTL5000_SHORT_CTRL_LVLADJC_MASK 0x70 //Capless headphone center channel short detector in 50 mA steps. |
| aidan1971 | 0:8f28f25e3435 | 649 | #define SGTL5000_SHORT_CTRL_LVLADJC_SHIFT 0x4 |
| aidan1971 | 0:8f28f25e3435 | 650 | // 0x3=50 mA |
| aidan1971 | 0:8f28f25e3435 | 651 | // 0x2=100 mA |
| aidan1971 | 0:8f28f25e3435 | 652 | // 0x1=150 mA |
| aidan1971 | 0:8f28f25e3435 | 653 | // 0x0=200 mA |
| aidan1971 | 0:8f28f25e3435 | 654 | // 0x4=250 mA |
| aidan1971 | 0:8f28f25e3435 | 655 | // 0x5=300 mA |
| aidan1971 | 0:8f28f25e3435 | 656 | // 0x6=350 mA |
| aidan1971 | 0:8f28f25e3435 | 657 | // 0x7=400 mA |
| aidan1971 | 0:8f28f25e3435 | 658 | // 3:2 |
| aidan1971 | 0:8f28f25e3435 | 659 | #define SGTL5000_SHORT_CTRL_MODE_LR_MASK 0xC //Behavior of left/right short detection |
| aidan1971 | 0:8f28f25e3435 | 660 | #define SGTL5000_SHORT_CTRL_MODE_LR_SHIFT 0x2 |
| aidan1971 | 0:8f28f25e3435 | 661 | // 0x0 = Disable short detector, reset short detect latch, |
| aidan1971 | 0:8f28f25e3435 | 662 | // software view non-latched short signal |
| aidan1971 | 0:8f28f25e3435 | 663 | // 0x1 = Enable short detector and reset the latch at timeout |
| aidan1971 | 0:8f28f25e3435 | 664 | // (every ~50 ms) |
| aidan1971 | 0:8f28f25e3435 | 665 | // 0x2 = This mode is not used/invalid |
| aidan1971 | 0:8f28f25e3435 | 666 | // 0x3 = Enable short detector with only manual reset (have |
| aidan1971 | 0:8f28f25e3435 | 667 | // to return to 0x0 to reset the latch) |
| aidan1971 | 0:8f28f25e3435 | 668 | // 1:0 |
| aidan1971 | 0:8f28f25e3435 | 669 | #define SGTL5000_SHORT_CTRL_MODE_CM_MASK 0x3 //Behavior of capless headphone central short detection |
| aidan1971 | 0:8f28f25e3435 | 670 | #define SGTL5000_SHORT_CTRL_MODE_CM_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 671 | // (same settings as MODE_LR) |
| aidan1971 | 0:8f28f25e3435 | 672 | |
| aidan1971 | 0:8f28f25e3435 | 673 | |
| aidan1971 | 0:8f28f25e3435 | 674 | #define SGTL5000_DAP_CONTROL 0x0100 |
| aidan1971 | 0:8f28f25e3435 | 675 | //4 |
| aidan1971 | 0:8f28f25e3435 | 676 | #define SGTL5000_DAP_CONTROL_MIX_EN_MASK 0x10 //Enable/Disable the DAP mixer path |
| aidan1971 | 0:8f28f25e3435 | 677 | #define SGTL5000_DAP_CONTROL_MIX_EN_SHIFT 0x4 |
| aidan1971 | 0:8f28f25e3435 | 678 | // 0x0 = Disable |
| aidan1971 | 0:8f28f25e3435 | 679 | // 0x1 = Enable |
| aidan1971 | 0:8f28f25e3435 | 680 | // When enabled, DAP_EN must also be enabled to use the mixer. |
| aidan1971 | 0:8f28f25e3435 | 681 | |
| aidan1971 | 0:8f28f25e3435 | 682 | //0 |
| aidan1971 | 0:8f28f25e3435 | 683 | #define SGTL5000_DAP_CONTROL_DAP_EN_MASK 0x1 // Enable/Disable digital audio processing (DAP) |
| aidan1971 | 0:8f28f25e3435 | 684 | #define SGTL5000_DAP_CONTROL_DAP_EN_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 685 | // 0x0 = Disable. When disabled, no audio passes through. |
| aidan1971 | 0:8f28f25e3435 | 686 | // 0x1 = Enable. When enabled, audio can pass through DAP even if none of the DAP |
| aidan1971 | 0:8f28f25e3435 | 687 | // functions are enabled. |
| aidan1971 | 0:8f28f25e3435 | 688 | |
| aidan1971 | 0:8f28f25e3435 | 689 | #define SGTL5000_DAP_PEQ 0x0102 |
| aidan1971 | 0:8f28f25e3435 | 690 | //2:0 |
| aidan1971 | 0:8f28f25e3435 | 691 | #define SGTL5000_DAP_PEQ_EN_MASK 0x7 //Set to Enable the PEQ filters |
| aidan1971 | 0:8f28f25e3435 | 692 | #define SGTL5000_DAP_PEQ_EN_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 693 | // 0x0 = Disabled |
| aidan1971 | 0:8f28f25e3435 | 694 | // 0x1 = 1 Filter Enabled |
| aidan1971 | 0:8f28f25e3435 | 695 | // 0x2 = 2 Filters Enabled |
| aidan1971 | 0:8f28f25e3435 | 696 | // ..... |
| aidan1971 | 0:8f28f25e3435 | 697 | // 0x7 = Cascaded 7 Filters |
| aidan1971 | 0:8f28f25e3435 | 698 | // DAP_AUDIO_EQ->EN bit must be set to 1 in order to enable the PEQ |
| aidan1971 | 0:8f28f25e3435 | 699 | |
| aidan1971 | 0:8f28f25e3435 | 700 | #define SGTL5000_DAP_BASS_ENHANCE 0x0104 |
| aidan1971 | 0:8f28f25e3435 | 701 | //8 |
| aidan1971 | 0:8f28f25e3435 | 702 | #define SGTL5000_DAP_BASS_ENHANCE_BYPASS_HPF_MASK 0x100 // Bypass high pass filter |
| aidan1971 | 0:8f28f25e3435 | 703 | #define SGTL5000_DAP_BASS_ENHANCE_BYPASS_HPF_SHIFT 0x8 |
| aidan1971 | 0:8f28f25e3435 | 704 | // 0x0 = Enable high pass filter |
| aidan1971 | 0:8f28f25e3435 | 705 | // 0x1 = Bypass high pass filter |
| aidan1971 | 0:8f28f25e3435 | 706 | //6:4 |
| aidan1971 | 0:8f28f25e3435 | 707 | #define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_MASK 0x70 //Set cut-off frequency |
| aidan1971 | 0:8f28f25e3435 | 708 | #define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_SHIFT 0x4 |
| aidan1971 | 0:8f28f25e3435 | 709 | // 0x0 = 80 Hz |
| aidan1971 | 0:8f28f25e3435 | 710 | // 0x1 = 100 Hz |
| aidan1971 | 0:8f28f25e3435 | 711 | // 0x2 = 125 Hz |
| aidan1971 | 0:8f28f25e3435 | 712 | // 0x3 = 150 Hz |
| aidan1971 | 0:8f28f25e3435 | 713 | // 0x4 = 175 Hz |
| aidan1971 | 0:8f28f25e3435 | 714 | // 0x5 = 200 Hz |
| aidan1971 | 0:8f28f25e3435 | 715 | // 0x6 = 225 Hz |
| aidan1971 | 0:8f28f25e3435 | 716 | //0 |
| aidan1971 | 0:8f28f25e3435 | 717 | #define SGTL5000_DAP_BASS_ENHANCE_EN_MASK 0x1 //Enable/Disable Bass Enhance |
| aidan1971 | 0:8f28f25e3435 | 718 | #define SGTL5000_DAP_BASS_ENHANCE_EN_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 719 | // 0x0 = Disable |
| aidan1971 | 0:8f28f25e3435 | 720 | // 0x1 = Enable |
| aidan1971 | 0:8f28f25e3435 | 721 | |
| aidan1971 | 0:8f28f25e3435 | 722 | |
| aidan1971 | 0:8f28f25e3435 | 723 | #define SGTL5000_DAP_BASS_ENHANCE_CTRL 0x0106 |
| aidan1971 | 0:8f28f25e3435 | 724 | //13:8 |
| aidan1971 | 0:8f28f25e3435 | 725 | #define SGTL5000_DAP_BASS_ENHANCE_CTRL_LR_LEVEL_MASK 0x3F00 //Left/Right Mix Level Control |
| aidan1971 | 0:8f28f25e3435 | 726 | #define SGTL5000_DAP_BASS_ENHANCE_CTRL_LR_LEVEL_SHIFT 0x8 |
| aidan1971 | 0:8f28f25e3435 | 727 | // 0x00= +6.0 dB for Main Channel |
| aidan1971 | 0:8f28f25e3435 | 728 | // ...... |
| aidan1971 | 0:8f28f25e3435 | 729 | // 0x3F= Least L/R Channel Level |
| aidan1971 | 0:8f28f25e3435 | 730 | //6:0 |
| aidan1971 | 0:8f28f25e3435 | 731 | #define SGTL5000_DAP_BASS_ENHANCE_BASS_LEVEL_MASK 0x7F //Bass Harmonic Level Control |
| aidan1971 | 0:8f28f25e3435 | 732 | #define SGTL5000_DAP_BASS_ENHANCE_BASS_LEVEL_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 733 | // 0x00= Most Harmonic Boost |
| aidan1971 | 0:8f28f25e3435 | 734 | // ...... |
| aidan1971 | 0:8f28f25e3435 | 735 | // 0x7F=Least Harmonic Boost |
| aidan1971 | 0:8f28f25e3435 | 736 | |
| aidan1971 | 0:8f28f25e3435 | 737 | |
| aidan1971 | 0:8f28f25e3435 | 738 | #define SGTL5000_DAP_AUDIO_EQ 0x0108 |
| aidan1971 | 0:8f28f25e3435 | 739 | //1:0 |
| aidan1971 | 0:8f28f25e3435 | 740 | #define SGTL5000_DAP_AUDIO_EQ_EN_MASK 0x3 //Selects between PEQ/GEQ/Tone Control and Enables it. |
| aidan1971 | 0:8f28f25e3435 | 741 | #define SGTL5000_DAP_AUDIO_EQ_EN_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 742 | // 0x0 = Disabled. |
| aidan1971 | 0:8f28f25e3435 | 743 | // 0x1 = Enable PEQ. NOTE: DAP_PEQ->EN bit must also be set to the desired number |
| aidan1971 | 0:8f28f25e3435 | 744 | // of filters (bands) in order for the PEQ to be enabled. |
| aidan1971 | 0:8f28f25e3435 | 745 | // 0x2 = Enable Tone Control |
| aidan1971 | 0:8f28f25e3435 | 746 | // 0x3 = Enable 5 Band GEQ |
| aidan1971 | 0:8f28f25e3435 | 747 | |
| aidan1971 | 0:8f28f25e3435 | 748 | |
| aidan1971 | 0:8f28f25e3435 | 749 | #define SGTL5000_DAP_SGTL_SURROUND 0x010A |
| aidan1971 | 0:8f28f25e3435 | 750 | //6:4 |
| aidan1971 | 0:8f28f25e3435 | 751 | #define SGTL5000_DAP_SGTL_SURROUND_WIDTH_CONTROL_MASK 0x70 //Freescale Surround Width Control - |
| aidan1971 | 0:8f28f25e3435 | 752 | #define SGTL5000_DAP_SGTL_SURROUND_WIDTH_CONTROL_SHIFT 0x4 |
| aidan1971 | 0:8f28f25e3435 | 753 | // The width control changes the perceived width of |
| aidan1971 | 0:8f28f25e3435 | 754 | // the sound field. |
| aidan1971 | 0:8f28f25e3435 | 755 | // 0x0 = Least Width |
| aidan1971 | 0:8f28f25e3435 | 756 | // ...... |
| aidan1971 | 0:8f28f25e3435 | 757 | // 0x7 = Most Width |
| aidan1971 | 0:8f28f25e3435 | 758 | //1:0 |
| aidan1971 | 0:8f28f25e3435 | 759 | #define SGTL5000_DAP_SGTL_SURROUND_SELECT_MASK 0x3 //Freescale Surround Selection |
| aidan1971 | 0:8f28f25e3435 | 760 | #define SGTL5000_DAP_SGTL_SURROUND_SELECT_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 761 | // 0x0 = Disabled |
| aidan1971 | 0:8f28f25e3435 | 762 | // 0x1 = Disabled |
| aidan1971 | 0:8f28f25e3435 | 763 | // 0x2 = Mono input Enable |
| aidan1971 | 0:8f28f25e3435 | 764 | // 0x3 = Stereo input Enable |
| aidan1971 | 0:8f28f25e3435 | 765 | |
| aidan1971 | 0:8f28f25e3435 | 766 | #define SGTL5000_DAP_FILTER_COEF_ACCESS 0x010C |
| aidan1971 | 0:8f28f25e3435 | 767 | //8 |
| aidan1971 | 0:8f28f25e3435 | 768 | #define SGTL5000_DAP_FILTER_COEF_ACCESS_WR_MASK 0x100 // When set, the coefficients written in the ten coefficient data registers are loaded into |
| aidan1971 | 0:8f28f25e3435 | 769 | #define SGTL5000_DAP_FILTER_COEF_ACCESS_WR_SHIFT 0x8 |
| aidan1971 | 0:8f28f25e3435 | 770 | // the filter specified by INDEX |
| aidan1971 | 0:8f28f25e3435 | 771 | //7:0 |
| aidan1971 | 0:8f28f25e3435 | 772 | #define SGTL5000_DAP_FILTER_COEF_ACCESS_INDEX_MASK 0xFF // Specifies the index for each of the seven bands of the filter coefficient that needs to be |
| aidan1971 | 0:8f28f25e3435 | 773 | #define SGTL5000_DAP_FILTER_COEF_ACCESS_INDEX_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 774 | // written to. Each filter has 5 coefficients that need to be loaded into the 10 coefficient |
| aidan1971 | 0:8f28f25e3435 | 775 | // registers (MSB, LSB) before setting the index and WR bit. |
| aidan1971 | 0:8f28f25e3435 | 776 | // Steps to write coefficients: |
| aidan1971 | 0:8f28f25e3435 | 777 | // 1. Write the five 20-bit coefficient values to DAP_COEF_WR_XX_MSB and |
| aidan1971 | 0:8f28f25e3435 | 778 | // DAP_COEF_WR_XX_LSB registers (XX= B0,B1,B2,A1,A2) |
| aidan1971 | 0:8f28f25e3435 | 779 | // 2. Set INDEX of the coefficient from the table below. |
| aidan1971 | 0:8f28f25e3435 | 780 | // 3. Set the WR bit to load the coefficient. |
| aidan1971 | 0:8f28f25e3435 | 781 | // NOTE: Steps 2 and 3 can be performed with a single write to |
| aidan1971 | 0:8f28f25e3435 | 782 | // DAP_FILTER_COEF_ACCESS register. |
| aidan1971 | 0:8f28f25e3435 | 783 | // Coefficient address: |
| aidan1971 | 0:8f28f25e3435 | 784 | // Band 0 = 0x00 |
| aidan1971 | 0:8f28f25e3435 | 785 | // Band 1 = 0x01 |
| aidan1971 | 0:8f28f25e3435 | 786 | // Band 2 = 0x02 |
| aidan1971 | 0:8f28f25e3435 | 787 | // Band 3 = 0x03 |
| aidan1971 | 0:8f28f25e3435 | 788 | // Band 4 = 0x04 |
| aidan1971 | 0:8f28f25e3435 | 789 | // ... |
| aidan1971 | 0:8f28f25e3435 | 790 | // Band 7 = 0x06 |
| aidan1971 | 0:8f28f25e3435 | 791 | |
| aidan1971 | 0:8f28f25e3435 | 792 | #define SGTL5000_DAP_COEF_WR_B0_MSB 0x010E |
| aidan1971 | 0:8f28f25e3435 | 793 | //15:0 |
| aidan1971 | 0:8f28f25e3435 | 794 | #define SGTL5000_DAP_COEF_WR_B0_MSB_MS16BITS_MASK 0xFFFF // Most significant 16-bits of the 20-bit filter coefficient that needs to be written |
| aidan1971 | 0:8f28f25e3435 | 795 | #define SGTL5000_DAP_COEF_WR_B0_MSB_MS16BITS_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 796 | |
| aidan1971 | 0:8f28f25e3435 | 797 | #define SGTL5000_DAP_COEF_WR_B0_LSB 0x0110 |
| aidan1971 | 0:8f28f25e3435 | 798 | //3:0 |
| aidan1971 | 0:8f28f25e3435 | 799 | #define SGTL5000_DAP_COEF_WR_B0_LSB_LS4BITS_MASK 0xF // Least significant 4 bits of the 20-bit filter coefficient that needs to be written. |
| aidan1971 | 0:8f28f25e3435 | 800 | #define SGTL5000_DAP_COEF_WR_B0_LSB_LS4BITS_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 801 | |
| aidan1971 | 0:8f28f25e3435 | 802 | #define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0 0x0116 // 115 Hz |
| aidan1971 | 0:8f28f25e3435 | 803 | //6:0 |
| aidan1971 | 0:8f28f25e3435 | 804 | #define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0_VOLUME_MASK 0x7F // Sets Tone Control Bass/GEQ Band0 |
| aidan1971 | 0:8f28f25e3435 | 805 | #define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0_VOLUME_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 806 | // 0x5F = sets to 12 dB |
| aidan1971 | 0:8f28f25e3435 | 807 | // 0x2F = sets to 0 dB |
| aidan1971 | 0:8f28f25e3435 | 808 | // 0x00 = sets to -11.75 dB |
| aidan1971 | 0:8f28f25e3435 | 809 | // Each LSB is 0.25 dB |
| aidan1971 | 0:8f28f25e3435 | 810 | |
| aidan1971 | 0:8f28f25e3435 | 811 | #define SGTL5000_DAP_AUDIO_EQ_BAND1 0x0118 // 330 Hz |
| aidan1971 | 0:8f28f25e3435 | 812 | //6:0 |
| aidan1971 | 0:8f28f25e3435 | 813 | #define SGTL5000_DAP_AUDIO_EQ_BAND1_VOLUME_MASK 0x7F //Sets GEQ Band1 |
| aidan1971 | 0:8f28f25e3435 | 814 | #define SGTL5000_DAP_AUDIO_EQ_BAND1_VOLUME_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 815 | // 0x5F = sets to 12 dB |
| aidan1971 | 0:8f28f25e3435 | 816 | // 0x2F = sets to 0 dB |
| aidan1971 | 0:8f28f25e3435 | 817 | // 0x00 = sets to -11.75 dB |
| aidan1971 | 0:8f28f25e3435 | 818 | // Each LSB is 0.25 dB |
| aidan1971 | 0:8f28f25e3435 | 819 | |
| aidan1971 | 0:8f28f25e3435 | 820 | #define SGTL5000_DAP_AUDIO_EQ_BAND2 0x011A // 990 Hz |
| aidan1971 | 0:8f28f25e3435 | 821 | //6:0 |
| aidan1971 | 0:8f28f25e3435 | 822 | #define SGTL5000_DAP_AUDIO_EQ_BAND2_VOLUME_MASK 0x7F //Sets GEQ Band2 |
| aidan1971 | 0:8f28f25e3435 | 823 | #define SGTL5000_DAP_AUDIO_EQ_BAND2_VOLUME_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 824 | // 0x5F = sets to 12 dB |
| aidan1971 | 0:8f28f25e3435 | 825 | // 0x2F = sets to 0 dB |
| aidan1971 | 0:8f28f25e3435 | 826 | // 0x00 = sets to -11.75 dB |
| aidan1971 | 0:8f28f25e3435 | 827 | // Each LSB is 0.25 dB |
| aidan1971 | 0:8f28f25e3435 | 828 | |
| aidan1971 | 0:8f28f25e3435 | 829 | #define SGTL5000_DAP_AUDIO_EQ_BAND3 0x011C // 3000 Hz |
| aidan1971 | 0:8f28f25e3435 | 830 | //6:0 |
| aidan1971 | 0:8f28f25e3435 | 831 | #define SGTL5000_DAP_AUDIO_EQ_BAND3_VOLUME_MASK 0x7F //Sets GEQ Band3 |
| aidan1971 | 0:8f28f25e3435 | 832 | #define SGTL5000_DAP_AUDIO_EQ_BAND3_VOLUME_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 833 | // 0x5F = sets to 12 dB |
| aidan1971 | 0:8f28f25e3435 | 834 | // 0x2F = sets to 0 dB |
| aidan1971 | 0:8f28f25e3435 | 835 | // 0x00 = sets to -11.75 dB |
| aidan1971 | 0:8f28f25e3435 | 836 | // Each LSB is 0.25 dB |
| aidan1971 | 0:8f28f25e3435 | 837 | |
| aidan1971 | 0:8f28f25e3435 | 838 | #define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4 0x011E // 9900 Hz |
| aidan1971 | 0:8f28f25e3435 | 839 | //6:0 |
| aidan1971 | 0:8f28f25e3435 | 840 | #define SGTL5000_DAP_AUDIO_EQ_BAND4_VOLUME_MASK 0x7F //Sets GEQ Band4 |
| aidan1971 | 0:8f28f25e3435 | 841 | #define SGTL5000_DAP_AUDIO_EQ_BAND4_VOLUME_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 842 | // 0x5F = sets to 12 dB |
| aidan1971 | 0:8f28f25e3435 | 843 | // 0x2F = sets to 0 dB |
| aidan1971 | 0:8f28f25e3435 | 844 | // 0x00 = sets to -11.75 dB |
| aidan1971 | 0:8f28f25e3435 | 845 | // Each LSB is 0.25 dB |
| aidan1971 | 0:8f28f25e3435 | 846 | |
| aidan1971 | 0:8f28f25e3435 | 847 | #define SGTL5000_DAP_MAIN_CHAN 0x0120 |
| aidan1971 | 0:8f28f25e3435 | 848 | //15:0 |
| aidan1971 | 0:8f28f25e3435 | 849 | #define SGTL5000_DAP_MAIN_CHAN_VOL_MASK 0xFFFF // DAP Main Channel Volume |
| aidan1971 | 0:8f28f25e3435 | 850 | #define SGTL5000_DAP_MAIN_CHAN_VOL_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 851 | // 0xFFFF = 200% |
| aidan1971 | 0:8f28f25e3435 | 852 | // 0x8000 (default) = 100% |
| aidan1971 | 0:8f28f25e3435 | 853 | // 0x0000 = 0% |
| aidan1971 | 0:8f28f25e3435 | 854 | |
| aidan1971 | 0:8f28f25e3435 | 855 | #define SGTL5000_DAP_MIX_CHAN 0x0122 |
| aidan1971 | 0:8f28f25e3435 | 856 | //15:0 |
| aidan1971 | 0:8f28f25e3435 | 857 | #define SGTL5000_DAP_MIX_CHAN_VOL_MASK 0xFFFF // DAP Mix Channel Volume |
| aidan1971 | 0:8f28f25e3435 | 858 | #define SGTL5000_DAP_MIX_CHAN_VOL_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 859 | // 0xFFFF = 200% |
| aidan1971 | 0:8f28f25e3435 | 860 | // 0x8000 (default) = 100% |
| aidan1971 | 0:8f28f25e3435 | 861 | // 0x0000 = 0% |
| aidan1971 | 0:8f28f25e3435 | 862 | |
| aidan1971 | 0:8f28f25e3435 | 863 | #define SGTL5000_DAP_AVC_CTRL 0x0124 |
| aidan1971 | 0:8f28f25e3435 | 864 | //13:12 |
| aidan1971 | 0:8f28f25e3435 | 865 | #define SGTL5000_DAP_AVC_CTRL_MAX_GAIN_MASK 0x3000 //Maximum gain that can be applied by the AVC in expander mode. |
| aidan1971 | 0:8f28f25e3435 | 866 | #define SGTL5000_DAP_AVC_CTRL_MAX_GAIN_SHIFT 0xC |
| aidan1971 | 0:8f28f25e3435 | 867 | // 0x0 = 0 dB gain |
| aidan1971 | 0:8f28f25e3435 | 868 | // 0x1 = 6.0 dB of gain |
| aidan1971 | 0:8f28f25e3435 | 869 | // 0x2 = 12 dB of gain |
| aidan1971 | 0:8f28f25e3435 | 870 | //9:8 |
| aidan1971 | 0:8f28f25e3435 | 871 | #define SGTL5000_DAP_AVC_CTRL_LBI_RESPONSE_MASK 0x300 // Integrator Response |
| aidan1971 | 0:8f28f25e3435 | 872 | #define SGTL5000_DAP_AVC_CTRL_LBI_RESPONSE_SHIFT 0x8 |
| aidan1971 | 0:8f28f25e3435 | 873 | // 0x0 = 0 mS LBI |
| aidan1971 | 0:8f28f25e3435 | 874 | // 0x1 = 25 mS LBI |
| aidan1971 | 0:8f28f25e3435 | 875 | // 0x2 = 50 mS LBI |
| aidan1971 | 0:8f28f25e3435 | 876 | // 0x3 = 100 mS LBI |
| aidan1971 | 0:8f28f25e3435 | 877 | //5 |
| aidan1971 | 0:8f28f25e3435 | 878 | #define SGTL5000_DAP_AVC_CTRL_HARD_LIMIT_EN_MASK 0x20 // Enable Hard Limiter Mode |
| aidan1971 | 0:8f28f25e3435 | 879 | #define SGTL5000_DAP_AVC_CTRL_HARD_LIMIT_EN_SHIFT 0x5 |
| aidan1971 | 0:8f28f25e3435 | 880 | // 0x0 = Hard limit disabled. AVC Compressor/Expander is enabled. |
| aidan1971 | 0:8f28f25e3435 | 881 | // 0x1 = Hard limit enabled. The signal is limited to the programmed threshold. (Signal |
| aidan1971 | 0:8f28f25e3435 | 882 | // saturates at the threshold) |
| aidan1971 | 0:8f28f25e3435 | 883 | //0 |
| aidan1971 | 0:8f28f25e3435 | 884 | #define SGTL5000_DAP_AVC_CTRL_EN_MASK 0x1 // Enable/disable AVC |
| aidan1971 | 0:8f28f25e3435 | 885 | #define SGTL5000_DAP_AVC_CTRL_EN_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 886 | // 0x0 = Disable |
| aidan1971 | 0:8f28f25e3435 | 887 | // 0x1 = Enable |
| aidan1971 | 0:8f28f25e3435 | 888 | |
| aidan1971 | 0:8f28f25e3435 | 889 | #define SGTL5000_DAP_AVC_THRESHOLD 0x0126 |
| aidan1971 | 0:8f28f25e3435 | 890 | //15:0 |
| aidan1971 | 0:8f28f25e3435 | 891 | #define SGTL5000_DAP_AVC_THRESHOLD_THRESH_MASK 0xFFFF // AVC Threshold Value |
| aidan1971 | 0:8f28f25e3435 | 892 | #define SGTL5000_DAP_AVC_THRESHOLD_THRESH_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 893 | // Threshold is programmable. Use the following formula to calculate hex value: |
| aidan1971 | 0:8f28f25e3435 | 894 | // Hex Value = ((10^(THRESHOLD_dB/20))*0.636)*2^15 |
| aidan1971 | 0:8f28f25e3435 | 895 | // Threshold can be set in the range of 0 dB to -96 dB |
| aidan1971 | 0:8f28f25e3435 | 896 | // Example Values: |
| aidan1971 | 0:8f28f25e3435 | 897 | // 0x1473 = Set Threshold to -12 dB |
| aidan1971 | 0:8f28f25e3435 | 898 | // 0x0A40 = Set Threshold to -18 dB |
| aidan1971 | 0:8f28f25e3435 | 899 | |
| aidan1971 | 0:8f28f25e3435 | 900 | #define SGTL5000_DAP_AVC_ATTACK 0x0128 |
| aidan1971 | 0:8f28f25e3435 | 901 | //11:0 |
| aidan1971 | 0:8f28f25e3435 | 902 | #define SGTL5000_DAP_AVC_ATTACK_RATE_MASK 0xFFF //AVC Attack Rate |
| aidan1971 | 0:8f28f25e3435 | 903 | #define SGTL5000_DAP_AVC_ATTACK_RATE_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 904 | // This is the rate at which the AVC applies attenuation to the signal to bring it to the |
| aidan1971 | 0:8f28f25e3435 | 905 | // threshold level. AVC Attack Rate is programmable. To use a custom rate, use the |
| aidan1971 | 0:8f28f25e3435 | 906 | // formula below to convert from dB/S to hex value: |
| aidan1971 | 0:8f28f25e3435 | 907 | // Hex Value = (1 - (10^(-(Rate_dBs/(20*SYS_FS)))) * 2^19 |
| aidan1971 | 0:8f28f25e3435 | 908 | // where, SYS_FS is the system sample rate configured in CHIP_CLK_CTRL register. |
| aidan1971 | 0:8f28f25e3435 | 909 | // Example values: |
| aidan1971 | 0:8f28f25e3435 | 910 | // 0x28 = 32 dB/s |
| aidan1971 | 0:8f28f25e3435 | 911 | // 0x10 = 8.0 dB/s |
| aidan1971 | 0:8f28f25e3435 | 912 | // 0x05 = 4.0 dB/s |
| aidan1971 | 0:8f28f25e3435 | 913 | // 0x03 = 2.0 dB/s |
| aidan1971 | 0:8f28f25e3435 | 914 | |
| aidan1971 | 0:8f28f25e3435 | 915 | #define SGTL5000_DAP_AVC_DECAY 0x012A |
| aidan1971 | 0:8f28f25e3435 | 916 | //11:0 |
| aidan1971 | 0:8f28f25e3435 | 917 | #define SGTL5000_DAP_AVC_DECAY_RATE_MASK 0xFFF //AVC Decay Rate |
| aidan1971 | 0:8f28f25e3435 | 918 | #define SGTL5000_DAP_AVC_ATTACK_RATE_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 919 | // This is the rate at which the AVC releases the attenuation previously applied to the |
| aidan1971 | 0:8f28f25e3435 | 920 | // signal during attack. AVC Decay Rate is programmable. To use a custom rate, use the |
| aidan1971 | 0:8f28f25e3435 | 921 | // formula below to convert from dB/S to hex value: |
| aidan1971 | 0:8f28f25e3435 | 922 | // Hex Value = (1 - (10^(-(Rate_dBs/(20*SYS_FS)))) * 2^23 |
| aidan1971 | 0:8f28f25e3435 | 923 | // where, SYS_FS is the system sample rate configured in CHIP_CLK_CTRL register. |
| aidan1971 | 0:8f28f25e3435 | 924 | // Example values: |
| aidan1971 | 0:8f28f25e3435 | 925 | // 0x284 = 32 dB/s |
| aidan1971 | 0:8f28f25e3435 | 926 | // 0xA0 = 8.0 dB/s |
| aidan1971 | 0:8f28f25e3435 | 927 | // 0x50 = 4.0 dB/s |
| aidan1971 | 0:8f28f25e3435 | 928 | // 0x28 = 2.0 dB/s |
| aidan1971 | 0:8f28f25e3435 | 929 | |
| aidan1971 | 0:8f28f25e3435 | 930 | #define SGTL5000_DAP_COEF_WR_B1_MSB 0x012C |
| aidan1971 | 0:8f28f25e3435 | 931 | //15:0 |
| aidan1971 | 0:8f28f25e3435 | 932 | #define SGTL5000_DAP_COEF_WR_B1_MSB_MSB_MASK 0xFFFF // Most significant 16-bits of the 20-bit filter coefficient that needs to be written |
| aidan1971 | 0:8f28f25e3435 | 933 | #define SGTL5000_DAP_COEF_WR_B1_MSB_MSB_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 934 | |
| aidan1971 | 0:8f28f25e3435 | 935 | #define SGTL5000_DAP_COEF_WR_B1_LSB 0x012E |
| aidan1971 | 0:8f28f25e3435 | 936 | //3:0 |
| aidan1971 | 0:8f28f25e3435 | 937 | #define SGTL5000_DAP_COEF_WR_B1_LSB_LSB_MASK 0xF // Least significant 4 bits of the 20-bit filter coefficient that needs to be written. |
| aidan1971 | 0:8f28f25e3435 | 938 | #define SGTL5000_DAP_COEF_WR_B1_LSB_LSB_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 939 | |
| aidan1971 | 0:8f28f25e3435 | 940 | #define SGTL5000_DAP_COEF_WR_B2_MSB 0x0130 |
| aidan1971 | 0:8f28f25e3435 | 941 | //15:0 |
| aidan1971 | 0:8f28f25e3435 | 942 | #define SGTL5000_DAP_COEF_WR_B2_MSB_MSB_MASK 0xFFFF // Most significant 16-bits of the 20-bit filter coefficient that needs to be written |
| aidan1971 | 0:8f28f25e3435 | 943 | #define SGTL5000_DAP_COEF_WR_B2_MSB_MSB_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 944 | |
| aidan1971 | 0:8f28f25e3435 | 945 | #define SGTL5000_DAP_COEF_WR_B2_LSB 0x0132 |
| aidan1971 | 0:8f28f25e3435 | 946 | //3:0 |
| aidan1971 | 0:8f28f25e3435 | 947 | #define SGTL5000_DAP_COEF_WR_B2_LSB_LSB_MASK 0xF // Least significant 4 bits of the 20-bit filter coefficient that needs to be written. |
| aidan1971 | 0:8f28f25e3435 | 948 | #define SGTL5000_DAP_COEF_WR_B2_LSB_LSB_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 949 | |
| aidan1971 | 0:8f28f25e3435 | 950 | #define SGTL5000_DAP_COEF_WR_A1_MSB 0x0134 |
| aidan1971 | 0:8f28f25e3435 | 951 | //15:0 |
| aidan1971 | 0:8f28f25e3435 | 952 | #define SGTL5000_DAP_COEF_WR_A1_MSB_MSB_MASK 0xFFFF // Most significant 16-bits of the 20-bit filter coefficient that needs to be written |
| aidan1971 | 0:8f28f25e3435 | 953 | #define SGTL5000_DAP_COEF_WR_A1_MSB_MSB_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 954 | |
| aidan1971 | 0:8f28f25e3435 | 955 | #define SGTL5000_DAP_COEF_WR_A1_LSB 0x0136 |
| aidan1971 | 0:8f28f25e3435 | 956 | //3:0 |
| aidan1971 | 0:8f28f25e3435 | 957 | #define SGTL5000_DAP_COEF_WR_A1_LSB_LSB_MASK 0xF // Least significant 4 bits of the 20-bit filter coefficient that needs to be written. |
| aidan1971 | 0:8f28f25e3435 | 958 | #define SGTL5000_DAP_COEF_WR_A1_LSB_LSB_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 959 | |
| aidan1971 | 0:8f28f25e3435 | 960 | #define SGTL5000_DAP_COEF_WR_A2_MSB 0x0138 |
| aidan1971 | 0:8f28f25e3435 | 961 | //15:0 |
| aidan1971 | 0:8f28f25e3435 | 962 | #define SGTL5000_DAP_COEF_WR_A2_MSB_MSB_MASK 0xFFFF // Most significant 16-bits of the 20-bit filter coefficient that needs to be written |
| aidan1971 | 0:8f28f25e3435 | 963 | #define SGTL5000_DAP_COEF_WR_A2_MSB_MSB_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 964 | |
| aidan1971 | 0:8f28f25e3435 | 965 | #define SGTL5000_DAP_COEF_WR_A2_LSB 0x013A |
| aidan1971 | 0:8f28f25e3435 | 966 | //3:0 |
| aidan1971 | 0:8f28f25e3435 | 967 | #define SGTL5000_DAP_COEF_WR_A2_LSB_LSB_MASK 0xF // Least significant 4 bits of the 20-bit filter coefficient that needs to be written. |
| aidan1971 | 0:8f28f25e3435 | 968 | #define SGTL5000_DAP_COEF_WR_A2_LSB_LSB_SHIFT 0x0 |
| aidan1971 | 0:8f28f25e3435 | 969 | |
| aidan1971 | 0:8f28f25e3435 | 970 | |
| aidan1971 | 0:8f28f25e3435 | 971 | |
| aidan1971 | 0:8f28f25e3435 | 972 | |
| aidan1971 | 0:8f28f25e3435 | 973 | #endif |