Aidan Walton / Mbed 2 deprecated ClockControl

Updated functions to deal with USB clocking. (PPL1) See http://www.nxp.com/documents/user_manual/UM10360.pdf Section 4.6 & 4.7.3

Dependencies:   mbed

Fork of ClockControl by Michael Wei

LPC1768.h@2:ab85c20317b5, 2016-09-12 (annotated)

Committer:
aidan1971
Date:
Mon Sep 12 13:11:32 2016 +0000
Revision:
2:ab85c20317b5
Parent:
1:8b04bd33c7cd 
Added comments and command to change TIMER3 prescaler

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aidan1971 1:8b04bd33c7cd 1 /**************************************************************************//**
aidan1971 1:8b04bd33c7cd 2 * @file LPC17xx.h
aidan1971 1:8b04bd33c7cd 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
aidan1971 1:8b04bd33c7cd 4 * NXP LPC17xx Device Series
aidan1971 1:8b04bd33c7cd 5 * @version: V1.09
aidan1971 1:8b04bd33c7cd 6 * @date: 17. March 2010
aidan1971 1:8b04bd33c7cd 7
aidan1971 1:8b04bd33c7cd 8 *
aidan1971 1:8b04bd33c7cd 9 * @note
aidan1971 1:8b04bd33c7cd 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
aidan1971 1:8b04bd33c7cd 11 *
aidan1971 1:8b04bd33c7cd 12 * @par
aidan1971 1:8b04bd33c7cd 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
aidan1971 1:8b04bd33c7cd 14 * processor based microcontrollers. This file can be freely distributed
aidan1971 1:8b04bd33c7cd 15 * within development tools that are supporting such ARM based processors.
aidan1971 1:8b04bd33c7cd 16 *
aidan1971 1:8b04bd33c7cd 17 * @par
aidan1971 1:8b04bd33c7cd 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
aidan1971 1:8b04bd33c7cd 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
aidan1971 1:8b04bd33c7cd 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
aidan1971 1:8b04bd33c7cd 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
aidan1971 1:8b04bd33c7cd 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
aidan1971 1:8b04bd33c7cd 23 *
aidan1971 1:8b04bd33c7cd 24 ******************************************************************************/
aidan1971 1:8b04bd33c7cd 25
aidan1971 1:8b04bd33c7cd 26
aidan1971 1:8b04bd33c7cd 27 #ifndef __LPC17xx_H__
aidan1971 1:8b04bd33c7cd 28 #define __LPC17xx_H__
aidan1971 1:8b04bd33c7cd 29
aidan1971 1:8b04bd33c7cd 30 /*
aidan1971 1:8b04bd33c7cd 31 * ==========================================================================
aidan1971 1:8b04bd33c7cd 32 * ---------- Interrupt Number Definition -----------------------------------
aidan1971 1:8b04bd33c7cd 33 * ==========================================================================
aidan1971 1:8b04bd33c7cd 34 */
aidan1971 1:8b04bd33c7cd 35
aidan1971 1:8b04bd33c7cd 36 typedef enum IRQn
aidan1971 1:8b04bd33c7cd 37 {
aidan1971 1:8b04bd33c7cd 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
aidan1971 1:8b04bd33c7cd 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
aidan1971 1:8b04bd33c7cd 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
aidan1971 1:8b04bd33c7cd 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
aidan1971 1:8b04bd33c7cd 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
aidan1971 1:8b04bd33c7cd 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
aidan1971 1:8b04bd33c7cd 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
aidan1971 1:8b04bd33c7cd 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
aidan1971 1:8b04bd33c7cd 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
aidan1971 1:8b04bd33c7cd 47
aidan1971 1:8b04bd33c7cd 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
aidan1971 1:8b04bd33c7cd 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
aidan1971 1:8b04bd33c7cd 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
aidan1971 1:8b04bd33c7cd 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
aidan1971 1:8b04bd33c7cd 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
aidan1971 1:8b04bd33c7cd 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
aidan1971 1:8b04bd33c7cd 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
aidan1971 1:8b04bd33c7cd 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
aidan1971 1:8b04bd33c7cd 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
aidan1971 1:8b04bd33c7cd 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
aidan1971 1:8b04bd33c7cd 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
aidan1971 1:8b04bd33c7cd 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
aidan1971 1:8b04bd33c7cd 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
aidan1971 1:8b04bd33c7cd 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
aidan1971 1:8b04bd33c7cd 62 SPI_IRQn = 13, /*!< SPI Interrupt */
aidan1971 1:8b04bd33c7cd 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
aidan1971 1:8b04bd33c7cd 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
aidan1971 1:8b04bd33c7cd 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
aidan1971 1:8b04bd33c7cd 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
aidan1971 1:8b04bd33c7cd 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
aidan1971 1:8b04bd33c7cd 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
aidan1971 1:8b04bd33c7cd 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
aidan1971 1:8b04bd33c7cd 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
aidan1971 1:8b04bd33c7cd 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
aidan1971 1:8b04bd33c7cd 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
aidan1971 1:8b04bd33c7cd 73 USB_IRQn = 24, /*!< USB Interrupt */
aidan1971 1:8b04bd33c7cd 74 CAN_IRQn = 25, /*!< CAN Interrupt */
aidan1971 1:8b04bd33c7cd 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
aidan1971 1:8b04bd33c7cd 76 I2S_IRQn = 27, /*!< I2S Interrupt */
aidan1971 1:8b04bd33c7cd 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
aidan1971 1:8b04bd33c7cd 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
aidan1971 1:8b04bd33c7cd 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
aidan1971 1:8b04bd33c7cd 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
aidan1971 1:8b04bd33c7cd 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
aidan1971 1:8b04bd33c7cd 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
aidan1971 1:8b04bd33c7cd 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
aidan1971 1:8b04bd33c7cd 84 } IRQn_Type;
aidan1971 1:8b04bd33c7cd 85
aidan1971 1:8b04bd33c7cd 86
aidan1971 1:8b04bd33c7cd 87 /*
aidan1971 1:8b04bd33c7cd 88 * ==========================================================================
aidan1971 1:8b04bd33c7cd 89 * ----------- Processor and Core Peripheral Section ------------------------
aidan1971 1:8b04bd33c7cd 90 * ==========================================================================
aidan1971 1:8b04bd33c7cd 91 */
aidan1971 1:8b04bd33c7cd 92
aidan1971 1:8b04bd33c7cd 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
aidan1971 1:8b04bd33c7cd 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
aidan1971 1:8b04bd33c7cd 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
aidan1971 1:8b04bd33c7cd 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
aidan1971 1:8b04bd33c7cd 97
aidan1971 1:8b04bd33c7cd 98
aidan1971 1:8b04bd33c7cd 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
aidan1971 1:8b04bd33c7cd 100 #include "system_LPC17xx.h" /* System Header */
aidan1971 1:8b04bd33c7cd 101
aidan1971 1:8b04bd33c7cd 102
aidan1971 1:8b04bd33c7cd 103 /******************************************************************************/
aidan1971 1:8b04bd33c7cd 104 /* Device Specific Peripheral registers structures */
aidan1971 1:8b04bd33c7cd 105 /******************************************************************************/
aidan1971 1:8b04bd33c7cd 106
aidan1971 1:8b04bd33c7cd 107 #if defined ( __CC_ARM )
aidan1971 1:8b04bd33c7cd 108 #pragma anon_unions
aidan1971 1:8b04bd33c7cd 109 #endif
aidan1971 1:8b04bd33c7cd 110
aidan1971 1:8b04bd33c7cd 111 /*------------- System Control (SC) ------------------------------------------*/
aidan1971 1:8b04bd33c7cd 112 typedef struct
aidan1971 1:8b04bd33c7cd 113 {
aidan1971 1:8b04bd33c7cd 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
aidan1971 1:8b04bd33c7cd 115 uint32_t RESERVED0[31];
aidan1971 1:8b04bd33c7cd 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
aidan1971 1:8b04bd33c7cd 117 __IO uint32_t PLL0CFG;
aidan1971 1:8b04bd33c7cd 118 __I uint32_t PLL0STAT;
aidan1971 1:8b04bd33c7cd 119 __O uint32_t PLL0FEED;
aidan1971 1:8b04bd33c7cd 120 uint32_t RESERVED1[4];
aidan1971 1:8b04bd33c7cd 121 __IO uint32_t PLL1CON;
aidan1971 1:8b04bd33c7cd 122 __IO uint32_t PLL1CFG;
aidan1971 1:8b04bd33c7cd 123 __I uint32_t PLL1STAT;
aidan1971 1:8b04bd33c7cd 124 __O uint32_t PLL1FEED;
aidan1971 1:8b04bd33c7cd 125 uint32_t RESERVED2[4];
aidan1971 1:8b04bd33c7cd 126 __IO uint32_t PCON;
aidan1971 1:8b04bd33c7cd 127 __IO uint32_t PCONP;
aidan1971 1:8b04bd33c7cd 128 uint32_t RESERVED3[15];
aidan1971 1:8b04bd33c7cd 129 __IO uint32_t CCLKCFG;
aidan1971 1:8b04bd33c7cd 130 __IO uint32_t USBCLKCFG;
aidan1971 1:8b04bd33c7cd 131 __IO uint32_t CLKSRCSEL;
aidan1971 1:8b04bd33c7cd 132 __IO uint32_t CANSLEEPCLR;
aidan1971 1:8b04bd33c7cd 133 __IO uint32_t CANWAKEFLAGS;
aidan1971 1:8b04bd33c7cd 134 uint32_t RESERVED4[10];
aidan1971 1:8b04bd33c7cd 135 __IO uint32_t EXTINT; /* External Interrupts */
aidan1971 1:8b04bd33c7cd 136 uint32_t RESERVED5;
aidan1971 1:8b04bd33c7cd 137 __IO uint32_t EXTMODE;
aidan1971 1:8b04bd33c7cd 138 __IO uint32_t EXTPOLAR;
aidan1971 1:8b04bd33c7cd 139 uint32_t RESERVED6[12];
aidan1971 1:8b04bd33c7cd 140 __IO uint32_t RSID; /* Reset */
aidan1971 1:8b04bd33c7cd 141 uint32_t RESERVED7[7];
aidan1971 1:8b04bd33c7cd 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
aidan1971 1:8b04bd33c7cd 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
aidan1971 1:8b04bd33c7cd 144 __IO uint32_t PCLKSEL0;
aidan1971 1:8b04bd33c7cd 145 __IO uint32_t PCLKSEL1;
aidan1971 1:8b04bd33c7cd 146 uint32_t RESERVED8[4];
aidan1971 1:8b04bd33c7cd 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
aidan1971 1:8b04bd33c7cd 148 __IO uint32_t DMAREQSEL;
aidan1971 1:8b04bd33c7cd 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
aidan1971 1:8b04bd33c7cd 150 } LPC_SC_TypeDef;
aidan1971 1:8b04bd33c7cd 151
aidan1971 1:8b04bd33c7cd 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
aidan1971 1:8b04bd33c7cd 153 typedef struct
aidan1971 1:8b04bd33c7cd 154 {
aidan1971 1:8b04bd33c7cd 155 __IO uint32_t PINSEL0;
aidan1971 1:8b04bd33c7cd 156 __IO uint32_t PINSEL1;
aidan1971 1:8b04bd33c7cd 157 __IO uint32_t PINSEL2;
aidan1971 1:8b04bd33c7cd 158 __IO uint32_t PINSEL3;
aidan1971 1:8b04bd33c7cd 159 __IO uint32_t PINSEL4;
aidan1971 1:8b04bd33c7cd 160 __IO uint32_t PINSEL5;
aidan1971 1:8b04bd33c7cd 161 __IO uint32_t PINSEL6;
aidan1971 1:8b04bd33c7cd 162 __IO uint32_t PINSEL7;
aidan1971 1:8b04bd33c7cd 163 __IO uint32_t PINSEL8;
aidan1971 1:8b04bd33c7cd 164 __IO uint32_t PINSEL9;
aidan1971 1:8b04bd33c7cd 165 __IO uint32_t PINSEL10;
aidan1971 1:8b04bd33c7cd 166 uint32_t RESERVED0[5];
aidan1971 1:8b04bd33c7cd 167 __IO uint32_t PINMODE0;
aidan1971 1:8b04bd33c7cd 168 __IO uint32_t PINMODE1;
aidan1971 1:8b04bd33c7cd 169 __IO uint32_t PINMODE2;
aidan1971 1:8b04bd33c7cd 170 __IO uint32_t PINMODE3;
aidan1971 1:8b04bd33c7cd 171 __IO uint32_t PINMODE4;
aidan1971 1:8b04bd33c7cd 172 __IO uint32_t PINMODE5;
aidan1971 1:8b04bd33c7cd 173 __IO uint32_t PINMODE6;
aidan1971 1:8b04bd33c7cd 174 __IO uint32_t PINMODE7;
aidan1971 1:8b04bd33c7cd 175 __IO uint32_t PINMODE8;
aidan1971 1:8b04bd33c7cd 176 __IO uint32_t PINMODE9;
aidan1971 1:8b04bd33c7cd 177 __IO uint32_t PINMODE_OD0;
aidan1971 1:8b04bd33c7cd 178 __IO uint32_t PINMODE_OD1;
aidan1971 1:8b04bd33c7cd 179 __IO uint32_t PINMODE_OD2;
aidan1971 1:8b04bd33c7cd 180 __IO uint32_t PINMODE_OD3;
aidan1971 1:8b04bd33c7cd 181 __IO uint32_t PINMODE_OD4;
aidan1971 1:8b04bd33c7cd 182 __IO uint32_t I2CPADCFG;
aidan1971 1:8b04bd33c7cd 183 } LPC_PINCON_TypeDef;
aidan1971 1:8b04bd33c7cd 184
aidan1971 1:8b04bd33c7cd 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
aidan1971 1:8b04bd33c7cd 186 typedef struct
aidan1971 1:8b04bd33c7cd 187 {
aidan1971 1:8b04bd33c7cd 188 union {
aidan1971 1:8b04bd33c7cd 189 __IO uint32_t FIODIR;
aidan1971 1:8b04bd33c7cd 190 struct {
aidan1971 1:8b04bd33c7cd 191 __IO uint16_t FIODIRL;
aidan1971 1:8b04bd33c7cd 192 __IO uint16_t FIODIRH;
aidan1971 1:8b04bd33c7cd 193 };
aidan1971 1:8b04bd33c7cd 194 struct {
aidan1971 1:8b04bd33c7cd 195 __IO uint8_t FIODIR0;
aidan1971 1:8b04bd33c7cd 196 __IO uint8_t FIODIR1;
aidan1971 1:8b04bd33c7cd 197 __IO uint8_t FIODIR2;
aidan1971 1:8b04bd33c7cd 198 __IO uint8_t FIODIR3;
aidan1971 1:8b04bd33c7cd 199 };
aidan1971 1:8b04bd33c7cd 200 };
aidan1971 1:8b04bd33c7cd 201 uint32_t RESERVED0[3];
aidan1971 1:8b04bd33c7cd 202 union {
aidan1971 1:8b04bd33c7cd 203 __IO uint32_t FIOMASK;
aidan1971 1:8b04bd33c7cd 204 struct {
aidan1971 1:8b04bd33c7cd 205 __IO uint16_t FIOMASKL;
aidan1971 1:8b04bd33c7cd 206 __IO uint16_t FIOMASKH;
aidan1971 1:8b04bd33c7cd 207 };
aidan1971 1:8b04bd33c7cd 208 struct {
aidan1971 1:8b04bd33c7cd 209 __IO uint8_t FIOMASK0;
aidan1971 1:8b04bd33c7cd 210 __IO uint8_t FIOMASK1;
aidan1971 1:8b04bd33c7cd 211 __IO uint8_t FIOMASK2;
aidan1971 1:8b04bd33c7cd 212 __IO uint8_t FIOMASK3;
aidan1971 1:8b04bd33c7cd 213 };
aidan1971 1:8b04bd33c7cd 214 };
aidan1971 1:8b04bd33c7cd 215 union {
aidan1971 1:8b04bd33c7cd 216 __IO uint32_t FIOPIN;
aidan1971 1:8b04bd33c7cd 217 struct {
aidan1971 1:8b04bd33c7cd 218 __IO uint16_t FIOPINL;
aidan1971 1:8b04bd33c7cd 219 __IO uint16_t FIOPINH;
aidan1971 1:8b04bd33c7cd 220 };
aidan1971 1:8b04bd33c7cd 221 struct {
aidan1971 1:8b04bd33c7cd 222 __IO uint8_t FIOPIN0;
aidan1971 1:8b04bd33c7cd 223 __IO uint8_t FIOPIN1;
aidan1971 1:8b04bd33c7cd 224 __IO uint8_t FIOPIN2;
aidan1971 1:8b04bd33c7cd 225 __IO uint8_t FIOPIN3;
aidan1971 1:8b04bd33c7cd 226 };
aidan1971 1:8b04bd33c7cd 227 };
aidan1971 1:8b04bd33c7cd 228 union {
aidan1971 1:8b04bd33c7cd 229 __IO uint32_t FIOSET;
aidan1971 1:8b04bd33c7cd 230 struct {
aidan1971 1:8b04bd33c7cd 231 __IO uint16_t FIOSETL;
aidan1971 1:8b04bd33c7cd 232 __IO uint16_t FIOSETH;
aidan1971 1:8b04bd33c7cd 233 };
aidan1971 1:8b04bd33c7cd 234 struct {
aidan1971 1:8b04bd33c7cd 235 __IO uint8_t FIOSET0;
aidan1971 1:8b04bd33c7cd 236 __IO uint8_t FIOSET1;
aidan1971 1:8b04bd33c7cd 237 __IO uint8_t FIOSET2;
aidan1971 1:8b04bd33c7cd 238 __IO uint8_t FIOSET3;
aidan1971 1:8b04bd33c7cd 239 };
aidan1971 1:8b04bd33c7cd 240 };
aidan1971 1:8b04bd33c7cd 241 union {
aidan1971 1:8b04bd33c7cd 242 __O uint32_t FIOCLR;
aidan1971 1:8b04bd33c7cd 243 struct {
aidan1971 1:8b04bd33c7cd 244 __O uint16_t FIOCLRL;
aidan1971 1:8b04bd33c7cd 245 __O uint16_t FIOCLRH;
aidan1971 1:8b04bd33c7cd 246 };
aidan1971 1:8b04bd33c7cd 247 struct {
aidan1971 1:8b04bd33c7cd 248 __O uint8_t FIOCLR0;
aidan1971 1:8b04bd33c7cd 249 __O uint8_t FIOCLR1;
aidan1971 1:8b04bd33c7cd 250 __O uint8_t FIOCLR2;
aidan1971 1:8b04bd33c7cd 251 __O uint8_t FIOCLR3;
aidan1971 1:8b04bd33c7cd 252 };
aidan1971 1:8b04bd33c7cd 253 };
aidan1971 1:8b04bd33c7cd 254 } LPC_GPIO_TypeDef;
aidan1971 1:8b04bd33c7cd 255
aidan1971 1:8b04bd33c7cd 256 typedef struct
aidan1971 1:8b04bd33c7cd 257 {
aidan1971 1:8b04bd33c7cd 258 __I uint32_t IntStatus;
aidan1971 1:8b04bd33c7cd 259 __I uint32_t IO0IntStatR;
aidan1971 1:8b04bd33c7cd 260 __I uint32_t IO0IntStatF;
aidan1971 1:8b04bd33c7cd 261 __O uint32_t IO0IntClr;
aidan1971 1:8b04bd33c7cd 262 __IO uint32_t IO0IntEnR;
aidan1971 1:8b04bd33c7cd 263 __IO uint32_t IO0IntEnF;
aidan1971 1:8b04bd33c7cd 264 uint32_t RESERVED0[3];
aidan1971 1:8b04bd33c7cd 265 __I uint32_t IO2IntStatR;
aidan1971 1:8b04bd33c7cd 266 __I uint32_t IO2IntStatF;
aidan1971 1:8b04bd33c7cd 267 __O uint32_t IO2IntClr;
aidan1971 1:8b04bd33c7cd 268 __IO uint32_t IO2IntEnR;
aidan1971 1:8b04bd33c7cd 269 __IO uint32_t IO2IntEnF;
aidan1971 1:8b04bd33c7cd 270 } LPC_GPIOINT_TypeDef;
aidan1971 1:8b04bd33c7cd 271
aidan1971 1:8b04bd33c7cd 272 /*------------- Timer (TIM) --------------------------------------------------*/
aidan1971 1:8b04bd33c7cd 273 typedef struct
aidan1971 1:8b04bd33c7cd 274 {
aidan1971 1:8b04bd33c7cd 275 __IO uint32_t IR;
aidan1971 1:8b04bd33c7cd 276 __IO uint32_t TCR;
aidan1971 1:8b04bd33c7cd 277 __IO uint32_t TC;
aidan1971 1:8b04bd33c7cd 278 __IO uint32_t PR;
aidan1971 1:8b04bd33c7cd 279 __IO uint32_t PC;
aidan1971 1:8b04bd33c7cd 280 __IO uint32_t MCR;
aidan1971 1:8b04bd33c7cd 281 __IO uint32_t MR0;
aidan1971 1:8b04bd33c7cd 282 __IO uint32_t MR1;
aidan1971 1:8b04bd33c7cd 283 __IO uint32_t MR2;
aidan1971 1:8b04bd33c7cd 284 __IO uint32_t MR3;
aidan1971 1:8b04bd33c7cd 285 __IO uint32_t CCR;
aidan1971 1:8b04bd33c7cd 286 __I uint32_t CR0;
aidan1971 1:8b04bd33c7cd 287 __I uint32_t CR1;
aidan1971 1:8b04bd33c7cd 288 uint32_t RESERVED0[2];
aidan1971 1:8b04bd33c7cd 289 __IO uint32_t EMR;
aidan1971 1:8b04bd33c7cd 290 uint32_t RESERVED1[12];
aidan1971 1:8b04bd33c7cd 291 __IO uint32_t CTCR;
aidan1971 1:8b04bd33c7cd 292 } LPC_TIM_TypeDef;
aidan1971 1:8b04bd33c7cd 293
aidan1971 1:8b04bd33c7cd 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
aidan1971 1:8b04bd33c7cd 295 typedef struct
aidan1971 1:8b04bd33c7cd 296 {
aidan1971 1:8b04bd33c7cd 297 __IO uint32_t IR;
aidan1971 1:8b04bd33c7cd 298 __IO uint32_t TCR;
aidan1971 1:8b04bd33c7cd 299 __IO uint32_t TC;
aidan1971 1:8b04bd33c7cd 300 __IO uint32_t PR;
aidan1971 1:8b04bd33c7cd 301 __IO uint32_t PC;
aidan1971 1:8b04bd33c7cd 302 __IO uint32_t MCR;
aidan1971 1:8b04bd33c7cd 303 __IO uint32_t MR0;
aidan1971 1:8b04bd33c7cd 304 __IO uint32_t MR1;
aidan1971 1:8b04bd33c7cd 305 __IO uint32_t MR2;
aidan1971 1:8b04bd33c7cd 306 __IO uint32_t MR3;
aidan1971 1:8b04bd33c7cd 307 __IO uint32_t CCR;
aidan1971 1:8b04bd33c7cd 308 __I uint32_t CR0;
aidan1971 1:8b04bd33c7cd 309 __I uint32_t CR1;
aidan1971 1:8b04bd33c7cd 310 __I uint32_t CR2;
aidan1971 1:8b04bd33c7cd 311 __I uint32_t CR3;
aidan1971 1:8b04bd33c7cd 312 uint32_t RESERVED0;
aidan1971 1:8b04bd33c7cd 313 __IO uint32_t MR4;
aidan1971 1:8b04bd33c7cd 314 __IO uint32_t MR5;
aidan1971 1:8b04bd33c7cd 315 __IO uint32_t MR6;
aidan1971 1:8b04bd33c7cd 316 __IO uint32_t PCR;
aidan1971 1:8b04bd33c7cd 317 __IO uint32_t LER;
aidan1971 1:8b04bd33c7cd 318 uint32_t RESERVED1[7];
aidan1971 1:8b04bd33c7cd 319 __IO uint32_t CTCR;
aidan1971 1:8b04bd33c7cd 320 } LPC_PWM_TypeDef;
aidan1971 1:8b04bd33c7cd 321
aidan1971 1:8b04bd33c7cd 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
aidan1971 1:8b04bd33c7cd 323 typedef struct
aidan1971 1:8b04bd33c7cd 324 {
aidan1971 1:8b04bd33c7cd 325 union {
aidan1971 1:8b04bd33c7cd 326 __I uint8_t RBR;
aidan1971 1:8b04bd33c7cd 327 __O uint8_t THR;
aidan1971 1:8b04bd33c7cd 328 __IO uint8_t DLL;
aidan1971 1:8b04bd33c7cd 329 uint32_t RESERVED0;
aidan1971 1:8b04bd33c7cd 330 };
aidan1971 1:8b04bd33c7cd 331 union {
aidan1971 1:8b04bd33c7cd 332 __IO uint8_t DLM;
aidan1971 1:8b04bd33c7cd 333 __IO uint32_t IER;
aidan1971 1:8b04bd33c7cd 334 };
aidan1971 1:8b04bd33c7cd 335 union {
aidan1971 1:8b04bd33c7cd 336 __I uint32_t IIR;
aidan1971 1:8b04bd33c7cd 337 __O uint8_t FCR;
aidan1971 1:8b04bd33c7cd 338 };
aidan1971 1:8b04bd33c7cd 339 __IO uint8_t LCR;
aidan1971 1:8b04bd33c7cd 340 uint8_t RESERVED1[7];
aidan1971 1:8b04bd33c7cd 341 __I uint8_t LSR;
aidan1971 1:8b04bd33c7cd 342 uint8_t RESERVED2[7];
aidan1971 1:8b04bd33c7cd 343 __IO uint8_t SCR;
aidan1971 1:8b04bd33c7cd 344 uint8_t RESERVED3[3];
aidan1971 1:8b04bd33c7cd 345 __IO uint32_t ACR;
aidan1971 1:8b04bd33c7cd 346 __IO uint8_t ICR;
aidan1971 1:8b04bd33c7cd 347 uint8_t RESERVED4[3];
aidan1971 1:8b04bd33c7cd 348 __IO uint8_t FDR;
aidan1971 1:8b04bd33c7cd 349 uint8_t RESERVED5[7];
aidan1971 1:8b04bd33c7cd 350 __IO uint8_t TER;
aidan1971 1:8b04bd33c7cd 351 uint8_t RESERVED6[39];
aidan1971 1:8b04bd33c7cd 352 __IO uint32_t FIFOLVL;
aidan1971 1:8b04bd33c7cd 353 } LPC_UART_TypeDef;
aidan1971 1:8b04bd33c7cd 354
aidan1971 1:8b04bd33c7cd 355 typedef struct
aidan1971 1:8b04bd33c7cd 356 {
aidan1971 1:8b04bd33c7cd 357 union {
aidan1971 1:8b04bd33c7cd 358 __I uint8_t RBR;
aidan1971 1:8b04bd33c7cd 359 __O uint8_t THR;
aidan1971 1:8b04bd33c7cd 360 __IO uint8_t DLL;
aidan1971 1:8b04bd33c7cd 361 uint32_t RESERVED0;
aidan1971 1:8b04bd33c7cd 362 };
aidan1971 1:8b04bd33c7cd 363 union {
aidan1971 1:8b04bd33c7cd 364 __IO uint8_t DLM;
aidan1971 1:8b04bd33c7cd 365 __IO uint32_t IER;
aidan1971 1:8b04bd33c7cd 366 };
aidan1971 1:8b04bd33c7cd 367 union {
aidan1971 1:8b04bd33c7cd 368 __I uint32_t IIR;
aidan1971 1:8b04bd33c7cd 369 __O uint8_t FCR;
aidan1971 1:8b04bd33c7cd 370 };
aidan1971 1:8b04bd33c7cd 371 __IO uint8_t LCR;
aidan1971 1:8b04bd33c7cd 372 uint8_t RESERVED1[7];
aidan1971 1:8b04bd33c7cd 373 __I uint8_t LSR;
aidan1971 1:8b04bd33c7cd 374 uint8_t RESERVED2[7];
aidan1971 1:8b04bd33c7cd 375 __IO uint8_t SCR;
aidan1971 1:8b04bd33c7cd 376 uint8_t RESERVED3[3];
aidan1971 1:8b04bd33c7cd 377 __IO uint32_t ACR;
aidan1971 1:8b04bd33c7cd 378 __IO uint8_t ICR;
aidan1971 1:8b04bd33c7cd 379 uint8_t RESERVED4[3];
aidan1971 1:8b04bd33c7cd 380 __IO uint8_t FDR;
aidan1971 1:8b04bd33c7cd 381 uint8_t RESERVED5[7];
aidan1971 1:8b04bd33c7cd 382 __IO uint8_t TER;
aidan1971 1:8b04bd33c7cd 383 uint8_t RESERVED6[39];
aidan1971 1:8b04bd33c7cd 384 __IO uint32_t FIFOLVL;
aidan1971 1:8b04bd33c7cd 385 } LPC_UART0_TypeDef;
aidan1971 1:8b04bd33c7cd 386
aidan1971 1:8b04bd33c7cd 387 typedef struct
aidan1971 1:8b04bd33c7cd 388 {
aidan1971 1:8b04bd33c7cd 389 union {
aidan1971 1:8b04bd33c7cd 390 __I uint8_t RBR;
aidan1971 1:8b04bd33c7cd 391 __O uint8_t THR;
aidan1971 1:8b04bd33c7cd 392 __IO uint8_t DLL;
aidan1971 1:8b04bd33c7cd 393 uint32_t RESERVED0;
aidan1971 1:8b04bd33c7cd 394 };
aidan1971 1:8b04bd33c7cd 395 union {
aidan1971 1:8b04bd33c7cd 396 __IO uint8_t DLM;
aidan1971 1:8b04bd33c7cd 397 __IO uint32_t IER;
aidan1971 1:8b04bd33c7cd 398 };
aidan1971 1:8b04bd33c7cd 399 union {
aidan1971 1:8b04bd33c7cd 400 __I uint32_t IIR;
aidan1971 1:8b04bd33c7cd 401 __O uint8_t FCR;
aidan1971 1:8b04bd33c7cd 402 };
aidan1971 1:8b04bd33c7cd 403 __IO uint8_t LCR;
aidan1971 1:8b04bd33c7cd 404 uint8_t RESERVED1[3];
aidan1971 1:8b04bd33c7cd 405 __IO uint8_t MCR;
aidan1971 1:8b04bd33c7cd 406 uint8_t RESERVED2[3];
aidan1971 1:8b04bd33c7cd 407 __I uint8_t LSR;
aidan1971 1:8b04bd33c7cd 408 uint8_t RESERVED3[3];
aidan1971 1:8b04bd33c7cd 409 __I uint8_t MSR;
aidan1971 1:8b04bd33c7cd 410 uint8_t RESERVED4[3];
aidan1971 1:8b04bd33c7cd 411 __IO uint8_t SCR;
aidan1971 1:8b04bd33c7cd 412 uint8_t RESERVED5[3];
aidan1971 1:8b04bd33c7cd 413 __IO uint32_t ACR;
aidan1971 1:8b04bd33c7cd 414 uint32_t RESERVED6;
aidan1971 1:8b04bd33c7cd 415 __IO uint32_t FDR;
aidan1971 1:8b04bd33c7cd 416 uint32_t RESERVED7;
aidan1971 1:8b04bd33c7cd 417 __IO uint8_t TER;
aidan1971 1:8b04bd33c7cd 418 uint8_t RESERVED8[27];
aidan1971 1:8b04bd33c7cd 419 __IO uint8_t RS485CTRL;
aidan1971 1:8b04bd33c7cd 420 uint8_t RESERVED9[3];
aidan1971 1:8b04bd33c7cd 421 __IO uint8_t ADRMATCH;
aidan1971 1:8b04bd33c7cd 422 uint8_t RESERVED10[3];
aidan1971 1:8b04bd33c7cd 423 __IO uint8_t RS485DLY;
aidan1971 1:8b04bd33c7cd 424 uint8_t RESERVED11[3];
aidan1971 1:8b04bd33c7cd 425 __IO uint32_t FIFOLVL;
aidan1971 1:8b04bd33c7cd 426 } LPC_UART1_TypeDef;
aidan1971 1:8b04bd33c7cd 427
aidan1971 1:8b04bd33c7cd 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
aidan1971 1:8b04bd33c7cd 429 typedef struct
aidan1971 1:8b04bd33c7cd 430 {
aidan1971 1:8b04bd33c7cd 431 __IO uint32_t SPCR;
aidan1971 1:8b04bd33c7cd 432 __I uint32_t SPSR;
aidan1971 1:8b04bd33c7cd 433 __IO uint32_t SPDR;
aidan1971 1:8b04bd33c7cd 434 __IO uint32_t SPCCR;
aidan1971 1:8b04bd33c7cd 435 uint32_t RESERVED0[3];
aidan1971 1:8b04bd33c7cd 436 __IO uint32_t SPINT;
aidan1971 1:8b04bd33c7cd 437 } LPC_SPI_TypeDef;
aidan1971 1:8b04bd33c7cd 438
aidan1971 1:8b04bd33c7cd 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
aidan1971 1:8b04bd33c7cd 440 typedef struct
aidan1971 1:8b04bd33c7cd 441 {
aidan1971 1:8b04bd33c7cd 442 __IO uint32_t CR0;
aidan1971 1:8b04bd33c7cd 443 __IO uint32_t CR1;
aidan1971 1:8b04bd33c7cd 444 __IO uint32_t DR;
aidan1971 1:8b04bd33c7cd 445 __I uint32_t SR;
aidan1971 1:8b04bd33c7cd 446 __IO uint32_t CPSR;
aidan1971 1:8b04bd33c7cd 447 __IO uint32_t IMSC;
aidan1971 1:8b04bd33c7cd 448 __IO uint32_t RIS;
aidan1971 1:8b04bd33c7cd 449 __IO uint32_t MIS;
aidan1971 1:8b04bd33c7cd 450 __IO uint32_t ICR;
aidan1971 1:8b04bd33c7cd 451 __IO uint32_t DMACR;
aidan1971 1:8b04bd33c7cd 452 } LPC_SSP_TypeDef;
aidan1971 1:8b04bd33c7cd 453
aidan1971 1:8b04bd33c7cd 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
aidan1971 1:8b04bd33c7cd 455 typedef struct
aidan1971 1:8b04bd33c7cd 456 {
aidan1971 1:8b04bd33c7cd 457 __IO uint32_t I2CONSET;
aidan1971 1:8b04bd33c7cd 458 __I uint32_t I2STAT;
aidan1971 1:8b04bd33c7cd 459 __IO uint32_t I2DAT;
aidan1971 1:8b04bd33c7cd 460 __IO uint32_t I2ADR0;
aidan1971 1:8b04bd33c7cd 461 __IO uint32_t I2SCLH;
aidan1971 1:8b04bd33c7cd 462 __IO uint32_t I2SCLL;
aidan1971 1:8b04bd33c7cd 463 __O uint32_t I2CONCLR;
aidan1971 1:8b04bd33c7cd 464 __IO uint32_t MMCTRL;
aidan1971 1:8b04bd33c7cd 465 __IO uint32_t I2ADR1;
aidan1971 1:8b04bd33c7cd 466 __IO uint32_t I2ADR2;
aidan1971 1:8b04bd33c7cd 467 __IO uint32_t I2ADR3;
aidan1971 1:8b04bd33c7cd 468 __I uint32_t I2DATA_BUFFER;
aidan1971 1:8b04bd33c7cd 469 __IO uint32_t I2MASK0;
aidan1971 1:8b04bd33c7cd 470 __IO uint32_t I2MASK1;
aidan1971 1:8b04bd33c7cd 471 __IO uint32_t I2MASK2;
aidan1971 1:8b04bd33c7cd 472 __IO uint32_t I2MASK3;
aidan1971 1:8b04bd33c7cd 473 } LPC_I2C_TypeDef;
aidan1971 1:8b04bd33c7cd 474
aidan1971 1:8b04bd33c7cd 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
aidan1971 1:8b04bd33c7cd 476 typedef struct
aidan1971 1:8b04bd33c7cd 477 {
aidan1971 1:8b04bd33c7cd 478 __IO uint32_t I2SDAO;
aidan1971 1:8b04bd33c7cd 479 __IO uint32_t I2SDAI;
aidan1971 1:8b04bd33c7cd 480 __O uint32_t I2STXFIFO;
aidan1971 1:8b04bd33c7cd 481 __I uint32_t I2SRXFIFO;
aidan1971 1:8b04bd33c7cd 482 __I uint32_t I2SSTATE;
aidan1971 1:8b04bd33c7cd 483 __IO uint32_t I2SDMA1;
aidan1971 1:8b04bd33c7cd 484 __IO uint32_t I2SDMA2;
aidan1971 1:8b04bd33c7cd 485 __IO uint32_t I2SIRQ;
aidan1971 1:8b04bd33c7cd 486 __IO uint32_t I2STXRATE;
aidan1971 1:8b04bd33c7cd 487 __IO uint32_t I2SRXRATE;
aidan1971 1:8b04bd33c7cd 488 __IO uint32_t I2STXBITRATE;
aidan1971 1:8b04bd33c7cd 489 __IO uint32_t I2SRXBITRATE;
aidan1971 1:8b04bd33c7cd 490 __IO uint32_t I2STXMODE;
aidan1971 1:8b04bd33c7cd 491 __IO uint32_t I2SRXMODE;
aidan1971 1:8b04bd33c7cd 492 } LPC_I2S_TypeDef;
aidan1971 1:8b04bd33c7cd 493
aidan1971 1:8b04bd33c7cd 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
aidan1971 1:8b04bd33c7cd 495 typedef struct
aidan1971 1:8b04bd33c7cd 496 {
aidan1971 1:8b04bd33c7cd 497 __IO uint32_t RICOMPVAL;
aidan1971 1:8b04bd33c7cd 498 __IO uint32_t RIMASK;
aidan1971 1:8b04bd33c7cd 499 __IO uint8_t RICTRL;
aidan1971 1:8b04bd33c7cd 500 uint8_t RESERVED0[3];
aidan1971 1:8b04bd33c7cd 501 __IO uint32_t RICOUNTER;
aidan1971 1:8b04bd33c7cd 502 } LPC_RIT_TypeDef;
aidan1971 1:8b04bd33c7cd 503
aidan1971 1:8b04bd33c7cd 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
aidan1971 1:8b04bd33c7cd 505 typedef struct
aidan1971 1:8b04bd33c7cd 506 {
aidan1971 1:8b04bd33c7cd 507 __IO uint8_t ILR;
aidan1971 1:8b04bd33c7cd 508 uint8_t RESERVED0[7];
aidan1971 1:8b04bd33c7cd 509 __IO uint8_t CCR;
aidan1971 1:8b04bd33c7cd 510 uint8_t RESERVED1[3];
aidan1971 1:8b04bd33c7cd 511 __IO uint8_t CIIR;
aidan1971 1:8b04bd33c7cd 512 uint8_t RESERVED2[3];
aidan1971 1:8b04bd33c7cd 513 __IO uint8_t AMR;
aidan1971 1:8b04bd33c7cd 514 uint8_t RESERVED3[3];
aidan1971 1:8b04bd33c7cd 515 __I uint32_t CTIME0;
aidan1971 1:8b04bd33c7cd 516 __I uint32_t CTIME1;
aidan1971 1:8b04bd33c7cd 517 __I uint32_t CTIME2;
aidan1971 1:8b04bd33c7cd 518 __IO uint8_t SEC;
aidan1971 1:8b04bd33c7cd 519 uint8_t RESERVED4[3];
aidan1971 1:8b04bd33c7cd 520 __IO uint8_t MIN;
aidan1971 1:8b04bd33c7cd 521 uint8_t RESERVED5[3];
aidan1971 1:8b04bd33c7cd 522 __IO uint8_t HOUR;
aidan1971 1:8b04bd33c7cd 523 uint8_t RESERVED6[3];
aidan1971 1:8b04bd33c7cd 524 __IO uint8_t DOM;
aidan1971 1:8b04bd33c7cd 525 uint8_t RESERVED7[3];
aidan1971 1:8b04bd33c7cd 526 __IO uint8_t DOW;
aidan1971 1:8b04bd33c7cd 527 uint8_t RESERVED8[3];
aidan1971 1:8b04bd33c7cd 528 __IO uint16_t DOY;
aidan1971 1:8b04bd33c7cd 529 uint16_t RESERVED9;
aidan1971 1:8b04bd33c7cd 530 __IO uint8_t MONTH;
aidan1971 1:8b04bd33c7cd 531 uint8_t RESERVED10[3];
aidan1971 1:8b04bd33c7cd 532 __IO uint16_t YEAR;
aidan1971 1:8b04bd33c7cd 533 uint16_t RESERVED11;
aidan1971 1:8b04bd33c7cd 534 __IO uint32_t CALIBRATION;
aidan1971 1:8b04bd33c7cd 535 __IO uint32_t GPREG0;
aidan1971 1:8b04bd33c7cd 536 __IO uint32_t GPREG1;
aidan1971 1:8b04bd33c7cd 537 __IO uint32_t GPREG2;
aidan1971 1:8b04bd33c7cd 538 __IO uint32_t GPREG3;
aidan1971 1:8b04bd33c7cd 539 __IO uint32_t GPREG4;
aidan1971 1:8b04bd33c7cd 540 __IO uint8_t RTC_AUXEN;
aidan1971 1:8b04bd33c7cd 541 uint8_t RESERVED12[3];
aidan1971 1:8b04bd33c7cd 542 __IO uint8_t RTC_AUX;
aidan1971 1:8b04bd33c7cd 543 uint8_t RESERVED13[3];
aidan1971 1:8b04bd33c7cd 544 __IO uint8_t ALSEC;
aidan1971 1:8b04bd33c7cd 545 uint8_t RESERVED14[3];
aidan1971 1:8b04bd33c7cd 546 __IO uint8_t ALMIN;
aidan1971 1:8b04bd33c7cd 547 uint8_t RESERVED15[3];
aidan1971 1:8b04bd33c7cd 548 __IO uint8_t ALHOUR;
aidan1971 1:8b04bd33c7cd 549 uint8_t RESERVED16[3];
aidan1971 1:8b04bd33c7cd 550 __IO uint8_t ALDOM;
aidan1971 1:8b04bd33c7cd 551 uint8_t RESERVED17[3];
aidan1971 1:8b04bd33c7cd 552 __IO uint8_t ALDOW;
aidan1971 1:8b04bd33c7cd 553 uint8_t RESERVED18[3];
aidan1971 1:8b04bd33c7cd 554 __IO uint16_t ALDOY;
aidan1971 1:8b04bd33c7cd 555 uint16_t RESERVED19;
aidan1971 1:8b04bd33c7cd 556 __IO uint8_t ALMON;
aidan1971 1:8b04bd33c7cd 557 uint8_t RESERVED20[3];
aidan1971 1:8b04bd33c7cd 558 __IO uint16_t ALYEAR;
aidan1971 1:8b04bd33c7cd 559 uint16_t RESERVED21;
aidan1971 1:8b04bd33c7cd 560 } LPC_RTC_TypeDef;
aidan1971 1:8b04bd33c7cd 561
aidan1971 1:8b04bd33c7cd 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
aidan1971 1:8b04bd33c7cd 563 typedef struct
aidan1971 1:8b04bd33c7cd 564 {
aidan1971 1:8b04bd33c7cd 565 __IO uint8_t WDMOD;
aidan1971 1:8b04bd33c7cd 566 uint8_t RESERVED0[3];
aidan1971 1:8b04bd33c7cd 567 __IO uint32_t WDTC;
aidan1971 1:8b04bd33c7cd 568 __O uint8_t WDFEED;
aidan1971 1:8b04bd33c7cd 569 uint8_t RESERVED1[3];
aidan1971 1:8b04bd33c7cd 570 __I uint32_t WDTV;
aidan1971 1:8b04bd33c7cd 571 __IO uint32_t WDCLKSEL;
aidan1971 1:8b04bd33c7cd 572 } LPC_WDT_TypeDef;
aidan1971 1:8b04bd33c7cd 573
aidan1971 1:8b04bd33c7cd 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
aidan1971 1:8b04bd33c7cd 575 typedef struct
aidan1971 1:8b04bd33c7cd 576 {
aidan1971 1:8b04bd33c7cd 577 __IO uint32_t ADCR;
aidan1971 1:8b04bd33c7cd 578 __IO uint32_t ADGDR;
aidan1971 1:8b04bd33c7cd 579 uint32_t RESERVED0;
aidan1971 1:8b04bd33c7cd 580 __IO uint32_t ADINTEN;
aidan1971 1:8b04bd33c7cd 581 __I uint32_t ADDR0;
aidan1971 1:8b04bd33c7cd 582 __I uint32_t ADDR1;
aidan1971 1:8b04bd33c7cd 583 __I uint32_t ADDR2;
aidan1971 1:8b04bd33c7cd 584 __I uint32_t ADDR3;
aidan1971 1:8b04bd33c7cd 585 __I uint32_t ADDR4;
aidan1971 1:8b04bd33c7cd 586 __I uint32_t ADDR5;
aidan1971 1:8b04bd33c7cd 587 __I uint32_t ADDR6;
aidan1971 1:8b04bd33c7cd 588 __I uint32_t ADDR7;
aidan1971 1:8b04bd33c7cd 589 __I uint32_t ADSTAT;
aidan1971 1:8b04bd33c7cd 590 __IO uint32_t ADTRM;
aidan1971 1:8b04bd33c7cd 591 } LPC_ADC_TypeDef;
aidan1971 1:8b04bd33c7cd 592
aidan1971 1:8b04bd33c7cd 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
aidan1971 1:8b04bd33c7cd 594 typedef struct
aidan1971 1:8b04bd33c7cd 595 {
aidan1971 1:8b04bd33c7cd 596 __IO uint32_t DACR;
aidan1971 1:8b04bd33c7cd 597 __IO uint32_t DACCTRL;
aidan1971 1:8b04bd33c7cd 598 __IO uint16_t DACCNTVAL;
aidan1971 1:8b04bd33c7cd 599 } LPC_DAC_TypeDef;
aidan1971 1:8b04bd33c7cd 600
aidan1971 1:8b04bd33c7cd 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
aidan1971 1:8b04bd33c7cd 602 typedef struct
aidan1971 1:8b04bd33c7cd 603 {
aidan1971 1:8b04bd33c7cd 604 __I uint32_t MCCON;
aidan1971 1:8b04bd33c7cd 605 __O uint32_t MCCON_SET;
aidan1971 1:8b04bd33c7cd 606 __O uint32_t MCCON_CLR;
aidan1971 1:8b04bd33c7cd 607 __I uint32_t MCCAPCON;
aidan1971 1:8b04bd33c7cd 608 __O uint32_t MCCAPCON_SET;
aidan1971 1:8b04bd33c7cd 609 __O uint32_t MCCAPCON_CLR;
aidan1971 1:8b04bd33c7cd 610 __IO uint32_t MCTIM0;
aidan1971 1:8b04bd33c7cd 611 __IO uint32_t MCTIM1;
aidan1971 1:8b04bd33c7cd 612 __IO uint32_t MCTIM2;
aidan1971 1:8b04bd33c7cd 613 __IO uint32_t MCPER0;
aidan1971 1:8b04bd33c7cd 614 __IO uint32_t MCPER1;
aidan1971 1:8b04bd33c7cd 615 __IO uint32_t MCPER2;
aidan1971 1:8b04bd33c7cd 616 __IO uint32_t MCPW0;
aidan1971 1:8b04bd33c7cd 617 __IO uint32_t MCPW1;
aidan1971 1:8b04bd33c7cd 618 __IO uint32_t MCPW2;
aidan1971 1:8b04bd33c7cd 619 __IO uint32_t MCDEADTIME;
aidan1971 1:8b04bd33c7cd 620 __IO uint32_t MCCCP;
aidan1971 1:8b04bd33c7cd 621 __IO uint32_t MCCR0;
aidan1971 1:8b04bd33c7cd 622 __IO uint32_t MCCR1;
aidan1971 1:8b04bd33c7cd 623 __IO uint32_t MCCR2;
aidan1971 1:8b04bd33c7cd 624 __I uint32_t MCINTEN;
aidan1971 1:8b04bd33c7cd 625 __O uint32_t MCINTEN_SET;
aidan1971 1:8b04bd33c7cd 626 __O uint32_t MCINTEN_CLR;
aidan1971 1:8b04bd33c7cd 627 __I uint32_t MCCNTCON;
aidan1971 1:8b04bd33c7cd 628 __O uint32_t MCCNTCON_SET;
aidan1971 1:8b04bd33c7cd 629 __O uint32_t MCCNTCON_CLR;
aidan1971 1:8b04bd33c7cd 630 __I uint32_t MCINTFLAG;
aidan1971 1:8b04bd33c7cd 631 __O uint32_t MCINTFLAG_SET;
aidan1971 1:8b04bd33c7cd 632 __O uint32_t MCINTFLAG_CLR;
aidan1971 1:8b04bd33c7cd 633 __O uint32_t MCCAP_CLR;
aidan1971 1:8b04bd33c7cd 634 } LPC_MCPWM_TypeDef;
aidan1971 1:8b04bd33c7cd 635
aidan1971 1:8b04bd33c7cd 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
aidan1971 1:8b04bd33c7cd 637 typedef struct
aidan1971 1:8b04bd33c7cd 638 {
aidan1971 1:8b04bd33c7cd 639 __O uint32_t QEICON;
aidan1971 1:8b04bd33c7cd 640 __I uint32_t QEISTAT;
aidan1971 1:8b04bd33c7cd 641 __IO uint32_t QEICONF;
aidan1971 1:8b04bd33c7cd 642 __I uint32_t QEIPOS;
aidan1971 1:8b04bd33c7cd 643 __IO uint32_t QEIMAXPOS;
aidan1971 1:8b04bd33c7cd 644 __IO uint32_t CMPOS0;
aidan1971 1:8b04bd33c7cd 645 __IO uint32_t CMPOS1;
aidan1971 1:8b04bd33c7cd 646 __IO uint32_t CMPOS2;
aidan1971 1:8b04bd33c7cd 647 __I uint32_t INXCNT;
aidan1971 1:8b04bd33c7cd 648 __IO uint32_t INXCMP;
aidan1971 1:8b04bd33c7cd 649 __IO uint32_t QEILOAD;
aidan1971 1:8b04bd33c7cd 650 __I uint32_t QEITIME;
aidan1971 1:8b04bd33c7cd 651 __I uint32_t QEIVEL;
aidan1971 1:8b04bd33c7cd 652 __I uint32_t QEICAP;
aidan1971 1:8b04bd33c7cd 653 __IO uint32_t VELCOMP;
aidan1971 1:8b04bd33c7cd 654 __IO uint32_t FILTER;
aidan1971 1:8b04bd33c7cd 655 uint32_t RESERVED0[998];
aidan1971 1:8b04bd33c7cd 656 __O uint32_t QEIIEC;
aidan1971 1:8b04bd33c7cd 657 __O uint32_t QEIIES;
aidan1971 1:8b04bd33c7cd 658 __I uint32_t QEIINTSTAT;
aidan1971 1:8b04bd33c7cd 659 __I uint32_t QEIIE;
aidan1971 1:8b04bd33c7cd 660 __O uint32_t QEICLR;
aidan1971 1:8b04bd33c7cd 661 __O uint32_t QEISET;
aidan1971 1:8b04bd33c7cd 662 } LPC_QEI_TypeDef;
aidan1971 1:8b04bd33c7cd 663
aidan1971 1:8b04bd33c7cd 664 /*------------- Controller Area Network (CAN) --------------------------------*/
aidan1971 1:8b04bd33c7cd 665 typedef struct
aidan1971 1:8b04bd33c7cd 666 {
aidan1971 1:8b04bd33c7cd 667 __IO uint32_t mask[512]; /* ID Masks */
aidan1971 1:8b04bd33c7cd 668 } LPC_CANAF_RAM_TypeDef;
aidan1971 1:8b04bd33c7cd 669
aidan1971 1:8b04bd33c7cd 670 typedef struct /* Acceptance Filter Registers */
aidan1971 1:8b04bd33c7cd 671 {
aidan1971 1:8b04bd33c7cd 672 __IO uint32_t AFMR;
aidan1971 1:8b04bd33c7cd 673 __IO uint32_t SFF_sa;
aidan1971 1:8b04bd33c7cd 674 __IO uint32_t SFF_GRP_sa;
aidan1971 1:8b04bd33c7cd 675 __IO uint32_t EFF_sa;
aidan1971 1:8b04bd33c7cd 676 __IO uint32_t EFF_GRP_sa;
aidan1971 1:8b04bd33c7cd 677 __IO uint32_t ENDofTable;
aidan1971 1:8b04bd33c7cd 678 __I uint32_t LUTerrAd;
aidan1971 1:8b04bd33c7cd 679 __I uint32_t LUTerr;
aidan1971 1:8b04bd33c7cd 680 __IO uint32_t FCANIE;
aidan1971 1:8b04bd33c7cd 681 __IO uint32_t FCANIC0;
aidan1971 1:8b04bd33c7cd 682 __IO uint32_t FCANIC1;
aidan1971 1:8b04bd33c7cd 683 } LPC_CANAF_TypeDef;
aidan1971 1:8b04bd33c7cd 684
aidan1971 1:8b04bd33c7cd 685 typedef struct /* Central Registers */
aidan1971 1:8b04bd33c7cd 686 {
aidan1971 1:8b04bd33c7cd 687 __I uint32_t CANTxSR;
aidan1971 1:8b04bd33c7cd 688 __I uint32_t CANRxSR;
aidan1971 1:8b04bd33c7cd 689 __I uint32_t CANMSR;
aidan1971 1:8b04bd33c7cd 690 } LPC_CANCR_TypeDef;
aidan1971 1:8b04bd33c7cd 691
aidan1971 1:8b04bd33c7cd 692 typedef struct /* Controller Registers */
aidan1971 1:8b04bd33c7cd 693 {
aidan1971 1:8b04bd33c7cd 694 __IO uint32_t MOD;
aidan1971 1:8b04bd33c7cd 695 __O uint32_t CMR;
aidan1971 1:8b04bd33c7cd 696 __IO uint32_t GSR;
aidan1971 1:8b04bd33c7cd 697 __I uint32_t ICR;
aidan1971 1:8b04bd33c7cd 698 __IO uint32_t IER;
aidan1971 1:8b04bd33c7cd 699 __IO uint32_t BTR;
aidan1971 1:8b04bd33c7cd 700 __IO uint32_t EWL;
aidan1971 1:8b04bd33c7cd 701 __I uint32_t SR;
aidan1971 1:8b04bd33c7cd 702 __IO uint32_t RFS;
aidan1971 1:8b04bd33c7cd 703 __IO uint32_t RID;
aidan1971 1:8b04bd33c7cd 704 __IO uint32_t RDA;
aidan1971 1:8b04bd33c7cd 705 __IO uint32_t RDB;
aidan1971 1:8b04bd33c7cd 706 __IO uint32_t TFI1;
aidan1971 1:8b04bd33c7cd 707 __IO uint32_t TID1;
aidan1971 1:8b04bd33c7cd 708 __IO uint32_t TDA1;
aidan1971 1:8b04bd33c7cd 709 __IO uint32_t TDB1;
aidan1971 1:8b04bd33c7cd 710 __IO uint32_t TFI2;
aidan1971 1:8b04bd33c7cd 711 __IO uint32_t TID2;
aidan1971 1:8b04bd33c7cd 712 __IO uint32_t TDA2;
aidan1971 1:8b04bd33c7cd 713 __IO uint32_t TDB2;
aidan1971 1:8b04bd33c7cd 714 __IO uint32_t TFI3;
aidan1971 1:8b04bd33c7cd 715 __IO uint32_t TID3;
aidan1971 1:8b04bd33c7cd 716 __IO uint32_t TDA3;
aidan1971 1:8b04bd33c7cd 717 __IO uint32_t TDB3;
aidan1971 1:8b04bd33c7cd 718 } LPC_CAN_TypeDef;
aidan1971 1:8b04bd33c7cd 719
aidan1971 1:8b04bd33c7cd 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
aidan1971 1:8b04bd33c7cd 721 typedef struct /* Common Registers */
aidan1971 1:8b04bd33c7cd 722 {
aidan1971 1:8b04bd33c7cd 723 __I uint32_t DMACIntStat;
aidan1971 1:8b04bd33c7cd 724 __I uint32_t DMACIntTCStat;
aidan1971 1:8b04bd33c7cd 725 __O uint32_t DMACIntTCClear;
aidan1971 1:8b04bd33c7cd 726 __I uint32_t DMACIntErrStat;
aidan1971 1:8b04bd33c7cd 727 __O uint32_t DMACIntErrClr;
aidan1971 1:8b04bd33c7cd 728 __I uint32_t DMACRawIntTCStat;
aidan1971 1:8b04bd33c7cd 729 __I uint32_t DMACRawIntErrStat;
aidan1971 1:8b04bd33c7cd 730 __I uint32_t DMACEnbldChns;
aidan1971 1:8b04bd33c7cd 731 __IO uint32_t DMACSoftBReq;
aidan1971 1:8b04bd33c7cd 732 __IO uint32_t DMACSoftSReq;
aidan1971 1:8b04bd33c7cd 733 __IO uint32_t DMACSoftLBReq;
aidan1971 1:8b04bd33c7cd 734 __IO uint32_t DMACSoftLSReq;
aidan1971 1:8b04bd33c7cd 735 __IO uint32_t DMACConfig;
aidan1971 1:8b04bd33c7cd 736 __IO uint32_t DMACSync;
aidan1971 1:8b04bd33c7cd 737 } LPC_GPDMA_TypeDef;
aidan1971 1:8b04bd33c7cd 738
aidan1971 1:8b04bd33c7cd 739 typedef struct /* Channel Registers */
aidan1971 1:8b04bd33c7cd 740 {
aidan1971 1:8b04bd33c7cd 741 __IO uint32_t DMACCSrcAddr;
aidan1971 1:8b04bd33c7cd 742 __IO uint32_t DMACCDestAddr;
aidan1971 1:8b04bd33c7cd 743 __IO uint32_t DMACCLLI;
aidan1971 1:8b04bd33c7cd 744 __IO uint32_t DMACCControl;
aidan1971 1:8b04bd33c7cd 745 __IO uint32_t DMACCConfig;
aidan1971 1:8b04bd33c7cd 746 } LPC_GPDMACH_TypeDef;
aidan1971 1:8b04bd33c7cd 747
aidan1971 1:8b04bd33c7cd 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
aidan1971 1:8b04bd33c7cd 749 typedef struct
aidan1971 1:8b04bd33c7cd 750 {
aidan1971 1:8b04bd33c7cd 751 __I uint32_t HcRevision; /* USB Host Registers */
aidan1971 1:8b04bd33c7cd 752 __IO uint32_t HcControl;
aidan1971 1:8b04bd33c7cd 753 __IO uint32_t HcCommandStatus;
aidan1971 1:8b04bd33c7cd 754 __IO uint32_t HcInterruptStatus;
aidan1971 1:8b04bd33c7cd 755 __IO uint32_t HcInterruptEnable;
aidan1971 1:8b04bd33c7cd 756 __IO uint32_t HcInterruptDisable;
aidan1971 1:8b04bd33c7cd 757 __IO uint32_t HcHCCA;
aidan1971 1:8b04bd33c7cd 758 __I uint32_t HcPeriodCurrentED;
aidan1971 1:8b04bd33c7cd 759 __IO uint32_t HcControlHeadED;
aidan1971 1:8b04bd33c7cd 760 __IO uint32_t HcControlCurrentED;
aidan1971 1:8b04bd33c7cd 761 __IO uint32_t HcBulkHeadED;
aidan1971 1:8b04bd33c7cd 762 __IO uint32_t HcBulkCurrentED;
aidan1971 1:8b04bd33c7cd 763 __I uint32_t HcDoneHead;
aidan1971 1:8b04bd33c7cd 764 __IO uint32_t HcFmInterval;
aidan1971 1:8b04bd33c7cd 765 __I uint32_t HcFmRemaining;
aidan1971 1:8b04bd33c7cd 766 __I uint32_t HcFmNumber;
aidan1971 1:8b04bd33c7cd 767 __IO uint32_t HcPeriodicStart;
aidan1971 1:8b04bd33c7cd 768 __IO uint32_t HcLSTreshold;
aidan1971 1:8b04bd33c7cd 769 __IO uint32_t HcRhDescriptorA;
aidan1971 1:8b04bd33c7cd 770 __IO uint32_t HcRhDescriptorB;
aidan1971 1:8b04bd33c7cd 771 __IO uint32_t HcRhStatus;
aidan1971 1:8b04bd33c7cd 772 __IO uint32_t HcRhPortStatus1;
aidan1971 1:8b04bd33c7cd 773 __IO uint32_t HcRhPortStatus2;
aidan1971 1:8b04bd33c7cd 774 uint32_t RESERVED0[40];
aidan1971 1:8b04bd33c7cd 775 __I uint32_t Module_ID;
aidan1971 1:8b04bd33c7cd 776
aidan1971 1:8b04bd33c7cd 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
aidan1971 1:8b04bd33c7cd 778 __IO uint32_t OTGIntEn;
aidan1971 1:8b04bd33c7cd 779 __O uint32_t OTGIntSet;
aidan1971 1:8b04bd33c7cd 780 __O uint32_t OTGIntClr;
aidan1971 1:8b04bd33c7cd 781 __IO uint32_t OTGStCtrl;
aidan1971 1:8b04bd33c7cd 782 __IO uint32_t OTGTmr;
aidan1971 1:8b04bd33c7cd 783 uint32_t RESERVED1[58];
aidan1971 1:8b04bd33c7cd 784
aidan1971 1:8b04bd33c7cd 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
aidan1971 1:8b04bd33c7cd 786 __IO uint32_t USBDevIntEn;
aidan1971 1:8b04bd33c7cd 787 __O uint32_t USBDevIntClr;
aidan1971 1:8b04bd33c7cd 788 __O uint32_t USBDevIntSet;
aidan1971 1:8b04bd33c7cd 789
aidan1971 1:8b04bd33c7cd 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
aidan1971 1:8b04bd33c7cd 791 __I uint32_t USBCmdData;
aidan1971 1:8b04bd33c7cd 792
aidan1971 1:8b04bd33c7cd 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
aidan1971 1:8b04bd33c7cd 794 __O uint32_t USBTxData;
aidan1971 1:8b04bd33c7cd 795 __I uint32_t USBRxPLen;
aidan1971 1:8b04bd33c7cd 796 __O uint32_t USBTxPLen;
aidan1971 1:8b04bd33c7cd 797 __IO uint32_t USBCtrl;
aidan1971 1:8b04bd33c7cd 798 __O uint32_t USBDevIntPri;
aidan1971 1:8b04bd33c7cd 799
aidan1971 1:8b04bd33c7cd 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
aidan1971 1:8b04bd33c7cd 801 __IO uint32_t USBEpIntEn;
aidan1971 1:8b04bd33c7cd 802 __O uint32_t USBEpIntClr;
aidan1971 1:8b04bd33c7cd 803 __O uint32_t USBEpIntSet;
aidan1971 1:8b04bd33c7cd 804 __O uint32_t USBEpIntPri;
aidan1971 1:8b04bd33c7cd 805
aidan1971 1:8b04bd33c7cd 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
aidan1971 1:8b04bd33c7cd 807 __O uint32_t USBEpInd;
aidan1971 1:8b04bd33c7cd 808 __IO uint32_t USBMaxPSize;
aidan1971 1:8b04bd33c7cd 809
aidan1971 1:8b04bd33c7cd 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
aidan1971 1:8b04bd33c7cd 811 __O uint32_t USBDMARClr;
aidan1971 1:8b04bd33c7cd 812 __O uint32_t USBDMARSet;
aidan1971 1:8b04bd33c7cd 813 uint32_t RESERVED2[9];
aidan1971 1:8b04bd33c7cd 814 __IO uint32_t USBUDCAH;
aidan1971 1:8b04bd33c7cd 815 __I uint32_t USBEpDMASt;
aidan1971 1:8b04bd33c7cd 816 __O uint32_t USBEpDMAEn;
aidan1971 1:8b04bd33c7cd 817 __O uint32_t USBEpDMADis;
aidan1971 1:8b04bd33c7cd 818 __I uint32_t USBDMAIntSt;
aidan1971 1:8b04bd33c7cd 819 __IO uint32_t USBDMAIntEn;
aidan1971 1:8b04bd33c7cd 820 uint32_t RESERVED3[2];
aidan1971 1:8b04bd33c7cd 821 __I uint32_t USBEoTIntSt;
aidan1971 1:8b04bd33c7cd 822 __O uint32_t USBEoTIntClr;
aidan1971 1:8b04bd33c7cd 823 __O uint32_t USBEoTIntSet;
aidan1971 1:8b04bd33c7cd 824 __I uint32_t USBNDDRIntSt;
aidan1971 1:8b04bd33c7cd 825 __O uint32_t USBNDDRIntClr;
aidan1971 1:8b04bd33c7cd 826 __O uint32_t USBNDDRIntSet;
aidan1971 1:8b04bd33c7cd 827 __I uint32_t USBSysErrIntSt;
aidan1971 1:8b04bd33c7cd 828 __O uint32_t USBSysErrIntClr;
aidan1971 1:8b04bd33c7cd 829 __O uint32_t USBSysErrIntSet;
aidan1971 1:8b04bd33c7cd 830 uint32_t RESERVED4[15];
aidan1971 1:8b04bd33c7cd 831
aidan1971 1:8b04bd33c7cd 832 union {
aidan1971 1:8b04bd33c7cd 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
aidan1971 1:8b04bd33c7cd 834 __O uint32_t I2C_TX;
aidan1971 1:8b04bd33c7cd 835 };
aidan1971 1:8b04bd33c7cd 836 __I uint32_t I2C_STS;
aidan1971 1:8b04bd33c7cd 837 __IO uint32_t I2C_CTL;
aidan1971 1:8b04bd33c7cd 838 __IO uint32_t I2C_CLKHI;
aidan1971 1:8b04bd33c7cd 839 __O uint32_t I2C_CLKLO;
aidan1971 1:8b04bd33c7cd 840 uint32_t RESERVED5[824];
aidan1971 1:8b04bd33c7cd 841
aidan1971 1:8b04bd33c7cd 842 union {
aidan1971 1:8b04bd33c7cd 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
aidan1971 1:8b04bd33c7cd 844 __IO uint32_t OTGClkCtrl;
aidan1971 1:8b04bd33c7cd 845 };
aidan1971 1:8b04bd33c7cd 846 union {
aidan1971 1:8b04bd33c7cd 847 __I uint32_t USBClkSt;
aidan1971 1:8b04bd33c7cd 848 __I uint32_t OTGClkSt;
aidan1971 1:8b04bd33c7cd 849 };
aidan1971 1:8b04bd33c7cd 850 } LPC_USB_TypeDef;
aidan1971 1:8b04bd33c7cd 851
aidan1971 1:8b04bd33c7cd 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
aidan1971 1:8b04bd33c7cd 853 typedef struct
aidan1971 1:8b04bd33c7cd 854 {
aidan1971 1:8b04bd33c7cd 855 __IO uint32_t MAC1; /* MAC Registers */
aidan1971 1:8b04bd33c7cd 856 __IO uint32_t MAC2;
aidan1971 1:8b04bd33c7cd 857 __IO uint32_t IPGT;
aidan1971 1:8b04bd33c7cd 858 __IO uint32_t IPGR;
aidan1971 1:8b04bd33c7cd 859 __IO uint32_t CLRT;
aidan1971 1:8b04bd33c7cd 860 __IO uint32_t MAXF;
aidan1971 1:8b04bd33c7cd 861 __IO uint32_t SUPP;
aidan1971 1:8b04bd33c7cd 862 __IO uint32_t TEST;
aidan1971 1:8b04bd33c7cd 863 __IO uint32_t MCFG;
aidan1971 1:8b04bd33c7cd 864 __IO uint32_t MCMD;
aidan1971 1:8b04bd33c7cd 865 __IO uint32_t MADR;
aidan1971 1:8b04bd33c7cd 866 __O uint32_t MWTD;
aidan1971 1:8b04bd33c7cd 867 __I uint32_t MRDD;
aidan1971 1:8b04bd33c7cd 868 __I uint32_t MIND;
aidan1971 1:8b04bd33c7cd 869 uint32_t RESERVED0[2];
aidan1971 1:8b04bd33c7cd 870 __IO uint32_t SA0;
aidan1971 1:8b04bd33c7cd 871 __IO uint32_t SA1;
aidan1971 1:8b04bd33c7cd 872 __IO uint32_t SA2;
aidan1971 1:8b04bd33c7cd 873 uint32_t RESERVED1[45];
aidan1971 1:8b04bd33c7cd 874 __IO uint32_t Command; /* Control Registers */
aidan1971 1:8b04bd33c7cd 875 __I uint32_t Status;
aidan1971 1:8b04bd33c7cd 876 __IO uint32_t RxDescriptor;
aidan1971 1:8b04bd33c7cd 877 __IO uint32_t RxStatus;
aidan1971 1:8b04bd33c7cd 878 __IO uint32_t RxDescriptorNumber;
aidan1971 1:8b04bd33c7cd 879 __I uint32_t RxProduceIndex;
aidan1971 1:8b04bd33c7cd 880 __IO uint32_t RxConsumeIndex;
aidan1971 1:8b04bd33c7cd 881 __IO uint32_t TxDescriptor;
aidan1971 1:8b04bd33c7cd 882 __IO uint32_t TxStatus;
aidan1971 1:8b04bd33c7cd 883 __IO uint32_t TxDescriptorNumber;
aidan1971 1:8b04bd33c7cd 884 __IO uint32_t TxProduceIndex;
aidan1971 1:8b04bd33c7cd 885 __I uint32_t TxConsumeIndex;
aidan1971 1:8b04bd33c7cd 886 uint32_t RESERVED2[10];
aidan1971 1:8b04bd33c7cd 887 __I uint32_t TSV0;
aidan1971 1:8b04bd33c7cd 888 __I uint32_t TSV1;
aidan1971 1:8b04bd33c7cd 889 __I uint32_t RSV;
aidan1971 1:8b04bd33c7cd 890 uint32_t RESERVED3[3];
aidan1971 1:8b04bd33c7cd 891 __IO uint32_t FlowControlCounter;
aidan1971 1:8b04bd33c7cd 892 __I uint32_t FlowControlStatus;
aidan1971 1:8b04bd33c7cd 893 uint32_t RESERVED4[34];
aidan1971 1:8b04bd33c7cd 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
aidan1971 1:8b04bd33c7cd 895 __IO uint32_t RxFilterWoLStatus;
aidan1971 1:8b04bd33c7cd 896 __IO uint32_t RxFilterWoLClear;
aidan1971 1:8b04bd33c7cd 897 uint32_t RESERVED5;
aidan1971 1:8b04bd33c7cd 898 __IO uint32_t HashFilterL;
aidan1971 1:8b04bd33c7cd 899 __IO uint32_t HashFilterH;
aidan1971 1:8b04bd33c7cd 900 uint32_t RESERVED6[882];
aidan1971 1:8b04bd33c7cd 901 __I uint32_t IntStatus; /* Module Control Registers */
aidan1971 1:8b04bd33c7cd 902 __IO uint32_t IntEnable;
aidan1971 1:8b04bd33c7cd 903 __O uint32_t IntClear;
aidan1971 1:8b04bd33c7cd 904 __O uint32_t IntSet;
aidan1971 1:8b04bd33c7cd 905 uint32_t RESERVED7;
aidan1971 1:8b04bd33c7cd 906 __IO uint32_t PowerDown;
aidan1971 1:8b04bd33c7cd 907 uint32_t RESERVED8;
aidan1971 1:8b04bd33c7cd 908 __IO uint32_t Module_ID;
aidan1971 1:8b04bd33c7cd 909 } LPC_EMAC_TypeDef;
aidan1971 1:8b04bd33c7cd 910
aidan1971 1:8b04bd33c7cd 911 #if defined ( __CC_ARM )
aidan1971 1:8b04bd33c7cd 912 #pragma no_anon_unions
aidan1971 1:8b04bd33c7cd 913 #endif
aidan1971 1:8b04bd33c7cd 914
aidan1971 1:8b04bd33c7cd 915
aidan1971 1:8b04bd33c7cd 916 /******************************************************************************/
aidan1971 1:8b04bd33c7cd 917 /* Peripheral memory map */
aidan1971 1:8b04bd33c7cd 918 /******************************************************************************/
aidan1971 1:8b04bd33c7cd 919 /* Base addresses */
aidan1971 1:8b04bd33c7cd 920 #define LPC_FLASH_BASE (0x00000000UL)
aidan1971 1:8b04bd33c7cd 921 #define LPC_RAM_BASE (0x10000000UL)
aidan1971 1:8b04bd33c7cd 922 #define LPC_GPIO_BASE (0x2009C000UL)
aidan1971 1:8b04bd33c7cd 923 #define LPC_APB0_BASE (0x40000000UL)
aidan1971 1:8b04bd33c7cd 924 #define LPC_APB1_BASE (0x40080000UL)
aidan1971 1:8b04bd33c7cd 925 #define LPC_AHB_BASE (0x50000000UL)
aidan1971 1:8b04bd33c7cd 926 #define LPC_CM3_BASE (0xE0000000UL)
aidan1971 1:8b04bd33c7cd 927
aidan1971 1:8b04bd33c7cd 928 /* APB0 peripherals */
aidan1971 1:8b04bd33c7cd 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
aidan1971 1:8b04bd33c7cd 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
aidan1971 1:8b04bd33c7cd 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
aidan1971 1:8b04bd33c7cd 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
aidan1971 1:8b04bd33c7cd 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
aidan1971 1:8b04bd33c7cd 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
aidan1971 1:8b04bd33c7cd 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
aidan1971 1:8b04bd33c7cd 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
aidan1971 1:8b04bd33c7cd 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
aidan1971 1:8b04bd33c7cd 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
aidan1971 1:8b04bd33c7cd 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
aidan1971 1:8b04bd33c7cd 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
aidan1971 1:8b04bd33c7cd 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
aidan1971 1:8b04bd33c7cd 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
aidan1971 1:8b04bd33c7cd 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
aidan1971 1:8b04bd33c7cd 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
aidan1971 1:8b04bd33c7cd 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
aidan1971 1:8b04bd33c7cd 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
aidan1971 1:8b04bd33c7cd 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
aidan1971 1:8b04bd33c7cd 948
aidan1971 1:8b04bd33c7cd 949 /* APB1 peripherals */
aidan1971 1:8b04bd33c7cd 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
aidan1971 1:8b04bd33c7cd 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
aidan1971 1:8b04bd33c7cd 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
aidan1971 1:8b04bd33c7cd 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
aidan1971 1:8b04bd33c7cd 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
aidan1971 1:8b04bd33c7cd 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
aidan1971 1:8b04bd33c7cd 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
aidan1971 1:8b04bd33c7cd 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
aidan1971 1:8b04bd33c7cd 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
aidan1971 1:8b04bd33c7cd 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
aidan1971 1:8b04bd33c7cd 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
aidan1971 1:8b04bd33c7cd 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
aidan1971 1:8b04bd33c7cd 962
aidan1971 1:8b04bd33c7cd 963 /* AHB peripherals */
aidan1971 1:8b04bd33c7cd 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
aidan1971 1:8b04bd33c7cd 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
aidan1971 1:8b04bd33c7cd 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
aidan1971 1:8b04bd33c7cd 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
aidan1971 1:8b04bd33c7cd 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
aidan1971 1:8b04bd33c7cd 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
aidan1971 1:8b04bd33c7cd 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
aidan1971 1:8b04bd33c7cd 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
aidan1971 1:8b04bd33c7cd 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
aidan1971 1:8b04bd33c7cd 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
aidan1971 1:8b04bd33c7cd 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
aidan1971 1:8b04bd33c7cd 975
aidan1971 1:8b04bd33c7cd 976 /* GPIOs */
aidan1971 1:8b04bd33c7cd 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
aidan1971 1:8b04bd33c7cd 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
aidan1971 1:8b04bd33c7cd 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
aidan1971 1:8b04bd33c7cd 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
aidan1971 1:8b04bd33c7cd 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
aidan1971 1:8b04bd33c7cd 982
aidan1971 1:8b04bd33c7cd 983
aidan1971 1:8b04bd33c7cd 984 /******************************************************************************/
aidan1971 1:8b04bd33c7cd 985 /* Peripheral declaration */
aidan1971 1:8b04bd33c7cd 986 /******************************************************************************/
aidan1971 1:8b04bd33c7cd 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
aidan1971 1:8b04bd33c7cd 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
aidan1971 1:8b04bd33c7cd 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
aidan1971 1:8b04bd33c7cd 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
aidan1971 1:8b04bd33c7cd 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
aidan1971 1:8b04bd33c7cd 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
aidan1971 1:8b04bd33c7cd 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
aidan1971 1:8b04bd33c7cd 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
aidan1971 1:8b04bd33c7cd 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
aidan1971 1:8b04bd33c7cd 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
aidan1971 1:8b04bd33c7cd 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
aidan1971 1:8b04bd33c7cd 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
aidan1971 1:8b04bd33c7cd 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
aidan1971 1:8b04bd33c7cd 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
aidan1971 1:8b04bd33c7cd 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
aidan1971 1:8b04bd33c7cd 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
aidan1971 1:8b04bd33c7cd 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
aidan1971 1:8b04bd33c7cd 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
aidan1971 1:8b04bd33c7cd 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
aidan1971 1:8b04bd33c7cd 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
aidan1971 1:8b04bd33c7cd 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
aidan1971 1:8b04bd33c7cd 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
aidan1971 1:8b04bd33c7cd 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
aidan1971 1:8b04bd33c7cd 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
aidan1971 1:8b04bd33c7cd 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
aidan1971 1:8b04bd33c7cd 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
aidan1971 1:8b04bd33c7cd 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
aidan1971 1:8b04bd33c7cd 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
aidan1971 1:8b04bd33c7cd 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
aidan1971 1:8b04bd33c7cd 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
aidan1971 1:8b04bd33c7cd 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
aidan1971 1:8b04bd33c7cd 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
aidan1971 1:8b04bd33c7cd 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
aidan1971 1:8b04bd33c7cd 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
aidan1971 1:8b04bd33c7cd 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
aidan1971 1:8b04bd33c7cd 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
aidan1971 1:8b04bd33c7cd 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
aidan1971 1:8b04bd33c7cd 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
aidan1971 1:8b04bd33c7cd 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
aidan1971 1:8b04bd33c7cd 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
aidan1971 1:8b04bd33c7cd 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
aidan1971 1:8b04bd33c7cd 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
aidan1971 1:8b04bd33c7cd 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
aidan1971 1:8b04bd33c7cd 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
aidan1971 1:8b04bd33c7cd 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
aidan1971 1:8b04bd33c7cd 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
aidan1971 1:8b04bd33c7cd 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
aidan1971 1:8b04bd33c7cd 1034
aidan1971 1:8b04bd33c7cd 1035 #endif // __LPC17xx_H__