adamump simus / IP12B512

IP12B512 class for comunicating with the IPSiLog IP12B512 SPI RAM

IP12B512.cpp@2:a0029473868c, 2016-11-06 (annotated)

Committer:
adamumpsimus
Date:
Sun Nov 06 16:08:04 2016 +0000
Revision:
2:a0029473868c
Parent:
1:bcbe2cf57840 
updated the docs

Who changed what in which revision?

UserRevisionLine numberNew contents of line
adamumpsimus 0:35077a3db00c 1 #include "IP12B512.h"
adamumpsimus 0:35077a3db00c 2
adamumpsimus 2:a0029473868c 3 // Constructor
adamumpsimus 0:35077a3db00c 4 IP12B512::IP12B512(
adamumpsimus 0:35077a3db00c 5 PinName pin_mosi,
adamumpsimus 0:35077a3db00c 6 PinName pin_miso,
adamumpsimus 0:35077a3db00c 7 PinName pin_sclk,
adamumpsimus 0:35077a3db00c 8 PinName pin_cs
adamumpsimus 0:35077a3db00c 9 ) :
adamumpsimus 0:35077a3db00c 10 _device(pin_mosi, pin_miso, pin_sclk),
adamumpsimus 0:35077a3db00c 11 _cs(pin_cs, 1) // even with pullup resistor, this pin goes down at startup, so a HIGH value is preferred
adamumpsimus 0:35077a3db00c 12 {
adamumpsimus 0:35077a3db00c 13 // Configure Interface
adamumpsimus 0:35077a3db00c 14 _device.format(8, 0); // NOTE: different format (not 8.3)
adamumpsimus 0:35077a3db00c 15 _device.frequency(20e6); // max speed of IP12B512 SRAM is 20MHz
adamumpsimus 0:35077a3db00c 16
adamumpsimus 0:35077a3db00c 17 // Idle SPI RAM
adamumpsimus 0:35077a3db00c 18 _cs = 0;
adamumpsimus 0:35077a3db00c 19 _cs = 1;
adamumpsimus 0:35077a3db00c 20
adamumpsimus 0:35077a3db00c 21 // Configure SPI RAM
adamumpsimus 0:35077a3db00c 22 _cs = 0;
adamumpsimus 0:35077a3db00c 23 _device.write(IP12B512_WRSR); // Write to Status Register
adamumpsimus 0:35077a3db00c 24 _device.write(0x41); // Set to Virtual Chip Mode (0x40 - with HOLD, 0x41 - no HOLD)
adamumpsimus 0:35077a3db00c 25 _cs = 1;
adamumpsimus 0:35077a3db00c 26 }
adamumpsimus 0:35077a3db00c 27
adamumpsimus 2:a0029473868c 28 // Write SRAM in byte mode (sends the most data to SRAM prior to write)
adamumpsimus 0:35077a3db00c 29 void IP12B512::Write(uint16_t addr, uint8_t data)
adamumpsimus 0:35077a3db00c 30 {
adamumpsimus 0:35077a3db00c 31 _cs = 0;
adamumpsimus 0:35077a3db00c 32 _device.write(IP12B512_WRITE); // OpCode
adamumpsimus 0:35077a3db00c 33 _device.write(addr >> 8); // Addr
adamumpsimus 0:35077a3db00c 34 _device.write(addr); // Addr
adamumpsimus 0:35077a3db00c 35 _device.write(data); // Pump out data to RAM
adamumpsimus 0:35077a3db00c 36 _cs = 1;
adamumpsimus 0:35077a3db00c 37 }
adamumpsimus 0:35077a3db00c 38
adamumpsimus 2:a0029473868c 39 // Write SRAM in stream mode (sends the least data to SRAM prior to write)
adamumpsimus 0:35077a3db00c 40 void IP12B512::StreamWrite(uint16_t addr, uint8_t *data, uint32_t size)
adamumpsimus 0:35077a3db00c 41 {
adamumpsimus 0:35077a3db00c 42 uint8_t * p = data;
adamumpsimus 0:35077a3db00c 43 uint32_t i;
adamumpsimus 0:35077a3db00c 44
adamumpsimus 0:35077a3db00c 45 _cs = 0;
adamumpsimus 0:35077a3db00c 46 _device.write(IP12B512_WRITE); // OpCode
adamumpsimus 0:35077a3db00c 47 _device.write(addr >> 8); // Addr
adamumpsimus 0:35077a3db00c 48 _device.write(addr); // Addr
adamumpsimus 0:35077a3db00c 49
adamumpsimus 0:35077a3db00c 50 for (i = 0; i < size; i++) {
adamumpsimus 0:35077a3db00c 51 _device.write(*p++); // Write to SPI ram
adamumpsimus 0:35077a3db00c 52 }
adamumpsimus 0:35077a3db00c 53 _cs = 1;
adamumpsimus 0:35077a3db00c 54 }
adamumpsimus 0:35077a3db00c 55
adamumpsimus 2:a0029473868c 56 // Read SRAM in byte mode (sends the most data to SRAM prior to read)
adamumpsimus 0:35077a3db00c 57 uint8_t IP12B512::Read(uint16_t addr)
adamumpsimus 0:35077a3db00c 58 {
adamumpsimus 0:35077a3db00c 59 uint8_t data;
adamumpsimus 0:35077a3db00c 60
adamumpsimus 0:35077a3db00c 61 _cs = 0;
adamumpsimus 0:35077a3db00c 62 _device.write(IP12B512_READ); // OpCode
adamumpsimus 0:35077a3db00c 63 _device.write(addr >> 8); // Addr
adamumpsimus 0:35077a3db00c 64 _device.write(addr); // Addr
adamumpsimus 0:35077a3db00c 65 data = _device.write(0x00); // Clock in data from RAM (doesn't matter the value)
adamumpsimus 0:35077a3db00c 66 _cs = 1;
adamumpsimus 0:35077a3db00c 67
adamumpsimus 0:35077a3db00c 68 return data;
adamumpsimus 0:35077a3db00c 69 }
adamumpsimus 0:35077a3db00c 70
adamumpsimus 2:a0029473868c 71 // Read SRAM in stream mode (sends the least data to SRAM prior to read)
adamumpsimus 0:35077a3db00c 72 void IP12B512::StreamRead(uint16_t addr, uint8_t *data, uint32_t size)
adamumpsimus 0:35077a3db00c 73 {
adamumpsimus 0:35077a3db00c 74 uint8_t * p = data;
adamumpsimus 0:35077a3db00c 75 uint32_t i;
adamumpsimus 0:35077a3db00c 76
adamumpsimus 0:35077a3db00c 77 _cs = 0;
adamumpsimus 0:35077a3db00c 78 _device.write(IP12B512_READ); // OpCode
adamumpsimus 0:35077a3db00c 79 _device.write(addr >> 8); // Addr
adamumpsimus 0:35077a3db00c 80 _device.write(addr); // Addr
adamumpsimus 0:35077a3db00c 81
adamumpsimus 0:35077a3db00c 82 for (i = 0; i < size; i++) {
adamumpsimus 0:35077a3db00c 83 *p++ = _device.write(0x00); // Clock in data from RAM(doesn't matter the value)
adamumpsimus 0:35077a3db00c 84 }
adamumpsimus 0:35077a3db00c 85 _cs = 1;
adamumpsimus 0:35077a3db00c 86 }
adamumpsimus 0:35077a3db00c 87
adamumpsimus 2:a0029473868c 88 // Fill SRAM with data
adamumpsimus 0:35077a3db00c 89 void IP12B512::ClearAll()
adamumpsimus 0:35077a3db00c 90 {
adamumpsimus 0:35077a3db00c 91 uint32_t ram_size = GetRamSize();
adamumpsimus 0:35077a3db00c 92 uint32_t i;
adamumpsimus 0:35077a3db00c 93
adamumpsimus 0:35077a3db00c 94 _cs = 0;
adamumpsimus 0:35077a3db00c 95 _device.write(IP12B512_WRITE); // OpCode
adamumpsimus 0:35077a3db00c 96 _device.write(0x00); // Addr
adamumpsimus 0:35077a3db00c 97 _device.write(0x00); // Addr
adamumpsimus 0:35077a3db00c 98
adamumpsimus 0:35077a3db00c 99 for (i = 0; i < ram_size; i++) {
adamumpsimus 0:35077a3db00c 100 _device.write(0x00); // Write to SPI ram
adamumpsimus 0:35077a3db00c 101 }
adamumpsimus 0:35077a3db00c 102 _cs = 1;
adamumpsimus 0:35077a3db00c 103 }
adamumpsimus 0:35077a3db00c 104
adamumpsimus 2:a0029473868c 105 // Gets the SRAM size in bytes
adamumpsimus 0:35077a3db00c 106 uint32_t IP12B512::GetRamSize()
adamumpsimus 0:35077a3db00c 107 {
adamumpsimus 0:35077a3db00c 108 uint8_t data;
adamumpsimus 0:35077a3db00c 109
adamumpsimus 0:35077a3db00c 110 _cs = 0;
adamumpsimus 0:35077a3db00c 111 _device.write(IP12B512_RDMI); // OpCode
adamumpsimus 0:35077a3db00c 112 data = _device.write(0xFF); // Clock in data from RAM
adamumpsimus 0:35077a3db00c 113 _cs = 1;
adamumpsimus 0:35077a3db00c 114
adamumpsimus 0:35077a3db00c 115 if (data == 0b0000) return (64 * 1024) / 8; // 64Kbit = 8KByte
adamumpsimus 0:35077a3db00c 116 if (data == 0b0001) return (128 * 1024) / 8; // 128Kbit = 16KByte
adamumpsimus 0:35077a3db00c 117 if (data == 0b0010) return (256 * 1024) / 8; // 256Kbit = 32KByte
adamumpsimus 0:35077a3db00c 118 if (data == 0b0011) return (512 * 1024) / 8; // 512Kbit = 64KByte
adamumpsimus 0:35077a3db00c 119
adamumpsimus 0:35077a3db00c 120 return 0;
adamumpsimus 0:35077a3db00c 121 }