adamump simus / IP12B512

IP12B512 class for comunicating with the IPSiLog IP12B512 SPI RAM

IP12B512.cpp@0:35077a3db00c, 2016-11-04 (annotated)

Committer:
adamumpsimus
Date:
Fri Nov 04 07:58:20 2016 +0000
Revision:
0:35077a3db00c
Child:
1:bcbe2cf57840
working version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
adamumpsimus 0:35077a3db00c 1 /** IP12B512 class.
adamumpsimus 0:35077a3db00c 2 * Main class for comunicating with the IP12B512 SPI RAM.
adamumpsimus 0:35077a3db00c 3 */
adamumpsimus 0:35077a3db00c 4 #include "IP12B512.h"
adamumpsimus 0:35077a3db00c 5
adamumpsimus 0:35077a3db00c 6 /** Constructor: setup the SPI and write to "Status Register" that we are going to use it in "Virtual Chip Mode"
adamumpsimus 0:35077a3db00c 7 *
adamumpsimus 0:35077a3db00c 8 * Notes:
adamumpsimus 0:35077a3db00c 9 * - the MOSI and MISO pins must have 5k6 pulldown resistors
adamumpsimus 0:35077a3db00c 10 * - the SCLK pin has a 5k6 pulldown resistor
adamumpsimus 0:35077a3db00c 11 * - the HOLD pin is connected to VCC
adamumpsimus 0:35077a3db00c 12 * - the CS pin has a 5k6 pullup resistor
adamumpsimus 0:35077a3db00c 13 *
adamumpsimus 0:35077a3db00c 14 * @param pin_mosi the hardware MOSI pin on the board
adamumpsimus 0:35077a3db00c 15 * @param pin_miso the hardware MISO pin on the board
adamumpsimus 0:35077a3db00c 16 * @param pin_sclk the hardware SCLK pin on the board
adamumpsimus 0:35077a3db00c 17 * @param pin_cs the software CS pin on the board (can be any output pin)
adamumpsimus 0:35077a3db00c 18 *
adamumpsimus 0:35077a3db00c 19 * Example:
adamumpsimus 0:35077a3db00c 20 * @code
adamumpsimus 0:35077a3db00c 21 *
adamumpsimus 0:35077a3db00c 22 * #include "mbed.h"
adamumpsimus 0:35077a3db00c 23 * #include "IP12B512.cpp"
adamumpsimus 0:35077a3db00c 24 *
adamumpsimus 0:35077a3db00c 25 * IP12B512 sram(SPI_MOSI, SPI_MISO, SPI_SCK, D6); // MOSI, MISO, SCK, CS
adamumpsimus 0:35077a3db00c 26 *
adamumpsimus 0:35077a3db00c 27 * int main() {
adamumpsimus 0:35077a3db00c 28 * // GET SRAM SIZE
adamumpsimus 0:35077a3db00c 29 * uint32_t ram_size = sram.GetRamSize();
adamumpsimus 0:35077a3db00c 30 * printf("ram_size %d\n", ram_size);
adamumpsimus 0:35077a3db00c 31 *
adamumpsimus 0:35077a3db00c 32 * // CLEAR ALL SRAM
adamumpsimus 0:35077a3db00c 33 * sram.ClearAll();
adamumpsimus 0:35077a3db00c 34 *
adamumpsimus 0:35077a3db00c 35 * // WRITE A SINGLE BYTE TO SRAM
adamumpsimus 0:35077a3db00c 36 * uint16_t ram_addr = 0;
adamumpsimus 0:35077a3db00c 37 * uint8_t sent_data = 0x6F;
adamumpsimus 0:35077a3db00c 38 * sram.Write(ram_addr, sent_data);
adamumpsimus 0:35077a3db00c 39 * printf("written at address %d data 0x%02X\n", ram_addr, sent_data);
adamumpsimus 0:35077a3db00c 40 *
adamumpsimus 0:35077a3db00c 41 * // READ A SINGLE BYTE FROM RAM
adamumpsimus 0:35077a3db00c 42 * uint8_t rec_data = sram.Read(address);
adamumpsimus 0:35077a3db00c 43 * printf("read at address %d data 0x%02X\n", address, rec_data);
adamumpsimus 0:35077a3db00c 44 * }
adamumpsimus 0:35077a3db00c 45 * @endcode
adamumpsimus 0:35077a3db00c 46 */
adamumpsimus 0:35077a3db00c 47 IP12B512::IP12B512(
adamumpsimus 0:35077a3db00c 48 PinName pin_mosi,
adamumpsimus 0:35077a3db00c 49 PinName pin_miso,
adamumpsimus 0:35077a3db00c 50 PinName pin_sclk,
adamumpsimus 0:35077a3db00c 51 PinName pin_cs
adamumpsimus 0:35077a3db00c 52 ) :
adamumpsimus 0:35077a3db00c 53 _device(pin_mosi, pin_miso, pin_sclk),
adamumpsimus 0:35077a3db00c 54 _cs(pin_cs, 1) // even with pullup resistor, this pin goes down at startup, so a HIGH value is preferred
adamumpsimus 0:35077a3db00c 55 {
adamumpsimus 0:35077a3db00c 56 // Configure Interface
adamumpsimus 0:35077a3db00c 57 _device.format(8, 0); // NOTE: different format (not 8.3)
adamumpsimus 0:35077a3db00c 58 _device.frequency(20e6); // max speed of IP12B512 SRAM is 20MHz
adamumpsimus 0:35077a3db00c 59
adamumpsimus 0:35077a3db00c 60 // Idle SPI RAM
adamumpsimus 0:35077a3db00c 61 _cs = 0;
adamumpsimus 0:35077a3db00c 62 _cs = 1;
adamumpsimus 0:35077a3db00c 63
adamumpsimus 0:35077a3db00c 64 // Configure SPI RAM
adamumpsimus 0:35077a3db00c 65 _cs = 0;
adamumpsimus 0:35077a3db00c 66 _device.write(IP12B512_WRSR); // Write to Status Register
adamumpsimus 0:35077a3db00c 67 _device.write(0x41); // Set to Virtual Chip Mode (0x40 - with HOLD, 0x41 - no HOLD)
adamumpsimus 0:35077a3db00c 68 _cs = 1;
adamumpsimus 0:35077a3db00c 69 }
adamumpsimus 0:35077a3db00c 70
adamumpsimus 0:35077a3db00c 71 /// Write SRAM in byte mode (sends the most data to SRAM prior to write)
adamumpsimus 0:35077a3db00c 72 void IP12B512::Write(uint16_t addr, uint8_t data)
adamumpsimus 0:35077a3db00c 73 {
adamumpsimus 0:35077a3db00c 74 _cs = 0;
adamumpsimus 0:35077a3db00c 75 _device.write(IP12B512_WRITE); // OpCode
adamumpsimus 0:35077a3db00c 76 _device.write(addr >> 8); // Addr
adamumpsimus 0:35077a3db00c 77 _device.write(addr); // Addr
adamumpsimus 0:35077a3db00c 78 _device.write(data); // Pump out data to RAM
adamumpsimus 0:35077a3db00c 79 _cs = 1;
adamumpsimus 0:35077a3db00c 80 }
adamumpsimus 0:35077a3db00c 81
adamumpsimus 0:35077a3db00c 82 /// Write SRAM in stream mode (sends the least data to SRAM prior to write)
adamumpsimus 0:35077a3db00c 83 void IP12B512::StreamWrite(uint16_t addr, uint8_t *data, uint32_t size)
adamumpsimus 0:35077a3db00c 84 {
adamumpsimus 0:35077a3db00c 85 uint8_t * p = data;
adamumpsimus 0:35077a3db00c 86 uint32_t i;
adamumpsimus 0:35077a3db00c 87
adamumpsimus 0:35077a3db00c 88 _cs = 0;
adamumpsimus 0:35077a3db00c 89 _device.write(IP12B512_WRITE); // OpCode
adamumpsimus 0:35077a3db00c 90 _device.write(addr >> 8); // Addr
adamumpsimus 0:35077a3db00c 91 _device.write(addr); // Addr
adamumpsimus 0:35077a3db00c 92
adamumpsimus 0:35077a3db00c 93 for (i = 0; i < size; i++) {
adamumpsimus 0:35077a3db00c 94 _device.write(*p++); // Write to SPI ram
adamumpsimus 0:35077a3db00c 95 }
adamumpsimus 0:35077a3db00c 96 _cs = 1;
adamumpsimus 0:35077a3db00c 97 }
adamumpsimus 0:35077a3db00c 98
adamumpsimus 0:35077a3db00c 99 /// Read SRAM in byte mode (sends the most data to SRAM prior to read)
adamumpsimus 0:35077a3db00c 100 uint8_t IP12B512::Read(uint16_t addr)
adamumpsimus 0:35077a3db00c 101 {
adamumpsimus 0:35077a3db00c 102 uint8_t data;
adamumpsimus 0:35077a3db00c 103
adamumpsimus 0:35077a3db00c 104 _cs = 0;
adamumpsimus 0:35077a3db00c 105 _device.write(IP12B512_READ); // OpCode
adamumpsimus 0:35077a3db00c 106 _device.write(addr >> 8); // Addr
adamumpsimus 0:35077a3db00c 107 _device.write(addr); // Addr
adamumpsimus 0:35077a3db00c 108 data = _device.write(0x00); // Clock in data from RAM (doesn't matter the value)
adamumpsimus 0:35077a3db00c 109 _cs = 1;
adamumpsimus 0:35077a3db00c 110
adamumpsimus 0:35077a3db00c 111 return data;
adamumpsimus 0:35077a3db00c 112 }
adamumpsimus 0:35077a3db00c 113
adamumpsimus 0:35077a3db00c 114 /// Read SRAM in stream mode (sends the least data to SRAM prior to read)
adamumpsimus 0:35077a3db00c 115 void IP12B512::StreamRead(uint16_t addr, uint8_t *data, uint32_t size)
adamumpsimus 0:35077a3db00c 116 {
adamumpsimus 0:35077a3db00c 117 uint8_t * p = data;
adamumpsimus 0:35077a3db00c 118 uint32_t i;
adamumpsimus 0:35077a3db00c 119
adamumpsimus 0:35077a3db00c 120 _cs = 0;
adamumpsimus 0:35077a3db00c 121 _device.write(IP12B512_READ); // OpCode
adamumpsimus 0:35077a3db00c 122 _device.write(addr >> 8); // Addr
adamumpsimus 0:35077a3db00c 123 _device.write(addr); // Addr
adamumpsimus 0:35077a3db00c 124
adamumpsimus 0:35077a3db00c 125 for (i = 0; i < size; i++) {
adamumpsimus 0:35077a3db00c 126 *p++ = _device.write(0x00); // Clock in data from RAM(doesn't matter the value)
adamumpsimus 0:35077a3db00c 127 }
adamumpsimus 0:35077a3db00c 128 _cs = 1;
adamumpsimus 0:35077a3db00c 129 }
adamumpsimus 0:35077a3db00c 130
adamumpsimus 0:35077a3db00c 131 /// Fill SRAM with data
adamumpsimus 0:35077a3db00c 132 void IP12B512::ClearAll()
adamumpsimus 0:35077a3db00c 133 {
adamumpsimus 0:35077a3db00c 134 uint32_t ram_size = GetRamSize();
adamumpsimus 0:35077a3db00c 135 uint32_t i;
adamumpsimus 0:35077a3db00c 136
adamumpsimus 0:35077a3db00c 137 _cs = 0;
adamumpsimus 0:35077a3db00c 138 _device.write(IP12B512_WRITE); // OpCode
adamumpsimus 0:35077a3db00c 139 _device.write(0x00); // Addr
adamumpsimus 0:35077a3db00c 140 _device.write(0x00); // Addr
adamumpsimus 0:35077a3db00c 141
adamumpsimus 0:35077a3db00c 142 for (i = 0; i < ram_size; i++) {
adamumpsimus 0:35077a3db00c 143 _device.write(0x00); // Write to SPI ram
adamumpsimus 0:35077a3db00c 144 }
adamumpsimus 0:35077a3db00c 145 _cs = 1;
adamumpsimus 0:35077a3db00c 146 }
adamumpsimus 0:35077a3db00c 147
adamumpsimus 0:35077a3db00c 148 /// Gets the SRAM size in bytes
adamumpsimus 0:35077a3db00c 149 uint32_t IP12B512::GetRamSize()
adamumpsimus 0:35077a3db00c 150 {
adamumpsimus 0:35077a3db00c 151 uint8_t data;
adamumpsimus 0:35077a3db00c 152
adamumpsimus 0:35077a3db00c 153 _cs = 0;
adamumpsimus 0:35077a3db00c 154 _device.write(IP12B512_RDMI); // OpCode
adamumpsimus 0:35077a3db00c 155 data = _device.write(0xFF); // Clock in data from RAM
adamumpsimus 0:35077a3db00c 156 _cs = 1;
adamumpsimus 0:35077a3db00c 157
adamumpsimus 0:35077a3db00c 158 if (data == 0b0000) return (64 * 1024) / 8; // 64Kbit = 8KByte
adamumpsimus 0:35077a3db00c 159 if (data == 0b0001) return (128 * 1024) / 8; // 128Kbit = 16KByte
adamumpsimus 0:35077a3db00c 160 if (data == 0b0010) return (256 * 1024) / 8; // 256Kbit = 32KByte
adamumpsimus 0:35077a3db00c 161 if (data == 0b0011) return (512 * 1024) / 8; // 512Kbit = 64KByte
adamumpsimus 0:35077a3db00c 162
adamumpsimus 0:35077a3db00c 163 return 0;
adamumpsimus 0:35077a3db00c 164 }