Zbigniew Druzbacki / Mbed 2 deprecated SPI_Slave

SPI slave program to enable communication between the FPGA and the STM32L432 board.

Dependencies:   mbed

DMA_SPI.h@15:791f35b0f220, 2019-05-15 (annotated)

Committer:
Zbyszek
Date:
Wed May 15 22:56:20 2019 +0000
Revision:
15:791f35b0f220
Parent:
13:c7e8e277f884 
Official Code used on the 15/05/2019

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Zbyszek 8:e87027349167 1 #ifndef _DMA_SPI_H_
Zbyszek 8:e87027349167 2 #define _DMA_SPI_H_
Zbyszek 8:e87027349167 3
Zbyszek 8:e87027349167 4 #define C2S 2
Zbyszek 8:e87027349167 5 #define C3S 3
Zbyszek 8:e87027349167 6
Zbyszek 9:9ed9dffd602a 7 #define CCR_EN 0
Zbyszek 9:9ed9dffd602a 8 #define CCR_TCIE 1
Zbyszek 9:9ed9dffd602a 9 #define CCR_HTIE 2
Zbyszek 9:9ed9dffd602a 10 #define CCR_TEIE 3
Zbyszek 9:9ed9dffd602a 11 #define CCR_DIR 4
Zbyszek 9:9ed9dffd602a 12 #define CCR_CIRC 5
Zbyszek 9:9ed9dffd602a 13 #define CCR_PINC 6
Zbyszek 9:9ed9dffd602a 14 #define CCR_MINC 7
Zbyszek 9:9ed9dffd602a 15 #define CCR_PSIZE 8
Zbyszek 9:9ed9dffd602a 16 #define CCR_MSIZE 10
Zbyszek 9:9ed9dffd602a 17 #define CCR_PL 12
Zbyszek 9:9ed9dffd602a 18 #define CCR_MEM2MEM 14
Zbyszek 9:9ed9dffd602a 19
Zbyszek 9:9ed9dffd602a 20
Zbyszek 15:791f35b0f220 21 #define SPI1_DISABLE() SPI1->CR1 &= ~SPI_CR1_SPE //Clear SPE bit in SPI1 CR1 register
Zbyszek 9:9ed9dffd602a 22 #define SPI1_ENABLE() SPI1->CR1 |= SPI_CR1_SPE
Zbyszek 9:9ed9dffd602a 23
Zbyszek 9:9ed9dffd602a 24 #define CLEAR_SPI1_CR1_CRC_BIT() SPI1->CR1 &= ~SPI_CR1_CRCEN
Zbyszek 9:9ed9dffd602a 25
Zbyszek 9:9ed9dffd602a 26 #define CLEAR_SPI1_CR1_MSTR_BIT() SPI1->CR1 &= ~SPI_CR1_MSTR
Zbyszek 9:9ed9dffd602a 27 #define SET_SPI1_CR1_MSTR_BIT() SPI1->CR1 |= SPI_CR1_MSTR
Zbyszek 9:9ed9dffd602a 28
Zbyszek 9:9ed9dffd602a 29 #define CLEAR_SPI1_CR1_BR_BITS() SPI1->CR1 &= ~SPI_CR1_BR
Zbyszek 9:9ed9dffd602a 30 #define SET_SPI1_CR1_BR_BITS() SPI1->CR1 |= (3u<<3) //Sets the frequency to 1MHz 16/16 = 1
Zbyszek 9:9ed9dffd602a 31
Zbyszek 9:9ed9dffd602a 32 #define CLEAR_SPI1_CR1_SSM_BIT() SPI1->CR1 &= ~SPI_CR1_SSM
Zbyszek 9:9ed9dffd602a 33 #define SET_SPI1_CR1_SSM_BIT() SPI1->CR1 |= SPI_CR1_SSM
Zbyszek 9:9ed9dffd602a 34
Zbyszek 9:9ed9dffd602a 35 #define CLEAR_SPI1_CR1_SSI_BIT() SPI1->CR1 &= ~SPI_CR1_SSI
Zbyszek 9:9ed9dffd602a 36 #define SET_SPI1_CR1_SSI_BIT() SPI1->CR1 |= SPI_CR1_SSI
Zbyszek 9:9ed9dffd602a 37
Zbyszek 9:9ed9dffd602a 38 #define CLEAR_SPI1_CR1_CPOL_BIT() SPI1->CR1 &= ~SPI_CR1_CPOL
Zbyszek 9:9ed9dffd602a 39 #define SET_SPI1_CR1_CPOL_BIT() SPI1->CR1 |= SPI_CR1_CPOL
Zbyszek 9:9ed9dffd602a 40
Zbyszek 9:9ed9dffd602a 41 #define CLEAR_SPI1_CR1_CPHA_BIT() SPI1->CR1 &= ~SPI_CR1_CPHA
Zbyszek 9:9ed9dffd602a 42 #define SET_SPI1_CR1_CPHA_BIT() SPI1->CR1 |= SPI_CR1_CPHA
Zbyszek 9:9ed9dffd602a 43
Zbyszek 9:9ed9dffd602a 44 #define CLEAR_SPI1_CR2_DS_BITS() SPI1->CR2 &= ~(0xF<<8)
Zbyszek 9:9ed9dffd602a 45 #define SET_SPI1_CR2_DS_BITS() SPI1->CR2 |= (0xF<<8) //Sets data frame to 16-bits
Zbyszek 9:9ed9dffd602a 46
Zbyszek 9:9ed9dffd602a 47 #define CLEAR_SPI1_CR2_RXDMAEN_BIT() SPI1->CR2 &= ~(0x01<<0)
Zbyszek 9:9ed9dffd602a 48 #define SET_SPI1_CR2_RXDMAEN_BIT() SPI1->CR2 |= (0x01<<0)
Zbyszek 9:9ed9dffd602a 49
Zbyszek 9:9ed9dffd602a 50 #define CLEAR_SPI1_CR2_TXDMAEN_BIT() SPI1->CR2 &= ~(0x01<<1)
Zbyszek 9:9ed9dffd602a 51 #define SET_SPI1_CR2_TXDMAEN_BIT() SPI1->CR2 |= (0x01<<1)
Zbyszek 9:9ed9dffd602a 52
Zbyszek 9:9ed9dffd602a 53 #define CLEAR_SPI1_CR2_RXEIE_BIT() SPI1->CR2 &= ~(0x01<<6)
Zbyszek 9:9ed9dffd602a 54 #define SET_SPI1_CR2_RXEIE_BIT() SPI1->CR2 |= (0x01<<6)
Zbyszek 9:9ed9dffd602a 55
Zbyszek 9:9ed9dffd602a 56 #define CLEAR_SPI1_CR2_TXEIE_BIT() SPI1->CR2 &= ~(0x01<<7)
Zbyszek 9:9ed9dffd602a 57 #define SET_SPI1_CR2_TXEIE_BIT() SPI1->CR2 |= (0x01<<7)
Zbyszek 9:9ed9dffd602a 58
Zbyszek 9:9ed9dffd602a 59
Zbyszek 9:9ed9dffd602a 60 #define CLEAR_DMA1_SPI1RX_CSELR_BITS() DMA1_CSELR->CSELR &= ~(0x01<<(4*(C2S - 1))) //deselect SPI1_Rx on DMA1 Channel 2
Zbyszek 9:9ed9dffd602a 61 #define SET_DMA1_SPI1RX_CSELR_BITS() DMA1_CSELR->CSELR |= (0x01<<(4*(C2S - 1))) //Select SPI1_Rx on DMA1 Channel 2
Zbyszek 9:9ed9dffd602a 62
Zbyszek 9:9ed9dffd602a 63 #define CLEAR_DMA1_SPI1TX_CSELR_BITS() DMA1_CSELR->CSELR &= ~(0x01<<(4*(C3S - 1))) //deselect SPI1_Tx on DMA1 Channel 3
Zbyszek 9:9ed9dffd602a 64 #define SET_DMA1_SPI1TX_CSELR_BITS() DMA1_CSELR->CSELR |= (0x01<<(4*(C3S - 1))) //Select SPI1_Tx on DMA1 Channel 3
Zbyszek 9:9ed9dffd602a 65
Zbyszek 9:9ed9dffd602a 66
Zbyszek 9:9ed9dffd602a 67 //--------------------------------------Channel2-----------------------------------------------------
Zbyszek 9:9ed9dffd602a 68
Zbyszek 9:9ed9dffd602a 69 #define DMA1_CH2_DISABLE() DMA1_Channel2->CCR &= ~(0x01<<CCR_EN)
Zbyszek 9:9ed9dffd602a 70 #define DMA1_CH2_ENABLE() DMA1_Channel2->CCR |= (0x01<<CCR_EN)
Zbyszek 9:9ed9dffd602a 71
Zbyszek 9:9ed9dffd602a 72 #define CLEAR_DMA1_CH2_CCR_DIR_BIT() DMA1_Channel2->CCR &= ~(0x01 << CCR_DIR)
Zbyszek 9:9ed9dffd602a 73 #define SET_DMA1_CH2_CCR_DIR_BIT() DMA1_Channel2->CCR |= (0x01 << CCR_DIR)
Zbyszek 9:9ed9dffd602a 74
Zbyszek 9:9ed9dffd602a 75 #define CLEAR_DMA1_CH2_CCR_PSIZE_BITS() DMA1_Channel2->CCR &= ~(0x01 << CCR_PSIZE)
Zbyszek 9:9ed9dffd602a 76 #define SET_DMA1_CH2_CCR_PSIZE_BITS() DMA1_Channel2->CCR |= (0x01 << CCR_PSIZE) //Set peripheral size to 16-bits
Zbyszek 9:9ed9dffd602a 77
Zbyszek 9:9ed9dffd602a 78 #define CLEAR_DMA1_CH2_CCR_MSIZE_BITS() DMA1_Channel2->CCR &= ~(0x01 << CCR_MSIZE)
Zbyszek 9:9ed9dffd602a 79 #define SET_DMA1_CH2_CCR_MSIZE_BITS() DMA1_Channel2->CCR |= (0x01 << CCR_MSIZE) //Set peripheral size to 16-bits
Zbyszek 9:9ed9dffd602a 80
Zbyszek 9:9ed9dffd602a 81 #define CLEAR_DMA1_CH2_CCR_MINC_BIT() DMA1_Channel2->CCR &= ~(0x01 << CCR_MINC)
Zbyszek 9:9ed9dffd602a 82 #define SET_DMA1_CH2_CCR_MINC_BIT() DMA1_Channel2->CCR |= (0x01 << CCR_MINC)
Zbyszek 9:9ed9dffd602a 83
Zbyszek 9:9ed9dffd602a 84 #define CLEAR_DMA1_CH2_CCR_PINC_BIT() DMA1_Channel2->CCR &= ~(0x01 << CCR_PINC)
Zbyszek 9:9ed9dffd602a 85 #define SET_DMA1_CH2_CCR_PINC_BIT() DMA1_Channel2->CCR |= (0x01 << CCR_PINC)
Zbyszek 9:9ed9dffd602a 86
Zbyszek 9:9ed9dffd602a 87 #define CLEAR_DMA1_CH2_CCR_TCIE_BIT() DMA1_Channel2->CCR &= ~(0x01 << CCR_TCIE)
Zbyszek 9:9ed9dffd602a 88 #define SET_DMA1_CH2_CCR_TCIE_BIT() DMA1_Channel2->CCR |= (0x01 << CCR_TCIE)
Zbyszek 9:9ed9dffd602a 89
Zbyszek 9:9ed9dffd602a 90 #define CLEAR_DMA1_CH2_CCR_CIRC_BIT() DMA1_Channel2->CCR &= ~(0x01 << CCR_CIRC)
Zbyszek 9:9ed9dffd602a 91 #define SET_DMA1_CH2_CCR_CIRC_BIT() DMA1_Channel2->CCR |= (0x01 << CCR_CIRC)
Zbyszek 9:9ed9dffd602a 92
Zbyszek 9:9ed9dffd602a 93 #define CLEAR_DMA1_CH2_CCR_MEM2MEM_BIT() DMA1_Channel2->CCR &= ~(0x01 << CCR_CIRC)
Zbyszek 9:9ed9dffd602a 94 #define SET_DMA1_CH2_CCR_MEM2MEM_BIT() DMA1_Channel2->CCR |= (0x01 << CCR_CIRC)
Zbyszek 9:9ed9dffd602a 95
Zbyszek 9:9ed9dffd602a 96 #define CLEAR_DMA1_CH2_CCR_PL_BITS() DMA1_Channel2->CCR &= ~(0x03 << CCR_PL)
Zbyszek 9:9ed9dffd602a 97 #define SET_DMA1_CH2_CCR_PL_BITS() DMA1_Channel2->CCR |= (0x03 << CCR_PL) //Set to highest priority level
Zbyszek 9:9ed9dffd602a 98
Zbyszek 9:9ed9dffd602a 99 #define CLEAR_DMA1_CH2_CCR_TEIE_BIT() DMA1_Channel2->CCR &= ~(0x01<< CCR_TEIE)
Zbyszek 9:9ed9dffd602a 100 #define SET_DMA1_CH2_CCR_TEIE_BIT() DMA1_Channel2->CCR |= (0x01<< CCR_TEIE)
Zbyszek 9:9ed9dffd602a 101
Zbyszek 9:9ed9dffd602a 102 #define CLEAR_DMA1_CH2_CNDTR_BITS() DMA1_Channel2->CNDTR = 0
Zbyszek 9:9ed9dffd602a 103 #define CLEAR_DMA1_CH2_CPAR_BITS() DMA1_Channel2->CPAR = 0
Zbyszek 9:9ed9dffd602a 104 #define CLEAR_DMA1_CH2_CMAR_BITS() DMA1_Channel2->CMAR = 0
Zbyszek 9:9ed9dffd602a 105
Zbyszek 9:9ed9dffd602a 106 #define CLEAR_DMA1_CH2_IFCR_GFLAG() DMA1->IFCR |= (1u << (4*(C2S - 1)))
Zbyszek 9:9ed9dffd602a 107
Zbyszek 9:9ed9dffd602a 108 //--------------------------------------Channel3-----------------------------------------------------
Zbyszek 9:9ed9dffd602a 109
Zbyszek 9:9ed9dffd602a 110 #define DMA1_CH3_DISABLE() DMA1_Channel3->CCR &= ~(0x01<<CCR_EN)
Zbyszek 9:9ed9dffd602a 111 #define DMA1_CH3_ENABLE() DMA1_Channel3->CCR |= (0x01<<CCR_EN)
Zbyszek 9:9ed9dffd602a 112
Zbyszek 9:9ed9dffd602a 113 #define CLEAR_DMA1_CH3_CCR_DIR_BIT() DMA1_Channel3->CCR &= ~(0x01 << CCR_DIR)
Zbyszek 9:9ed9dffd602a 114 #define SET_DMA1_CH3_CCR_DIR_BIT() DMA1_Channel3->CCR |= (0x01 << CCR_DIR)
Zbyszek 9:9ed9dffd602a 115
Zbyszek 9:9ed9dffd602a 116 #define CLEAR_DMA1_CH3_CCR_PSIZE_BITS() DMA1_Channel3->CCR &= ~(0x01 << CCR_PSIZE)
Zbyszek 9:9ed9dffd602a 117 #define SET_DMA1_CH3_CCR_PSIZE_BITS() DMA1_Channel3->CCR |= (0x01 << CCR_PSIZE) //Set peripheral size to 16-bits
Zbyszek 9:9ed9dffd602a 118
Zbyszek 9:9ed9dffd602a 119 #define CLEAR_DMA1_CH3_CCR_MSIZE_BITS() DMA1_Channel3->CCR &= ~(0x01 << CCR_MSIZE)
Zbyszek 9:9ed9dffd602a 120 #define SET_DMA1_CH3_CCR_MSIZE_BITS() DMA1_Channel3->CCR |= (0x01 << CCR_MSIZE) //Set peripheral size to 16-bits
Zbyszek 9:9ed9dffd602a 121
Zbyszek 9:9ed9dffd602a 122 #define CLEAR_DMA1_CH3_CCR_MINC_BIT() DMA1_Channel3->CCR &= ~(0x01 << CCR_MINC)
Zbyszek 9:9ed9dffd602a 123 #define SET_DMA1_CH3_CCR_MINC_BIT() DMA1_Channel3->CCR |= (0x01 << CCR_MINC)
Zbyszek 9:9ed9dffd602a 124
Zbyszek 9:9ed9dffd602a 125 #define CLEAR_DMA1_CH3_CCR_PINC_BIT() DMA1_Channel3->CCR &= ~(0x01 << CCR_PINC)
Zbyszek 9:9ed9dffd602a 126 #define SET_DMA1_CH3_CCR_PINC_BIT() DMA1_Channel3->CCR |= (0x01 << CCR_PINC)
Zbyszek 9:9ed9dffd602a 127
Zbyszek 9:9ed9dffd602a 128 #define CLEAR_DMA1_CH3_CCR_TCIE_BIT() DMA1_Channel3->CCR &= ~(0x01 << CCR_TCIE)
Zbyszek 9:9ed9dffd602a 129 #define SET_DMA1_CH3_CCR_TCIE_BIT() DMA1_Channel3->CCR |= (0x01 << CCR_TCIE)
Zbyszek 9:9ed9dffd602a 130
Zbyszek 9:9ed9dffd602a 131 #define CLEAR_DMA1_CH3_CCR_CIRC_BIT() DMA1_Channel3->CCR &= ~(0x01 << CCR_CIRC)
Zbyszek 9:9ed9dffd602a 132 #define SET_DMA1_CH3_CCR_CIRC_BIT() DMA1_Channel3->CCR |= (0x01 << CCR_CIRC)
Zbyszek 9:9ed9dffd602a 133
Zbyszek 9:9ed9dffd602a 134 #define CLEAR_DMA1_CH3_CCR_MEM2MEM_BIT() DMA1_Channel3->CCR &= ~(0x01 << CCR_CIRC)
Zbyszek 9:9ed9dffd602a 135 #define SET_DMA1_CH3_CCR_MEM2MEM_BIT() DMA1_Channel3->CCR |= (0x01 << CCR_CIRC)
Zbyszek 9:9ed9dffd602a 136
Zbyszek 9:9ed9dffd602a 137 #define CLEAR_DMA1_CH3_CCR_PL_BITS() DMA1_Channel3->CCR &= ~(0x03 << CCR_PL)
Zbyszek 9:9ed9dffd602a 138 #define SET_DMA1_CH3_CCR_PL_BITS() DMA1_Channel3->CCR |= (0x03 << CCR_PL) //Set to highest priority level
Zbyszek 9:9ed9dffd602a 139
Zbyszek 9:9ed9dffd602a 140 #define CLEAR_DMA1_CH3_CCR_TEIE_BIT() DMA1_Channel3->CCR &= ~(0x01<< CCR_TEIE)
Zbyszek 9:9ed9dffd602a 141 #define SET_DMA1_CH3_CCR_TEIE_BIT() DMA1_Channel3->CCR |= (0x01<< CCR_TEIE)
Zbyszek 9:9ed9dffd602a 142
Zbyszek 9:9ed9dffd602a 143 #define CLEAR_DMA1_CH3_CNDTR_BITS() DMA1_Channel3->CNDTR = 0
Zbyszek 9:9ed9dffd602a 144 #define CLEAR_DMA1_CH3_CPAR_BITS() DMA1_Channel3->CPAR = 0
Zbyszek 9:9ed9dffd602a 145 #define CLEAR_DMA1_CH3_CMAR_BITS() DMA1_Channel3->CMAR = 0
Zbyszek 9:9ed9dffd602a 146
Zbyszek 9:9ed9dffd602a 147 #define CLEAR_DMA1_CH3_IFCR_GFLAG() DMA1->IFCR |= (1u << (4*(C3S - 1)))
Zbyszek 9:9ed9dffd602a 148
Zbyszek 9:9ed9dffd602a 149
Zbyszek 13:c7e8e277f884 150 #define SCK_slave 1
Zbyszek 9:9ed9dffd602a 151 #define MISO_slave 6
Zbyszek 11:366f1186c121 152 #define MOSI_slave 7
Zbyszek 9:9ed9dffd602a 153
Zbyszek 9:9ed9dffd602a 154 #define clr_CS() GPIOA->BSRR=(1u<<(CS_slave+16))
Zbyszek 9:9ed9dffd602a 155 #define set_CS() GPIOA->BSRR=(1u<<CS_slave)
Zbyszek 9:9ed9dffd602a 156
Zbyszek 9:9ed9dffd602a 157
Zbyszek 8:e87027349167 158 #include <stm32l4xx.h>
Zbyszek 8:e87027349167 159 void initDMA();
Zbyszek 9:9ed9dffd602a 160 extern int16_t data_to_transmit[12];
Zbyszek 9:9ed9dffd602a 161 extern int16_t received_data[12];
Zbyszek 13:c7e8e277f884 162 extern int16_t IMU_Data_Array[12];
Zbyszek 11:366f1186c121 163 extern int16_t SampleFIFO[10][12];
Zbyszek 11:366f1186c121 164
Zbyszek 11:366f1186c121 165 extern int pointerOS;
Zbyszek 11:366f1186c121 166 extern int pointerNS;
Zbyszek 11:366f1186c121 167 extern int pointerFS;
Zbyszek 11:366f1186c121 168
Zbyszek 11:366f1186c121 169 extern char newDataFlag;
Zbyszek 13:c7e8e277f884 170 volatile extern char dataRequestFlag;
Zbyszek 13:c7e8e277f884 171 volatile extern char dataLoadedFlag;
Zbyszek 11:366f1186c121 172
Zbyszek 9:9ed9dffd602a 173 void SPI_DMA_init();
Zbyszek 9:9ed9dffd602a 174 void SPI_DMA_SLAVE_init();
Zbyszek 9:9ed9dffd602a 175 void SPI_DMA_SLAVE_deinit();
Zbyszek 9:9ed9dffd602a 176 void deinitDMA();
Zbyszek 9:9ed9dffd602a 177 void startCommunication();
Zbyszek 8:e87027349167 178
Zbyszek 8:e87027349167 179 #endif