Zbigniew Druzbacki / Mbed 2 deprecated SPI_Slave

SPI slave program to enable communication between the FPGA and the STM32L432 board.

Dependencies:   mbed

SPI.cpp@11:366f1186c121, 2019-03-19 (annotated)

Committer:
Zbyszek
Date:
Tue Mar 19 01:26:11 2019 +0000
Revision:
11:366f1186c121
Parent:
9:9ed9dffd602a 
Several IMUs can now be read using STM32L432.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Zbyszek 0:8e367d6d8f03 1 #include "SPI.h"
Zbyszek 0:8e367d6d8f03 2 #include "mbed.h"
Zbyszek 0:8e367d6d8f03 3
Zbyszek 0:8e367d6d8f03 4 /*
Zbyszek 0:8e367d6d8f03 5 This SPI slave is written for the STM32L432 board as it has different pin layout to the
Zbyszek 0:8e367d6d8f03 6 STM32F429.
Zbyszek 0:8e367d6d8f03 7 */
Zbyszek 0:8e367d6d8f03 8
Zbyszek 0:8e367d6d8f03 9 int transfer_spi_slave(unsigned short send_val)
Zbyszek 0:8e367d6d8f03 10 {
Zbyszek 0:8e367d6d8f03 11 int16_t rx_data = 0;
Zbyszek 0:8e367d6d8f03 12
Zbyszek 0:8e367d6d8f03 13 SPI1->DR=send_val; //Send data
Zbyszek 0:8e367d6d8f03 14 while((SPI1->SR&0x01) != 1 && (SPI1->SR&0x02) != 1); //wait while BSY bit set and TXE bit sets, when BSY bit clears spi bus is no longer busy, when data is transmitted TXE bit sets
Zbyszek 0:8e367d6d8f03 15 rx_data = SPI1->DR; //Save the read data to rx_data
Zbyszek 0:8e367d6d8f03 16
Zbyszek 0:8e367d6d8f03 17 return rx_data;
Zbyszek 0:8e367d6d8f03 18 }
Zbyszek 0:8e367d6d8f03 19
Zbyszek 0:8e367d6d8f03 20
Zbyszek 0:8e367d6d8f03 21 void init_spi_slave(void)
Zbyszek 0:8e367d6d8f03 22 {
Zbyszek 0:8e367d6d8f03 23
Zbyszek 0:8e367d6d8f03 24 RCC->APB2ENR|=RCC_APB2ENR_SPI1EN;
Zbyszek 0:8e367d6d8f03 25 //CONFIG GPIOS
Zbyszek 0:8e367d6d8f03 26 GPIOA->MODER&=~((3u<<(2*CS_slave))); //clear GPIOA pin mode (in input mode when reset)
Zbyszek 0:8e367d6d8f03 27
Zbyszek 1:6766e7f4f12f 28 GPIOA->MODER&=~( //clear GPIOB
Zbyszek 0:8e367d6d8f03 29 (3u<<(2*SCK_slave))
Zbyszek 0:8e367d6d8f03 30 |(3u<<(2*MISO_slave))
Zbyszek 0:8e367d6d8f03 31 |(3u<<(2*MOSI_slave))
Zbyszek 0:8e367d6d8f03 32 // |(3u<<(2*CS_pin))
Zbyszek 0:8e367d6d8f03 33 |0x03
Zbyszek 0:8e367d6d8f03 34 );
Zbyszek 1:6766e7f4f12f 35 GPIOA->MODER|=( //reset GPIOA pins
Zbyszek 0:8e367d6d8f03 36 (2u<<(2*SCK_slave))
Zbyszek 0:8e367d6d8f03 37 |(2u<<(2*MISO_slave))
Zbyszek 0:8e367d6d8f03 38 |(2u<<(2*MOSI_slave))
Zbyszek 0:8e367d6d8f03 39 // |(3u<<(2*CS_pin))
Zbyszek 0:8e367d6d8f03 40 |0x01
Zbyszek 0:8e367d6d8f03 41 );
Zbyszek 0:8e367d6d8f03 42 GPIOA->AFR[0]&=~( //clear alternate function selector bits
Zbyszek 0:8e367d6d8f03 43 (0x0f<<(4*SCK_slave))
Zbyszek 0:8e367d6d8f03 44 |(0x0f<<(4*MISO_slave))
Zbyszek 0:8e367d6d8f03 45 |(15u<<(4*MOSI_slave))
Zbyszek 0:8e367d6d8f03 46 // |(0x0f<<(4*CS_pin))
Zbyszek 0:8e367d6d8f03 47 );
Zbyszek 0:8e367d6d8f03 48 GPIOA->AFR[0]|=( //reset alternate function selector bits to SPI1
Zbyszek 0:8e367d6d8f03 49 (5u<<(4*SCK_slave))
Zbyszek 0:8e367d6d8f03 50 |(5u<<(4*MISO_slave))
Zbyszek 0:8e367d6d8f03 51 |(5u<<(4*MOSI_slave))
Zbyszek 0:8e367d6d8f03 52 // |(5u<<(4*CS_pin))
Zbyszek 0:8e367d6d8f03 53 );
Zbyszek 0:8e367d6d8f03 54
Zbyszek 9:9ed9dffd602a 55 //set_CS();
Zbyszek 0:8e367d6d8f03 56
Zbyszek 11:366f1186c121 57 CLEAR_SPI1_CR2_RXDMAEN_BIT();
Zbyszek 11:366f1186c121 58 CLEAR_SPI1_CR2_TXDMAEN_BIT();
Zbyszek 11:366f1186c121 59 DMA1_CH2_DISABLE();
Zbyszek 11:366f1186c121 60 DMA1_CH3_DISABLE();
Zbyszek 0:8e367d6d8f03 61
Zbyszek 0:8e367d6d8f03 62 //CONFIG SPI MODULE
Zbyszek 0:8e367d6d8f03 63 RCC->APB2ENR|=RCC_APB2ENR_SPI1EN;
Zbyszek 0:8e367d6d8f03 64 SPI1->CR1&=~( //module disabled, clear bad rate bits
Zbyszek 0:8e367d6d8f03 65 SPI_CR1_SPE //SPE has to be disabled so that the SPI can be set to 16-bit mode
Zbyszek 0:8e367d6d8f03 66 |SPI_CR1_MSTR //Bit cleared to put the board into slave mode.
Zbyszek 0:8e367d6d8f03 67 |SPI_CR1_BR
Zbyszek 0:8e367d6d8f03 68 |SPI_CR1_SSM
Zbyszek 0:8e367d6d8f03 69 // |SPI_CR1_CPOL //Set clock polirty to 0
Zbyszek 0:8e367d6d8f03 70 // |SPI_CR1_CPHA //Set clock phase to 0
Zbyszek 0:8e367d6d8f03 71 );
Zbyszek 0:8e367d6d8f03 72
Zbyszek 0:8e367d6d8f03 73 SPI1->CR2 |=(0xF<<8); //Set the data frame to 16 bits STM32L432 only.
Zbyszek 0:8e367d6d8f03 74
Zbyszek 0:8e367d6d8f03 75 SPI1->CR1|=(
Zbyszek 0:8e367d6d8f03 76 SPI_CR1_SSI //set internal slave select
Zbyszek 0:8e367d6d8f03 77 //|SPI_CR1_SSM //SS control set
Zbyszek 0:8e367d6d8f03 78 //|SPI_CR1_MSTR //master mode
Zbyszek 0:8e367d6d8f03 79 |(3u<<3) //baud rate bits set /16 giving 1MHz SCK frequency
Zbyszek 0:8e367d6d8f03 80 |SPI_CR1_CPOL //Set clock polirty to 1
Zbyszek 0:8e367d6d8f03 81 |SPI_CR1_CPHA //Set clock phase to 1
Zbyszek 0:8e367d6d8f03 82 |SPI_CR1_SPE //SPI module enabled
Zbyszek 0:8e367d6d8f03 83 );
Zbyszek 1:6766e7f4f12f 84
Zbyszek 0:8e367d6d8f03 85 }
Zbyszek 0:8e367d6d8f03 86
Zbyszek 0:8e367d6d8f03 87 void init_spi_ports(void) {
Zbyszek 0:8e367d6d8f03 88 //Enable GPIOA clock on which the SPI1 pins are located
Zbyszek 0:8e367d6d8f03 89 RCC->AHB2ENR|= (RCC_AHB2ENR_GPIOAEN); //GPIO A clock enable
Zbyszek 0:8e367d6d8f03 90 init_spi_slave(); //Initialise SPI slave
Zbyszek 0:8e367d6d8f03 91 }
Zbyszek 0:8e367d6d8f03 92
Zbyszek 0:8e367d6d8f03 93 void init_spi1(void)
Zbyszek 0:8e367d6d8f03 94 {
Zbyszek 0:8e367d6d8f03 95 init_spi_ports();
Zbyszek 0:8e367d6d8f03 96
Zbyszek 0:8e367d6d8f03 97 }