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nrf52.h

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00001 
00002 /****************************************************************************************************//**
00003  * @file     nrf52.h
00004  *
00005  * @brief    CMSIS Cortex-M4 Peripheral Access Layer Header File for
00006  *           nrf52 from Nordic Semiconductor.
00007  *
00008  * @version  V1
00009  * @date     23. February 2016
00010  *
00011  * @note     Generated with SVDConv V2.81d 
00012  *           from CMSIS SVD File 'nrf52.svd' Version 1,
00013  *
00014  * @par      Copyright (c) 2015, Nordic Semiconductor ASA
00015  *           All rights reserved.
00016  *           
00017  *           Redistribution and use in source and binary forms, with or without
00018  *           modification, are permitted provided that the following conditions are met:
00019  *           
00020  *           * Redistributions of source code must retain the above copyright notice, this
00021  *           list of conditions and the following disclaimer.
00022  *           
00023  *           * Redistributions in binary form must reproduce the above copyright notice,
00024  *           this list of conditions and the following disclaimer in the documentation
00025  *           and/or other materials provided with the distribution.
00026  *           
00027  *           * Neither the name of Nordic Semiconductor ASA nor the names of its
00028  *           contributors may be used to endorse or promote products derived from
00029  *           this software without specific prior written permission.
00030  *           
00031  *           THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00032  *           AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00033  *           IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00034  *           DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00035  *           FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00036  *           DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00037  *           SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00038  *           CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00039  *           OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00040  *           OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00041  *           
00042  *
00043  *******************************************************************************************************/
00044 
00045 
00046 
00047 /** @addtogroup Nordic Semiconductor
00048   * @{
00049   */
00050 
00051 /** @addtogroup nrf52
00052   * @{
00053   */
00054 
00055 #ifndef NRF52_H
00056 #define NRF52_H
00057 
00058 #ifdef __cplusplus
00059 extern "C" {
00060 #endif
00061 
00062 
00063 /* -------------------------  Interrupt Number Definition  ------------------------ */
00064 
00065 typedef enum {
00066 /* -------------------  Cortex-M4 Processor Exceptions Numbers  ------------------- */
00067   Reset_IRQn                     = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */
00068   NonMaskableInt_IRQn            = -14,              /*!<   2  Non maskable Interrupt, cannot be stopped or preempted           */
00069   HardFault_IRQn                 = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */
00070   MemoryManagement_IRQn          = -12,              /*!<   4  Memory Management, MPU mismatch, including Access Violation
00071                                                          and No Match                                                          */
00072   BusFault_IRQn                  = -11,              /*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
00073                                                          related Fault                                                         */
00074   UsageFault_IRQn                = -10,              /*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition    */
00075   SVCall_IRQn                    =  -5,              /*!<  11  System Service Call via SVC instruction                          */
00076   DebugMonitor_IRQn              =  -4,              /*!<  12  Debug Monitor                                                    */
00077   PendSV_IRQn                    =  -2,              /*!<  14  Pendable request for system service                              */
00078   SysTick_IRQn                   =  -1,              /*!<  15  System Tick Timer                                                */
00079 /* ----------------------  nrf52 Specific Interrupt Numbers  ---------------------- */
00080   POWER_CLOCK_IRQn               =   0,              /*!<   0  POWER_CLOCK                                                      */
00081   RADIO_IRQn                     =   1,              /*!<   1  RADIO                                                            */
00082   UARTE0_UART0_IRQn              =   2,              /*!<   2  UARTE0_UART0                                                     */
00083   SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn =   3,      /*!<   3  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0                                */
00084   SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn =   4,      /*!<   4  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1                                */
00085   NFCT_IRQn                      =   5,              /*!<   5  NFCT                                                             */
00086   GPIOTE_IRQn                    =   6,              /*!<   6  GPIOTE                                                           */
00087   SAADC_IRQn                     =   7,              /*!<   7  SAADC                                                            */
00088   TIMER0_IRQn                    =   8,              /*!<   8  TIMER0                                                           */
00089   TIMER1_IRQn                    =   9,              /*!<   9  TIMER1                                                           */
00090   TIMER2_IRQn                    =  10,              /*!<  10  TIMER2                                                           */
00091   RTC0_IRQn                      =  11,              /*!<  11  RTC0                                                             */
00092   TEMP_IRQn                      =  12,              /*!<  12  TEMP                                                             */
00093   RNG_IRQn                       =  13,              /*!<  13  RNG                                                              */
00094   ECB_IRQn                       =  14,              /*!<  14  ECB                                                              */
00095   CCM_AAR_IRQn                   =  15,              /*!<  15  CCM_AAR                                                          */
00096   WDT_IRQn                       =  16,              /*!<  16  WDT                                                              */
00097   RTC1_IRQn                      =  17,              /*!<  17  RTC1                                                             */
00098   QDEC_IRQn                      =  18,              /*!<  18  QDEC                                                             */
00099   COMP_LPCOMP_IRQn               =  19,              /*!<  19  COMP_LPCOMP                                                      */
00100   SWI0_EGU0_IRQn                 =  20,              /*!<  20  SWI0_EGU0                                                        */
00101   SWI1_EGU1_IRQn                 =  21,              /*!<  21  SWI1_EGU1                                                        */
00102   SWI2_EGU2_IRQn                 =  22,              /*!<  22  SWI2_EGU2                                                        */
00103   SWI3_EGU3_IRQn                 =  23,              /*!<  23  SWI3_EGU3                                                        */
00104   SWI4_EGU4_IRQn                 =  24,              /*!<  24  SWI4_EGU4                                                        */
00105   SWI5_EGU5_IRQn                 =  25,              /*!<  25  SWI5_EGU5                                                        */
00106   TIMER3_IRQn                    =  26,              /*!<  26  TIMER3                                                           */
00107   TIMER4_IRQn                    =  27,              /*!<  27  TIMER4                                                           */
00108   PWM0_IRQn                      =  28,              /*!<  28  PWM0                                                             */
00109   PDM_IRQn                       =  29,              /*!<  29  PDM                                                              */
00110   MWU_IRQn                       =  32,              /*!<  32  MWU                                                              */
00111   PWM1_IRQn                      =  33,              /*!<  33  PWM1                                                             */
00112   PWM2_IRQn                      =  34,              /*!<  34  PWM2                                                             */
00113   SPIM2_SPIS2_SPI2_IRQn          =  35,              /*!<  35  SPIM2_SPIS2_SPI2                                                 */
00114   RTC2_IRQn                      =  36,              /*!<  36  RTC2                                                             */
00115   I2S_IRQn                       =  37,              /*!<  37  I2S                                                              */
00116   FPU_IRQn                       =  38               /*!<  38  FPU                                                              */
00117 } IRQn_Type ;
00118 
00119 
00120 /** @addtogroup Configuration_of_CMSIS
00121   * @{
00122   */
00123 
00124 
00125 /* ================================================================================ */
00126 /* ================      Processor and Core Peripheral Section     ================ */
00127 /* ================================================================================ */
00128 
00129 /* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */
00130 #define __CM4_REV                 0x0001            /*!< Cortex-M4 Core Revision                                               */
00131 #define __MPU_PRESENT                  1            /*!< MPU present or not                                                    */
00132 #define __NVIC_PRIO_BITS               3            /*!< Number of Bits used for Priority Levels                               */
00133 #define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */
00134 #define __FPU_PRESENT                  1            /*!< FPU present or not                                                    */
00135 /** @} */ /* End of group Configuration_of_CMSIS */
00136 
00137 #include "core_cm4.h"                               /*!< Cortex-M4 processor and core peripherals                              */
00138 #include "system_nrf52.h"                           /*!< nrf52 System                                                          */
00139 
00140 
00141 /* ================================================================================ */
00142 /* ================       Device Specific Peripheral Section       ================ */
00143 /* ================================================================================ */
00144 
00145 
00146 /** @addtogroup Device_Peripheral_Registers
00147   * @{
00148   */
00149 
00150 
00151 /* -------------------  Start of section using anonymous unions  ------------------ */
00152 #if defined(__CC_ARM)
00153   #pragma push
00154   #pragma anon_unions
00155 #elif defined(__ICCARM__)
00156   #pragma language=extended
00157 #elif defined(__GNUC__)
00158   /* anonymous unions are enabled by default */
00159 #elif defined(__TMS470__)
00160 /* anonymous unions are enabled by default */
00161 #elif defined(__TASKING__)
00162   #pragma warning 586
00163 #else
00164   #warning Not supported compiler type
00165 #endif
00166 
00167 
00168 typedef struct {
00169   __I  uint32_t  PART;                              /*!< Part code                                                             */
00170   __I  uint32_t  VARIANT;                           /*!< Part Variant, Hardware version and Production configuration           */
00171   __I  uint32_t  PACKAGE;                           /*!< Package option                                                        */
00172   __I  uint32_t  RAM;                               /*!< RAM variant                                                           */
00173   __I  uint32_t  FLASH;                             /*!< Flash variant                                                         */
00174   __IO uint32_t  UNUSED0[3];                        /*!< Description collection[0]: Unspecified                                */
00175 } FICR_INFO_Type;
00176 
00177 typedef struct {
00178   __I  uint32_t  A0;                                /*!< Slope definition A0.                                                  */
00179   __I  uint32_t  A1;                                /*!< Slope definition A1.                                                  */
00180   __I  uint32_t  A2;                                /*!< Slope definition A2.                                                  */
00181   __I  uint32_t  A3;                                /*!< Slope definition A3.                                                  */
00182   __I  uint32_t  A4;                                /*!< Slope definition A4.                                                  */
00183   __I  uint32_t  A5;                                /*!< Slope definition A5.                                                  */
00184   __I  uint32_t  B0;                                /*!< y-intercept B0.                                                       */
00185   __I  uint32_t  B1;                                /*!< y-intercept B1.                                                       */
00186   __I  uint32_t  B2;                                /*!< y-intercept B2.                                                       */
00187   __I  uint32_t  B3;                                /*!< y-intercept B3.                                                       */
00188   __I  uint32_t  B4;                                /*!< y-intercept B4.                                                       */
00189   __I  uint32_t  B5;                                /*!< y-intercept B5.                                                       */
00190   __I  uint32_t  T0;                                /*!< Segment end T0.                                                       */
00191   __I  uint32_t  T1;                                /*!< Segment end T1.                                                       */
00192   __I  uint32_t  T2;                                /*!< Segment end T2.                                                       */
00193   __I  uint32_t  T3;                                /*!< Segment end T3.                                                       */
00194   __I  uint32_t  T4;                                /*!< Segment end T4.                                                       */
00195 } FICR_TEMP_Type;
00196 
00197 typedef struct {
00198   __I  uint32_t  TAGHEADER0;                        /*!< Default header for NFC Tag. Software can read these values to
00199                                                          populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
00200   __I  uint32_t  TAGHEADER1;                        /*!< Default header for NFC Tag. Software can read these values to
00201                                                          populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
00202   __I  uint32_t  TAGHEADER2;                        /*!< Default header for NFC Tag. Software can read these values to
00203                                                          populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
00204   __I  uint32_t  TAGHEADER3;                        /*!< Default header for NFC Tag. Software can read these values to
00205                                                          populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
00206 } FICR_NFC_Type;
00207 
00208 typedef struct {
00209   __IO uint32_t  POWER;                             /*!< Description cluster[0]: RAM0 power control register                   */
00210   __O  uint32_t  POWERSET;                          /*!< Description cluster[0]: RAM0 power control set register               */
00211   __O  uint32_t  POWERCLR;                          /*!< Description cluster[0]: RAM0 power control clear register             */
00212   __I  uint32_t  RESERVED0;
00213 } POWER_RAM_Type;
00214 
00215 typedef struct {
00216   __IO uint32_t  CPU0;                              /*!< AHB bus master priority register for CPU0                             */
00217   __IO uint32_t  SPIS1;                             /*!< AHB bus master priority register for SPIM1, SPIS1, TWIM1 and
00218                                                          TWIS1                                                                 */
00219   __IO uint32_t  RADIO;                             /*!< AHB bus master priority register for RADIO                            */
00220   __IO uint32_t  ECB;                               /*!< AHB bus master priority register for ECB                              */
00221   __IO uint32_t  CCM;                               /*!< AHB bus master priority register for CCM                              */
00222   __IO uint32_t  AAR;                               /*!< AHB bus master priority register for AAR                              */
00223   __IO uint32_t  SAADC;                             /*!< AHB bus master priority register for SAADC                            */
00224   __IO uint32_t  UARTE;                             /*!< AHB bus master priority register for UARTE                            */
00225   __IO uint32_t  SERIAL0;                           /*!< AHB bus master priority register for SPIM0, SPIS0, TWIM0 and
00226                                                          TWIS0                                                                 */
00227   __IO uint32_t  SERIAL2;                           /*!< AHB bus master priority register for SPIM2 and SPIS2                  */
00228   __IO uint32_t  NFCT;                              /*!< AHB bus master priority register for NFCT                             */
00229   __IO uint32_t  I2S;                               /*!< AHB bus master priority register for I2S                              */
00230   __IO uint32_t  PDM;                               /*!< AHB bus master priority register for PDM                              */
00231   __IO uint32_t  PWM;                               /*!< AHB bus master priority register for PWM0, PWM1 and PWM2              */
00232 } AMLI_RAMPRI_Type;
00233 
00234 typedef struct {
00235   __IO uint32_t  RTS;                               /*!< Pin select for RTS signal                                             */
00236   __IO uint32_t  TXD;                               /*!< Pin select for TXD signal                                             */
00237   __IO uint32_t  CTS;                               /*!< Pin select for CTS signal                                             */
00238   __IO uint32_t  RXD;                               /*!< Pin select for RXD signal                                             */
00239 } UARTE_PSEL_Type;
00240 
00241 typedef struct {
00242   __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
00243   __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
00244   __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
00245 } UARTE_RXD_Type;
00246 
00247 typedef struct {
00248   __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
00249   __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
00250   __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
00251 } UARTE_TXD_Type;
00252 
00253 typedef struct {
00254   __IO uint32_t  SCK;                               /*!< Pin select for SCK                                                    */
00255   __IO uint32_t  MOSI;                              /*!< Pin select for MOSI signal                                            */
00256   __IO uint32_t  MISO;                              /*!< Pin select for MISO signal                                            */
00257 } SPIM_PSEL_Type;
00258 
00259 typedef struct {
00260   __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
00261   __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
00262   __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
00263   __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
00264 } SPIM_RXD_Type;
00265 
00266 typedef struct {
00267   __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
00268   __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
00269   __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
00270   __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
00271 } SPIM_TXD_Type;
00272 
00273 typedef struct {
00274   __IO uint32_t  SCK;                               /*!< Pin select for SCK                                                    */
00275   __IO uint32_t  MISO;                              /*!< Pin select for MISO signal                                            */
00276   __IO uint32_t  MOSI;                              /*!< Pin select for MOSI signal                                            */
00277   __IO uint32_t  CSN;                               /*!< Pin select for CSN signal                                             */
00278 } SPIS_PSEL_Type;
00279 
00280 typedef struct {
00281   __IO uint32_t  PTR;                               /*!< RXD data pointer                                                      */
00282   __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
00283   __I  uint32_t  AMOUNT;                            /*!< Number of bytes received in last granted transaction                  */
00284 } SPIS_RXD_Type;
00285 
00286 typedef struct {
00287   __IO uint32_t  PTR;                               /*!< TXD data pointer                                                      */
00288   __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
00289   __I  uint32_t  AMOUNT;                            /*!< Number of bytes transmitted in last granted transaction               */
00290 } SPIS_TXD_Type;
00291 
00292 typedef struct {
00293   __IO uint32_t  SCL;                               /*!< Pin select for SCL signal                                             */
00294   __IO uint32_t  SDA;                               /*!< Pin select for SDA signal                                             */
00295 } TWIM_PSEL_Type;
00296 
00297 typedef struct {
00298   __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
00299   __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
00300   __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
00301   __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
00302 } TWIM_RXD_Type;
00303 
00304 typedef struct {
00305   __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
00306   __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
00307   __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
00308   __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
00309 } TWIM_TXD_Type;
00310 
00311 typedef struct {
00312   __IO uint32_t  SCL;                               /*!< Pin select for SCL signal                                             */
00313   __IO uint32_t  SDA;                               /*!< Pin select for SDA signal                                             */
00314 } TWIS_PSEL_Type;
00315 
00316 typedef struct {
00317   __IO uint32_t  PTR;                               /*!< RXD Data pointer                                                      */
00318   __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in RXD buffer                                 */
00319   __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last RXD transaction               */
00320 } TWIS_RXD_Type;
00321 
00322 typedef struct {
00323   __IO uint32_t  PTR;                               /*!< TXD Data pointer                                                      */
00324   __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in TXD buffer                                 */
00325   __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last TXD transaction               */
00326 } TWIS_TXD_Type;
00327 
00328 typedef struct {
00329   __IO uint32_t  SCK;                               /*!< Pin select for SCK                                                    */
00330   __IO uint32_t  MOSI;                              /*!< Pin select for MOSI                                                   */
00331   __IO uint32_t  MISO;                              /*!< Pin select for MISO                                                   */
00332 } SPI_PSEL_Type;
00333 
00334 typedef struct {
00335   __IO uint32_t  RX;                                /*!< Result of last incoming frames                                        */
00336 } NFCT_FRAMESTATUS_Type;
00337 
00338 typedef struct {
00339   __IO uint32_t  FRAMECONFIG;                       /*!< Configuration of outgoing frames                                      */
00340   __IO uint32_t  AMOUNT;                            /*!< Size of outgoing frame                                                */
00341 } NFCT_TXD_Type;
00342 
00343 typedef struct {
00344   __IO uint32_t  FRAMECONFIG;                       /*!< Configuration of incoming frames                                      */
00345   __I  uint32_t  AMOUNT;                            /*!< Size of last incoming frame                                           */
00346 } NFCT_RXD_Type;
00347 
00348 typedef struct {
00349   __IO uint32_t  LIMITH;                            /*!< Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH */
00350   __IO uint32_t  LIMITL;                            /*!< Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW */
00351 } SAADC_EVENTS_CH_Type;
00352 
00353 typedef struct {
00354   __IO uint32_t  PSELP;                             /*!< Description cluster[0]: Input positive pin selection for CH[0]        */
00355   __IO uint32_t  PSELN;                             /*!< Description cluster[0]: Input negative pin selection for CH[0]        */
00356   __IO uint32_t  CONFIG;                            /*!< Description cluster[0]: Input configuration for CH[0]                 */
00357   __IO uint32_t  LIMIT;                             /*!< Description cluster[0]: High/low limits for event monitoring
00358                                                          a channel                                                             */
00359 } SAADC_CH_Type;
00360 
00361 typedef struct {
00362   __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
00363   __IO uint32_t  MAXCNT;                            /*!< Maximum number of buffer words to transfer                            */
00364   __I  uint32_t  AMOUNT;                            /*!< Number of buffer words transferred since last START                   */
00365 } SAADC_RESULT_Type;
00366 
00367 typedef struct {
00368   __IO uint32_t  LED;                               /*!< Pin select for LED signal                                             */
00369   __IO uint32_t  A;                                 /*!< Pin select for A signal                                               */
00370   __IO uint32_t  B;                                 /*!< Pin select for B signal                                               */
00371 } QDEC_PSEL_Type;
00372 
00373 typedef struct {
00374   __IO uint32_t  PTR;                               /*!< Description cluster[0]: Beginning address in Data RAM of sequence
00375                                                          A                                                                     */
00376   __IO uint32_t  CNT;                               /*!< Description cluster[0]: Amount of values (duty cycles) in sequence
00377                                                          A                                                                     */
00378   __IO uint32_t  REFRESH;                           /*!< Description cluster[0]: Amount of additional PWM periods between
00379                                                          samples loaded to compare register (load every CNT+1 PWM periods)     */
00380   __IO uint32_t  ENDDELAY;                          /*!< Description cluster[0]: Time added after the sequence                 */
00381   __I  uint32_t  RESERVED1[4];
00382 } PWM_SEQ_Type;
00383 
00384 typedef struct {
00385   __IO uint32_t  OUT[4];                            /*!< Description collection[0]: Output pin select for PWM channel
00386                                                          0                                                                     */
00387 } PWM_PSEL_Type;
00388 
00389 typedef struct {
00390   __IO uint32_t  CLK;                               /*!< Pin number configuration for PDM CLK signal                           */
00391   __IO uint32_t  DIN;                               /*!< Pin number configuration for PDM DIN signal                           */
00392 } PDM_PSEL_Type;
00393 
00394 typedef struct {
00395   __IO uint32_t  PTR;                               /*!< RAM address pointer to write samples to with EasyDMA                  */
00396   __IO uint32_t  MAXCNT;                            /*!< Number of samples to allocate memory for in EasyDMA mode              */
00397 } PDM_SAMPLE_Type;
00398 
00399 typedef struct {
00400   __O  uint32_t  EN;                                /*!< Description cluster[0]: Enable channel group 0                        */
00401   __O  uint32_t  DIS;                               /*!< Description cluster[0]: Disable channel group 0                       */
00402 } PPI_TASKS_CHG_Type;
00403 
00404 typedef struct {
00405   __IO uint32_t  EEP;                               /*!< Description cluster[0]: Channel 0 event end-point                     */
00406   __IO uint32_t  TEP;                               /*!< Description cluster[0]: Channel 0 task end-point                      */
00407 } PPI_CH_Type;
00408 
00409 typedef struct {
00410   __IO uint32_t  TEP;                               /*!< Description cluster[0]: Channel 0 task end-point                      */
00411 } PPI_FORK_Type;
00412 
00413 typedef struct {
00414   __IO uint32_t  WA;                                /*!< Description cluster[0]: Write access to region 0 detected             */
00415   __IO uint32_t  RA;                                /*!< Description cluster[0]: Read access to region 0 detected              */
00416 } MWU_EVENTS_REGION_Type;
00417 
00418 typedef struct {
00419   __IO uint32_t  WA;                                /*!< Description cluster[0]: Write access to peripheral region 0
00420                                                          detected                                                              */
00421   __IO uint32_t  RA;                                /*!< Description cluster[0]: Read access to peripheral region 0 detected   */
00422 } MWU_EVENTS_PREGION_Type;
00423 
00424 typedef struct {
00425   __IO uint32_t  SUBSTATWA;                         /*!< Description cluster[0]: Source of event/interrupt in region
00426                                                          0, write access detected while corresponding subregion was enabled
00427                                                           for watching                                                         */
00428   __IO uint32_t  SUBSTATRA;                         /*!< Description cluster[0]: Source of event/interrupt in region
00429                                                          0, read access detected while corresponding subregion was enabled
00430                                                           for watching                                                         */
00431 } MWU_PERREGION_Type;
00432 
00433 typedef struct {
00434   __IO uint32_t  START;                             /*!< Description cluster[0]: Start address for region 0                    */
00435   __IO uint32_t  END;                               /*!< Description cluster[0]: End address of region 0                       */
00436   __I  uint32_t  RESERVED2[2];
00437 } MWU_REGION_Type;
00438 
00439 typedef struct {
00440   __I  uint32_t  START;                             /*!< Description cluster[0]: Reserved for future use                       */
00441   __I  uint32_t  END;                               /*!< Description cluster[0]: Reserved for future use                       */
00442   __IO uint32_t  SUBS;                              /*!< Description cluster[0]: Subregions of region 0                        */
00443   __I  uint32_t  RESERVED3;
00444 } MWU_PREGION_Type;
00445 
00446 typedef struct {
00447   __IO uint32_t  MODE;                              /*!< I2S mode.                                                             */
00448   __IO uint32_t  RXEN;                              /*!< Reception (RX) enable.                                                */
00449   __IO uint32_t  TXEN;                              /*!< Transmission (TX) enable.                                             */
00450   __IO uint32_t  MCKEN;                             /*!< Master clock generator enable.                                        */
00451   __IO uint32_t  MCKFREQ;                           /*!< Master clock generator frequency.                                     */
00452   __IO uint32_t  RATIO;                             /*!< MCK / LRCK ratio.                                                     */
00453   __IO uint32_t  SWIDTH;                            /*!< Sample width.                                                         */
00454   __IO uint32_t  ALIGN;                             /*!< Alignment of sample within a frame.                                   */
00455   __IO uint32_t  FORMAT;                            /*!< Frame format.                                                         */
00456   __IO uint32_t  CHANNELS;                          /*!< Enable channels.                                                      */
00457 } I2S_CONFIG_Type;
00458 
00459 typedef struct {
00460   __IO uint32_t  PTR;                               /*!< Receive buffer RAM start address.                                     */
00461 } I2S_RXD_Type;
00462 
00463 typedef struct {
00464   __IO uint32_t  PTR;                               /*!< Transmit buffer RAM start address.                                    */
00465 } I2S_TXD_Type;
00466 
00467 typedef struct {
00468   __IO uint32_t  MAXCNT;                            /*!< Size of RXD and TXD buffers.                                          */
00469 } I2S_RXTXD_Type;
00470 
00471 typedef struct {
00472   __IO uint32_t  MCK;                               /*!< Pin select for MCK signal.                                            */
00473   __IO uint32_t  SCK;                               /*!< Pin select for SCK signal.                                            */
00474   __IO uint32_t  LRCK;                              /*!< Pin select for LRCK signal.                                           */
00475   __IO uint32_t  SDIN;                              /*!< Pin select for SDIN signal.                                           */
00476   __IO uint32_t  SDOUT;                             /*!< Pin select for SDOUT signal.                                          */
00477 } I2S_PSEL_Type;
00478 
00479 
00480 /* ================================================================================ */
00481 /* ================                      FICR                      ================ */
00482 /* ================================================================================ */
00483 
00484 
00485 /**
00486   * @brief Factory Information Configuration Registers (FICR)
00487   */
00488 
00489 typedef struct {                                    /*!< FICR Structure                                                        */
00490   __I  uint32_t  RESERVED0[4];
00491   __I  uint32_t  CODEPAGESIZE;                      /*!< Code memory page size                                                 */
00492   __I  uint32_t  CODESIZE;                          /*!< Code memory size                                                      */
00493   __I  uint32_t  RESERVED1[18];
00494   __I  uint32_t  DEVICEID[2];                       /*!< Description collection[0]: Device identifier                          */
00495   __I  uint32_t  RESERVED2[6];
00496   __I  uint32_t  ER[4];                             /*!< Description collection[0]: Encryption Root, word 0                    */
00497   __I  uint32_t  IR[4];                             /*!< Description collection[0]: Identity Root, word 0                      */
00498   __I  uint32_t  DEVICEADDRTYPE;                    /*!< Device address type                                                   */
00499   __I  uint32_t  DEVICEADDR[2];                     /*!< Description collection[0]: Device address 0                           */
00500   __I  uint32_t  RESERVED3[21];
00501   FICR_INFO_Type INFO ;                              /*!< Device info                                                           */
00502   __I  uint32_t  RESERVED4[185];
00503   FICR_TEMP_Type TEMP ;                              /*!< Registers storing factory TEMP module linearization coefficients      */
00504   __I  uint32_t  RESERVED5[2];
00505   FICR_NFC_Type NFC ;                                /*!< Unspecified                                                           */
00506 } NRF_FICR_Type;
00507 
00508 
00509 /* ================================================================================ */
00510 /* ================                      UICR                      ================ */
00511 /* ================================================================================ */
00512 
00513 
00514 /**
00515   * @brief User Information Configuration Registers (UICR)
00516   */
00517 
00518 typedef struct {                                    /*!< UICR Structure                                                        */
00519   __IO uint32_t  UNUSED0 ;                           /*!< Unspecified                                                           */
00520   __IO uint32_t  UNUSED1 ;                           /*!< Unspecified                                                           */
00521   __IO uint32_t  UNUSED2 ;                           /*!< Unspecified                                                           */
00522   __I  uint32_t  RESERVED0;
00523   __IO uint32_t  UNUSED3 ;                           /*!< Unspecified                                                           */
00524   __IO uint32_t  NRFFW[15];                         /*!< Description collection[0]: Reserved for Nordic firmware design        */
00525   __IO uint32_t  NRFHW[12];                         /*!< Description collection[0]: Reserved for Nordic hardware design        */
00526   __IO uint32_t  CUSTOMER[32];                      /*!< Description collection[0]: Reserved for customer                      */
00527   __I  uint32_t  RESERVED1[64];
00528   __IO uint32_t  PSELRESET[2];                      /*!< Description collection[0]: Mapping of the nRESET function (see
00529                                                          POWER chapter for details)                                            */
00530   __IO uint32_t  APPROTECT ;                         /*!< Access Port protection                                                */
00531   __IO uint32_t  NFCPINS;                           /*!< Setting of pins dedicated to NFC functionality: NFC antenna
00532                                                          or GPIO                                                               */
00533 } NRF_UICR_Type;
00534 
00535 
00536 /* ================================================================================ */
00537 /* ================                      BPROT                     ================ */
00538 /* ================================================================================ */
00539 
00540 
00541 /**
00542   * @brief Block Protect (BPROT)
00543   */
00544 
00545 typedef struct {                                    /*!< BPROT Structure                                                       */
00546   __I  uint32_t  RESERVED0[384];
00547   __IO uint32_t  CONFIG0 ;                           /*!< Block protect configuration register 0                                */
00548   __IO uint32_t  CONFIG1 ;                           /*!< Block protect configuration register 1                                */
00549   __IO uint32_t  DISABLEINDEBUG ;                    /*!< Disable protection mechanism in debug interface mode                  */
00550   __IO uint32_t  UNUSED0 ;                           /*!< Unspecified                                                           */
00551   __IO uint32_t  CONFIG2 ;                           /*!< Block protect configuration register 2                                */
00552   __IO uint32_t  CONFIG3 ;                           /*!< Block protect configuration register 3                                */
00553 } NRF_BPROT_Type;
00554 
00555 
00556 /* ================================================================================ */
00557 /* ================                      POWER                     ================ */
00558 /* ================================================================================ */
00559 
00560 
00561 /**
00562   * @brief Power control (POWER)
00563   */
00564 
00565 typedef struct {                                    /*!< POWER Structure                                                       */
00566   __I  uint32_t  RESERVED0[30];
00567   __O  uint32_t  TASKS_CONSTLAT;                    /*!< Enable constant latency mode                                          */
00568   __O  uint32_t  TASKS_LOWPWR;                      /*!< Enable low power mode (variable latency)                              */
00569   __I  uint32_t  RESERVED1[34];
00570   __IO uint32_t  EVENTS_POFWARN;                    /*!< Power failure warning                                                 */
00571   __I  uint32_t  RESERVED2[2];
00572   __IO uint32_t  EVENTS_SLEEPENTER ;                 /*!< CPU entered WFI/WFE sleep                                             */
00573   __IO uint32_t  EVENTS_SLEEPEXIT ;                  /*!< CPU exited WFI/WFE sleep                                              */
00574   __I  uint32_t  RESERVED3[122];
00575   __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
00576   __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
00577   __I  uint32_t  RESERVED4[61];
00578   __IO uint32_t  RESETREAS;                         /*!< Reset reason                                                          */
00579   __I  uint32_t  RESERVED5[9];
00580   __I  uint32_t  RAMSTATUS;                         /*!< Deprecated register - RAM status register                             */
00581   __I  uint32_t  RESERVED6[53];
00582   __O  uint32_t  SYSTEMOFF;                         /*!< System OFF register                                                   */
00583   __I  uint32_t  RESERVED7[3];
00584   __IO uint32_t  POFCON;                            /*!< Power failure comparator configuration                                */
00585   __I  uint32_t  RESERVED8[2];
00586   __IO uint32_t  GPREGRET;                          /*!< General purpose retention register                                    */
00587   __IO uint32_t  GPREGRET2 ;                         /*!< General purpose retention register                                    */
00588   __IO uint32_t  RAMON;                             /*!< Deprecated register - RAM on/off register (this register is
00589                                                          retained)                                                             */
00590   __I  uint32_t  RESERVED9[11];
00591   __IO uint32_t  RAMONB;                            /*!< Deprecated register - RAM on/off register (this register is
00592                                                          retained)                                                             */
00593   __I  uint32_t  RESERVED10[8];
00594   __IO uint32_t  DCDCEN;                            /*!< DC/DC enable register                                                 */
00595   __I  uint32_t  RESERVED11[225];
00596   POWER_RAM_Type RAM[8];                            /*!< Unspecified                                                           */
00597 } NRF_POWER_Type;
00598 
00599 
00600 /* ================================================================================ */
00601 /* ================                      CLOCK                     ================ */
00602 /* ================================================================================ */
00603 
00604 
00605 /**
00606   * @brief Clock control (CLOCK)
00607   */
00608 
00609 typedef struct {                                    /*!< CLOCK Structure                                                       */
00610   __O  uint32_t  TASKS_HFCLKSTART;                  /*!< Start HFCLK crystal oscillator                                        */
00611   __O  uint32_t  TASKS_HFCLKSTOP;                   /*!< Stop HFCLK crystal oscillator                                         */
00612   __O  uint32_t  TASKS_LFCLKSTART;                  /*!< Start LFCLK source                                                    */
00613   __O  uint32_t  TASKS_LFCLKSTOP;                   /*!< Stop LFCLK source                                                     */
00614   __O  uint32_t  TASKS_CAL;                         /*!< Start calibration of LFRC oscillator                                  */
00615   __O  uint32_t  TASKS_CTSTART;                     /*!< Start calibration timer                                               */
00616   __O  uint32_t  TASKS_CTSTOP;                      /*!< Stop calibration timer                                                */
00617   __I  uint32_t  RESERVED0[57];
00618   __IO uint32_t  EVENTS_HFCLKSTARTED;               /*!< HFCLK oscillator started                                              */
00619   __IO uint32_t  EVENTS_LFCLKSTARTED;               /*!< LFCLK started                                                         */
00620   __I  uint32_t  RESERVED1;
00621   __IO uint32_t  EVENTS_DONE;                       /*!< Calibration of LFCLK RC oscillator complete event                     */
00622   __IO uint32_t  EVENTS_CTTO;                       /*!< Calibration timer timeout                                             */
00623   __I  uint32_t  RESERVED2[124];
00624   __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
00625   __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
00626   __I  uint32_t  RESERVED3[63];
00627   __I  uint32_t  HFCLKRUN;                          /*!< Status indicating that HFCLKSTART task has been triggered             */
00628   __I  uint32_t  HFCLKSTAT;                         /*!< HFCLK status                                                          */
00629   __I  uint32_t  RESERVED4;
00630   __I  uint32_t  LFCLKRUN;                          /*!< Status indicating that LFCLKSTART task has been triggered             */
00631   __I  uint32_t  LFCLKSTAT;                         /*!< LFCLK status                                                          */
00632   __I  uint32_t  LFCLKSRCCOPY;                      /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered     */
00633   __I  uint32_t  RESERVED5[62];
00634   __IO uint32_t  LFCLKSRC;                          /*!< Clock source for the LFCLK                                            */
00635   __I  uint32_t  RESERVED6[7];
00636   __IO uint32_t  CTIV;                              /*!< Calibration timer interval (retained register, same reset behaviour
00637                                                          as RESETREAS)                                                         */
00638   __I  uint32_t  RESERVED7[8];
00639   __IO uint32_t  TRACECONFIG ;                       /*!< Clocking options for the Trace Port debug interface                   */
00640 } NRF_CLOCK_Type;
00641 
00642 
00643 /* ================================================================================ */
00644 /* ================                      AMLI                      ================ */
00645 /* ================================================================================ */
00646 
00647 
00648 /**
00649   * @brief AHB Multi-Layer Interface (AMLI)
00650   */
00651 
00652 typedef struct {                                    /*!< AMLI Structure                                                        */
00653   __I  uint32_t  RESERVED0[896];
00654   AMLI_RAMPRI_Type RAMPRI;                          /*!< RAM configurable priority configuration structure                     */
00655 } NRF_AMLI_Type;
00656 
00657 
00658 /* ================================================================================ */
00659 /* ================                      RADIO                     ================ */
00660 /* ================================================================================ */
00661 
00662 
00663 /**
00664   * @brief 2.4 GHz Radio (RADIO)
00665   */
00666 
00667 typedef struct {                                    /*!< RADIO Structure                                                       */
00668   __O  uint32_t  TASKS_TXEN;                        /*!< Enable RADIO in TX mode                                               */
00669   __O  uint32_t  TASKS_RXEN;                        /*!< Enable RADIO in RX mode                                               */
00670   __O  uint32_t  TASKS_START;                       /*!< Start RADIO                                                           */
00671   __O  uint32_t  TASKS_STOP;                        /*!< Stop RADIO                                                            */
00672   __O  uint32_t  TASKS_DISABLE;                     /*!< Disable RADIO                                                         */
00673   __O  uint32_t  TASKS_RSSISTART;                   /*!< Start the RSSI and take one single sample of the receive signal
00674                                                          strength.                                                             */
00675   __O  uint32_t  TASKS_RSSISTOP;                    /*!< Stop the RSSI measurement                                             */
00676   __O  uint32_t  TASKS_BCSTART;                     /*!< Start the bit counter                                                 */
00677   __O  uint32_t  TASKS_BCSTOP;                      /*!< Stop the bit counter                                                  */
00678   __I  uint32_t  RESERVED0[55];
00679   __IO uint32_t  EVENTS_READY;                      /*!< RADIO has ramped up and is ready to be started                        */
00680   __IO uint32_t  EVENTS_ADDRESS;                    /*!< Address sent or received                                              */
00681   __IO uint32_t  EVENTS_PAYLOAD;                    /*!< Packet payload sent or received                                       */
00682   __IO uint32_t  EVENTS_END;                        /*!< Packet sent or received                                               */
00683   __IO uint32_t  EVENTS_DISABLED;                   /*!< RADIO has been disabled                                               */
00684   __IO uint32_t  EVENTS_DEVMATCH;                   /*!< A device address match occurred on the last received packet           */
00685   __IO uint32_t  EVENTS_DEVMISS;                    /*!< No device address match occurred on the last received packet          */
00686   __IO uint32_t  EVENTS_RSSIEND;                    /*!< Sampling of receive signal strength complete.                         */
00687   __I  uint32_t  RESERVED1[2];
00688   __IO uint32_t  EVENTS_BCMATCH;                    /*!< Bit counter reached bit count value.                                  */
00689   __I  uint32_t  RESERVED2;
00690   __IO uint32_t  EVENTS_CRCOK ;                      /*!< Packet received with CRC ok                                           */
00691   __IO uint32_t  EVENTS_CRCERROR ;                   /*!< Packet received with CRC error                                        */
00692   __I  uint32_t  RESERVED3[50];
00693   __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
00694   __I  uint32_t  RESERVED4[64];
00695   __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
00696   __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
00697   __I  uint32_t  RESERVED5[61];
00698   __I  uint32_t  CRCSTATUS;                         /*!< CRC status                                                            */
00699   __I  uint32_t  RESERVED6;
00700   __I  uint32_t  RXMATCH;                           /*!< Received address                                                      */
00701   __I  uint32_t  RXCRC;                             /*!< CRC field of previously received packet                               */
00702   __I  uint32_t  DAI;                               /*!< Device address match index                                            */
00703   __I  uint32_t  RESERVED7[60];
00704   __IO uint32_t  PACKETPTR;                         /*!< Packet pointer                                                        */
00705   __IO uint32_t  FREQUENCY;                         /*!< Frequency                                                             */
00706   __IO uint32_t  TXPOWER;                           /*!< Output power                                                          */
00707   __IO uint32_t  MODE;                              /*!< Data rate and modulation                                              */
00708   __IO uint32_t  PCNF0;                             /*!< Packet configuration register 0                                       */
00709   __IO uint32_t  PCNF1;                             /*!< Packet configuration register 1                                       */
00710   __IO uint32_t  BASE0;                             /*!< Base address 0                                                        */
00711   __IO uint32_t  BASE1;                             /*!< Base address 1                                                        */
00712   __IO uint32_t  PREFIX0;                           /*!< Prefixes bytes for logical addresses 0-3                              */
00713   __IO uint32_t  PREFIX1;                           /*!< Prefixes bytes for logical addresses 4-7                              */
00714   __IO uint32_t  TXADDRESS;                         /*!< Transmit address select                                               */
00715   __IO uint32_t  RXADDRESSES;                       /*!< Receive address select                                                */
00716   __IO uint32_t  CRCCNF;                            /*!< CRC configuration                                                     */
00717   __IO uint32_t  CRCPOLY;                           /*!< CRC polynomial                                                        */
00718   __IO uint32_t  CRCINIT;                           /*!< CRC initial value                                                     */
00719   __IO uint32_t  UNUSED0 ;                           /*!< Unspecified                                                           */
00720   __IO uint32_t  TIFS;                              /*!< Inter Frame Spacing in us                                             */
00721   __I  uint32_t  RSSISAMPLE;                        /*!< RSSI sample                                                           */
00722   __I  uint32_t  RESERVED8;
00723   __I  uint32_t  STATE;                             /*!< Current radio state                                                   */
00724   __IO uint32_t  DATAWHITEIV;                       /*!< Data whitening initial value                                          */
00725   __I  uint32_t  RESERVED9[2];
00726   __IO uint32_t  BCC;                               /*!< Bit counter compare                                                   */
00727   __I  uint32_t  RESERVED10[39];
00728   __IO uint32_t  DAB[8];                            /*!< Description collection[0]: Device address base segment 0              */
00729   __IO uint32_t  DAP[8];                            /*!< Description collection[0]: Device address prefix 0                    */
00730   __IO uint32_t  DACNF;                             /*!< Device address match configuration                                    */
00731   __I  uint32_t  RESERVED11[3];
00732   __IO uint32_t  MODECNF0 ;                          /*!< Radio mode configuration register 0                                   */
00733   __I  uint32_t  RESERVED12[618];
00734   __IO uint32_t  POWER;                             /*!< Peripheral power control                                              */
00735 } NRF_RADIO_Type;
00736 
00737 
00738 /* ================================================================================ */
00739 /* ================                      UARTE                     ================ */
00740 /* ================================================================================ */
00741 
00742 
00743 /**
00744   * @brief UART with EasyDMA (UARTE)
00745   */
00746 
00747 typedef struct {                                    /*!< UARTE Structure                                                       */
00748   __O  uint32_t  TASKS_STARTRX ;                     /*!< Start UART receiver                                                   */
00749   __O  uint32_t  TASKS_STOPRX ;                      /*!< Stop UART receiver                                                    */
00750   __O  uint32_t  TASKS_STARTTX ;                     /*!< Start UART transmitter                                                */
00751   __O  uint32_t  TASKS_STOPTX ;                      /*!< Stop UART transmitter                                                 */
00752   __I  uint32_t  RESERVED0[7];
00753   __O  uint32_t  TASKS_FLUSHRX ;                     /*!< Flush RX FIFO into RX buffer                                          */
00754   __I  uint32_t  RESERVED1[52];
00755   __IO uint32_t  EVENTS_CTS ;                        /*!< CTS is activated (set low). Clear To Send.                            */
00756   __IO uint32_t  EVENTS_NCTS ;                       /*!< CTS is deactivated (set high). Not Clear To Send.                     */
00757   __I  uint32_t  RESERVED2[2];
00758   __IO uint32_t  EVENTS_ENDRX ;                      /*!< Receive buffer is filled up                                           */
00759   __I  uint32_t  RESERVED3[3];
00760   __IO uint32_t  EVENTS_ENDTX ;                      /*!< Last TX byte transmitted                                              */
00761   __IO uint32_t  EVENTS_ERROR ;                      /*!< Error detected                                                        */
00762   __I  uint32_t  RESERVED4[7];
00763   __IO uint32_t  EVENTS_RXTO ;                       /*!< Receiver timeout                                                      */
00764   __I  uint32_t  RESERVED5;
00765   __IO uint32_t  EVENTS_RXSTARTED ;                  /*!< UART receiver has started                                             */
00766   __IO uint32_t  EVENTS_TXSTARTED ;                  /*!< UART transmitter has started                                          */
00767   __I  uint32_t  RESERVED6;
00768   __IO uint32_t  EVENTS_TXSTOPPED ;                  /*!< Transmitter stopped                                                   */
00769   __I  uint32_t  RESERVED7[41];
00770   __IO uint32_t  SHORTS ;                            /*!< Shortcut register                                                     */
00771   __I  uint32_t  RESERVED8[63];
00772   __IO uint32_t  INTEN ;                             /*!< Enable or disable interrupt                                           */
00773   __IO uint32_t  INTENSET ;                          /*!< Enable interrupt                                                      */
00774   __IO uint32_t  INTENCLR ;                          /*!< Disable interrupt                                                     */
00775   __I  uint32_t  RESERVED9[93];
00776   __IO uint32_t  ERRORSRC ;                          /*!< Error source                                                          */
00777   __I  uint32_t  RESERVED10[31];
00778   __IO uint32_t  ENABLE ;                            /*!< Enable UART                                                           */
00779   __I  uint32_t  RESERVED11;
00780   UARTE_PSEL_Type PSEL ;                             /*!< Unspecified                                                           */
00781   __I  uint32_t  RESERVED12[3];
00782   __IO uint32_t  BAUDRATE ;                          /*!< Baud rate                                                             */
00783   __I  uint32_t  RESERVED13[3];
00784   UARTE_RXD_Type RXD ;                               /*!< RXD EasyDMA channel                                                   */
00785   __I  uint32_t  RESERVED14;
00786   UARTE_TXD_Type TXD ;                               /*!< TXD EasyDMA channel                                                   */
00787   __I  uint32_t  RESERVED15[7];
00788   __IO uint32_t  CONFIG ;                            /*!< Configuration of parity and hardware flow control                     */
00789 } NRF_UARTE_Type;
00790 
00791 
00792 /* ================================================================================ */
00793 /* ================                      UART                      ================ */
00794 /* ================================================================================ */
00795 
00796 
00797 /**
00798   * @brief Universal Asynchronous Receiver/Transmitter (UART)
00799   */
00800 
00801 typedef struct {                                    /*!< UART Structure                                                        */
00802   __O  uint32_t  TASKS_STARTRX;                     /*!< Start UART receiver                                                   */
00803   __O  uint32_t  TASKS_STOPRX;                      /*!< Stop UART receiver                                                    */
00804   __O  uint32_t  TASKS_STARTTX;                     /*!< Start UART transmitter                                                */
00805   __O  uint32_t  TASKS_STOPTX;                      /*!< Stop UART transmitter                                                 */
00806   __I  uint32_t  RESERVED0[3];
00807   __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend UART                                                          */
00808   __I  uint32_t  RESERVED1[56];
00809   __IO uint32_t  EVENTS_CTS;                        /*!< CTS is activated (set low). Clear To Send.                            */
00810   __IO uint32_t  EVENTS_NCTS;                       /*!< CTS is deactivated (set high). Not Clear To Send.                     */
00811   __IO uint32_t  EVENTS_RXDRDY;                     /*!< Data received in RXD                                                  */
00812   __I  uint32_t  RESERVED2[4];
00813   __IO uint32_t  EVENTS_TXDRDY;                     /*!< Data sent from TXD                                                    */
00814   __I  uint32_t  RESERVED3;
00815   __IO uint32_t  EVENTS_ERROR;                      /*!< Error detected                                                        */
00816   __I  uint32_t  RESERVED4[7];
00817   __IO uint32_t  EVENTS_RXTO;                       /*!< Receiver timeout                                                      */
00818   __I  uint32_t  RESERVED5[46];
00819   __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
00820   __I  uint32_t  RESERVED6[64];
00821   __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
00822   __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
00823   __I  uint32_t  RESERVED7[93];
00824   __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
00825   __I  uint32_t  RESERVED8[31];
00826   __IO uint32_t  ENABLE;                            /*!< Enable UART                                                           */
00827   __I  uint32_t  RESERVED9;
00828   __IO uint32_t  PSELRTS;                           /*!< Pin select for RTS                                                    */
00829   __IO uint32_t  PSELTXD;                           /*!< Pin select for TXD                                                    */
00830   __IO uint32_t  PSELCTS;                           /*!< Pin select for CTS                                                    */
00831   __IO uint32_t  PSELRXD;                           /*!< Pin select for RXD                                                    */
00832   __I  uint32_t  RXD;                               /*!< RXD register                                                          */
00833   __O  uint32_t  TXD;                               /*!< TXD register                                                          */
00834   __I  uint32_t  RESERVED10;
00835   __IO uint32_t  BAUDRATE;                          /*!< Baud rate                                                             */
00836   __I  uint32_t  RESERVED11[17];
00837   __IO uint32_t  CONFIG;                            /*!< Configuration of parity and hardware flow control                     */
00838 } NRF_UART_Type;
00839 
00840 
00841 /* ================================================================================ */
00842 /* ================                      SPIM                      ================ */
00843 /* ================================================================================ */
00844 
00845 
00846 /**
00847   * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM)
00848   */
00849 
00850 typedef struct {                                    /*!< SPIM Structure                                                        */
00851   __I  uint32_t  RESERVED0[4];
00852   __O  uint32_t  TASKS_START;                       /*!< Start SPI transaction                                                 */
00853   __O  uint32_t  TASKS_STOP;                        /*!< Stop SPI transaction                                                  */
00854   __I  uint32_t  RESERVED1;
00855   __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend SPI transaction                                               */
00856   __O  uint32_t  TASKS_RESUME;                      /*!< Resume SPI transaction                                                */
00857   __I  uint32_t  RESERVED2[56];
00858   __IO uint32_t  EVENTS_STOPPED;                    /*!< SPI transaction has stopped                                           */
00859   __I  uint32_t  RESERVED3[2];
00860   __IO uint32_t  EVENTS_ENDRX;                      /*!< End of RXD buffer reached                                             */
00861   __I  uint32_t  RESERVED4;
00862   __IO uint32_t  EVENTS_END ;                        /*!< End of RXD buffer and TXD buffer reached                              */
00863   __I  uint32_t  RESERVED5;
00864   __IO uint32_t  EVENTS_ENDTX;                      /*!< End of TXD buffer reached                                             */
00865   __I  uint32_t  RESERVED6[10];
00866   __IO uint32_t  EVENTS_STARTED;                    /*!< Transaction started                                                   */
00867   __I  uint32_t  RESERVED7[44];
00868   __IO uint32_t  SHORTS ;                            /*!< Shortcut register                                                     */
00869   __I  uint32_t  RESERVED8[64];
00870   __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
00871   __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
00872   __I  uint32_t  RESERVED9[125];
00873   __IO uint32_t  ENABLE;                            /*!< Enable SPIM                                                           */
00874   __I  uint32_t  RESERVED10;
00875   SPIM_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
00876   __I  uint32_t  RESERVED11[4];
00877   __IO uint32_t  FREQUENCY;                         /*!< SPI frequency                                                         */
00878   __I  uint32_t  RESERVED12[3];
00879   SPIM_RXD_Type RXD;                                /*!< RXD EasyDMA channel                                                   */
00880   SPIM_TXD_Type TXD;                                /*!< TXD EasyDMA channel                                                   */
00881   __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
00882   __I  uint32_t  RESERVED13[26];
00883   __IO uint32_t  ORC;                               /*!< Over-read character. Character clocked out in case and over-read
00884                                                          of the TXD buffer.                                                    */
00885 } NRF_SPIM_Type;
00886 
00887 
00888 /* ================================================================================ */
00889 /* ================                      SPIS                      ================ */
00890 /* ================================================================================ */
00891 
00892 
00893 /**
00894   * @brief SPI Slave 0 (SPIS)
00895   */
00896 
00897 typedef struct {                                    /*!< SPIS Structure                                                        */
00898   __I  uint32_t  RESERVED0[9];
00899   __O  uint32_t  TASKS_ACQUIRE;                     /*!< Acquire SPI semaphore                                                 */
00900   __O  uint32_t  TASKS_RELEASE;                     /*!< Release SPI semaphore, enabling the SPI slave to acquire it           */
00901   __I  uint32_t  RESERVED1[54];
00902   __IO uint32_t  EVENTS_END;                        /*!< Granted transaction completed                                         */
00903   __I  uint32_t  RESERVED2[2];
00904   __IO uint32_t  EVENTS_ENDRX;                      /*!< End of RXD buffer reached                                             */
00905   __I  uint32_t  RESERVED3[5];
00906   __IO uint32_t  EVENTS_ACQUIRED;                   /*!< Semaphore acquired                                                    */
00907   __I  uint32_t  RESERVED4[53];
00908   __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
00909   __I  uint32_t  RESERVED5[64];
00910   __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
00911   __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
00912   __I  uint32_t  RESERVED6[61];
00913   __I  uint32_t  SEMSTAT;                           /*!< Semaphore status register                                             */
00914   __I  uint32_t  RESERVED7[15];
00915   __IO uint32_t  STATUS;                            /*!< Status from last transaction                                          */
00916   __I  uint32_t  RESERVED8[47];
00917   __IO uint32_t  ENABLE;                            /*!< Enable SPI slave                                                      */
00918   __I  uint32_t  RESERVED9;
00919   SPIS_PSEL_Type PSEL ;                              /*!< Unspecified                                                           */
00920   __I  uint32_t  RESERVED10[7];
00921   SPIS_RXD_Type RXD ;                                /*!< Unspecified                                                           */
00922   __I  uint32_t  RESERVED11;
00923   SPIS_TXD_Type TXD ;                                /*!< Unspecified                                                           */
00924   __I  uint32_t  RESERVED12;
00925   __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
00926   __I  uint32_t  RESERVED13;
00927   __IO uint32_t  DEF;                               /*!< Default character. Character clocked out in case of an ignored
00928                                                          transaction.                                                          */
00929   __I  uint32_t  RESERVED14[24];
00930   __IO uint32_t  ORC;                               /*!< Over-read character                                                   */
00931 } NRF_SPIS_Type;
00932 
00933 
00934 /* ================================================================================ */
00935 /* ================                      TWIM                      ================ */
00936 /* ================================================================================ */
00937 
00938 
00939 /**
00940   * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM)
00941   */
00942 
00943 typedef struct {                                    /*!< TWIM Structure                                                        */
00944   __O  uint32_t  TASKS_STARTRX ;                     /*!< Start TWI receive sequence                                            */
00945   __I  uint32_t  RESERVED0;
00946   __O  uint32_t  TASKS_STARTTX ;                     /*!< Start TWI transmit sequence                                           */
00947   __I  uint32_t  RESERVED1[2];
00948   __O  uint32_t  TASKS_STOP;                        /*!< Stop TWI transaction. Must be issued while the TWI master is
00949                                                          not suspended.                                                        */
00950   __I  uint32_t  RESERVED2;
00951   __O  uint32_t  TASKS_SUSPEND ;                     /*!< Suspend TWI transaction                                               */
00952   __O  uint32_t  TASKS_RESUME ;                      /*!< Resume TWI transaction                                                */
00953   __I  uint32_t  RESERVED3[56];
00954   __IO uint32_t  EVENTS_STOPPED ;                    /*!< TWI stopped                                                           */
00955   __I  uint32_t  RESERVED4[7];
00956   __IO uint32_t  EVENTS_ERROR ;                      /*!< TWI error                                                             */
00957   __I  uint32_t  RESERVED5[8];
00958   __IO uint32_t  EVENTS_SUSPENDED;                  /*!< Last byte has been sent out after the SUSPEND task has been
00959                                                          issued, TWI traffic is now suspended.                                 */
00960   __IO uint32_t  EVENTS_RXSTARTED ;                  /*!< Receive sequence started                                              */
00961   __IO uint32_t  EVENTS_TXSTARTED ;                  /*!< Transmit sequence started                                             */
00962   __I  uint32_t  RESERVED6[2];
00963   __IO uint32_t  EVENTS_LASTRX ;                     /*!< Byte boundary, starting to receive the last byte                      */
00964   __IO uint32_t  EVENTS_LASTTX ;                     /*!< Byte boundary, starting to transmit the last byte                     */
00965   __I  uint32_t  RESERVED7[39];
00966   __IO uint32_t  SHORTS ;                            /*!< Shortcut register                                                     */
00967   __I  uint32_t  RESERVED8[63];
00968   __IO uint32_t  INTEN ;                             /*!< Enable or disable interrupt                                           */
00969   __IO uint32_t  INTENSET ;                          /*!< Enable interrupt                                                      */
00970   __IO uint32_t  INTENCLR ;                          /*!< Disable interrupt                                                     */
00971   __I  uint32_t  RESERVED9[110];
00972   __IO uint32_t  ERRORSRC ;                          /*!< Error source                                                          */
00973   __I  uint32_t  RESERVED10[14];
00974   __IO uint32_t  ENABLE ;                            /*!< Enable TWIM                                                           */
00975   __I  uint32_t  RESERVED11;
00976   TWIM_PSEL_Type PSEL ;                              /*!< Unspecified                                                           */
00977   __I  uint32_t  RESERVED12[5];
00978   __IO uint32_t  FREQUENCY ;                         /*!< TWI frequency                                                         */
00979   __I  uint32_t  RESERVED13[3];
00980   TWIM_RXD_Type RXD ;                                /*!< RXD EasyDMA channel                                                   */
00981   TWIM_TXD_Type TXD ;                                /*!< TXD EasyDMA channel                                                   */
00982   __I  uint32_t  RESERVED14[13];
00983   __IO uint32_t  ADDRESS ;                           /*!< Address used in the TWI transfer                                      */
00984 } NRF_TWIM_Type;
00985 
00986 
00987 /* ================================================================================ */
00988 /* ================                      TWIS                      ================ */
00989 /* ================================================================================ */
00990 
00991 
00992 /**
00993   * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS)
00994   */
00995 
00996 typedef struct {                                    /*!< TWIS Structure                                                        */
00997   __I  uint32_t  RESERVED0[5];
00998   __O  uint32_t  TASKS_STOP ;                        /*!< Stop TWI transaction                                                  */
00999   __I  uint32_t  RESERVED1;
01000   __O  uint32_t  TASKS_SUSPEND ;                     /*!< Suspend TWI transaction                                               */
01001   __O  uint32_t  TASKS_RESUME ;                      /*!< Resume TWI transaction                                                */
01002   __I  uint32_t  RESERVED2[3];
01003   __O  uint32_t  TASKS_PREPARERX ;                   /*!< Prepare the TWI slave to respond to a write command                   */
01004   __O  uint32_t  TASKS_PREPARETX ;                   /*!< Prepare the TWI slave to respond to a read command                    */
01005   __I  uint32_t  RESERVED3[51];
01006   __IO uint32_t  EVENTS_STOPPED ;                    /*!< TWI stopped                                                           */
01007   __I  uint32_t  RESERVED4[7];
01008   __IO uint32_t  EVENTS_ERROR ;                      /*!< TWI error                                                             */
01009   __I  uint32_t  RESERVED5[9];
01010   __IO uint32_t  EVENTS_RXSTARTED ;                  /*!< Receive sequence started                                              */
01011   __IO uint32_t  EVENTS_TXSTARTED ;                  /*!< Transmit sequence started                                             */
01012   __I  uint32_t  RESERVED6[4];
01013   __IO uint32_t  EVENTS_WRITE ;                      /*!< Write command received                                                */
01014   __IO uint32_t  EVENTS_READ ;                       /*!< Read command received                                                 */
01015   __I  uint32_t  RESERVED7[37];
01016   __IO uint32_t  SHORTS ;                            /*!< Shortcut register                                                     */
01017   __I  uint32_t  RESERVED8[63];
01018   __IO uint32_t  INTEN ;                             /*!< Enable or disable interrupt                                           */
01019   __IO uint32_t  INTENSET ;                          /*!< Enable interrupt                                                      */
01020   __IO uint32_t  INTENCLR ;                          /*!< Disable interrupt                                                     */
01021   __I  uint32_t  RESERVED9[113];
01022   __IO uint32_t  ERRORSRC ;                          /*!< Error source                                                          */
01023   __I  uint32_t  MATCH ;                             /*!< Status register indicating which address had a match                  */
01024   __I  uint32_t  RESERVED10[10];
01025   __IO uint32_t  ENABLE ;                            /*!< Enable TWIS                                                           */
01026   __I  uint32_t  RESERVED11;
01027   TWIS_PSEL_Type PSEL ;                              /*!< Unspecified                                                           */
01028   __I  uint32_t  RESERVED12[9];
01029   TWIS_RXD_Type RXD ;                                /*!< RXD EasyDMA channel                                                   */
01030   __I  uint32_t  RESERVED13;
01031   TWIS_TXD_Type TXD ;                                /*!< TXD EasyDMA channel                                                   */
01032   __I  uint32_t  RESERVED14[14];
01033   __IO uint32_t  ADDRESS[2];                        /*!< Description collection[0]: TWI slave address 0                        */
01034   __I  uint32_t  RESERVED15;
01035   __IO uint32_t  CONFIG ;                            /*!< Configuration register for the address match mechanism                */
01036   __I  uint32_t  RESERVED16[10];
01037   __IO uint32_t  ORC;                               /*!< Over-read character. Character sent out in case of an over-read
01038                                                          of the transmit buffer.                                               */
01039 } NRF_TWIS_Type;
01040 
01041 
01042 /* ================================================================================ */
01043 /* ================                       SPI                      ================ */
01044 /* ================================================================================ */
01045 
01046 
01047 /**
01048   * @brief Serial Peripheral Interface 0 (SPI)
01049   */
01050 
01051 typedef struct {                                    /*!< SPI Structure                                                         */
01052   __I  uint32_t  RESERVED0[66];
01053   __IO uint32_t  EVENTS_READY;                      /*!< TXD byte sent and RXD byte received                                   */
01054   __I  uint32_t  RESERVED1[126];
01055   __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
01056   __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
01057   __I  uint32_t  RESERVED2[125];
01058   __IO uint32_t  ENABLE;                            /*!< Enable SPI                                                            */
01059   __I  uint32_t  RESERVED3;
01060   SPI_PSEL_Type PSEL ;                               /*!< Unspecified                                                           */
01061   __I  uint32_t  RESERVED4;
01062   __I  uint32_t  RXD;                               /*!< RXD register                                                          */
01063   __IO uint32_t  TXD;                               /*!< TXD register                                                          */
01064   __I  uint32_t  RESERVED5;
01065   __IO uint32_t  FREQUENCY;                         /*!< SPI frequency                                                         */
01066   __I  uint32_t  RESERVED6[11];
01067   __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
01068 } NRF_SPI_Type;
01069 
01070 
01071 /* ================================================================================ */
01072 /* ================                       TWI                      ================ */
01073 /* ================================================================================ */
01074 
01075 
01076 /**
01077   * @brief I2C compatible Two-Wire Interface 0 (TWI)
01078   */
01079 
01080 typedef struct {                                    /*!< TWI Structure                                                         */
01081   __O  uint32_t  TASKS_STARTRX;                     /*!< Start TWI receive sequence                                            */
01082   __I  uint32_t  RESERVED0;
01083   __O  uint32_t  TASKS_STARTTX;                     /*!< Start TWI transmit sequence                                           */
01084   __I  uint32_t  RESERVED1[2];
01085   __O  uint32_t  TASKS_STOP;                        /*!< Stop TWI transaction                                                  */
01086   __I  uint32_t  RESERVED2;
01087   __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend TWI transaction                                               */
01088   __O  uint32_t  TASKS_RESUME;                      /*!< Resume TWI transaction                                                */
01089   __I  uint32_t  RESERVED3[56];
01090   __IO uint32_t  EVENTS_STOPPED;                    /*!< TWI stopped                                                           */
01091   __IO uint32_t  EVENTS_RXDREADY;                   /*!< TWI RXD byte received                                                 */
01092   __I  uint32_t  RESERVED4[4];
01093   __IO uint32_t  EVENTS_TXDSENT;                    /*!< TWI TXD byte sent                                                     */
01094   __I  uint32_t  RESERVED5;
01095   __IO uint32_t  EVENTS_ERROR;                      /*!< TWI error                                                             */
01096   __I  uint32_t  RESERVED6[4];
01097   __IO uint32_t  EVENTS_BB;                         /*!< TWI byte boundary, generated before each byte that is sent or
01098                                                          received                                                              */
01099   __I  uint32_t  RESERVED7[3];
01100   __IO uint32_t  EVENTS_SUSPENDED;                  /*!< TWI entered the suspended state                                       */
01101   __I  uint32_t  RESERVED8[45];
01102   __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
01103   __I  uint32_t  RESERVED9[64];
01104   __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
01105   __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
01106   __I  uint32_t  RESERVED10[110];
01107   __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
01108   __I  uint32_t  RESERVED11[14];
01109   __IO uint32_t  ENABLE;                            /*!< Enable TWI                                                            */
01110   __I  uint32_t  RESERVED12;
01111   __IO uint32_t  PSELSCL;                           /*!< Pin select for SCL                                                    */
01112   __IO uint32_t  PSELSDA;                           /*!< Pin select for SDA                                                    */
01113   __I  uint32_t  RESERVED13[2];
01114   __I  uint32_t  RXD;                               /*!< RXD register                                                          */
01115   __IO uint32_t  TXD;                               /*!< TXD register                                                          */
01116   __I  uint32_t  RESERVED14;
01117   __IO uint32_t  FREQUENCY;                         /*!< TWI frequency                                                         */
01118   __I  uint32_t  RESERVED15[24];
01119   __IO uint32_t  ADDRESS;                           /*!< Address used in the TWI transfer                                      */
01120 } NRF_TWI_Type;
01121 
01122 
01123 /* ================================================================================ */
01124 /* ================                      NFCT                      ================ */
01125 /* ================================================================================ */
01126 
01127 
01128 /**
01129   * @brief NFC-A compatible radio (NFCT)
01130   */
01131 
01132 typedef struct {                                    /*!< NFCT Structure                                                        */
01133   __O  uint32_t  TASKS_ACTIVATE;                    /*!< Activate NFC peripheral for incoming and outgoing frames, change
01134                                                          state to activated                                                    */
01135   __O  uint32_t  TASKS_DISABLE ;                     /*!< Disable NFC peripheral                                                */
01136   __O  uint32_t  TASKS_SENSE ;                       /*!< Enable NFC sense field mode, change state to sense mode               */
01137   __O  uint32_t  TASKS_STARTTX ;                     /*!< Start transmission of a outgoing frame, change state to transmit      */
01138   __I  uint32_t  RESERVED0[3];
01139   __O  uint32_t  TASKS_ENABLERXDATA ;                /*!< Initializes the EasyDMA for receive.                                  */
01140   __I  uint32_t  RESERVED1;
01141   __O  uint32_t  TASKS_GOIDLE ;                      /*!< Force state machine to IDLE state                                     */
01142   __O  uint32_t  TASKS_GOSLEEP ;                     /*!< Force state machine to SLEEP_A state                                  */
01143   __I  uint32_t  RESERVED2[53];
01144   __IO uint32_t  EVENTS_READY ;                      /*!< The NFC peripheral is ready to receive and send frames                */
01145   __IO uint32_t  EVENTS_FIELDDETECTED ;              /*!< Remote NFC field detected                                             */
01146   __IO uint32_t  EVENTS_FIELDLOST ;                  /*!< Remote NFC field lost                                                 */
01147   __IO uint32_t  EVENTS_TXFRAMESTART ;               /*!< Marks the start of the first symbol of a transmitted frame            */
01148   __IO uint32_t  EVENTS_TXFRAMEEND ;                 /*!< Marks the end of the last transmitted on-air symbol of a frame        */
01149   __IO uint32_t  EVENTS_RXFRAMESTART ;               /*!< Marks the end of the first symbol of a received frame                 */
01150   __IO uint32_t  EVENTS_RXFRAMEEND;                 /*!< Received data have been checked (CRC, parity) and transferred
01151                                                          to RAM, and EasyDMA has ended accessing the RX buffer                 */
01152   __IO uint32_t  EVENTS_ERROR;                      /*!< NFC error reported. The ERRORSTATUS register contains details
01153                                                          on the source of the error.                                           */
01154   __I  uint32_t  RESERVED3[2];
01155   __IO uint32_t  EVENTS_RXERROR;                    /*!< NFC RX frame error reported. The FRAMESTATUS.RX register contains
01156                                                          details on the source of the error.                                   */
01157   __IO uint32_t  EVENTS_ENDRX ;                      /*!< RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.      */
01158   __IO uint32_t  EVENTS_ENDTX;                      /*!< Transmission of data in RAM has ended, and EasyDMA has ended
01159                                                          accessing the TX buffer                                               */
01160   __I  uint32_t  RESERVED4;
01161   __IO uint32_t  EVENTS_AUTOCOLRESSTARTED ;          /*!< Auto collision resolution process has started                         */
01162   __I  uint32_t  RESERVED5[3];
01163   __IO uint32_t  EVENTS_COLLISION ;                  /*!< NFC Auto collision resolution error reported.                         */
01164   __IO uint32_t  EVENTS_SELECTED ;                   /*!< NFC Auto collision resolution successfully completed                  */
01165   __IO uint32_t  EVENTS_STARTED ;                    /*!< EasyDMA is ready to receive or send frames.                           */
01166   __I  uint32_t  RESERVED6[43];
01167   __IO uint32_t  SHORTS ;                            /*!< Shortcut register                                                     */
01168   __I  uint32_t  RESERVED7[63];
01169   __IO uint32_t  INTEN ;                             /*!< Enable or disable interrupt                                           */
01170   __IO uint32_t  INTENSET ;                          /*!< Enable interrupt                                                      */
01171   __IO uint32_t  INTENCLR ;                          /*!< Disable interrupt                                                     */
01172   __I  uint32_t  RESERVED8[62];
01173   __IO uint32_t  ERRORSTATUS ;                       /*!< NFC Error Status register                                             */
01174   __I  uint32_t  RESERVED9;
01175   NFCT_FRAMESTATUS_Type FRAMESTATUS ;                /*!< Unspecified                                                           */
01176   __I  uint32_t  RESERVED10[8];
01177   __I  uint32_t  CURRENTLOADCTRL ;                   /*!< Current value driven to the NFC Load Control                          */
01178   __I  uint32_t  RESERVED11[2];
01179   __I  uint32_t  FIELDPRESENT ;                      /*!< Indicates the presence or not of a valid field                        */
01180   __I  uint32_t  RESERVED12[49];
01181   __IO uint32_t  FRAMEDELAYMIN ;                     /*!< Minimum frame delay                                                   */
01182   __IO uint32_t  FRAMEDELAYMAX ;                     /*!< Maximum frame delay                                                   */
01183   __IO uint32_t  FRAMEDELAYMODE ;                    /*!< Configuration register for the Frame Delay Timer                      */
01184   __IO uint32_t  PACKETPTR ;                         /*!< Packet pointer for TXD and RXD data storage in Data RAM               */
01185   __IO uint32_t  MAXLEN;                            /*!< Size of allocated for TXD and RXD data storage buffer in Data
01186                                                          RAM                                                                   */
01187   NFCT_TXD_Type TXD ;                                /*!< Unspecified                                                           */
01188   NFCT_RXD_Type RXD ;                                /*!< Unspecified                                                           */
01189   __I  uint32_t  RESERVED13[26];
01190   __IO uint32_t  NFCID1_LAST ;                       /*!< Last NFCID1 part (4, 7 or 10 bytes ID)                                */
01191   __IO uint32_t  NFCID1_2ND_LAST ;                   /*!< Second last NFCID1 part (7 or 10 bytes ID)                            */
01192   __IO uint32_t  NFCID1_3RD_LAST ;                   /*!< Third last NFCID1 part (10 bytes ID)                                  */
01193   __I  uint32_t  RESERVED14;
01194   __IO uint32_t  SENSRES ;                           /*!< NFC-A SENS_RES auto-response settings                                 */
01195   __IO uint32_t  SELRES ;                            /*!< NFC-A SEL_RES auto-response settings                                  */
01196 } NRF_NFCT_Type;
01197 
01198 
01199 /* ================================================================================ */
01200 /* ================                     GPIOTE                     ================ */
01201 /* ================================================================================ */
01202 
01203 
01204 /**
01205   * @brief GPIO Tasks and Events (GPIOTE)
01206   */
01207 
01208 typedef struct {                                    /*!< GPIOTE Structure                                                      */
01209   __O  uint32_t  TASKS_OUT[8];                      /*!< Description collection[0]: Task for writing to pin specified
01210                                                          in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. */
01211   __I  uint32_t  RESERVED0[4];
01212   __O  uint32_t  TASKS_SET[8];                      /*!< Description collection[0]: Task for writing to pin specified
01213                                                          in CONFIG[0].PSEL. Action on pin is to set it high.                   */
01214   __I  uint32_t  RESERVED1[4];
01215   __O  uint32_t  TASKS_CLR[8];                      /*!< Description collection[0]: Task for writing to pin specified
01216                                                          in CONFIG[0].PSEL. Action on pin is to set it low.                    */
01217   __I  uint32_t  RESERVED2[32];
01218   __IO uint32_t  EVENTS_IN[8];                      /*!< Description collection[0]: Event generated from pin specified
01219                                                          in CONFIG[0].PSEL                                                     */
01220   __I  uint32_t  RESERVED3[23];
01221   __IO uint32_t  EVENTS_PORT;                       /*!< Event generated from multiple input GPIO pins with SENSE mechanism
01222                                                          enabled                                                               */
01223   __I  uint32_t  RESERVED4[97];
01224   __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
01225   __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
01226   __I  uint32_t  RESERVED5[129];
01227   __IO uint32_t  CONFIG[8];                         /*!< Description collection[0]: Configuration for OUT[n], SET[n]
01228                                                          and CLR[n] tasks and IN[n] event                                      */
01229 } NRF_GPIOTE_Type;
01230 
01231 
01232 /* ================================================================================ */
01233 /* ================                      SAADC                     ================ */
01234 /* ================================================================================ */
01235 
01236 
01237 /**
01238   * @brief Analog to Digital Converter (SAADC)
01239   */
01240 
01241 typedef struct {                                    /*!< SAADC Structure                                                       */
01242   __O  uint32_t  TASKS_START ;                       /*!< Start the ADC and prepare the result buffer in RAM                    */
01243   __O  uint32_t  TASKS_SAMPLE ;                      /*!< Take one ADC sample, if scan is enabled all channels are sampled      */
01244   __O  uint32_t  TASKS_STOP ;                        /*!< Stop the ADC and terminate any on-going conversion                    */
01245   __O  uint32_t  TASKS_CALIBRATEOFFSET ;             /*!< Starts offset auto-calibration                                        */
01246   __I  uint32_t  RESERVED0[60];
01247   __IO uint32_t  EVENTS_STARTED ;                    /*!< The ADC has started                                                   */
01248   __IO uint32_t  EVENTS_END ;                        /*!< The ADC has filled up the Result buffer                               */
01249   __IO uint32_t  EVENTS_DONE;                       /*!< A conversion task has been completed. Depending on the mode,
01250                                                          multiple conversions might be needed for a result to be transferred
01251                                                           to RAM.                                                              */
01252   __IO uint32_t  EVENTS_RESULTDONE ;                 /*!< A result is ready to get transferred to RAM.                          */
01253   __IO uint32_t  EVENTS_CALIBRATEDONE ;              /*!< Calibration is complete                                               */
01254   __IO uint32_t  EVENTS_STOPPED ;                    /*!< The ADC has stopped                                                   */
01255   SAADC_EVENTS_CH_Type EVENTS_CH[8];                /*!< Unspecified                                                           */
01256   __I  uint32_t  RESERVED1[106];
01257   __IO uint32_t  INTEN ;                             /*!< Enable or disable interrupt                                           */
01258   __IO uint32_t  INTENSET ;                          /*!< Enable interrupt                                                      */
01259   __IO uint32_t  INTENCLR ;                          /*!< Disable interrupt                                                     */
01260   __I  uint32_t  RESERVED2[61];
01261   __I  uint32_t  STATUS ;                            /*!< Status                                                                */
01262   __I  uint32_t  RESERVED3[63];
01263   __IO uint32_t  ENABLE ;                            /*!< Enable or disable ADC                                                 */
01264   __I  uint32_t  RESERVED4[3];
01265   SAADC_CH_Type CH[8];                              /*!< Unspecified                                                           */
01266   __I  uint32_t  RESERVED5[24];
01267   __IO uint32_t  RESOLUTION ;                        /*!< Resolution configuration                                              */
01268   __IO uint32_t  OVERSAMPLE;                        /*!< Oversampling configuration. OVERSAMPLE should not be combined
01269                                                          with SCAN. The RESOLUTION is applied before averaging, thus
01270                                                           for high OVERSAMPLE a higher RESOLUTION should be used.              */
01271   __IO uint32_t  SAMPLERATE ;                        /*!< Controls normal or continuous sample rate                             */
01272   __I  uint32_t  RESERVED6[12];
01273   SAADC_RESULT_Type RESULT ;                         /*!< RESULT EasyDMA channel                                                */
01274 } NRF_SAADC_Type;
01275 
01276 
01277 /* ================================================================================ */
01278 /* ================                      TIMER                     ================ */
01279 /* ================================================================================ */
01280 
01281 
01282 /**
01283   * @brief Timer/Counter 0 (TIMER)
01284   */
01285 
01286 typedef struct {                                    /*!< TIMER Structure                                                       */
01287   __O  uint32_t  TASKS_START;                       /*!< Start Timer                                                           */
01288   __O  uint32_t  TASKS_STOP;                        /*!< Stop Timer                                                            */
01289   __O  uint32_t  TASKS_COUNT;                       /*!< Increment Timer (Counter mode only)                                   */
01290   __O  uint32_t  TASKS_CLEAR;                       /*!< Clear time                                                            */
01291   __O  uint32_t  TASKS_SHUTDOWN;                    /*!< Deprecated register - Shut down timer                                 */
01292   __I  uint32_t  RESERVED0[11];
01293   __O  uint32_t  TASKS_CAPTURE[6];                  /*!< Description collection[0]: Capture Timer value to CC[0] register      */
01294   __I  uint32_t  RESERVED1[58];
01295   __IO uint32_t  EVENTS_COMPARE[6];                 /*!< Description collection[0]: Compare event on CC[0] match               */
01296   __I  uint32_t  RESERVED2[42];
01297   __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
01298   __I  uint32_t  RESERVED3[64];
01299   __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
01300   __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
01301   __I  uint32_t  RESERVED4[126];
01302   __IO uint32_t  MODE;                              /*!< Timer mode selection                                                  */
01303   __IO uint32_t  BITMODE;                           /*!< Configure the number of bits used by the TIMER                        */
01304   __I  uint32_t  RESERVED5;
01305   __IO uint32_t  PRESCALER;                         /*!< Timer prescaler register                                              */
01306   __I  uint32_t  RESERVED6[11];
01307   __IO uint32_t  CC[6];                             /*!< Description collection[0]: Capture/Compare register 0                 */
01308 } NRF_TIMER_Type;
01309 
01310 
01311 /* ================================================================================ */
01312 /* ================                       RTC                      ================ */
01313 /* ================================================================================ */
01314 
01315 
01316 /**
01317   * @brief Real time counter 0 (RTC)
01318   */
01319 
01320 typedef struct {                                    /*!< RTC Structure                                                         */
01321   __O  uint32_t  TASKS_START;                       /*!< Start RTC COUNTER                                                     */
01322   __O  uint32_t  TASKS_STOP;                        /*!< Stop RTC COUNTER                                                      */
01323   __O  uint32_t  TASKS_CLEAR;                       /*!< Clear RTC COUNTER                                                     */
01324   __O  uint32_t  TASKS_TRIGOVRFLW;                  /*!< Set COUNTER to 0xFFFFF0                                               */
01325   __I  uint32_t  RESERVED0[60];
01326   __IO uint32_t  EVENTS_TICK;                       /*!< Event on COUNTER increment                                            */
01327   __IO uint32_t  EVENTS_OVRFLW;                     /*!< Event on COUNTER overflow                                             */
01328   __I  uint32_t  RESERVED1[14];
01329   __IO uint32_t  EVENTS_COMPARE[4];                 /*!< Description collection[0]: Compare event on CC[0] match               */
01330   __I  uint32_t  RESERVED2[109];
01331   __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
01332   __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
01333   __I  uint32_t  RESERVED3[13];
01334   __IO uint32_t  EVTEN;                             /*!< Enable or disable event routing                                       */
01335   __IO uint32_t  EVTENSET;                          /*!< Enable event routing                                                  */
01336   __IO uint32_t  EVTENCLR;                          /*!< Disable event routing                                                 */
01337   __I  uint32_t  RESERVED4[110];
01338   __I  uint32_t  COUNTER;                           /*!< Current COUNTER value                                                 */
01339   __IO uint32_t  PRESCALER;                         /*!< 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must
01340                                                          be written when RTC is stopped                                        */
01341   __I  uint32_t  RESERVED5[13];
01342   __IO uint32_t  CC[4];                             /*!< Description collection[0]: Compare register 0                         */
01343 } NRF_RTC_Type;
01344 
01345 
01346 /* ================================================================================ */
01347 /* ================                      TEMP                      ================ */
01348 /* ================================================================================ */
01349 
01350 
01351 /**
01352   * @brief Temperature Sensor (TEMP)
01353   */
01354 
01355 typedef struct {                                    /*!< TEMP Structure                                                        */
01356   __O  uint32_t  TASKS_START;                       /*!< Start temperature measurement                                         */
01357   __O  uint32_t  TASKS_STOP;                        /*!< Stop temperature measurement                                          */
01358   __I  uint32_t  RESERVED0[62];
01359   __IO uint32_t  EVENTS_DATARDY;                    /*!< Temperature measurement complete, data ready                          */
01360   __I  uint32_t  RESERVED1[128];
01361   __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
01362   __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
01363   __I  uint32_t  RESERVED2[127];
01364   __I  int32_t   TEMP;                              /*!< Temperature in degC (0.25deg steps)                                   */
01365   __I  uint32_t  RESERVED3[5];
01366   __IO uint32_t  A0 ;                                /*!< Slope of 1st piece wise linear function                               */
01367   __IO uint32_t  A1 ;                                /*!< Slope of 2nd piece wise linear function                               */
01368   __IO uint32_t  A2 ;                                /*!< Slope of 3rd piece wise linear function                               */
01369   __IO uint32_t  A3 ;                                /*!< Slope of 4th piece wise linear function                               */
01370   __IO uint32_t  A4 ;                                /*!< Slope of 5th piece wise linear function                               */
01371   __IO uint32_t  A5 ;                                /*!< Slope of 6th piece wise linear function                               */
01372   __I  uint32_t  RESERVED4[2];
01373   __IO uint32_t  B0 ;                                /*!< y-intercept of 1st piece wise linear function                         */
01374   __IO uint32_t  B1 ;                                /*!< y-intercept of 2nd piece wise linear function                         */
01375   __IO uint32_t  B2 ;                                /*!< y-intercept of 3rd piece wise linear function                         */
01376   __IO uint32_t  B3 ;                                /*!< y-intercept of 4th piece wise linear function                         */
01377   __IO uint32_t  B4 ;                                /*!< y-intercept of 5th piece wise linear function                         */
01378   __IO uint32_t  B5 ;                                /*!< y-intercept of 6th piece wise linear function                         */
01379   __I  uint32_t  RESERVED5[2];
01380   __IO uint32_t  T0 ;                                /*!< End point of 1st piece wise linear function                           */
01381   __IO uint32_t  T1 ;                                /*!< End point of 2nd piece wise linear function                           */
01382   __IO uint32_t  T2 ;                                /*!< End point of 3rd piece wise linear function                           */
01383   __IO uint32_t  T3 ;                                /*!< End point of 4th piece wise linear function                           */
01384   __IO uint32_t  T4 ;                                /*!< End point of 5th piece wise linear function                           */
01385 } NRF_TEMP_Type;
01386 
01387 
01388 /* ================================================================================ */
01389 /* ================                       RNG                      ================ */
01390 /* ================================================================================ */
01391 
01392 
01393 /**
01394   * @brief Random Number Generator (RNG)
01395   */
01396 
01397 typedef struct {                                    /*!< RNG Structure                                                         */
01398   __O  uint32_t  TASKS_START;                       /*!< Task starting the random number generator                             */
01399   __O  uint32_t  TASKS_STOP;                        /*!< Task stopping the random number generator                             */
01400   __I  uint32_t  RESERVED0[62];
01401   __IO uint32_t  EVENTS_VALRDY;                     /*!< Event being generated for every new random number written to
01402                                                          the VALUE register                                                    */
01403   __I  uint32_t  RESERVED1[63];
01404   __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
01405   __I  uint32_t  RESERVED2[64];
01406   __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
01407   __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
01408   __I  uint32_t  RESERVED3[126];
01409   __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
01410   __I  uint32_t  VALUE;                             /*!< Output random number                                                  */
01411 } NRF_RNG_Type;
01412 
01413 
01414 /* ================================================================================ */
01415 /* ================                       ECB                      ================ */
01416 /* ================================================================================ */
01417 
01418 
01419 /**
01420   * @brief AES ECB Mode Encryption (ECB)
01421   */
01422 
01423 typedef struct {                                    /*!< ECB Structure                                                         */
01424   __O  uint32_t  TASKS_STARTECB;                    /*!< Start ECB block encrypt                                               */
01425   __O  uint32_t  TASKS_STOPECB;                     /*!< Abort a possible executing ECB operation                              */
01426   __I  uint32_t  RESERVED0[62];
01427   __IO uint32_t  EVENTS_ENDECB;                     /*!< ECB block encrypt complete                                            */
01428   __IO uint32_t  EVENTS_ERRORECB;                   /*!< ECB block encrypt aborted because of a STOPECB task or due to
01429                                                          an error                                                              */
01430   __I  uint32_t  RESERVED1[127];
01431   __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
01432   __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
01433   __I  uint32_t  RESERVED2[126];
01434   __IO uint32_t  ECBDATAPTR;                        /*!< ECB block encrypt memory pointers                                     */
01435 } NRF_ECB_Type;
01436 
01437 
01438 /* ================================================================================ */
01439 /* ================                       CCM                      ================ */
01440 /* ================================================================================ */
01441 
01442 
01443 /**
01444   * @brief AES CCM Mode Encryption (CCM)
01445   */
01446 
01447 typedef struct {                                    /*!< CCM Structure                                                         */
01448   __O  uint32_t  TASKS_KSGEN;                       /*!< Start generation of key-stream. This operation will stop by
01449                                                          itself when completed.                                                */
01450   __O  uint32_t  TASKS_CRYPT;                       /*!< Start encryption/decryption. This operation will stop by itself
01451                                                          when completed.                                                       */
01452   __O  uint32_t  TASKS_STOP;                        /*!< Stop encryption/decryption                                            */
01453   __I  uint32_t  RESERVED0[61];
01454   __IO uint32_t  EVENTS_ENDKSGEN;                   /*!< Key-stream generation complete                                        */
01455   __IO uint32_t  EVENTS_ENDCRYPT;                   /*!< Encrypt/decrypt complete                                              */
01456   __IO uint32_t  EVENTS_ERROR;                      /*!< CCM error event                                                       */
01457   __I  uint32_t  RESERVED1[61];
01458   __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
01459   __I  uint32_t  RESERVED2[64];
01460   __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
01461   __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
01462   __I  uint32_t  RESERVED3[61];
01463   __I  uint32_t  MICSTATUS;                         /*!< MIC check result                                                      */
01464   __I  uint32_t  RESERVED4[63];
01465   __IO uint32_t  ENABLE;                            /*!< Enable                                                                */
01466   __IO uint32_t  MODE;                              /*!< Operation mode                                                        */
01467   __IO uint32_t  CNFPTR;                            /*!< Pointer to data structure holding AES key and NONCE vector            */
01468   __IO uint32_t  INPTR;                             /*!< Input pointer                                                         */
01469   __IO uint32_t  OUTPTR;                            /*!< Output pointer                                                        */
01470   __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to data area used for temporary storage                       */
01471 } NRF_CCM_Type;
01472 
01473 
01474 /* ================================================================================ */
01475 /* ================                       AAR                      ================ */
01476 /* ================================================================================ */
01477 
01478 
01479 /**
01480   * @brief Accelerated Address Resolver (AAR)
01481   */
01482 
01483 typedef struct {                                    /*!< AAR Structure                                                         */
01484   __O  uint32_t  TASKS_START;                       /*!< Start resolving addresses based on IRKs specified in the IRK
01485                                                          data structure                                                        */
01486   __I  uint32_t  RESERVED0;
01487   __O  uint32_t  TASKS_STOP;                        /*!< Stop resolving addresses                                              */
01488   __I  uint32_t  RESERVED1[61];
01489   __IO uint32_t  EVENTS_END;                        /*!< Address resolution procedure complete                                 */
01490   __IO uint32_t  EVENTS_RESOLVED;                   /*!< Address resolved                                                      */
01491   __IO uint32_t  EVENTS_NOTRESOLVED;                /*!< Address not resolved                                                  */
01492   __I  uint32_t  RESERVED2[126];
01493   __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
01494   __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
01495   __I  uint32_t  RESERVED3[61];
01496   __I  uint32_t  STATUS;                            /*!< Resolution status                                                     */
01497   __I  uint32_t  RESERVED4[63];
01498   __IO uint32_t  ENABLE;                            /*!< Enable AAR                                                            */
01499   __IO uint32_t  NIRK;                              /*!< Number of IRKs                                                        */
01500   __IO uint32_t  IRKPTR;                            /*!< Pointer to IRK data structure                                         */
01501   __I  uint32_t  RESERVED5;
01502   __IO uint32_t  ADDRPTR;                           /*!< Pointer to the resolvable address                                     */
01503   __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to data area used for temporary storage                       */
01504 } NRF_AAR_Type;
01505 
01506 
01507 /* ================================================================================ */
01508 /* ================                       WDT                      ================ */
01509 /* ================================================================================ */
01510 
01511 
01512 /**
01513   * @brief Watchdog Timer (WDT)
01514   */
01515 
01516 typedef struct {                                    /*!< WDT Structure                                                         */
01517   __O  uint32_t  TASKS_START;                       /*!< Start the watchdog                                                    */
01518   __I  uint32_t  RESERVED0[63];
01519   __IO uint32_t  EVENTS_TIMEOUT;                    /*!< Watchdog timeout                                                      */
01520   __I  uint32_t  RESERVED1[128];
01521   __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
01522   __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
01523   __I  uint32_t  RESERVED2[61];
01524   __I  uint32_t  RUNSTATUS;                         /*!< Run status                                                            */
01525   __I  uint32_t  REQSTATUS;                         /*!< Request status                                                        */
01526   __I  uint32_t  RESERVED3[63];
01527   __IO uint32_t  CRV;                               /*!< Counter reload value                                                  */
01528   __IO uint32_t  RREN;                              /*!< Enable register for reload request registers                          */
01529   __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
01530   __I  uint32_t  RESERVED4[60];
01531   __O  uint32_t  RR[8];                             /*!< Description collection[0]: Reload request 0                           */
01532 } NRF_WDT_Type;
01533 
01534 
01535 /* ================================================================================ */
01536 /* ================                      QDEC                      ================ */
01537 /* ================================================================================ */
01538 
01539 
01540 /**
01541   * @brief Quadrature Decoder (QDEC)
01542   */
01543 
01544 typedef struct {                                    /*!< QDEC Structure                                                        */
01545   __O  uint32_t  TASKS_START;                       /*!< Task starting the quadrature decoder                                  */
01546   __O  uint32_t  TASKS_STOP;                        /*!< Task stopping the quadrature decoder                                  */
01547   __O  uint32_t  TASKS_READCLRACC;                  /*!< Read and clear ACC and ACCDBL                                         */
01548   __O  uint32_t  TASKS_RDCLRACC ;                    /*!< Read and clear ACC                                                    */
01549   __O  uint32_t  TASKS_RDCLRDBL ;                    /*!< Read and clear ACCDBL                                                 */
01550   __I  uint32_t  RESERVED0[59];
01551   __IO uint32_t  EVENTS_SAMPLERDY;                  /*!< Event being generated for every new sample value written to
01552                                                          the SAMPLE register                                                   */
01553   __IO uint32_t  EVENTS_REPORTRDY;                  /*!< Non-null report ready                                                 */
01554   __IO uint32_t  EVENTS_ACCOF;                      /*!< ACC or ACCDBL register overflow                                       */
01555   __IO uint32_t  EVENTS_DBLRDY ;                     /*!< Double displacement(s) detected                                       */
01556   __IO uint32_t  EVENTS_STOPPED ;                    /*!< QDEC has been stopped                                                 */
01557   __I  uint32_t  RESERVED1[59];
01558   __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
01559   __I  uint32_t  RESERVED2[64];
01560   __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
01561   __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
01562   __I  uint32_t  RESERVED3[125];
01563   __IO uint32_t  ENABLE;                            /*!< Enable the quadrature decoder                                         */
01564   __IO uint32_t  LEDPOL;                            /*!< LED output pin polarity                                               */
01565   __IO uint32_t  SAMPLEPER;                         /*!< Sample period                                                         */
01566   __I  int32_t   SAMPLE;                            /*!< Motion sample value                                                   */
01567   __IO uint32_t  REPORTPER;                         /*!< Number of samples to be taken before REPORTRDY and DBLRDY events
01568                                                          can be generated                                                      */
01569   __I  int32_t   ACC;                               /*!< Register accumulating the valid transitions                           */
01570   __I  int32_t   ACCREAD;                           /*!< Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC
01571                                                          task                                                                  */
01572   QDEC_PSEL_Type PSEL ;                              /*!< Unspecified                                                           */
01573   __IO uint32_t  DBFEN;                             /*!< Enable input debounce filters                                         */
01574   __I  uint32_t  RESERVED4[5];
01575   __IO uint32_t  LEDPRE;                            /*!< Time period the LED is switched ON prior to sampling                  */
01576   __I  uint32_t  ACCDBL;                            /*!< Register accumulating the number of detected double transitions       */
01577   __I  uint32_t  ACCDBLREAD;                        /*!< Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL
01578                                                          task                                                                  */
01579 } NRF_QDEC_Type;
01580 
01581 
01582 /* ================================================================================ */
01583 /* ================                      COMP                      ================ */
01584 /* ================================================================================ */
01585 
01586 
01587 /**
01588   * @brief Comparator (COMP)
01589   */
01590 
01591 typedef struct {                                    /*!< COMP Structure                                                        */
01592   __O  uint32_t  TASKS_START ;                       /*!< Start comparator                                                      */
01593   __O  uint32_t  TASKS_STOP ;                        /*!< Stop comparator                                                       */
01594   __O  uint32_t  TASKS_SAMPLE ;                      /*!< Sample comparator value                                               */
01595   __I  uint32_t  RESERVED0[61];
01596   __IO uint32_t  EVENTS_READY ;                      /*!< COMP is ready and output is valid                                     */
01597   __IO uint32_t  EVENTS_DOWN ;                       /*!< Downward crossing                                                     */
01598   __IO uint32_t  EVENTS_UP ;                         /*!< Upward crossing                                                       */
01599   __IO uint32_t  EVENTS_CROSS ;                      /*!< Downward or upward crossing                                           */
01600   __I  uint32_t  RESERVED1[60];
01601   __IO uint32_t  SHORTS ;                            /*!< Shortcut register                                                     */
01602   __I  uint32_t  RESERVED2[63];
01603   __IO uint32_t  INTEN ;                             /*!< Enable or disable interrupt                                           */
01604   __IO uint32_t  INTENSET ;                          /*!< Enable interrupt                                                      */
01605   __IO uint32_t  INTENCLR ;                          /*!< Disable interrupt                                                     */
01606   __I  uint32_t  RESERVED3[61];
01607   __I  uint32_t  RESULT ;                            /*!< Compare result                                                        */
01608   __I  uint32_t  RESERVED4[63];
01609   __IO uint32_t  ENABLE ;                            /*!< COMP enable                                                           */
01610   __IO uint32_t  PSEL ;                              /*!< Pin select                                                            */
01611   __IO uint32_t  REFSEL ;                            /*!< Reference source select                                               */
01612   __IO uint32_t  EXTREFSEL ;                         /*!< External reference select                                             */
01613   __I  uint32_t  RESERVED5[8];
01614   __IO uint32_t  TH ;                                /*!< Threshold configuration for hysteresis unit                           */
01615   __IO uint32_t  MODE ;                              /*!< Mode configuration                                                    */
01616   __IO uint32_t  HYST ;                              /*!< Comparator hysteresis enable                                          */
01617   __IO uint32_t  ISOURCE ;                           /*!< Current source select on analog input                                 */
01618 } NRF_COMP_Type;
01619 
01620 
01621 /* ================================================================================ */
01622 /* ================                     LPCOMP                     ================ */
01623 /* ================================================================================ */
01624 
01625 
01626 /**
01627   * @brief Low Power Comparator (LPCOMP)
01628   */
01629 
01630 typedef struct {                                    /*!< LPCOMP Structure                                                      */
01631   __O  uint32_t  TASKS_START;                       /*!< Start comparator                                                      */
01632   __O  uint32_t  TASKS_STOP;                        /*!< Stop comparator                                                       */
01633   __O  uint32_t  TASKS_SAMPLE;                      /*!< Sample comparator value                                               */
01634   __I  uint32_t  RESERVED0[61];
01635   __IO uint32_t  EVENTS_READY;                      /*!< LPCOMP is ready and output is valid                                   */
01636   __IO uint32_t  EVENTS_DOWN;                       /*!< Downward crossing                                                     */
01637   __IO uint32_t  EVENTS_UP;                         /*!< Upward crossing                                                       */
01638   __IO uint32_t  EVENTS_CROSS;                      /*!< Downward or upward crossing                                           */
01639   __I  uint32_t  RESERVED1[60];
01640   __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
01641   __I  uint32_t  RESERVED2[64];
01642   __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
01643   __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
01644   __I  uint32_t  RESERVED3[61];
01645   __I  uint32_t  RESULT;                            /*!< Compare result                                                        */
01646   __I  uint32_t  RESERVED4[63];
01647   __IO uint32_t  ENABLE;                            /*!< Enable LPCOMP                                                         */
01648   __IO uint32_t  PSEL;                              /*!< Input pin select                                                      */
01649   __IO uint32_t  REFSEL;                            /*!< Reference select                                                      */
01650   __IO uint32_t  EXTREFSEL;                         /*!< External reference select                                             */
01651   __I  uint32_t  RESERVED5[4];
01652   __IO uint32_t  ANADETECT;                         /*!< Analog detect configuration                                           */
01653   __I  uint32_t  RESERVED6[5];
01654   __IO uint32_t  HYST ;                              /*!< Comparator hysteresis enable                                          */
01655 } NRF_LPCOMP_Type;
01656 
01657 
01658 /* ================================================================================ */
01659 /* ================                       SWI                      ================ */
01660 /* ================================================================================ */
01661 
01662 
01663 /**
01664   * @brief Software interrupt 0 (SWI)
01665   */
01666 
01667 typedef struct {                                    /*!< SWI Structure                                                         */
01668   __I  uint32_t  UNUSED;                            /*!< Unused.                                                               */
01669 } NRF_SWI_Type;
01670 
01671 
01672 /* ================================================================================ */
01673 /* ================                       EGU                      ================ */
01674 /* ================================================================================ */
01675 
01676 
01677 /**
01678   * @brief Event Generator Unit 0 (EGU)
01679   */
01680 
01681 typedef struct {                                    /*!< EGU Structure                                                         */
01682   __O  uint32_t  TASKS_TRIGGER[16];                 /*!< Description collection[0]: Trigger 0 for triggering the corresponding
01683                                                          TRIGGERED[0] event                                                    */
01684   __I  uint32_t  RESERVED0[48];
01685   __IO uint32_t  EVENTS_TRIGGERED[16];              /*!< Description collection[0]: Event number 0 generated by triggering
01686                                                          the corresponding TRIGGER[0] task                                     */
01687   __I  uint32_t  RESERVED1[112];
01688   __IO uint32_t  INTEN ;                             /*!< Enable or disable interrupt                                           */
01689   __IO uint32_t  INTENSET ;                          /*!< Enable interrupt                                                      */
01690   __IO uint32_t  INTENCLR ;                          /*!< Disable interrupt                                                     */
01691 } NRF_EGU_Type;
01692 
01693 
01694 /* ================================================================================ */
01695 /* ================                       PWM                      ================ */
01696 /* ================================================================================ */
01697 
01698 
01699 /**
01700   * @brief Pulse Width Modulation Unit 0 (PWM)
01701   */
01702 
01703 typedef struct {                                    /*!< PWM Structure                                                         */
01704   __I  uint32_t  RESERVED0 ;
01705   __O  uint32_t  TASKS_STOP;                        /*!< Stops PWM pulse generation on all channels at the end of current
01706                                                          PWM period, and stops sequence playback                               */
01707   __O  uint32_t  TASKS_SEQSTART[2];                 /*!< Description collection[0]: Loads the first PWM value on all
01708                                                          enabled channels from sequence 0, and starts playing that sequence
01709                                                           at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes
01710                                                           PWM generation to start it was not running.                          */
01711   __O  uint32_t  TASKS_NEXTSTEP;                    /*!< Steps by one value in the current sequence on all enabled channels
01712                                                          if DECODER.MODE=NextStep. Does not cause PWM generation to start
01713                                                           it was not running.                                                  */
01714   __I  uint32_t  RESERVED1[60];
01715   __IO uint32_t  EVENTS_STOPPED;                    /*!< Response to STOP task, emitted when PWM pulses are no longer
01716                                                          generated                                                             */
01717   __IO uint32_t  EVENTS_SEQSTARTED[2];              /*!< Description collection[0]: First PWM period started on sequence
01718                                                          0                                                                     */
01719   __IO uint32_t  EVENTS_SEQEND[2];                  /*!< Description collection[0]: Emitted at end of every sequence
01720                                                          0, when last value from RAM has been applied to wave counter          */
01721   __IO uint32_t  EVENTS_PWMPERIODEND ;               /*!< Emitted at the end of each PWM period                                 */
01722   __IO uint32_t  EVENTS_LOOPSDONE;                  /*!< Concatenated sequences have been played the amount of times
01723                                                          defined in LOOP.CNT                                                   */
01724   __I  uint32_t  RESERVED2[56];
01725   __IO uint32_t  SHORTS ;                            /*!< Shortcut register                                                     */
01726   __I  uint32_t  RESERVED3[63];
01727   __IO uint32_t  INTEN ;                             /*!< Enable or disable interrupt                                           */
01728   __IO uint32_t  INTENSET ;                          /*!< Enable interrupt                                                      */
01729   __IO uint32_t  INTENCLR ;                          /*!< Disable interrupt                                                     */
01730   __I  uint32_t  RESERVED4[125];
01731   __IO uint32_t  ENABLE ;                            /*!< PWM module enable register                                            */
01732   __IO uint32_t  MODE ;                              /*!< Selects operating mode of the wave counter                            */
01733   __IO uint32_t  COUNTERTOP ;                        /*!< Value up to which the pulse generator counter counts                  */
01734   __IO uint32_t  PRESCALER ;                         /*!< Configuration for PWM_CLK                                             */
01735   __IO uint32_t  DECODER ;                           /*!< Configuration of the decoder                                          */
01736   __IO uint32_t  LOOP ;                              /*!< Amount of playback of a loop                                          */
01737   __I  uint32_t  RESERVED5[2];
01738   PWM_SEQ_Type SEQ[2];                              /*!< Unspecified                                                           */
01739   PWM_PSEL_Type PSEL ;                               /*!< Unspecified                                                           */
01740 } NRF_PWM_Type;
01741 
01742 
01743 /* ================================================================================ */
01744 /* ================                       PDM                      ================ */
01745 /* ================================================================================ */
01746 
01747 
01748 /**
01749   * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM)
01750   */
01751 
01752 typedef struct {                                    /*!< PDM Structure                                                         */
01753   __O  uint32_t  TASKS_START ;                       /*!< Starts continuous PDM transfer                                        */
01754   __O  uint32_t  TASKS_STOP ;                        /*!< Stops PDM transfer                                                    */
01755   __I  uint32_t  RESERVED0[62];
01756   __IO uint32_t  EVENTS_STARTED ;                    /*!< PDM transfer has started                                              */
01757   __IO uint32_t  EVENTS_STOPPED ;                    /*!< PDM transfer has finished                                             */
01758   __IO uint32_t  EVENTS_END;                        /*!< The PDM has written the last sample specified by SAMPLE.MAXCNT
01759                                                          (or the last sample after a STOP task has been received) to
01760                                                           Data RAM                                                             */
01761   __I  uint32_t  RESERVED1[125];
01762   __IO uint32_t  INTEN ;                             /*!< Enable or disable interrupt                                           */
01763   __IO uint32_t  INTENSET ;                          /*!< Enable interrupt                                                      */
01764   __IO uint32_t  INTENCLR ;                          /*!< Disable interrupt                                                     */
01765   __I  uint32_t  RESERVED2[125];
01766   __IO uint32_t  ENABLE ;                            /*!< PDM module enable register                                            */
01767   __IO uint32_t  PDMCLKCTRL ;                        /*!< PDM clock generator control                                           */
01768   __IO uint32_t  MODE ;                              /*!< Defines the routing of the connected PDM microphones' signals         */
01769   __I  uint32_t  RESERVED3[3];
01770   __IO uint32_t  GAINL ;                             /*!< Left output gain adjustment                                           */
01771   __IO uint32_t  GAINR ;                             /*!< Right output gain adjustment                                          */
01772   __I  uint32_t  RESERVED4[8];
01773   PDM_PSEL_Type PSEL ;                               /*!< Unspecified                                                           */
01774   __I  uint32_t  RESERVED5[6];
01775   PDM_SAMPLE_Type SAMPLE ;                           /*!< Unspecified                                                           */
01776 } NRF_PDM_Type;
01777 
01778 
01779 /* ================================================================================ */
01780 /* ================                      NVMC                      ================ */
01781 /* ================================================================================ */
01782 
01783 
01784 /**
01785   * @brief Non Volatile Memory Controller (NVMC)
01786   */
01787 
01788 typedef struct {                                    /*!< NVMC Structure                                                        */
01789   __I  uint32_t  RESERVED0[256];
01790   __I  uint32_t  READY;                             /*!< Ready flag                                                            */
01791   __I  uint32_t  RESERVED1[64];
01792   __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
01793   
01794   union {
01795     __IO uint32_t  ERASEPCR1;                       /*!< Deprecated register - Register for erasing a page in Code area.
01796                                                          Equivalent to ERASEPAGE.                                              */
01797     __IO uint32_t  ERASEPAGE;                       /*!< Register for erasing a page in Code area                              */
01798   };
01799   __IO uint32_t  ERASEALL;                          /*!< Register for erasing all non-volatile user memory                     */
01800   __IO uint32_t  ERASEPCR0;                         /*!< Deprecated register - Register for erasing a page in Code area.
01801                                                          Equivalent to ERASEPAGE.                                              */
01802   __IO uint32_t  ERASEUICR;                         /*!< Register for erasing User Information Configuration Registers         */
01803   __I  uint32_t  RESERVED2[10];
01804   __IO uint32_t  ICACHECNF ;                         /*!< I-Code cache configuration register.                                  */
01805   __I  uint32_t  RESERVED3;
01806   __IO uint32_t  IHIT ;                              /*!< I-Code cache hit counter.                                             */
01807   __IO uint32_t  IMISS ;                             /*!< I-Code cache miss counter.                                            */
01808 } NRF_NVMC_Type;
01809 
01810 
01811 /* ================================================================================ */
01812 /* ================                       PPI                      ================ */
01813 /* ================================================================================ */
01814 
01815 
01816 /**
01817   * @brief Programmable Peripheral Interconnect (PPI)
01818   */
01819 
01820 typedef struct {                                    /*!< PPI Structure                                                         */
01821   PPI_TASKS_CHG_Type TASKS_CHG[6];                  /*!< Channel group tasks                                                   */
01822   __I  uint32_t  RESERVED0[308];
01823   __IO uint32_t  CHEN;                              /*!< Channel enable register                                               */
01824   __IO uint32_t  CHENSET;                           /*!< Channel enable set register                                           */
01825   __IO uint32_t  CHENCLR;                           /*!< Channel enable clear register                                         */
01826   __I  uint32_t  RESERVED1;
01827   PPI_CH_Type CH[20];                               /*!< PPI Channel                                                           */
01828   __I  uint32_t  RESERVED2[148];
01829   __IO uint32_t  CHG[6];                            /*!< Description collection[0]: Channel group 0                            */
01830   __I  uint32_t  RESERVED3[62];
01831   PPI_FORK_Type FORK[32];                           /*!< Fork                                                                  */
01832 } NRF_PPI_Type;
01833 
01834 
01835 /* ================================================================================ */
01836 /* ================                       MWU                      ================ */
01837 /* ================================================================================ */
01838 
01839 
01840 /**
01841   * @brief Memory Watch Unit (MWU)
01842   */
01843 
01844 typedef struct {                                    /*!< MWU Structure                                                         */
01845   __I  uint32_t  RESERVED0[64];
01846   MWU_EVENTS_REGION_Type EVENTS_REGION[4];          /*!< Unspecified                                                           */
01847   __I  uint32_t  RESERVED1[16];
01848   MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];        /*!< Unspecified                                                           */
01849   __I  uint32_t  RESERVED2[100];
01850   __IO uint32_t  INTEN ;                             /*!< Enable or disable interrupt                                           */
01851   __IO uint32_t  INTENSET ;                          /*!< Enable interrupt                                                      */
01852   __IO uint32_t  INTENCLR ;                          /*!< Disable interrupt                                                     */
01853   __I  uint32_t  RESERVED3[5];
01854   __IO uint32_t  NMIEN ;                             /*!< Enable or disable non-maskable interrupt                              */
01855   __IO uint32_t  NMIENSET ;                          /*!< Enable non-maskable interrupt                                         */
01856   __IO uint32_t  NMIENCLR ;                          /*!< Disable non-maskable interrupt                                        */
01857   __I  uint32_t  RESERVED4[53];
01858   MWU_PERREGION_Type PERREGION[2];                  /*!< Unspecified                                                           */
01859   __I  uint32_t  RESERVED5[64];
01860   __IO uint32_t  REGIONEN ;                          /*!< Enable/disable regions watch                                          */
01861   __IO uint32_t  REGIONENSET ;                       /*!< Enable regions watch                                                  */
01862   __IO uint32_t  REGIONENCLR ;                       /*!< Disable regions watch                                                 */
01863   __I  uint32_t  RESERVED6[57];
01864   MWU_REGION_Type REGION[4];                        /*!< Unspecified                                                           */
01865   __I  uint32_t  RESERVED7[32];
01866   MWU_PREGION_Type PREGION[2];                      /*!< Unspecified                                                           */
01867 } NRF_MWU_Type;
01868 
01869 
01870 /* ================================================================================ */
01871 /* ================                       I2S                      ================ */
01872 /* ================================================================================ */
01873 
01874 
01875 /**
01876   * @brief Inter-IC Sound (I2S)
01877   */
01878 
01879 typedef struct {                                    /*!< I2S Structure                                                         */
01880   __O  uint32_t  TASKS_START;                       /*!< Starts continuous I2S transfer. Also starts MCK generator when
01881                                                          this is enabled.                                                      */
01882   __O  uint32_t  TASKS_STOP;                        /*!< Stops I2S transfer. Also stops MCK generator. Triggering this
01883                                                          task will cause the {event:STOPPED} event to be generated.            */
01884   __I  uint32_t  RESERVED0[63];
01885   __IO uint32_t  EVENTS_RXPTRUPD;                   /*!< The RXD.PTR register has been copied to internal double-buffers.
01886                                                          When the I2S module is started and RX is enabled, this event
01887                                                           will be generated for every RXTXD.MAXCNT words that are received
01888                                                           on the SDIN pin.                                                     */
01889   __IO uint32_t  EVENTS_STOPPED ;                    /*!< I2S transfer stopped.                                                 */
01890   __I  uint32_t  RESERVED1[2];
01891   __IO uint32_t  EVENTS_TXPTRUPD;                   /*!< The TDX.PTR register has been copied to internal double-buffers.
01892                                                          When the I2S module is started and TX is enabled, this event
01893                                                           will be generated for every RXTXD.MAXCNT words that are sent
01894                                                           on the SDOUT pin.                                                    */
01895   __I  uint32_t  RESERVED2[122];
01896   __IO uint32_t  INTEN ;                             /*!< Enable or disable interrupt                                           */
01897   __IO uint32_t  INTENSET ;                          /*!< Enable interrupt                                                      */
01898   __IO uint32_t  INTENCLR ;                          /*!< Disable interrupt                                                     */
01899   __I  uint32_t  RESERVED3[125];
01900   __IO uint32_t  ENABLE ;                            /*!< Enable I2S module.                                                    */
01901   I2S_CONFIG_Type CONFIG ;                           /*!< Unspecified                                                           */
01902   __I  uint32_t  RESERVED4[3];
01903   I2S_RXD_Type RXD ;                                 /*!< Unspecified                                                           */
01904   __I  uint32_t  RESERVED5;
01905   I2S_TXD_Type TXD ;                                 /*!< Unspecified                                                           */
01906   __I  uint32_t  RESERVED6[3];
01907   I2S_RXTXD_Type RXTXD ;                             /*!< Unspecified                                                           */
01908   __I  uint32_t  RESERVED7[3];
01909   I2S_PSEL_Type PSEL ;                               /*!< Unspecified                                                           */
01910 } NRF_I2S_Type;
01911 
01912 
01913 /* ================================================================================ */
01914 /* ================                       FPU                      ================ */
01915 /* ================================================================================ */
01916 
01917 
01918 /**
01919   * @brief FPU (FPU)
01920   */
01921 
01922 typedef struct {                                    /*!< FPU Structure                                                         */
01923   __I  uint32_t  UNUSED ;                            /*!< Unused.                                                               */
01924 } NRF_FPU_Type;
01925 
01926 
01927 /* ================================================================================ */
01928 /* ================                      GPIO                      ================ */
01929 /* ================================================================================ */
01930 
01931 
01932 /**
01933   * @brief GPIO Port 1 (GPIO)
01934   */
01935 
01936 typedef struct {                                    /*!< GPIO Structure                                                        */
01937   __I  uint32_t  RESERVED0[321];
01938   __IO uint32_t  OUT;                               /*!< Write GPIO port                                                       */
01939   __IO uint32_t  OUTSET;                            /*!< Set individual bits in GPIO port                                      */
01940   __IO uint32_t  OUTCLR;                            /*!< Clear individual bits in GPIO port                                    */
01941   __I  uint32_t  IN;                                /*!< Read GPIO port                                                        */
01942   __IO uint32_t  DIR;                               /*!< Direction of GPIO pins                                                */
01943   __IO uint32_t  DIRSET;                            /*!< DIR set register                                                      */
01944   __IO uint32_t  DIRCLR;                            /*!< DIR clear register                                                    */
01945   __IO uint32_t  LATCH;                             /*!< Latch register indicating what GPIO pins that have met the criteria
01946                                                          set in the PIN_CNF[n].SENSE registers                                 */
01947   __IO uint32_t  DETECTMODE ;                        /*!< Select between default DETECT signal behaviour and LDETECT mode       */
01948   __I  uint32_t  RESERVED1[118];
01949   __IO uint32_t  PIN_CNF[32];                       /*!< Description collection[0]: Configuration of GPIO pins                 */
01950 } NRF_GPIO_Type;
01951 
01952 
01953 /* --------------------  End of section using anonymous unions  ------------------- */
01954 #if defined(__CC_ARM)
01955   #pragma pop
01956 #elif defined(__ICCARM__)
01957   /* leave anonymous unions enabled */
01958 #elif defined(__GNUC__)
01959   /* anonymous unions are enabled by default */
01960 #elif defined(__TMS470__)
01961   /* anonymous unions are enabled by default */
01962 #elif defined(__TASKING__)
01963   #pragma warning restore
01964 #else
01965   #warning Not supported compiler type
01966 #endif
01967 
01968 
01969 
01970 
01971 /* ================================================================================ */
01972 /* ================              Peripheral memory map             ================ */
01973 /* ================================================================================ */
01974 
01975 #define NRF_FICR_BASE                   0x10000000UL
01976 #define NRF_UICR_BASE                   0x10001000UL
01977 #define NRF_BPROT_BASE                  0x40000000UL
01978 #define NRF_POWER_BASE                  0x40000000UL
01979 #define NRF_CLOCK_BASE                  0x40000000UL
01980 #define NRF_AMLI_BASE                   0x40000000UL
01981 #define NRF_RADIO_BASE                  0x40001000UL
01982 #define NRF_UARTE0_BASE                 0x40002000UL
01983 #define NRF_UART0_BASE                  0x40002000UL
01984 #define NRF_SPIM0_BASE                  0x40003000UL
01985 #define NRF_SPIS0_BASE                  0x40003000UL
01986 #define NRF_TWIM0_BASE                  0x40003000UL
01987 #define NRF_TWIS0_BASE                  0x40003000UL
01988 #define NRF_SPI0_BASE                   0x40003000UL
01989 #define NRF_TWI0_BASE                   0x40003000UL
01990 #define NRF_SPIM1_BASE                  0x40004000UL
01991 #define NRF_SPIS1_BASE                  0x40004000UL
01992 #define NRF_TWIM1_BASE                  0x40004000UL
01993 #define NRF_TWIS1_BASE                  0x40004000UL
01994 #define NRF_SPI1_BASE                   0x40004000UL
01995 #define NRF_TWI1_BASE                   0x40004000UL
01996 #define NRF_NFCT_BASE                   0x40005000UL
01997 #define NRF_GPIOTE_BASE                 0x40006000UL
01998 #define NRF_SAADC_BASE                  0x40007000UL
01999 #define NRF_TIMER0_BASE                 0x40008000UL
02000 #define NRF_TIMER1_BASE                 0x40009000UL
02001 #define NRF_TIMER2_BASE                 0x4000A000UL
02002 #define NRF_RTC0_BASE                   0x4000B000UL
02003 #define NRF_TEMP_BASE                   0x4000C000UL
02004 #define NRF_RNG_BASE                    0x4000D000UL
02005 #define NRF_ECB_BASE                    0x4000E000UL
02006 #define NRF_CCM_BASE                    0x4000F000UL
02007 #define NRF_AAR_BASE                    0x4000F000UL
02008 #define NRF_WDT_BASE                    0x40010000UL
02009 #define NRF_RTC1_BASE                   0x40011000UL
02010 #define NRF_QDEC_BASE                   0x40012000UL
02011 #define NRF_COMP_BASE                   0x40013000UL
02012 #define NRF_LPCOMP_BASE                 0x40013000UL
02013 #define NRF_SWI0_BASE                   0x40014000UL
02014 #define NRF_EGU0_BASE                   0x40014000UL
02015 #define NRF_SWI1_BASE                   0x40015000UL
02016 #define NRF_EGU1_BASE                   0x40015000UL
02017 #define NRF_SWI2_BASE                   0x40016000UL
02018 #define NRF_EGU2_BASE                   0x40016000UL
02019 #define NRF_SWI3_BASE                   0x40017000UL
02020 #define NRF_EGU3_BASE                   0x40017000UL
02021 #define NRF_SWI4_BASE                   0x40018000UL
02022 #define NRF_EGU4_BASE                   0x40018000UL
02023 #define NRF_SWI5_BASE                   0x40019000UL
02024 #define NRF_EGU5_BASE                   0x40019000UL
02025 #define NRF_TIMER3_BASE                 0x4001A000UL
02026 #define NRF_TIMER4_BASE                 0x4001B000UL
02027 #define NRF_PWM0_BASE                   0x4001C000UL
02028 #define NRF_PDM_BASE                    0x4001D000UL
02029 #define NRF_NVMC_BASE                   0x4001E000UL
02030 #define NRF_PPI_BASE                    0x4001F000UL
02031 #define NRF_MWU_BASE                    0x40020000UL
02032 #define NRF_PWM1_BASE                   0x40021000UL
02033 #define NRF_PWM2_BASE                   0x40022000UL
02034 #define NRF_SPIM2_BASE                  0x40023000UL
02035 #define NRF_SPIS2_BASE                  0x40023000UL
02036 #define NRF_SPI2_BASE                   0x40023000UL
02037 #define NRF_RTC2_BASE                   0x40024000UL
02038 #define NRF_I2S_BASE                    0x40025000UL
02039 #define NRF_FPU_BASE                    0x40026000UL
02040 #define NRF_P0_BASE                     0x50000000UL
02041 
02042 
02043 /* ================================================================================ */
02044 /* ================             Peripheral declaration             ================ */
02045 /* ================================================================================ */
02046 
02047 #define NRF_FICR                        ((NRF_FICR_Type           *) NRF_FICR_BASE)
02048 #define NRF_UICR                        ((NRF_UICR_Type           *) NRF_UICR_BASE)
02049 #define NRF_BPROT                       ((NRF_BPROT_Type          *) NRF_BPROT_BASE)
02050 #define NRF_POWER                       ((NRF_POWER_Type          *) NRF_POWER_BASE)
02051 #define NRF_CLOCK                       ((NRF_CLOCK_Type          *) NRF_CLOCK_BASE)
02052 #define NRF_AMLI                        ((NRF_AMLI_Type           *) NRF_AMLI_BASE)
02053 #define NRF_RADIO                       ((NRF_RADIO_Type          *) NRF_RADIO_BASE)
02054 #define NRF_UARTE0                      ((NRF_UARTE_Type          *) NRF_UARTE0_BASE)
02055 #define NRF_UART0                       ((NRF_UART_Type           *) NRF_UART0_BASE)
02056 #define NRF_SPIM0                       ((NRF_SPIM_Type           *) NRF_SPIM0_BASE)
02057 #define NRF_SPIS0                       ((NRF_SPIS_Type           *) NRF_SPIS0_BASE)
02058 #define NRF_TWIM0                       ((NRF_TWIM_Type           *) NRF_TWIM0_BASE)
02059 #define NRF_TWIS0                       ((NRF_TWIS_Type           *) NRF_TWIS0_BASE)
02060 #define NRF_SPI0                        ((NRF_SPI_Type            *) NRF_SPI0_BASE)
02061 #define NRF_TWI0                        ((NRF_TWI_Type            *) NRF_TWI0_BASE)
02062 #define NRF_SPIM1                       ((NRF_SPIM_Type           *) NRF_SPIM1_BASE)
02063 #define NRF_SPIS1                       ((NRF_SPIS_Type           *) NRF_SPIS1_BASE)
02064 #define NRF_TWIM1                       ((NRF_TWIM_Type           *) NRF_TWIM1_BASE)
02065 #define NRF_TWIS1                       ((NRF_TWIS_Type           *) NRF_TWIS1_BASE)
02066 #define NRF_SPI1                        ((NRF_SPI_Type            *) NRF_SPI1_BASE)
02067 #define NRF_TWI1                        ((NRF_TWI_Type            *) NRF_TWI1_BASE)
02068 #define NRF_NFCT                        ((NRF_NFCT_Type           *) NRF_NFCT_BASE)
02069 #define NRF_GPIOTE                      ((NRF_GPIOTE_Type         *) NRF_GPIOTE_BASE)
02070 #define NRF_SAADC                       ((NRF_SAADC_Type          *) NRF_SAADC_BASE)
02071 #define NRF_TIMER0                      ((NRF_TIMER_Type          *) NRF_TIMER0_BASE)
02072 #define NRF_TIMER1                      ((NRF_TIMER_Type          *) NRF_TIMER1_BASE)
02073 #define NRF_TIMER2                      ((NRF_TIMER_Type          *) NRF_TIMER2_BASE)
02074 #define NRF_RTC0                        ((NRF_RTC_Type            *) NRF_RTC0_BASE)
02075 #define NRF_TEMP                        ((NRF_TEMP_Type           *) NRF_TEMP_BASE)
02076 #define NRF_RNG                         ((NRF_RNG_Type            *) NRF_RNG_BASE)
02077 #define NRF_ECB                         ((NRF_ECB_Type            *) NRF_ECB_BASE)
02078 #define NRF_CCM                         ((NRF_CCM_Type            *) NRF_CCM_BASE)
02079 #define NRF_AAR                         ((NRF_AAR_Type            *) NRF_AAR_BASE)
02080 #define NRF_WDT                         ((NRF_WDT_Type            *) NRF_WDT_BASE)
02081 #define NRF_RTC1                        ((NRF_RTC_Type            *) NRF_RTC1_BASE)
02082 #define NRF_QDEC                        ((NRF_QDEC_Type           *) NRF_QDEC_BASE)
02083 #define NRF_COMP                        ((NRF_COMP_Type           *) NRF_COMP_BASE)
02084 #define NRF_LPCOMP                      ((NRF_LPCOMP_Type         *) NRF_LPCOMP_BASE)
02085 #define NRF_SWI0                        ((NRF_SWI_Type            *) NRF_SWI0_BASE)
02086 #define NRF_EGU0                        ((NRF_EGU_Type            *) NRF_EGU0_BASE)
02087 #define NRF_SWI1                        ((NRF_SWI_Type            *) NRF_SWI1_BASE)
02088 #define NRF_EGU1                        ((NRF_EGU_Type            *) NRF_EGU1_BASE)
02089 #define NRF_SWI2                        ((NRF_SWI_Type            *) NRF_SWI2_BASE)
02090 #define NRF_EGU2                        ((NRF_EGU_Type            *) NRF_EGU2_BASE)
02091 #define NRF_SWI3                        ((NRF_SWI_Type            *) NRF_SWI3_BASE)
02092 #define NRF_EGU3                        ((NRF_EGU_Type            *) NRF_EGU3_BASE)
02093 #define NRF_SWI4                        ((NRF_SWI_Type            *) NRF_SWI4_BASE)
02094 #define NRF_EGU4                        ((NRF_EGU_Type            *) NRF_EGU4_BASE)
02095 #define NRF_SWI5                        ((NRF_SWI_Type            *) NRF_SWI5_BASE)
02096 #define NRF_EGU5                        ((NRF_EGU_Type            *) NRF_EGU5_BASE)
02097 #define NRF_TIMER3                      ((NRF_TIMER_Type          *) NRF_TIMER3_BASE)
02098 #define NRF_TIMER4                      ((NRF_TIMER_Type          *) NRF_TIMER4_BASE)
02099 #define NRF_PWM0                        ((NRF_PWM_Type            *) NRF_PWM0_BASE)
02100 #define NRF_PDM                         ((NRF_PDM_Type            *) NRF_PDM_BASE)
02101 #define NRF_NVMC                        ((NRF_NVMC_Type           *) NRF_NVMC_BASE)
02102 #define NRF_PPI                         ((NRF_PPI_Type            *) NRF_PPI_BASE)
02103 #define NRF_MWU                         ((NRF_MWU_Type            *) NRF_MWU_BASE)
02104 #define NRF_PWM1                        ((NRF_PWM_Type            *) NRF_PWM1_BASE)
02105 #define NRF_PWM2                        ((NRF_PWM_Type            *) NRF_PWM2_BASE)
02106 #define NRF_SPIM2                       ((NRF_SPIM_Type           *) NRF_SPIM2_BASE)
02107 #define NRF_SPIS2                       ((NRF_SPIS_Type           *) NRF_SPIS2_BASE)
02108 #define NRF_SPI2                        ((NRF_SPI_Type            *) NRF_SPI2_BASE)
02109 #define NRF_RTC2                        ((NRF_RTC_Type            *) NRF_RTC2_BASE)
02110 #define NRF_I2S                         ((NRF_I2S_Type            *) NRF_I2S_BASE)
02111 #define NRF_FPU                         ((NRF_FPU_Type            *) NRF_FPU_BASE)
02112 #define NRF_P0                          ((NRF_GPIO_Type           *) NRF_P0_BASE)
02113 
02114 
02115 /** @} */ /* End of group Device_Peripheral_Registers */
02116 /** @} */ /* End of group nrf52 */
02117 /** @} */ /* End of group Nordic Semiconductor */
02118 
02119 #ifdef __cplusplus
02120 }
02121 #endif
02122 
02123 
02124 #endif  /* nrf52_H */
02125 
02126