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nrf52.h File Reference
CMSIS Cortex-M4 Peripheral Access Layer Header File for nrf52 from Nordic Semiconductor. More...
Go to the source code of this file.
Data Structures | |
struct | NRF_FICR_Type |
Factory Information Configuration. More... | |
struct | NRF_UICR_Type |
User Information Configuration. More... | |
struct | NRF_BPROT_Type |
Block Protect (BPROT) More... | |
struct | NRF_POWER_Type |
Power Control. More... | |
struct | NRF_CLOCK_Type |
Clock control. More... | |
struct | NRF_AMLI_Type |
AHB Multi-Layer Interface. More... | |
struct | NRF_RADIO_Type |
The radio. More... | |
struct | NRF_UARTE_Type |
UART with EasyDMA (UARTE) More... | |
struct | NRF_UART_Type |
Universal Asynchronous Receiver/Transmitter. More... | |
struct | NRF_SPIM_Type |
SPI master with easyDMA 1. More... | |
struct | NRF_SPIS_Type |
SPI slave 1. More... | |
struct | NRF_TWIM_Type |
I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM) More... | |
struct | NRF_TWIS_Type |
I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS) More... | |
struct | NRF_SPI_Type |
SPI master 0. More... | |
struct | NRF_TWI_Type |
Two-wire interface master 0. More... | |
struct | NRF_NFCT_Type |
NFC-A compatible radio (NFCT) More... | |
struct | NRF_GPIOTE_Type |
GPIO tasks and events. More... | |
struct | NRF_SAADC_Type |
Analog to Digital Converter (SAADC) More... | |
struct | NRF_TIMER_Type |
Timer 0. More... | |
struct | NRF_RTC_Type |
Real time counter 0. More... | |
struct | NRF_TEMP_Type |
Temperature Sensor. More... | |
struct | NRF_RNG_Type |
Random Number Generator. More... | |
struct | NRF_ECB_Type |
AES ECB Mode Encryption. More... | |
struct | NRF_CCM_Type |
AES CCM Mode Encryption. More... | |
struct | NRF_AAR_Type |
Accelerated Address Resolver. More... | |
struct | NRF_WDT_Type |
Watchdog Timer. More... | |
struct | NRF_QDEC_Type |
Rotary decoder. More... | |
struct | NRF_COMP_Type |
Comparator (COMP) More... | |
struct | NRF_LPCOMP_Type |
Low power comparator. More... | |
struct | NRF_SWI_Type |
SW Interrupts. More... | |
struct | NRF_EGU_Type |
Event Generator Unit 0 (EGU) More... | |
struct | NRF_PWM_Type |
Pulse Width Modulation Unit 0 (PWM) More... | |
struct | NRF_PDM_Type |
Pulse Density Modulation (Digital Microphone) Interface (PDM) More... | |
struct | NRF_NVMC_Type |
Non Volatile Memory Controller. More... | |
struct | NRF_PPI_Type |
PPI controller. More... | |
struct | NRF_MWU_Type |
Memory Watch Unit (MWU) More... | |
struct | NRF_I2S_Type |
Inter-IC Sound (I2S) More... | |
struct | NRF_FPU_Type |
FPU (FPU) More... | |
struct | NRF_GPIO_Type |
General purpose input and output. More... | |
Enumerations | |
enum | IRQn_Type { Reset_IRQn = -15, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, POWER_CLOCK_IRQn = 0, RADIO_IRQn = 1, UART0_IRQn = 2, SPI0_TWI0_IRQn = 3, SPI1_TWI1_IRQn = 4, GPIOTE_IRQn = 6, ADC_IRQn = 7, TIMER0_IRQn = 8, TIMER1_IRQn = 9, TIMER2_IRQn = 10, RTC0_IRQn = 11, TEMP_IRQn = 12, RNG_IRQn = 13, ECB_IRQn = 14, CCM_AAR_IRQn = 15, WDT_IRQn = 16, RTC1_IRQn = 17, QDEC_IRQn = 18, LPCOMP_IRQn = 19, SWI0_IRQn = 20, SWI1_IRQn = 21, SWI2_IRQn = 22, SWI3_IRQn = 23, SWI4_IRQn = 24, SWI5_IRQn = 25, Reset_IRQn = -15, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, POWER_CLOCK_IRQn = 0, RADIO_IRQn = 1, UARTE0_UART0_IRQn = 2, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn = 3, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn = 4, NFCT_IRQn = 5, GPIOTE_IRQn = 6, SAADC_IRQn = 7, TIMER0_IRQn = 8, TIMER1_IRQn = 9, TIMER2_IRQn = 10, RTC0_IRQn = 11, TEMP_IRQn = 12, RNG_IRQn = 13, ECB_IRQn = 14, CCM_AAR_IRQn = 15, WDT_IRQn = 16, RTC1_IRQn = 17, QDEC_IRQn = 18, COMP_LPCOMP_IRQn = 19, SWI0_EGU0_IRQn = 20, SWI1_EGU1_IRQn = 21, SWI2_EGU2_IRQn = 22, SWI3_EGU3_IRQn = 23, SWI4_EGU4_IRQn = 24, SWI5_EGU5_IRQn = 25, TIMER3_IRQn = 26, TIMER4_IRQn = 27, PWM0_IRQn = 28, PDM_IRQn = 29, MWU_IRQn = 32, PWM1_IRQn = 33, PWM2_IRQn = 34, SPIM2_SPIS2_SPI2_IRQn = 35, RTC2_IRQn = 36, I2S_IRQn = 37, FPU_IRQn = 38 } |
Detailed Description
CMSIS Cortex-M4 Peripheral Access Layer Header File for nrf52 from Nordic Semiconductor.
- Version:
- V1
- Date:
- 23. February 2016
- Note:
- Generated with SVDConv V2.81d from CMSIS SVD File 'nrf52.svd' Version 1,
- Copyright (c) 2015, Nordic Semiconductor ASA
- All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
* Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Definition in file nrf52.h.
Generated on Tue Jul 12 2022 14:11:21 by
