Vybhav Kadaba
Minor changes to support ADMW FWv1.17.75
inc/admw1001/ADMW1001_REGISTERS.h
- Committer:
- Vkadaba
- Date:
- 2019-06-05
- Revision:
- 5:0728bde67bdb
- Child:
- 6:9d393a9677f4
File content as of revision 5:0728bde67bdb:
/* ================================================================================
Project : ADMW1000_REGISTERS
File : ADMW1000_REGISTERS.h
Description : Register Definitions
Date : Nov 5, 2018
Copyright (c) 2018 Analog Devices, Inc. All Rights Reserved.
This software is proprietary and confidential to Analog Devices, Inc. and
its licensors.
This file was auto-generated. Do not make local changes to this file.
================================================================================ */
#ifndef _DEF_ADMW1001_REGISTERS_H
#define _DEF_ADMW1001_REGISTERS_H
#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__))
#include <stdint.h>
#endif /* _LANGUAGE_C */
#ifndef __ADI_GENERATED_DEF_HEADERS__
#define __ADI_GENERATED_DEF_HEADERS__ 1
#endif
#define __ADI_HAS_CORE__ 1
#define __ADI_HAS_SPI__ 1
#define __ADI_HAS_TEST__ 1
/* ============================================================================================================================
============================================================================================================================ */
/* ============================================================================================================================
ADMW_SPI
============================================================================================================================ */
#define REG_SPI_INTERFACE_CONFIG_A_RESET 0x00000030 /* Reset Value for Interface_Config_A */
#define REG_SPI_INTERFACE_CONFIG_A 0x00000000 /* ADMW_SPI Interface Configuration A */
#define REG_SPI_INTERFACE_CONFIG_B_RESET 0x00000000 /* Reset Value for Interface_Config_B */
#define REG_SPI_INTERFACE_CONFIG_B 0x00000001 /* ADMW_SPI Interface Configuration B */
#define REG_SPI_DEVICE_CONFIG_RESET 0x00000000 /* Reset Value for Device_Config */
#define REG_SPI_DEVICE_CONFIG 0x00000002 /* ADMW_SPI Device Configuration */
#define REG_SPI_CHIP_TYPE_RESET 0x00000007 /* Reset Value for Chip_Type */
#define REG_SPI_CHIP_TYPE 0x00000003 /* ADMW_SPI Chip Type */
#define REG_SPI_PRODUCT_ID_L_RESET 0x00000020 /* Reset Value for Product_ID_L */
#define REG_SPI_PRODUCT_ID_L 0x00000004 /* ADMW_SPI Product ID Low */
#define REG_SPI_PRODUCT_ID_H_RESET 0x00000000 /* Reset Value for Product_ID_H */
#define REG_SPI_PRODUCT_ID_H 0x00000005 /* ADMW_SPI Product ID High */
#define REG_SPI_CHIP_GRADE_RESET 0x00000000 /* Reset Value for Chip_Grade */
#define REG_SPI_CHIP_GRADE 0x00000006 /* ADMW_SPI Chip Grade */
#define REG_SPI_SCRATCH_PAD_RESET 0x00000000 /* Reset Value for Scratch_Pad */
#define REG_SPI_SCRATCH_PAD 0x0000000A /* ADMW_SPI Scratch Pad */
#define REG_SPI_SPI_REVISION_RESET 0x00000082 /* Reset Value for SPI_Revision */
#define REG_SPI_SPI_REVISION 0x0000000B /* ADMW_SPI SPI Revision */
#define REG_SPI_VENDOR_L_RESET 0x00000056 /* Reset Value for Vendor_L */
#define REG_SPI_VENDOR_L 0x0000000C /* ADMW_SPI Vendor ID Low */
#define REG_SPI_VENDOR_H_RESET 0x00000004 /* Reset Value for Vendor_H */
#define REG_SPI_VENDOR_H 0x0000000D /* ADMW_SPI Vendor ID High */
#define REG_SPI_STREAM_MODE_RESET 0x00000000 /* Reset Value for Stream_Mode */
#define REG_SPI_STREAM_MODE 0x0000000E /* ADMW_SPI Stream Mode */
#define REG_SPI_TRANSFER_CONFIG_RESET 0x00000000 /* Reset Value for Transfer_Config */
#define REG_SPI_TRANSFER_CONFIG 0x0000000F /* ADMW_SPI Transfer Config */
#define REG_SPI_INTERFACE_CONFIG_C_RESET 0x00000033 /* Reset Value for Interface_Config_C */
#define REG_SPI_INTERFACE_CONFIG_C 0x00000010 /* ADMW_SPI Interface Configuration C */
#define REG_SPI_INTERFACE_STATUS_A_RESET 0x00000000 /* Reset Value for Interface_Status_A */
#define REG_SPI_INTERFACE_STATUS_A 0x00000011 /* ADMW_SPI Interface Status A */
/* ============================================================================================================================
ADMW_SPI Register BitMasks, Positions & Enumerations
============================================================================================================================ */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_SPI_INTERFACE_CONFIG_A Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_SPI_INTERFACE_CONFIG_A_SW_RESET 7 /* First of Two of SW_RESET Bits. */
#define BITP_SPI_INTERFACE_CONFIG_A_ADDR_ASCENSION 5 /* Determines Sequential Addressing Behavior */
#define BITP_SPI_INTERFACE_CONFIG_A_SDO_ENABLE 4 /* SDO Pin Enable */
#define BITP_SPI_INTERFACE_CONFIG_A_SW_RESETX 0 /* Second of Two of SW_RESET Bits. */
#define BITM_SPI_INTERFACE_CONFIG_A_SW_RESET 0x00000080 /* First of Two of SW_RESET Bits. */
#define BITM_SPI_INTERFACE_CONFIG_A_ADDR_ASCENSION 0x00000020 /* Determines Sequential Addressing Behavior */
#define BITM_SPI_INTERFACE_CONFIG_A_SDO_ENABLE 0x00000010 /* SDO Pin Enable */
#define BITM_SPI_INTERFACE_CONFIG_A_SW_RESETX 0x00000001 /* Second of Two of SW_RESET Bits. */
#define ENUM_SPI_INTERFACE_CONFIG_A_DESCEND 0x00000000 /* Addr_Ascension: Address accessed is decremented by one for each data byte when streaming */
#define ENUM_SPI_INTERFACE_CONFIG_A_ASCEND 0x00000020 /* Addr_Ascension: Address accessed is incremented by one for each data byte when streaming */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_SPI_INTERFACE_CONFIG_B Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_SPI_SPI_INTERFACE_CONFIG_B_SINGLE_INST 7 /* Select Streaming or Single Instruction Mode */
#define BITM_SPI_INTERFACE_CONFIG_B_SINGLE_INST 0x00000080 /* Select Streaming or Single Instruction Mode */
#define ENUM_SPI_INTERFACE_CONFIG_B_STREAMING_MODE 0x00000000 /* Single_Inst: Streaming mode is enabled */
#define ENUM_SPI_INTERFACE_CONFIG_B_SINGLE_INSTRUCTION_MODE 0x00000080 /* Single_Inst: Single Instruction mode is enabled */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_SPI_DEVICE_CONFIG Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_SPI_SPI_DEVICE_CONFIG_OPERATING_MODES 0 /* Power Modes */
#define BITM_SPI_DEVICE_CONFIG_OPERATING_MODES 0x00000003 /* Power Modes */
#define ENUM_SPI_DEVICE_CONFIG_NORMAL 0x00000000 /* Operating_Modes: Normal Operating Mode */
#define ENUM_SPI_DEVICE_CONFIG_SLEEP 0x00000003 /* Operating_Modes: Low Power Mode */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_SPI_CHIP_TYPE Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_SPI_CHIP_TYPE_CHIP_TYPE 0 /* Precision ADC */
#define BITM_SPI_CHIP_TYPE_CHIP_TYPE 0x0000000F /* Precision ADC */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_SPI_PRODUCT_ID_L Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_SPI_PRODUCT_ID_L_PRODUCT_ID 0 /* This is Device Chip Type/Family */
#define BITM_SPI_PRODUCT_ID_L_PRODUCT_ID 0x000000FF /* This is Device Chip Type/Family */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_SPI_PRODUCT_ID_H Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_SPI_PRODUCT_ID_H_PRODUCT_ID 0 /* This is Device Chip Type/Family */
#define BITM_SPI_PRODUCT_ID_H_PRODUCT_ID 0x000000FF /* This is Device Chip Type/Family */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_SPI_CHIP_GRADE Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_SPI_CHIP_GRADE_GRADE 4 /* This is the Device Performance Grade */
#define BITP_SPI_CHIP_GRADE_DEVICE_REVISION 0 /* This is the Device Hardware Revision */
#define BITM_SPI_CHIP_GRADE_GRADE 0x000000F0 /* This is the Device Performance Grade */
#define BITM_SPI_CHIP_GRADE_DEVICE_REVISION 0x0000000F /* This is the Device Hardware Revision */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_SPI_SCRATCH_PAD Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_SPI_SCRATCH_PAD_SCRATCH_VALUE 0 /* Software Scratchpad */
#define BITM_SPI_SCRATCH_PAD_SCRATCH_VALUE 0x000000FF /* Software Scratchpad */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_SPI_SPI_REVISION Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_SPI_SPI_REVISION_SPI_TYPE 6 /* Always Reads as 0x2 */
#define BITP_SPI_SPI_REVISION_VERSION 0 /* SPI Version */
#define BITM_SPI_SPI_REVISION_SPI_TYPE 0x000000C0 /* Always Reads as 0x2 */
#define BITM_SPI_SPI_REVISION_VERSION 0x0000003F /* SPI Version */
#define ENUM_SPI_SPI_REVISION_ADI_SPI 0x00000000
#define ENUM_SPI_SPI_REVISION_LPT_SPI 0x00000080
#define ENUM_SPI_SPI_REVISION_REV1_0 0x00000002 /* Version: Revision 1.0 */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_SPI_VENDOR_L Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_SPI_VENDOR_L_VID 0 /* Analog Devices Vendor ID */
#define BITM_SPI_VENDOR_L_VID 0x000000FF /* Analog Devices Vendor ID */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_SPI_VENDOR_H Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_SPI_VENDOR_H_VID 0 /* Analog Devices Vendor ID */
#define BITM_SPI_VENDOR_H_VID 0x000000FF /* Analog Devices Vendor ID */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_SPI_STREAM_MODE Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_SPI_STREAM_MODE_LOOP_COUNT 0 /* Sets the Data Byte Count Before Looping to Start Address */
#define BITM_SPI_STREAM_MODE_LOOP_COUNT 0x000000FF /* Sets the Data Byte Count Before Looping to Start Address */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_SPI_TRANSFER_CONFIG Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_SPI_TRANSFER_CONFIG_STREAM_MODE 1 /* When Streaming, Controls Master-Slave Transfer */
#define BITM_SPI_TRANSFER_CONFIG_STREAM_MODE 0x00000002 /* When Streaming, Controls Master-Slave Transfer */
#define ENUM_SPI_TRANSFER_CONFIG_UPDATE_ON_WRITE 0x00000000 /* Stream_Mode: Transfers after each byte/mulit-byte register */
#define ENUM_SPI_TRANSFER_CONFIG_UPDATE_ON_ADDRESS_LOOP 0x00000002 /* Stream_Mode: Transfers when address loops */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_SPI_INTERFACE_CONFIG_C Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_SPI_INTERFACE_CONFIG_C_CRC_ENABLE 6 /* CRC Enable */
#define BITP_SPI_INTERFACE_CONFIG_C_STRICT_REGISTER_ACCESS 5 /* Multi-byte Registers Must Be Read/Written in Full */
#define BITP_SPI_INTERFACE_CONFIG_C_SEND_STATUS 4 /* Enables Sending of Status in 4-wire Mode */
#define BITP_SPI_INTERFACE_CONFIG_C_CRC_ENABLEB 0 /* Inverted CRC Enable */
#define BITM_SPI_INTERFACE_CONFIG_C_CRC_ENABLE 0x000000C0 /* CRC Enable */
#define BITM_SPI_INTERFACE_CONFIG_C_STRICT_REGISTER_ACCESS 0x00000020 /* Multi-byte Registers Must Be Read/Written in Full */
#define BITM_SPI_INTERFACE_CONFIG_C_SEND_STATUS 0x00000010 /* Enables Sending of Status in 4-wire Mode */
#define BITM_SPI_INTERFACE_CONFIG_C_CRC_ENABLEB 0x00000003 /* Inverted CRC Enable */
#define ENUM_SPI_INTERFACE_CONFIG_C_DISABLED 0x00000000 /* CRC_Enable: CRC Disabled */
#define ENUM_SPI_INTERFACE_CONFIG_C_ENABLED 0x00000040 /* CRC_Enable: CRC Enabled */
#define ENUM_SPI_INTERFACE_CONFIG_C_NORMAL_ACCESS 0x00000000 /* Strict_Register_Access: Normal mode, no access restrictions */
#define ENUM_SPI_INTERFACE_CONFIG_C_STRICT_ACCESS 0x00000020 /* Strict_Register_Access: Strict mode, multi-byte registers require all bytes read/written */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_SPI_INTERFACE_STATUS_A Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_SPI_INTERFACE_STATUS_A_NOT_READY_ERROR 7 /* Device Not Ready for Transaction */
#define BITP_SPI_INTERFACE_STATUS_A_CLOCK_COUNT_ERROR 4 /* Incorrect Number of Clocks Detected in a Transaction */
#define BITP_SPI_INTERFACE_STATUS_A_CRC_ERROR 3 /* Invalid/No CRC Received */
#define BITP_SPI_INTERFACE_STATUS_A_WR_TO_RD_ONLY_REG_ERROR 2 /* Write to Read-Only Register Attempted */
#define BITP_SPI_INTERFACE_STATUS_A_REGISTER_PARTIAL_ACCESS_ERROR 1 /* Set When Fewer Than Expected Number of Bytes Read/Written */
#define BITP_SPI_INTERFACE_STATUS_A_ADDRESS_INVALID_ERROR 0 /* Attempt to Read/Write Non-existent Register Address */
#define BITM_SPI_INTERFACE_STATUS_A_NOT_READY_ERROR 0x00000080 /* Device Not Ready for Transaction */
#define BITM_SPI_INTERFACE_STATUS_A_CLOCK_COUNT_ERROR 0x00000010 /* Incorrect Number of Clocks Detected in a Transaction */
#define BITM_SPI_INTERFACE_STATUS_A_CRC_ERROR 0x00000008 /* Invalid/No CRC Received */
#define BITM_SPI_INTERFACE_STATUS_A_WR_TO_RD_ONLY_REG_ERROR 0x00000004 /* Write to Read-Only Register Attempted */
#define BITM_SPI_INTERFACE_STATUS_A_REGISTER_PARTIAL_ACCESS_ERROR 0x00000002 /* Set When Fewer Than Expected Number of Bytes Read/Written */
#define BITM_SPI_INTERFACE_STATUS_A_ADDRESS_INVALID_ERROR 0x00000001 /* Attempt to Read/Write Non-existent Register Address */
/* ============================================================================================================================
ADMW1000 Core Registers
============================================================================================================================ */
/* ============================================================================================================================
ADMW_CORE
============================================================================================================================ */
#define REG_CORE_COMMAND_RESET 0x00000000 /* Reset Value for Command */
#define REG_CORE_COMMAND 0x00000014 /* ADMW_CORE Special Command */
#define REG_CORE_MODE_RESET 0x00000000 /* Reset Value for Mode */
#define REG_CORE_MODE 0x00000016 /* ADMW_CORE Operating Mode and DRDY Control */
#define REG_CORE_POWER_CONFIG_RESET 0x00000000 /* Reset Value for Power_Config */
#define REG_CORE_POWER_CONFIG 0x00000017 /* ADMW_CORE General Configuration */
#define REG_CORE_CYCLE_CONTROL_RESET 0x00000000 /* Reset Value for Cycle_Control */
#define REG_CORE_CYCLE_CONTROL 0x00000018 /* ADMW_CORE Measurement Cycle */
#define REG_CORE_FIFO_NUM_CYCLES_RESET 0x00000001 /* Reset Value for Fifo_Num_Cycles */
#define REG_CORE_FIFO_NUM_CYCLES 0x0000001A /* ADMW_CORE Number of Measurement Cycles to Store in FIFO */
#define REG_CORE_MULTI_CYCLE_REPEAT_INTERVAL_RESET 0x00000000 /* Reset Value for Multi_Cycle_Repeat_Interval */
#define REG_CORE_MULTI_CYCLE_REPEAT_INTERVAL 0x0000001C /* ADMW_CORE Time Between Repeats of Multi-Cycle Conversions.... */
#define REG_CORE_STATUS_RESET 0x00000000 /* Reset Value for Status */
#define REG_CORE_STATUS 0x00000020 /* ADMW_CORE General Status */
#define REG_CORE_DIAGNOSTICS_STATUS_RESET 0x00000000 /* Reset Value for Diagnostics_Status */
#define REG_CORE_DIAGNOSTICS_STATUS 0x00000024 /* ADMW_CORE Diagnostics Status */
#define REG_CORE_CHANNEL_ALERT_STATUS_RESET 0x00000000 /* Reset Value for Channel_Alert_Status */
#define REG_CORE_CHANNEL_ALERT_STATUS 0x00000026 /* ADMW_CORE Alert Status Summary */
#define REG_CORE_ALERT_STATUS_2_RESET 0x00000000 /* Reset Value for Alert_Status_2 */
#define REG_CORE_ALERT_STATUS_2 0x00000028 /* ADMW_CORE Additional Alert Status Information */
#define REG_CORE_ALERT_DETAIL_CHn_RESET 0x00000000 /* Reset Value for Alert_Detail_Ch[n] */
#define REG_CORE_ALERT_DETAIL_CH0_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH0 */
#define REG_CORE_ALERT_DETAIL_CH1_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH1 */
#define REG_CORE_ALERT_DETAIL_CH2_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH2 */
#define REG_CORE_ALERT_DETAIL_CH3_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH3 */
#define REG_CORE_ALERT_DETAIL_CH4_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH4 */
#define REG_CORE_ALERT_DETAIL_CH5_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH5 */
#define REG_CORE_ALERT_DETAIL_CH6_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH6 */
#define REG_CORE_ALERT_DETAIL_CH7_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH7 */
#define REG_CORE_ALERT_DETAIL_CH8_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH8 */
#define REG_CORE_ALERT_DETAIL_CH9_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH9 */
#define REG_CORE_ALERT_DETAIL_CH10_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH10 */
#define REG_CORE_ALERT_DETAIL_CH11_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH11 */
#define REG_CORE_ALERT_DETAIL_CH12_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH12 */
#define REG_CORE_ALERT_DETAIL_CH13_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH13 */
#define REG_CORE_ALERT_DETAIL_CH14_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH14 */
#define REG_CORE_ALERT_DETAIL_CH15_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH15 */
#define REG_CORE_ALERT_DETAIL_CH0 0x0000002A /* ADMW_CORE Detailed Error Information */
#define REG_CORE_ALERT_DETAIL_CH1 0x0000002C /* ADMW_CORE Detailed Error Information */
#define REG_CORE_ALERT_DETAIL_CH2 0x0000002E /* ADMW_CORE Detailed Error Information */
#define REG_CORE_ALERT_DETAIL_CH3 0x00000030 /* ADMW_CORE Detailed Error Information */
#define REG_CORE_ALERT_DETAIL_CH4 0x00000032 /* ADMW_CORE Detailed Error Information */
#define REG_CORE_ALERT_DETAIL_CH5 0x00000034 /* ADMW_CORE Detailed Error Information */
#define REG_CORE_ALERT_DETAIL_CH6 0x00000036 /* ADMW_CORE Detailed Error Information */
#define REG_CORE_ALERT_DETAIL_CH7 0x00000038 /* ADMW_CORE Detailed Error Information */
#define REG_CORE_ALERT_DETAIL_CH8 0x0000003A /* ADMW_CORE Detailed Error Information */
#define REG_CORE_ALERT_DETAIL_CH9 0x0000003C /* ADMW_CORE Detailed Error Information */
#define REG_CORE_ALERT_DETAIL_CH10 0x0000003E /* ADMW_CORE Detailed Error Information */
#define REG_CORE_ALERT_DETAIL_CH11 0x00000040 /* ADMW_CORE Detailed Error Information */
#define REG_CORE_ALERT_DETAIL_CH12 0x00000042 /* ADMW_CORE Detailed Error Information */
#define REG_CORE_ALERT_DETAIL_CH13 0x00000044 /* ADMW_CORE Detailed Error Information */
#define REG_CORE_ALERT_DETAIL_CH14 0x00000046 /* ADMW_CORE Detailed Error Information */
#define REG_CORE_ALERT_DETAIL_CH15 0x00000048 /* ADMW_CORE Detailed Error Information */
#define REG_CORE_ALERT_DETAIL_CHn(i) (REG_CORE_ALERT_DETAIL_CH0 + ((i) * 2))
#define REG_CORE_ALERT_DETAIL_CHn_COUNT 16
#define REG_CORE_ERROR_CODE_RESET 0x00000000 /* Reset Value for Error_Code */
#define REG_CORE_ERROR_CODE 0x0000004C /* ADMW_CORE Code Indicating Source of Error */
#define REG_CORE_ALERT_CODE_RESET 0x00000000 /* Reset Value for Alert_Code */
#define REG_CORE_ALERT_CODE 0x0000004E /* ADMW_CORE Code Indicating Source of Alert */
#define REG_CORE_EXTERNAL_REFERENCE1_RESET 0x00000000 /* Reset Value for External_Reference1 */
#define REG_CORE_EXTERNAL_REFERENCE1 0x00000050 /* ADMW_CORE External Reference Information */
#define REG_CORE_EXTERNAL_REFERENCE2_RESET 0x00000000 /* Reset Value for External_Reference2 */
#define REG_CORE_EXTERNAL_REFERENCE2 0x00000054 /* ADMW_CORE External Reference Information */
#define REG_CORE_DIAGNOSTICS_CONTROL_RESET 0x00000000 /* Reset Value for Diagnostics_Control */
#define REG_CORE_DIAGNOSTICS_CONTROL 0x0000005C /* ADMW_CORE Diagnostic Control */
#define REG_CORE_DATA_FIFO_RESET 0x00000000 /* Reset Value for Data_FIFO */
#define REG_CORE_DATA_FIFO 0x00000060 /* ADMW_CORE FIFO Buffer of Sensor Results */
#define REG_CORE_DEBUG_CODE_RESET 0x00000000 /* Reset Value for Debug_Code */
#define REG_CORE_DEBUG_CODE 0x00000064 /* ADMW_CORE Additional Information on Source of Alert or Errors */
#define REG_CORE_FFT_CONFIG_RESET 0x00000000 /* Reset Value for FFT_Config */
#define REG_CORE_FFT_CONFIG 0x00000068 /* ADMW_CORE FFT Configuration */
#define REG_CORE_ADVANCED_SENSOR_ACCESS_RESET 0x00000000 /* Reset Value for Advanced_Sensor_Access */
#define REG_CORE_ADVANCED_SENSOR_ACCESS 0x0000006E /* ADMW_CORE Enables Access to Advanced Sensor Configuration */
#define REG_CORE_LUT_SELECT_RESET 0x00000000 /* Reset Value for LUT_Select */
#define REG_CORE_LUT_SELECT 0x00000070 /* ADMW_CORE Read/Write Strobe */
#define REG_CORE_LUT_OFFSET_RESET 0x00000000 /* Reset Value for LUT_Offset */
#define REG_CORE_LUT_OFFSET 0x00000072 /* ADMW_CORE Offset into Selected LUT */
#define REG_CORE_LUT_DATA_RESET 0x00000000 /* Reset Value for LUT_Data */
#define REG_CORE_LUT_DATA 0x00000074 /* ADMW_CORE Data to Read/Write from Addressed LUT Entry */
#define REG_CORE_EXT_FLASH_INDEX_RESET 0x00000000 /* Reset Value for Ext_Flash_Index */
#define REG_CORE_EXT_FLASH_INDEX 0x00000080 /* ADMW_CORE Start Position (Sample No.) for Retrieval of Ext. Flash Data */
#define REG_CORE_EXT_FLASH_SAMPLE_COUNT_RESET 0x00000000 /* Reset Value for Ext_Flash_Sample_Count */
#define REG_CORE_EXT_FLASH_SAMPLE_COUNT 0x00000084 /* ADMW_CORE Indicates How Many Samples Stored in External Flash */
#define REG_CORE_EXT_FLASH_DATA_RESET 0x00000000 /* Reset Value for Ext_Flash_Data */
#define REG_CORE_EXT_FLASH_DATA 0x00000088 /* ADMW_CORE Data Read Back from External Flash */
#define REG_CORE_REVISION_RESET 0x00000000 /* Reset Value for Revision */
#define REG_CORE_REVISION 0x0000008C /* ADMW_CORE Hardware, Firmware Revision */
#define REG_CORE_CHANNEL_COUNTn_RESET 0x00000000 /* Reset Value for Channel_Count[n] */
#define REG_CORE_CHANNEL_COUNT0_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT0 */
#define REG_CORE_CHANNEL_COUNT1_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT1 */
#define REG_CORE_CHANNEL_COUNT2_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT2 */
#define REG_CORE_CHANNEL_COUNT3_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT3 */
#define REG_CORE_CHANNEL_COUNT4_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT4 */
#define REG_CORE_CHANNEL_COUNT5_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT5 */
#define REG_CORE_CHANNEL_COUNT6_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT6 */
#define REG_CORE_CHANNEL_COUNT7_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT7 */
#define REG_CORE_CHANNEL_COUNT8_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT8 */
#define REG_CORE_CHANNEL_COUNT9_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT9 */
#define REG_CORE_CHANNEL_COUNT10_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT10 */
#define REG_CORE_CHANNEL_COUNT11_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT11 */
#define REG_CORE_CHANNEL_COUNT12_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT12 */
#define REG_CORE_CHANNEL_COUNT13_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT13 */
#define REG_CORE_CHANNEL_COUNT14_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT14 */
#define REG_CORE_CHANNEL_COUNT15_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT15 */
#define REG_CORE_CHANNEL_COUNT0 0x00000090 /* ADMW_CORE Number of Channel Occurrences per Measurement Cycle */
#define REG_CORE_CHANNEL_COUNT1 0x000000D0 /* ADMW_CORE Number of Channel Occurrences per Measurement Cycle */
#define REG_CORE_CHANNEL_COUNT2 0x00000110 /* ADMW_CORE Number of Channel Occurrences per Measurement Cycle */
#define REG_CORE_CHANNEL_COUNT3 0x00000150 /* ADMW_CORE Number of Channel Occurrences per Measurement Cycle */
#define REG_CORE_CHANNEL_COUNT4 0x00000190 /* ADMW_CORE Number of Channel Occurrences per Measurement Cycle */
#define REG_CORE_CHANNEL_COUNT5 0x000001D0 /* ADMW_CORE Number of Channel Occurrences per Measurement Cycle */
#define REG_CORE_CHANNEL_COUNT6 0x00000210 /* ADMW_CORE Number of Channel Occurrences per Measurement Cycle */
#define REG_CORE_CHANNEL_COUNT7 0x00000250 /* ADMW_CORE Number of Channel Occurrences per Measurement Cycle */
#define REG_CORE_CHANNEL_COUNT8 0x00000290 /* ADMW_CORE Number of Channel Occurrences per Measurement Cycle */
#define REG_CORE_CHANNEL_COUNT9 0x000002D0 /* ADMW_CORE Number of Channel Occurrences per Measurement Cycle */
#define REG_CORE_CHANNEL_COUNT10 0x00000310 /* ADMW_CORE Number of Channel Occurrences per Measurement Cycle */
#define REG_CORE_CHANNEL_COUNT11 0x00000350 /* ADMW_CORE Number of Channel Occurrences per Measurement Cycle */
#define REG_CORE_CHANNEL_COUNT12 0x00000390 /* ADMW_CORE Number of Channel Occurrences per Measurement Cycle */
#define REG_CORE_CHANNEL_COUNT13 0x000003D0 /* ADMW_CORE Number of Channel Occurrences per Measurement Cycle */
#define REG_CORE_CHANNEL_COUNT14 0x00000410 /* ADMW_CORE Number of Channel Occurrences per Measurement Cycle */
#define REG_CORE_CHANNEL_COUNT15 0x00000450 /* ADMW_CORE Number of Channel Occurrences per Measurement Cycle */
#define REG_CORE_CHANNEL_COUNTn(i) (REG_CORE_CHANNEL_COUNT0 + ((i) * 64))
#define REG_CORE_CHANNEL_COUNTn_COUNT 16
#define REG_CORE_CHANNEL_OPTIONSn_RESET 0x00000000 /* Reset Value for Channel_Options[n] */
#define REG_CORE_CHANNEL_OPTIONS0_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS0 */
#define REG_CORE_CHANNEL_OPTIONS1_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS1 */
#define REG_CORE_CHANNEL_OPTIONS2_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS2 */
#define REG_CORE_CHANNEL_OPTIONS3_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS3 */
#define REG_CORE_CHANNEL_OPTIONS4_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS4 */
#define REG_CORE_CHANNEL_OPTIONS5_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS5 */
#define REG_CORE_CHANNEL_OPTIONS6_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS6 */
#define REG_CORE_CHANNEL_OPTIONS7_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS7 */
#define REG_CORE_CHANNEL_OPTIONS8_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS8 */
#define REG_CORE_CHANNEL_OPTIONS9_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS9 */
#define REG_CORE_CHANNEL_OPTIONS10_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS10 */
#define REG_CORE_CHANNEL_OPTIONS11_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS11 */
#define REG_CORE_CHANNEL_OPTIONS12_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS12 */
#define REG_CORE_CHANNEL_OPTIONS13_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS13 */
#define REG_CORE_CHANNEL_OPTIONS14_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS14 */
#define REG_CORE_CHANNEL_OPTIONS15_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS15 */
#define REG_CORE_CHANNEL_OPTIONS0 0x00000091 /* ADMW_CORE Position of Channel Within Sequence and Enable for FFT */
#define REG_CORE_CHANNEL_OPTIONS1 0x000000D1 /* ADMW_CORE Position of Channel Within Sequence and Enable for FFT */
#define REG_CORE_CHANNEL_OPTIONS2 0x00000111 /* ADMW_CORE Position of Channel Within Sequence and Enable for FFT */
#define REG_CORE_CHANNEL_OPTIONS3 0x00000151 /* ADMW_CORE Position of Channel Within Sequence and Enable for FFT */
#define REG_CORE_CHANNEL_OPTIONS4 0x00000191 /* ADMW_CORE Position of Channel Within Sequence and Enable for FFT */
#define REG_CORE_CHANNEL_OPTIONS5 0x000001D1 /* ADMW_CORE Position of Channel Within Sequence and Enable for FFT */
#define REG_CORE_CHANNEL_OPTIONS6 0x00000211 /* ADMW_CORE Position of Channel Within Sequence and Enable for FFT */
#define REG_CORE_CHANNEL_OPTIONS7 0x00000251 /* ADMW_CORE Position of Channel Within Sequence and Enable for FFT */
#define REG_CORE_CHANNEL_OPTIONS8 0x00000291 /* ADMW_CORE Position of Channel Within Sequence and Enable for FFT */
#define REG_CORE_CHANNEL_OPTIONS9 0x000002D1 /* ADMW_CORE Position of Channel Within Sequence and Enable for FFT */
#define REG_CORE_CHANNEL_OPTIONS10 0x00000311 /* ADMW_CORE Position of Channel Within Sequence and Enable for FFT */
#define REG_CORE_CHANNEL_OPTIONS11 0x00000351 /* ADMW_CORE Position of Channel Within Sequence and Enable for FFT */
#define REG_CORE_CHANNEL_OPTIONS12 0x00000391 /* ADMW_CORE Position of Channel Within Sequence and Enable for FFT */
#define REG_CORE_CHANNEL_OPTIONS13 0x000003D1 /* ADMW_CORE Position of Channel Within Sequence and Enable for FFT */
#define REG_CORE_CHANNEL_OPTIONS14 0x00000411 /* ADMW_CORE Position of Channel Within Sequence and Enable for FFT */
#define REG_CORE_CHANNEL_OPTIONS15 0x00000451 /* ADMW_CORE Position of Channel Within Sequence and Enable for FFT */
#define REG_CORE_CHANNEL_OPTIONSn(i) (REG_CORE_CHANNEL_OPTIONS0 + ((i) * 64))
#define REG_CORE_CHANNEL_OPTIONSn_COUNT 16
#define REG_CORE_SENSOR_TYPEn_RESET 0x00000000 /* Reset Value for Sensor_Type[n] */
#define REG_CORE_SENSOR_TYPE0_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE0 */
#define REG_CORE_SENSOR_TYPE1_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE1 */
#define REG_CORE_SENSOR_TYPE2_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE2 */
#define REG_CORE_SENSOR_TYPE3_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE3 */
#define REG_CORE_SENSOR_TYPE4_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE4 */
#define REG_CORE_SENSOR_TYPE5_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE5 */
#define REG_CORE_SENSOR_TYPE6_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE6 */
#define REG_CORE_SENSOR_TYPE7_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE7 */
#define REG_CORE_SENSOR_TYPE8_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE8 */
#define REG_CORE_SENSOR_TYPE9_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE9 */
#define REG_CORE_SENSOR_TYPE10_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE10 */
#define REG_CORE_SENSOR_TYPE11_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE11 */
#define REG_CORE_SENSOR_TYPE12_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE12 */
#define REG_CORE_SENSOR_TYPE13_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE13 */
#define REG_CORE_SENSOR_TYPE14_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE14 */
#define REG_CORE_SENSOR_TYPE15_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE15 */
#define REG_CORE_SENSOR_TYPE0 0x00000092 /* ADMW_CORE Sensor Select */
#define REG_CORE_SENSOR_TYPE1 0x000000D2 /* ADMW_CORE Sensor Select */
#define REG_CORE_SENSOR_TYPE2 0x00000112 /* ADMW_CORE Sensor Select */
#define REG_CORE_SENSOR_TYPE3 0x00000152 /* ADMW_CORE Sensor Select */
#define REG_CORE_SENSOR_TYPE4 0x00000192 /* ADMW_CORE Sensor Select */
#define REG_CORE_SENSOR_TYPE5 0x000001D2 /* ADMW_CORE Sensor Select */
#define REG_CORE_SENSOR_TYPE6 0x00000212 /* ADMW_CORE Sensor Select */
#define REG_CORE_SENSOR_TYPE7 0x00000252 /* ADMW_CORE Sensor Select */
#define REG_CORE_SENSOR_TYPE8 0x00000292 /* ADMW_CORE Sensor Select */
#define REG_CORE_SENSOR_TYPE9 0x000002D2 /* ADMW_CORE Sensor Select */
#define REG_CORE_SENSOR_TYPE10 0x00000312 /* ADMW_CORE Sensor Select */
#define REG_CORE_SENSOR_TYPE11 0x00000352 /* ADMW_CORE Sensor Select */
#define REG_CORE_SENSOR_TYPE12 0x00000392 /* ADMW_CORE Sensor Select */
#define REG_CORE_SENSOR_TYPE13 0x000003D2 /* ADMW_CORE Sensor Select */
#define REG_CORE_SENSOR_TYPE14 0x00000412 /* ADMW_CORE Sensor Select */
#define REG_CORE_SENSOR_TYPE15 0x00000452 /* ADMW_CORE Sensor Select */
#define REG_CORE_SENSOR_TYPEn(i) (REG_CORE_SENSOR_TYPE0 + ((i) * 64))
#define REG_CORE_SENSOR_TYPEn_COUNT 16
#define REG_CORE_SENSOR_DETAILSn_RESET 0x0000FFF0 /* Reset Value for Sensor_Details[n] */
#define REG_CORE_SENSOR_DETAILS0_RESET 0x0000FFF0 /* Reset Value for REG_CORE_SENSOR_DETAILS0 */
#define REG_CORE_SENSOR_DETAILS1_RESET 0x0000FFF0 /* Reset Value for REG_CORE_SENSOR_DETAILS1 */
#define REG_CORE_SENSOR_DETAILS2_RESET 0x0000FFF0 /* Reset Value for REG_CORE_SENSOR_DETAILS2 */
#define REG_CORE_SENSOR_DETAILS3_RESET 0x0000FFF0 /* Reset Value for REG_CORE_SENSOR_DETAILS3 */
#define REG_CORE_SENSOR_DETAILS4_RESET 0x0000FFF0 /* Reset Value for REG_CORE_SENSOR_DETAILS4 */
#define REG_CORE_SENSOR_DETAILS5_RESET 0x0000FFF0 /* Reset Value for REG_CORE_SENSOR_DETAILS5 */
#define REG_CORE_SENSOR_DETAILS6_RESET 0x0000FFF0 /* Reset Value for REG_CORE_SENSOR_DETAILS6 */
#define REG_CORE_SENSOR_DETAILS7_RESET 0x0000FFF0 /* Reset Value for REG_CORE_SENSOR_DETAILS7 */
#define REG_CORE_SENSOR_DETAILS8_RESET 0x0000FFF0 /* Reset Value for REG_CORE_SENSOR_DETAILS8 */
#define REG_CORE_SENSOR_DETAILS9_RESET 0x0000FFF0 /* Reset Value for REG_CORE_SENSOR_DETAILS9 */
#define REG_CORE_SENSOR_DETAILS10_RESET 0x0000FFF0 /* Reset Value for REG_CORE_SENSOR_DETAILS10 */
#define REG_CORE_SENSOR_DETAILS11_RESET 0x0000FFF0 /* Reset Value for REG_CORE_SENSOR_DETAILS11 */
#define REG_CORE_SENSOR_DETAILS12_RESET 0x0000FFF0 /* Reset Value for REG_CORE_SENSOR_DETAILS12 */
#define REG_CORE_SENSOR_DETAILS13_RESET 0x0000FFF0 /* Reset Value for REG_CORE_SENSOR_DETAILS13 */
#define REG_CORE_SENSOR_DETAILS14_RESET 0x0000FFF0 /* Reset Value for REG_CORE_SENSOR_DETAILS14 */
#define REG_CORE_SENSOR_DETAILS15_RESET 0x0000FFF0 /* Reset Value for REG_CORE_SENSOR_DETAILS15 */
#define REG_CORE_SENSOR_DETAILS0 0x00000094 /* ADMW_CORE Sensor Details */
#define REG_CORE_SENSOR_DETAILS1 0x000000D4 /* ADMW_CORE Sensor Details */
#define REG_CORE_SENSOR_DETAILS2 0x00000114 /* ADMW_CORE Sensor Details */
#define REG_CORE_SENSOR_DETAILS3 0x00000154 /* ADMW_CORE Sensor Details */
#define REG_CORE_SENSOR_DETAILS4 0x00000194 /* ADMW_CORE Sensor Details */
#define REG_CORE_SENSOR_DETAILS5 0x000001D4 /* ADMW_CORE Sensor Details */
#define REG_CORE_SENSOR_DETAILS6 0x00000214 /* ADMW_CORE Sensor Details */
#define REG_CORE_SENSOR_DETAILS7 0x00000254 /* ADMW_CORE Sensor Details */
#define REG_CORE_SENSOR_DETAILS8 0x00000294 /* ADMW_CORE Sensor Details */
#define REG_CORE_SENSOR_DETAILS9 0x000002D4 /* ADMW_CORE Sensor Details */
#define REG_CORE_SENSOR_DETAILS10 0x00000314 /* ADMW_CORE Sensor Details */
#define REG_CORE_SENSOR_DETAILS11 0x00000354 /* ADMW_CORE Sensor Details */
#define REG_CORE_SENSOR_DETAILS12 0x00000394 /* ADMW_CORE Sensor Details */
#define REG_CORE_SENSOR_DETAILS13 0x000003D4 /* ADMW_CORE Sensor Details */
#define REG_CORE_SENSOR_DETAILS14 0x00000414 /* ADMW_CORE Sensor Details */
#define REG_CORE_SENSOR_DETAILS15 0x00000454 /* ADMW_CORE Sensor Details */
#define REG_CORE_SENSOR_DETAILSn(i) (REG_CORE_SENSOR_DETAILS0 + ((i) * 64))
#define REG_CORE_SENSOR_DETAILSn_COUNT 16
#define REG_CORE_CHANNEL_EXCITATIONn_RESET 0x00000000 /* Reset Value for Channel_Excitation[n] */
#define REG_CORE_CHANNEL_EXCITATION0_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION0 */
#define REG_CORE_CHANNEL_EXCITATION1_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION1 */
#define REG_CORE_CHANNEL_EXCITATION2_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION2 */
#define REG_CORE_CHANNEL_EXCITATION3_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION3 */
#define REG_CORE_CHANNEL_EXCITATION4_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION4 */
#define REG_CORE_CHANNEL_EXCITATION5_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION5 */
#define REG_CORE_CHANNEL_EXCITATION6_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION6 */
#define REG_CORE_CHANNEL_EXCITATION7_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION7 */
#define REG_CORE_CHANNEL_EXCITATION8_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION8 */
#define REG_CORE_CHANNEL_EXCITATION9_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION9 */
#define REG_CORE_CHANNEL_EXCITATION10_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION10 */
#define REG_CORE_CHANNEL_EXCITATION11_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION11 */
#define REG_CORE_CHANNEL_EXCITATION12_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION12 */
#define REG_CORE_CHANNEL_EXCITATION13_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION13 */
#define REG_CORE_CHANNEL_EXCITATION14_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION14 */
#define REG_CORE_CHANNEL_EXCITATION15_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION15 */
#define REG_CORE_CHANNEL_EXCITATION0 0x00000098 /* ADMW_CORE Excitation Current */
#define REG_CORE_CHANNEL_EXCITATION1 0x000000D8 /* ADMW_CORE Excitation Current */
#define REG_CORE_CHANNEL_EXCITATION2 0x00000118 /* ADMW_CORE Excitation Current */
#define REG_CORE_CHANNEL_EXCITATION3 0x00000158 /* ADMW_CORE Excitation Current */
#define REG_CORE_CHANNEL_EXCITATION4 0x00000198 /* ADMW_CORE Excitation Current */
#define REG_CORE_CHANNEL_EXCITATION5 0x000001D8 /* ADMW_CORE Excitation Current */
#define REG_CORE_CHANNEL_EXCITATION6 0x00000218 /* ADMW_CORE Excitation Current */
#define REG_CORE_CHANNEL_EXCITATION7 0x00000258 /* ADMW_CORE Excitation Current */
#define REG_CORE_CHANNEL_EXCITATION8 0x00000298 /* ADMW_CORE Excitation Current */
#define REG_CORE_CHANNEL_EXCITATION9 0x000002D8 /* ADMW_CORE Excitation Current */
#define REG_CORE_CHANNEL_EXCITATION10 0x00000318 /* ADMW_CORE Excitation Current */
#define REG_CORE_CHANNEL_EXCITATION11 0x00000358 /* ADMW_CORE Excitation Current */
#define REG_CORE_CHANNEL_EXCITATION12 0x00000398 /* ADMW_CORE Excitation Current */
#define REG_CORE_CHANNEL_EXCITATION13 0x000003D8 /* ADMW_CORE Excitation Current */
#define REG_CORE_CHANNEL_EXCITATION14 0x00000418 /* ADMW_CORE Excitation Current */
#define REG_CORE_CHANNEL_EXCITATION15 0x00000458 /* ADMW_CORE Excitation Current */
#define REG_CORE_CHANNEL_EXCITATIONn(i) (REG_CORE_CHANNEL_EXCITATION0 + ((i) * 64))
#define REG_CORE_CHANNEL_EXCITATIONn_COUNT 16
#define REG_CORE_SETTLING_TIMEn_RESET 0x00000000 /* Reset Value for Settling_Time[n] */
#define REG_CORE_SETTLING_TIME0_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME0 */
#define REG_CORE_SETTLING_TIME1_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME1 */
#define REG_CORE_SETTLING_TIME2_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME2 */
#define REG_CORE_SETTLING_TIME3_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME3 */
#define REG_CORE_SETTLING_TIME4_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME4 */
#define REG_CORE_SETTLING_TIME5_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME5 */
#define REG_CORE_SETTLING_TIME6_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME6 */
#define REG_CORE_SETTLING_TIME7_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME7 */
#define REG_CORE_SETTLING_TIME8_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME8 */
#define REG_CORE_SETTLING_TIME9_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME9 */
#define REG_CORE_SETTLING_TIME10_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME10 */
#define REG_CORE_SETTLING_TIME11_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME11 */
#define REG_CORE_SETTLING_TIME12_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME12 */
#define REG_CORE_SETTLING_TIME13_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME13 */
#define REG_CORE_SETTLING_TIME14_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME14 */
#define REG_CORE_SETTLING_TIME15_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME15 */
#define REG_CORE_SETTLING_TIME0 0x0000009A /* ADMW_CORE Settling Time */
#define REG_CORE_SETTLING_TIME1 0x000000DA /* ADMW_CORE Settling Time */
#define REG_CORE_SETTLING_TIME2 0x0000011A /* ADMW_CORE Settling Time */
#define REG_CORE_SETTLING_TIME3 0x0000015A /* ADMW_CORE Settling Time */
#define REG_CORE_SETTLING_TIME4 0x0000019A /* ADMW_CORE Settling Time */
#define REG_CORE_SETTLING_TIME5 0x000001DA /* ADMW_CORE Settling Time */
#define REG_CORE_SETTLING_TIME6 0x0000021A /* ADMW_CORE Settling Time */
#define REG_CORE_SETTLING_TIME7 0x0000025A /* ADMW_CORE Settling Time */
#define REG_CORE_SETTLING_TIME8 0x0000029A /* ADMW_CORE Settling Time */
#define REG_CORE_SETTLING_TIME9 0x000002DA /* ADMW_CORE Settling Time */
#define REG_CORE_SETTLING_TIME10 0x0000031A /* ADMW_CORE Settling Time */
#define REG_CORE_SETTLING_TIME11 0x0000035A /* ADMW_CORE Settling Time */
#define REG_CORE_SETTLING_TIME12 0x0000039A /* ADMW_CORE Settling Time */
#define REG_CORE_SETTLING_TIME13 0x000003DA /* ADMW_CORE Settling Time */
#define REG_CORE_SETTLING_TIME14 0x0000041A /* ADMW_CORE Settling Time */
#define REG_CORE_SETTLING_TIME15 0x0000045A /* ADMW_CORE Settling Time */
#define REG_CORE_SETTLING_TIMEn(i) (REG_CORE_SETTLING_TIME0 + ((i) * 64))
#define REG_CORE_SETTLING_TIMEn_COUNT 16
#define REG_CORE_FILTER_SELECTn_RESET 0x00000000 /* Reset Value for Filter_Select[n] */
#define REG_CORE_FILTER_SELECT0_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT0 */
#define REG_CORE_FILTER_SELECT1_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT1 */
#define REG_CORE_FILTER_SELECT2_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT2 */
#define REG_CORE_FILTER_SELECT3_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT3 */
#define REG_CORE_FILTER_SELECT4_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT4 */
#define REG_CORE_FILTER_SELECT5_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT5 */
#define REG_CORE_FILTER_SELECT6_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT6 */
#define REG_CORE_FILTER_SELECT7_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT7 */
#define REG_CORE_FILTER_SELECT8_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT8 */
#define REG_CORE_FILTER_SELECT9_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT9 */
#define REG_CORE_FILTER_SELECT10_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT10 */
#define REG_CORE_FILTER_SELECT11_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT11 */
#define REG_CORE_FILTER_SELECT12_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT12 */
#define REG_CORE_FILTER_SELECT13_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT13 */
#define REG_CORE_FILTER_SELECT14_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT14 */
#define REG_CORE_FILTER_SELECT15_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT15 */
#define REG_CORE_FILTER_SELECT0 0x0000009C /* ADMW_CORE ADC Digital Filter Selection */
#define REG_CORE_FILTER_SELECT1 0x000000DC /* ADMW_CORE ADC Digital Filter Selection */
#define REG_CORE_FILTER_SELECT2 0x0000011C /* ADMW_CORE ADC Digital Filter Selection */
#define REG_CORE_FILTER_SELECT3 0x0000015C /* ADMW_CORE ADC Digital Filter Selection */
#define REG_CORE_FILTER_SELECT4 0x0000019C /* ADMW_CORE ADC Digital Filter Selection */
#define REG_CORE_FILTER_SELECT5 0x000001DC /* ADMW_CORE ADC Digital Filter Selection */
#define REG_CORE_FILTER_SELECT6 0x0000021C /* ADMW_CORE ADC Digital Filter Selection */
#define REG_CORE_FILTER_SELECT7 0x0000025C /* ADMW_CORE ADC Digital Filter Selection */
#define REG_CORE_FILTER_SELECT8 0x0000029C /* ADMW_CORE ADC Digital Filter Selection */
#define REG_CORE_FILTER_SELECT9 0x000002DC /* ADMW_CORE ADC Digital Filter Selection */
#define REG_CORE_FILTER_SELECT10 0x0000031C /* ADMW_CORE ADC Digital Filter Selection */
#define REG_CORE_FILTER_SELECT11 0x0000035C /* ADMW_CORE ADC Digital Filter Selection */
#define REG_CORE_FILTER_SELECT12 0x0000039C /* ADMW_CORE ADC Digital Filter Selection */
#define REG_CORE_FILTER_SELECT13 0x000003DC /* ADMW_CORE ADC Digital Filter Selection */
#define REG_CORE_FILTER_SELECT14 0x0000041C /* ADMW_CORE ADC Digital Filter Selection */
#define REG_CORE_FILTER_SELECT15 0x0000045C /* ADMW_CORE ADC Digital Filter Selection */
#define REG_CORE_FILTER_SELECTn(i) (REG_CORE_FILTER_SELECT0 + ((i) * 64))
#define REG_CORE_FILTER_SELECTn_COUNT 16
#define REG_CORE_HIGH_THRESHOLD_LIMITn_RESET 0x7F800000 /* Reset Value for High_Threshold_Limit[n] */
#define REG_CORE_HIGH_THRESHOLD_LIMIT0_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT0 */
#define REG_CORE_HIGH_THRESHOLD_LIMIT1_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT1 */
#define REG_CORE_HIGH_THRESHOLD_LIMIT2_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT2 */
#define REG_CORE_HIGH_THRESHOLD_LIMIT3_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT3 */
#define REG_CORE_HIGH_THRESHOLD_LIMIT4_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT4 */
#define REG_CORE_HIGH_THRESHOLD_LIMIT5_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT5 */
#define REG_CORE_HIGH_THRESHOLD_LIMIT6_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT6 */
#define REG_CORE_HIGH_THRESHOLD_LIMIT7_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT7 */
#define REG_CORE_HIGH_THRESHOLD_LIMIT8_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT8 */
#define REG_CORE_HIGH_THRESHOLD_LIMIT9_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT9 */
#define REG_CORE_HIGH_THRESHOLD_LIMIT10_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT10 */
#define REG_CORE_HIGH_THRESHOLD_LIMIT11_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT11 */
#define REG_CORE_HIGH_THRESHOLD_LIMIT12_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT12 */
#define REG_CORE_HIGH_THRESHOLD_LIMIT13_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT13 */
#define REG_CORE_HIGH_THRESHOLD_LIMIT14_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT14 */
#define REG_CORE_HIGH_THRESHOLD_LIMIT15_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT15 */
#define REG_CORE_HIGH_THRESHOLD_LIMIT0 0x000000A0 /* ADMW_CORE High Threshold */
#define REG_CORE_HIGH_THRESHOLD_LIMIT1 0x000000E0 /* ADMW_CORE High Threshold */
#define REG_CORE_HIGH_THRESHOLD_LIMIT2 0x00000120 /* ADMW_CORE High Threshold */
#define REG_CORE_HIGH_THRESHOLD_LIMIT3 0x00000160 /* ADMW_CORE High Threshold */
#define REG_CORE_HIGH_THRESHOLD_LIMIT4 0x000001A0 /* ADMW_CORE High Threshold */
#define REG_CORE_HIGH_THRESHOLD_LIMIT5 0x000001E0 /* ADMW_CORE High Threshold */
#define REG_CORE_HIGH_THRESHOLD_LIMIT6 0x00000220 /* ADMW_CORE High Threshold */
#define REG_CORE_HIGH_THRESHOLD_LIMIT7 0x00000260 /* ADMW_CORE High Threshold */
#define REG_CORE_HIGH_THRESHOLD_LIMIT8 0x000002A0 /* ADMW_CORE High Threshold */
#define REG_CORE_HIGH_THRESHOLD_LIMIT9 0x000002E0 /* ADMW_CORE High Threshold */
#define REG_CORE_HIGH_THRESHOLD_LIMIT10 0x00000320 /* ADMW_CORE High Threshold */
#define REG_CORE_HIGH_THRESHOLD_LIMIT11 0x00000360 /* ADMW_CORE High Threshold */
#define REG_CORE_HIGH_THRESHOLD_LIMIT12 0x000003A0 /* ADMW_CORE High Threshold */
#define REG_CORE_HIGH_THRESHOLD_LIMIT13 0x000003E0 /* ADMW_CORE High Threshold */
#define REG_CORE_HIGH_THRESHOLD_LIMIT14 0x00000420 /* ADMW_CORE High Threshold */
#define REG_CORE_HIGH_THRESHOLD_LIMIT15 0x00000460 /* ADMW_CORE High Threshold */
#define REG_CORE_HIGH_THRESHOLD_LIMITn(i) (REG_CORE_HIGH_THRESHOLD_LIMIT0 + ((i) * 64))
#define REG_CORE_HIGH_THRESHOLD_LIMITn_COUNT 16
#define REG_CORE_LOW_THRESHOLD_LIMITn_RESET 0xFF800000 /* Reset Value for Low_Threshold_Limit[n] */
#define REG_CORE_LOW_THRESHOLD_LIMIT0_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT0 */
#define REG_CORE_LOW_THRESHOLD_LIMIT1_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT1 */
#define REG_CORE_LOW_THRESHOLD_LIMIT2_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT2 */
#define REG_CORE_LOW_THRESHOLD_LIMIT3_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT3 */
#define REG_CORE_LOW_THRESHOLD_LIMIT4_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT4 */
#define REG_CORE_LOW_THRESHOLD_LIMIT5_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT5 */
#define REG_CORE_LOW_THRESHOLD_LIMIT6_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT6 */
#define REG_CORE_LOW_THRESHOLD_LIMIT7_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT7 */
#define REG_CORE_LOW_THRESHOLD_LIMIT8_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT8 */
#define REG_CORE_LOW_THRESHOLD_LIMIT9_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT9 */
#define REG_CORE_LOW_THRESHOLD_LIMIT10_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT10 */
#define REG_CORE_LOW_THRESHOLD_LIMIT11_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT11 */
#define REG_CORE_LOW_THRESHOLD_LIMIT12_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT12 */
#define REG_CORE_LOW_THRESHOLD_LIMIT13_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT13 */
#define REG_CORE_LOW_THRESHOLD_LIMIT14_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT14 */
#define REG_CORE_LOW_THRESHOLD_LIMIT15_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT15 */
#define REG_CORE_LOW_THRESHOLD_LIMIT0 0x000000A4 /* ADMW_CORE Low Threshold */
#define REG_CORE_LOW_THRESHOLD_LIMIT1 0x000000E4 /* ADMW_CORE Low Threshold */
#define REG_CORE_LOW_THRESHOLD_LIMIT2 0x00000124 /* ADMW_CORE Low Threshold */
#define REG_CORE_LOW_THRESHOLD_LIMIT3 0x00000164 /* ADMW_CORE Low Threshold */
#define REG_CORE_LOW_THRESHOLD_LIMIT4 0x000001A4 /* ADMW_CORE Low Threshold */
#define REG_CORE_LOW_THRESHOLD_LIMIT5 0x000001E4 /* ADMW_CORE Low Threshold */
#define REG_CORE_LOW_THRESHOLD_LIMIT6 0x00000224 /* ADMW_CORE Low Threshold */
#define REG_CORE_LOW_THRESHOLD_LIMIT7 0x00000264 /* ADMW_CORE Low Threshold */
#define REG_CORE_LOW_THRESHOLD_LIMIT8 0x000002A4 /* ADMW_CORE Low Threshold */
#define REG_CORE_LOW_THRESHOLD_LIMIT9 0x000002E4 /* ADMW_CORE Low Threshold */
#define REG_CORE_LOW_THRESHOLD_LIMIT10 0x00000324 /* ADMW_CORE Low Threshold */
#define REG_CORE_LOW_THRESHOLD_LIMIT11 0x00000364 /* ADMW_CORE Low Threshold */
#define REG_CORE_LOW_THRESHOLD_LIMIT12 0x000003A4 /* ADMW_CORE Low Threshold */
#define REG_CORE_LOW_THRESHOLD_LIMIT13 0x000003E4 /* ADMW_CORE Low Threshold */
#define REG_CORE_LOW_THRESHOLD_LIMIT14 0x00000424 /* ADMW_CORE Low Threshold */
#define REG_CORE_LOW_THRESHOLD_LIMIT15 0x00000464 /* ADMW_CORE Low Threshold */
#define REG_CORE_LOW_THRESHOLD_LIMITn(i) (REG_CORE_LOW_THRESHOLD_LIMIT0 + ((i) * 64))
#define REG_CORE_LOW_THRESHOLD_LIMITn_COUNT 16
#define REG_CORE_SENSOR_OFFSETn_RESET 0x00000000 /* Reset Value for Sensor_Offset[n] */
#define REG_CORE_SENSOR_OFFSET0_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET0 */
#define REG_CORE_SENSOR_OFFSET1_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET1 */
#define REG_CORE_SENSOR_OFFSET2_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET2 */
#define REG_CORE_SENSOR_OFFSET3_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET3 */
#define REG_CORE_SENSOR_OFFSET4_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET4 */
#define REG_CORE_SENSOR_OFFSET5_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET5 */
#define REG_CORE_SENSOR_OFFSET6_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET6 */
#define REG_CORE_SENSOR_OFFSET7_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET7 */
#define REG_CORE_SENSOR_OFFSET8_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET8 */
#define REG_CORE_SENSOR_OFFSET9_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET9 */
#define REG_CORE_SENSOR_OFFSET10_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET10 */
#define REG_CORE_SENSOR_OFFSET11_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET11 */
#define REG_CORE_SENSOR_OFFSET12_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET12 */
#define REG_CORE_SENSOR_OFFSET13_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET13 */
#define REG_CORE_SENSOR_OFFSET14_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET14 */
#define REG_CORE_SENSOR_OFFSET15_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET15 */
#define REG_CORE_SENSOR_OFFSET0 0x000000A8 /* ADMW_CORE Sensor Offset Adjustment */
#define REG_CORE_SENSOR_OFFSET1 0x000000E8 /* ADMW_CORE Sensor Offset Adjustment */
#define REG_CORE_SENSOR_OFFSET2 0x00000128 /* ADMW_CORE Sensor Offset Adjustment */
#define REG_CORE_SENSOR_OFFSET3 0x00000168 /* ADMW_CORE Sensor Offset Adjustment */
#define REG_CORE_SENSOR_OFFSET4 0x000001A8 /* ADMW_CORE Sensor Offset Adjustment */
#define REG_CORE_SENSOR_OFFSET5 0x000001E8 /* ADMW_CORE Sensor Offset Adjustment */
#define REG_CORE_SENSOR_OFFSET6 0x00000228 /* ADMW_CORE Sensor Offset Adjustment */
#define REG_CORE_SENSOR_OFFSET7 0x00000268 /* ADMW_CORE Sensor Offset Adjustment */
#define REG_CORE_SENSOR_OFFSET8 0x000002A8 /* ADMW_CORE Sensor Offset Adjustment */
#define REG_CORE_SENSOR_OFFSET9 0x000002E8 /* ADMW_CORE Sensor Offset Adjustment */
#define REG_CORE_SENSOR_OFFSET10 0x00000328 /* ADMW_CORE Sensor Offset Adjustment */
#define REG_CORE_SENSOR_OFFSET11 0x00000368 /* ADMW_CORE Sensor Offset Adjustment */
#define REG_CORE_SENSOR_OFFSET12 0x000003A8 /* ADMW_CORE Sensor Offset Adjustment */
#define REG_CORE_SENSOR_OFFSET13 0x000003E8 /* ADMW_CORE Sensor Offset Adjustment */
#define REG_CORE_SENSOR_OFFSET14 0x00000428 /* ADMW_CORE Sensor Offset Adjustment */
#define REG_CORE_SENSOR_OFFSET15 0x00000468 /* ADMW_CORE Sensor Offset Adjustment */
#define REG_CORE_SENSOR_OFFSETn(i) (REG_CORE_SENSOR_OFFSET0 + ((i) * 64))
#define REG_CORE_SENSOR_OFFSETn_COUNT 16
#define REG_CORE_SENSOR_GAINn_RESET 0x3F800000 /* Reset Value for Sensor_Gain[n] */
#define REG_CORE_SENSOR_GAIN0_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN0 */
#define REG_CORE_SENSOR_GAIN1_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN1 */
#define REG_CORE_SENSOR_GAIN2_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN2 */
#define REG_CORE_SENSOR_GAIN3_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN3 */
#define REG_CORE_SENSOR_GAIN4_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN4 */
#define REG_CORE_SENSOR_GAIN5_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN5 */
#define REG_CORE_SENSOR_GAIN6_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN6 */
#define REG_CORE_SENSOR_GAIN7_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN7 */
#define REG_CORE_SENSOR_GAIN8_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN8 */
#define REG_CORE_SENSOR_GAIN9_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN9 */
#define REG_CORE_SENSOR_GAIN10_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN10 */
#define REG_CORE_SENSOR_GAIN11_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN11 */
#define REG_CORE_SENSOR_GAIN12_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN12 */
#define REG_CORE_SENSOR_GAIN13_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN13 */
#define REG_CORE_SENSOR_GAIN14_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN14 */
#define REG_CORE_SENSOR_GAIN15_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN15 */
#define REG_CORE_SENSOR_GAIN0 0x000000AC /* ADMW_CORE Sensor Gain Adjustment */
#define REG_CORE_SENSOR_GAIN1 0x000000EC /* ADMW_CORE Sensor Gain Adjustment */
#define REG_CORE_SENSOR_GAIN2 0x0000012C /* ADMW_CORE Sensor Gain Adjustment */
#define REG_CORE_SENSOR_GAIN3 0x0000016C /* ADMW_CORE Sensor Gain Adjustment */
#define REG_CORE_SENSOR_GAIN4 0x000001AC /* ADMW_CORE Sensor Gain Adjustment */
#define REG_CORE_SENSOR_GAIN5 0x000001EC /* ADMW_CORE Sensor Gain Adjustment */
#define REG_CORE_SENSOR_GAIN6 0x0000022C /* ADMW_CORE Sensor Gain Adjustment */
#define REG_CORE_SENSOR_GAIN7 0x0000026C /* ADMW_CORE Sensor Gain Adjustment */
#define REG_CORE_SENSOR_GAIN8 0x000002AC /* ADMW_CORE Sensor Gain Adjustment */
#define REG_CORE_SENSOR_GAIN9 0x000002EC /* ADMW_CORE Sensor Gain Adjustment */
#define REG_CORE_SENSOR_GAIN10 0x0000032C /* ADMW_CORE Sensor Gain Adjustment */
#define REG_CORE_SENSOR_GAIN11 0x0000036C /* ADMW_CORE Sensor Gain Adjustment */
#define REG_CORE_SENSOR_GAIN12 0x000003AC /* ADMW_CORE Sensor Gain Adjustment */
#define REG_CORE_SENSOR_GAIN13 0x000003EC /* ADMW_CORE Sensor Gain Adjustment */
#define REG_CORE_SENSOR_GAIN14 0x0000042C /* ADMW_CORE Sensor Gain Adjustment */
#define REG_CORE_SENSOR_GAIN15 0x0000046C /* ADMW_CORE Sensor Gain Adjustment */
#define REG_CORE_SENSOR_GAINn(i) (REG_CORE_SENSOR_GAIN0 + ((i) * 64))
#define REG_CORE_SENSOR_GAINn_COUNT 16
#define REG_CORE_ALERT_CODE_CHn_RESET 0x00000000 /* Reset Value for Alert_Code_Ch[n] */
#define REG_CORE_ALERT_CODE_CH0_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH0 */
#define REG_CORE_ALERT_CODE_CH1_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH1 */
#define REG_CORE_ALERT_CODE_CH2_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH2 */
#define REG_CORE_ALERT_CODE_CH3_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH3 */
#define REG_CORE_ALERT_CODE_CH4_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH4 */
#define REG_CORE_ALERT_CODE_CH5_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH5 */
#define REG_CORE_ALERT_CODE_CH6_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH6 */
#define REG_CORE_ALERT_CODE_CH7_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH7 */
#define REG_CORE_ALERT_CODE_CH8_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH8 */
#define REG_CORE_ALERT_CODE_CH9_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH9 */
#define REG_CORE_ALERT_CODE_CH10_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH10 */
#define REG_CORE_ALERT_CODE_CH11_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH11 */
#define REG_CORE_ALERT_CODE_CH12_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH12 */
#define REG_CORE_ALERT_CODE_CH13_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH13 */
#define REG_CORE_ALERT_CODE_CH14_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH14 */
#define REG_CORE_ALERT_CODE_CH15_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH15 */
#define REG_CORE_ALERT_CODE_CH0 0x000000B0 /* ADMW_CORE Per-Channel Detailed Alert-Code Information */
#define REG_CORE_ALERT_CODE_CH1 0x000000F0 /* ADMW_CORE Per-Channel Detailed Alert-Code Information */
#define REG_CORE_ALERT_CODE_CH2 0x00000130 /* ADMW_CORE Per-Channel Detailed Alert-Code Information */
#define REG_CORE_ALERT_CODE_CH3 0x00000170 /* ADMW_CORE Per-Channel Detailed Alert-Code Information */
#define REG_CORE_ALERT_CODE_CH4 0x000001B0 /* ADMW_CORE Per-Channel Detailed Alert-Code Information */
#define REG_CORE_ALERT_CODE_CH5 0x000001F0 /* ADMW_CORE Per-Channel Detailed Alert-Code Information */
#define REG_CORE_ALERT_CODE_CH6 0x00000230 /* ADMW_CORE Per-Channel Detailed Alert-Code Information */
#define REG_CORE_ALERT_CODE_CH7 0x00000270 /* ADMW_CORE Per-Channel Detailed Alert-Code Information */
#define REG_CORE_ALERT_CODE_CH8 0x000002B0 /* ADMW_CORE Per-Channel Detailed Alert-Code Information */
#define REG_CORE_ALERT_CODE_CH9 0x000002F0 /* ADMW_CORE Per-Channel Detailed Alert-Code Information */
#define REG_CORE_ALERT_CODE_CH10 0x00000330 /* ADMW_CORE Per-Channel Detailed Alert-Code Information */
#define REG_CORE_ALERT_CODE_CH11 0x00000370 /* ADMW_CORE Per-Channel Detailed Alert-Code Information */
#define REG_CORE_ALERT_CODE_CH12 0x000003B0 /* ADMW_CORE Per-Channel Detailed Alert-Code Information */
#define REG_CORE_ALERT_CODE_CH13 0x000003F0 /* ADMW_CORE Per-Channel Detailed Alert-Code Information */
#define REG_CORE_ALERT_CODE_CH14 0x00000430 /* ADMW_CORE Per-Channel Detailed Alert-Code Information */
#define REG_CORE_ALERT_CODE_CH15 0x00000470 /* ADMW_CORE Per-Channel Detailed Alert-Code Information */
#define REG_CORE_ALERT_CODE_CHn(i) (REG_CORE_ALERT_CODE_CH0 + ((i) * 64))
#define REG_CORE_ALERT_CODE_CHn_COUNT 16
#define REG_CORE_CHANNEL_SKIPn_RESET 0x00000000 /* Reset Value for Channel_Skip[n] */
#define REG_CORE_CHANNEL_SKIP0_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP0 */
#define REG_CORE_CHANNEL_SKIP1_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP1 */
#define REG_CORE_CHANNEL_SKIP2_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP2 */
#define REG_CORE_CHANNEL_SKIP3_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP3 */
#define REG_CORE_CHANNEL_SKIP4_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP4 */
#define REG_CORE_CHANNEL_SKIP5_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP5 */
#define REG_CORE_CHANNEL_SKIP6_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP6 */
#define REG_CORE_CHANNEL_SKIP7_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP7 */
#define REG_CORE_CHANNEL_SKIP8_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP8 */
#define REG_CORE_CHANNEL_SKIP9_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP9 */
#define REG_CORE_CHANNEL_SKIP10_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP10 */
#define REG_CORE_CHANNEL_SKIP11_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP11 */
#define REG_CORE_CHANNEL_SKIP12_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP12 */
#define REG_CORE_CHANNEL_SKIP13_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP13 */
#define REG_CORE_CHANNEL_SKIP14_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP14 */
#define REG_CORE_CHANNEL_SKIP15_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP15 */
#define REG_CORE_CHANNEL_SKIP0 0x000000B2 /* ADMW_CORE Indicates If Channel Will Skip Some Measurement Cycles */
#define REG_CORE_CHANNEL_SKIP1 0x000000F2 /* ADMW_CORE Indicates If Channel Will Skip Some Measurement Cycles */
#define REG_CORE_CHANNEL_SKIP2 0x00000132 /* ADMW_CORE Indicates If Channel Will Skip Some Measurement Cycles */
#define REG_CORE_CHANNEL_SKIP3 0x00000172 /* ADMW_CORE Indicates If Channel Will Skip Some Measurement Cycles */
#define REG_CORE_CHANNEL_SKIP4 0x000001B2 /* ADMW_CORE Indicates If Channel Will Skip Some Measurement Cycles */
#define REG_CORE_CHANNEL_SKIP5 0x000001F2 /* ADMW_CORE Indicates If Channel Will Skip Some Measurement Cycles */
#define REG_CORE_CHANNEL_SKIP6 0x00000232 /* ADMW_CORE Indicates If Channel Will Skip Some Measurement Cycles */
#define REG_CORE_CHANNEL_SKIP7 0x00000272 /* ADMW_CORE Indicates If Channel Will Skip Some Measurement Cycles */
#define REG_CORE_CHANNEL_SKIP8 0x000002B2 /* ADMW_CORE Indicates If Channel Will Skip Some Measurement Cycles */
#define REG_CORE_CHANNEL_SKIP9 0x000002F2 /* ADMW_CORE Indicates If Channel Will Skip Some Measurement Cycles */
#define REG_CORE_CHANNEL_SKIP10 0x00000332 /* ADMW_CORE Indicates If Channel Will Skip Some Measurement Cycles */
#define REG_CORE_CHANNEL_SKIP11 0x00000372 /* ADMW_CORE Indicates If Channel Will Skip Some Measurement Cycles */
#define REG_CORE_CHANNEL_SKIP12 0x000003B2 /* ADMW_CORE Indicates If Channel Will Skip Some Measurement Cycles */
#define REG_CORE_CHANNEL_SKIP13 0x000003F2 /* ADMW_CORE Indicates If Channel Will Skip Some Measurement Cycles */
#define REG_CORE_CHANNEL_SKIP14 0x00000432 /* ADMW_CORE Indicates If Channel Will Skip Some Measurement Cycles */
#define REG_CORE_CHANNEL_SKIP15 0x00000472 /* ADMW_CORE Indicates If Channel Will Skip Some Measurement Cycles */
#define REG_CORE_CHANNEL_SKIPn(i) (REG_CORE_CHANNEL_SKIP0 + ((i) * 64))
#define REG_CORE_CHANNEL_SKIPn_COUNT 16
#define REG_CORE_SENSOR_PARAMETERn_RESET 0x7FC00000 /* Reset Value for Sensor_Parameter[n] */
#define REG_CORE_SENSOR_PARAMETER0_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER0 */
#define REG_CORE_SENSOR_PARAMETER1_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER1 */
#define REG_CORE_SENSOR_PARAMETER2_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER2 */
#define REG_CORE_SENSOR_PARAMETER3_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER3 */
#define REG_CORE_SENSOR_PARAMETER4_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER4 */
#define REG_CORE_SENSOR_PARAMETER5_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER5 */
#define REG_CORE_SENSOR_PARAMETER6_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER6 */
#define REG_CORE_SENSOR_PARAMETER7_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER7 */
#define REG_CORE_SENSOR_PARAMETER8_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER8 */
#define REG_CORE_SENSOR_PARAMETER9_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER9 */
#define REG_CORE_SENSOR_PARAMETER10_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER10 */
#define REG_CORE_SENSOR_PARAMETER11_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER11 */
#define REG_CORE_SENSOR_PARAMETER12_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER12 */
#define REG_CORE_SENSOR_PARAMETER13_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER13 */
#define REG_CORE_SENSOR_PARAMETER14_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER14 */
#define REG_CORE_SENSOR_PARAMETER15_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER15 */
#define REG_CORE_SENSOR_PARAMETER0 0x000000B4 /* ADMW_CORE Sensor Parameter Adjustment */
#define REG_CORE_SENSOR_PARAMETER1 0x000000F4 /* ADMW_CORE Sensor Parameter Adjustment */
#define REG_CORE_SENSOR_PARAMETER2 0x00000134 /* ADMW_CORE Sensor Parameter Adjustment */
#define REG_CORE_SENSOR_PARAMETER3 0x00000174 /* ADMW_CORE Sensor Parameter Adjustment */
#define REG_CORE_SENSOR_PARAMETER4 0x000001B4 /* ADMW_CORE Sensor Parameter Adjustment */
#define REG_CORE_SENSOR_PARAMETER5 0x000001F4 /* ADMW_CORE Sensor Parameter Adjustment */
#define REG_CORE_SENSOR_PARAMETER6 0x00000234 /* ADMW_CORE Sensor Parameter Adjustment */
#define REG_CORE_SENSOR_PARAMETER7 0x00000274 /* ADMW_CORE Sensor Parameter Adjustment */
#define REG_CORE_SENSOR_PARAMETER8 0x000002B4 /* ADMW_CORE Sensor Parameter Adjustment */
#define REG_CORE_SENSOR_PARAMETER9 0x000002F4 /* ADMW_CORE Sensor Parameter Adjustment */
#define REG_CORE_SENSOR_PARAMETER10 0x00000334 /* ADMW_CORE Sensor Parameter Adjustment */
#define REG_CORE_SENSOR_PARAMETER11 0x00000374 /* ADMW_CORE Sensor Parameter Adjustment */
#define REG_CORE_SENSOR_PARAMETER12 0x000003B4 /* ADMW_CORE Sensor Parameter Adjustment */
#define REG_CORE_SENSOR_PARAMETER13 0x000003F4 /* ADMW_CORE Sensor Parameter Adjustment */
#define REG_CORE_SENSOR_PARAMETER14 0x00000434 /* ADMW_CORE Sensor Parameter Adjustment */
#define REG_CORE_SENSOR_PARAMETER15 0x00000474 /* ADMW_CORE Sensor Parameter Adjustment */
#define REG_CORE_SENSOR_PARAMETERn(i) (REG_CORE_SENSOR_PARAMETER0 + ((i) * 64))
#define REG_CORE_SENSOR_PARAMETERn_COUNT 16
#define REG_CORE_CALIBRATION_PARAMETERn_RESET 0x00000000 /* Reset Value for Calibration_Parameter[n] */
#define REG_CORE_CALIBRATION_PARAMETER0_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER0 */
#define REG_CORE_CALIBRATION_PARAMETER1_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER1 */
#define REG_CORE_CALIBRATION_PARAMETER2_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER2 */
#define REG_CORE_CALIBRATION_PARAMETER3_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER3 */
#define REG_CORE_CALIBRATION_PARAMETER4_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER4 */
#define REG_CORE_CALIBRATION_PARAMETER5_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER5 */
#define REG_CORE_CALIBRATION_PARAMETER6_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER6 */
#define REG_CORE_CALIBRATION_PARAMETER7_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER7 */
#define REG_CORE_CALIBRATION_PARAMETER8_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER8 */
#define REG_CORE_CALIBRATION_PARAMETER9_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER9 */
#define REG_CORE_CALIBRATION_PARAMETER10_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER10 */
#define REG_CORE_CALIBRATION_PARAMETER11_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER11 */
#define REG_CORE_CALIBRATION_PARAMETER12_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER12 */
#define REG_CORE_CALIBRATION_PARAMETER13_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER13 */
#define REG_CORE_CALIBRATION_PARAMETER14_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER14 */
#define REG_CORE_CALIBRATION_PARAMETER15_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER15 */
#define REG_CORE_CALIBRATION_PARAMETER0 0x000000B8 /* ADMW_CORE Calibration Parameter Value */
#define REG_CORE_CALIBRATION_PARAMETER1 0x000000F8 /* ADMW_CORE Calibration Parameter Value */
#define REG_CORE_CALIBRATION_PARAMETER2 0x00000138 /* ADMW_CORE Calibration Parameter Value */
#define REG_CORE_CALIBRATION_PARAMETER3 0x00000178 /* ADMW_CORE Calibration Parameter Value */
#define REG_CORE_CALIBRATION_PARAMETER4 0x000001B8 /* ADMW_CORE Calibration Parameter Value */
#define REG_CORE_CALIBRATION_PARAMETER5 0x000001F8 /* ADMW_CORE Calibration Parameter Value */
#define REG_CORE_CALIBRATION_PARAMETER6 0x00000238 /* ADMW_CORE Calibration Parameter Value */
#define REG_CORE_CALIBRATION_PARAMETER7 0x00000278 /* ADMW_CORE Calibration Parameter Value */
#define REG_CORE_CALIBRATION_PARAMETER8 0x000002B8 /* ADMW_CORE Calibration Parameter Value */
#define REG_CORE_CALIBRATION_PARAMETER9 0x000002F8 /* ADMW_CORE Calibration Parameter Value */
#define REG_CORE_CALIBRATION_PARAMETER10 0x00000338 /* ADMW_CORE Calibration Parameter Value */
#define REG_CORE_CALIBRATION_PARAMETER11 0x00000378 /* ADMW_CORE Calibration Parameter Value */
#define REG_CORE_CALIBRATION_PARAMETER12 0x000003B8 /* ADMW_CORE Calibration Parameter Value */
#define REG_CORE_CALIBRATION_PARAMETER13 0x000003F8 /* ADMW_CORE Calibration Parameter Value */
#define REG_CORE_CALIBRATION_PARAMETER14 0x00000438 /* ADMW_CORE Calibration Parameter Value */
#define REG_CORE_CALIBRATION_PARAMETER15 0x00000478 /* ADMW_CORE Calibration Parameter Value */
#define REG_CORE_CALIBRATION_PARAMETERn(i) (REG_CORE_CALIBRATION_PARAMETER0 + ((i) * 64))
#define REG_CORE_CALIBRATION_PARAMETERn_COUNT 16
#define REG_CORE_DIGITAL_SENSOR_CONFIGn_RESET 0x00000000 /* Reset Value for Digital_Sensor_Config[n] */
#define REG_CORE_DIGITAL_SENSOR_CONFIG0_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG0 */
#define REG_CORE_DIGITAL_SENSOR_CONFIG1_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG1 */
#define REG_CORE_DIGITAL_SENSOR_CONFIG2_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG2 */
#define REG_CORE_DIGITAL_SENSOR_CONFIG3_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG3 */
#define REG_CORE_DIGITAL_SENSOR_CONFIG4_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG4 */
#define REG_CORE_DIGITAL_SENSOR_CONFIG5_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG5 */
#define REG_CORE_DIGITAL_SENSOR_CONFIG6_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG6 */
#define REG_CORE_DIGITAL_SENSOR_CONFIG7_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG7 */
#define REG_CORE_DIGITAL_SENSOR_CONFIG8_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG8 */
#define REG_CORE_DIGITAL_SENSOR_CONFIG9_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG9 */
#define REG_CORE_DIGITAL_SENSOR_CONFIG10_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG10 */
#define REG_CORE_DIGITAL_SENSOR_CONFIG11_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG11 */
#define REG_CORE_DIGITAL_SENSOR_CONFIG12_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG12 */
#define REG_CORE_DIGITAL_SENSOR_CONFIG13_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG13 */
#define REG_CORE_DIGITAL_SENSOR_CONFIG14_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG14 */
#define REG_CORE_DIGITAL_SENSOR_CONFIG15_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG15 */
#define REG_CORE_DIGITAL_SENSOR_CONFIG0 0x000000BC /* ADMW_CORE Digital Sensor Data Coding */
#define REG_CORE_DIGITAL_SENSOR_CONFIG1 0x000000FC /* ADMW_CORE Digital Sensor Data Coding */
#define REG_CORE_DIGITAL_SENSOR_CONFIG2 0x0000013C /* ADMW_CORE Digital Sensor Data Coding */
#define REG_CORE_DIGITAL_SENSOR_CONFIG3 0x0000017C /* ADMW_CORE Digital Sensor Data Coding */
#define REG_CORE_DIGITAL_SENSOR_CONFIG4 0x000001BC /* ADMW_CORE Digital Sensor Data Coding */
#define REG_CORE_DIGITAL_SENSOR_CONFIG5 0x000001FC /* ADMW_CORE Digital Sensor Data Coding */
#define REG_CORE_DIGITAL_SENSOR_CONFIG6 0x0000023C /* ADMW_CORE Digital Sensor Data Coding */
#define REG_CORE_DIGITAL_SENSOR_CONFIG7 0x0000027C /* ADMW_CORE Digital Sensor Data Coding */
#define REG_CORE_DIGITAL_SENSOR_CONFIG8 0x000002BC /* ADMW_CORE Digital Sensor Data Coding */
#define REG_CORE_DIGITAL_SENSOR_CONFIG9 0x000002FC /* ADMW_CORE Digital Sensor Data Coding */
#define REG_CORE_DIGITAL_SENSOR_CONFIG10 0x0000033C /* ADMW_CORE Digital Sensor Data Coding */
#define REG_CORE_DIGITAL_SENSOR_CONFIG11 0x0000037C /* ADMW_CORE Digital Sensor Data Coding */
#define REG_CORE_DIGITAL_SENSOR_CONFIG12 0x000003BC /* ADMW_CORE Digital Sensor Data Coding */
#define REG_CORE_DIGITAL_SENSOR_CONFIG13 0x000003FC /* ADMW_CORE Digital Sensor Data Coding */
#define REG_CORE_DIGITAL_SENSOR_CONFIG14 0x0000043C /* ADMW_CORE Digital Sensor Data Coding */
#define REG_CORE_DIGITAL_SENSOR_CONFIG15 0x0000047C /* ADMW_CORE Digital Sensor Data Coding */
#define REG_CORE_DIGITAL_SENSOR_CONFIGn(i) (REG_CORE_DIGITAL_SENSOR_CONFIG0 + ((i) * 64))
#define REG_CORE_DIGITAL_SENSOR_CONFIGn_COUNT 16
#define REG_CORE_DIGITAL_SENSOR_ADDRESSn_RESET 0x00000000 /* Reset Value for Digital_Sensor_Address[n] */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS0_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS0 */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS1_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS1 */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS2_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS2 */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS3_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS3 */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS4_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS4 */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS5_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS5 */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS6_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS6 */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS7_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS7 */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS8_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS8 */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS9_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS9 */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS10_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS10 */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS11_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS11 */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS12_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS12 */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS13_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS13 */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS14_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS14 */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS15_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS15 */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS0 0x000000BE /* ADMW_CORE Sensor Address */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS1 0x000000FE /* ADMW_CORE Sensor Address */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS2 0x0000013E /* ADMW_CORE Sensor Address */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS3 0x0000017E /* ADMW_CORE Sensor Address */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS4 0x000001BE /* ADMW_CORE Sensor Address */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS5 0x000001FE /* ADMW_CORE Sensor Address */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS6 0x0000023E /* ADMW_CORE Sensor Address */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS7 0x0000027E /* ADMW_CORE Sensor Address */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS8 0x000002BE /* ADMW_CORE Sensor Address */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS9 0x000002FE /* ADMW_CORE Sensor Address */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS10 0x0000033E /* ADMW_CORE Sensor Address */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS11 0x0000037E /* ADMW_CORE Sensor Address */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS12 0x000003BE /* ADMW_CORE Sensor Address */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS13 0x000003FE /* ADMW_CORE Sensor Address */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS14 0x0000043E /* ADMW_CORE Sensor Address */
#define REG_CORE_DIGITAL_SENSOR_ADDRESS15 0x0000047E /* ADMW_CORE Sensor Address */
#define REG_CORE_DIGITAL_SENSOR_ADDRESSn(i) (REG_CORE_DIGITAL_SENSOR_ADDRESS0 + ((i) * 64))
#define REG_CORE_DIGITAL_SENSOR_ADDRESSn_COUNT 16
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDSn_RESET 0x00000000 /* Reset Value for Digital_Sensor_Num_Cmds[n] */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS0_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS0 */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS1_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS1 */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS2_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS2 */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS3_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS3 */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS4_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS4 */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS5_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS5 */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS6_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS6 */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS7_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS7 */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS8_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS8 */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS9_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS9 */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS10_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS10 */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS11_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS11 */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS12_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS12 */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS13_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS13 */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS14_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS14 */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS15_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS15 */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS0 0x000000BF /* ADMW_CORE Number of Configuration, Read Commands for Digital Sensors */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS1 0x000000FF /* ADMW_CORE Number of Configuration, Read Commands for Digital Sensors */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS2 0x0000013F /* ADMW_CORE Number of Configuration, Read Commands for Digital Sensors */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS3 0x0000017F /* ADMW_CORE Number of Configuration, Read Commands for Digital Sensors */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS4 0x000001BF /* ADMW_CORE Number of Configuration, Read Commands for Digital Sensors */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS5 0x000001FF /* ADMW_CORE Number of Configuration, Read Commands for Digital Sensors */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS6 0x0000023F /* ADMW_CORE Number of Configuration, Read Commands for Digital Sensors */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS7 0x0000027F /* ADMW_CORE Number of Configuration, Read Commands for Digital Sensors */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS8 0x000002BF /* ADMW_CORE Number of Configuration, Read Commands for Digital Sensors */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS9 0x000002FF /* ADMW_CORE Number of Configuration, Read Commands for Digital Sensors */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS10 0x0000033F /* ADMW_CORE Number of Configuration, Read Commands for Digital Sensors */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS11 0x0000037F /* ADMW_CORE Number of Configuration, Read Commands for Digital Sensors */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS12 0x000003BF /* ADMW_CORE Number of Configuration, Read Commands for Digital Sensors */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS13 0x000003FF /* ADMW_CORE Number of Configuration, Read Commands for Digital Sensors */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS14 0x0000043F /* ADMW_CORE Number of Configuration, Read Commands for Digital Sensors */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS15 0x0000047F /* ADMW_CORE Number of Configuration, Read Commands for Digital Sensors */
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDSn(i) (REG_CORE_DIGITAL_SENSOR_NUM_CMDS0 + ((i) * 64))
#define REG_CORE_DIGITAL_SENSOR_NUM_CMDSn_COUNT 16
#define REG_CORE_DIGITAL_SENSOR_COMMSn_RESET 0x00000006 /* Reset Value for Digital_Sensor_Comms[n] */
#define REG_CORE_DIGITAL_SENSOR_COMMS0_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS0 */
#define REG_CORE_DIGITAL_SENSOR_COMMS1_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS1 */
#define REG_CORE_DIGITAL_SENSOR_COMMS2_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS2 */
#define REG_CORE_DIGITAL_SENSOR_COMMS3_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS3 */
#define REG_CORE_DIGITAL_SENSOR_COMMS4_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS4 */
#define REG_CORE_DIGITAL_SENSOR_COMMS5_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS5 */
#define REG_CORE_DIGITAL_SENSOR_COMMS6_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS6 */
#define REG_CORE_DIGITAL_SENSOR_COMMS7_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS7 */
#define REG_CORE_DIGITAL_SENSOR_COMMS8_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS8 */
#define REG_CORE_DIGITAL_SENSOR_COMMS9_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS9 */
#define REG_CORE_DIGITAL_SENSOR_COMMS10_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS10 */
#define REG_CORE_DIGITAL_SENSOR_COMMS11_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS11 */
#define REG_CORE_DIGITAL_SENSOR_COMMS12_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS12 */
#define REG_CORE_DIGITAL_SENSOR_COMMS13_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS13 */
#define REG_CORE_DIGITAL_SENSOR_COMMS14_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS14 */
#define REG_CORE_DIGITAL_SENSOR_COMMS15_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS15 */
#define REG_CORE_DIGITAL_SENSOR_COMMS0 0x000000C0 /* ADMW_CORE Digital Sensor Communication Clock Configuration */
#define REG_CORE_DIGITAL_SENSOR_COMMS1 0x00000100 /* ADMW_CORE Digital Sensor Communication Clock Configuration */
#define REG_CORE_DIGITAL_SENSOR_COMMS2 0x00000140 /* ADMW_CORE Digital Sensor Communication Clock Configuration */
#define REG_CORE_DIGITAL_SENSOR_COMMS3 0x00000180 /* ADMW_CORE Digital Sensor Communication Clock Configuration */
#define REG_CORE_DIGITAL_SENSOR_COMMS4 0x000001C0 /* ADMW_CORE Digital Sensor Communication Clock Configuration */
#define REG_CORE_DIGITAL_SENSOR_COMMS5 0x00000200 /* ADMW_CORE Digital Sensor Communication Clock Configuration */
#define REG_CORE_DIGITAL_SENSOR_COMMS6 0x00000240 /* ADMW_CORE Digital Sensor Communication Clock Configuration */
#define REG_CORE_DIGITAL_SENSOR_COMMS7 0x00000280 /* ADMW_CORE Digital Sensor Communication Clock Configuration */
#define REG_CORE_DIGITAL_SENSOR_COMMS8 0x000002C0 /* ADMW_CORE Digital Sensor Communication Clock Configuration */
#define REG_CORE_DIGITAL_SENSOR_COMMS9 0x00000300 /* ADMW_CORE Digital Sensor Communication Clock Configuration */
#define REG_CORE_DIGITAL_SENSOR_COMMS10 0x00000340 /* ADMW_CORE Digital Sensor Communication Clock Configuration */
#define REG_CORE_DIGITAL_SENSOR_COMMS11 0x00000380 /* ADMW_CORE Digital Sensor Communication Clock Configuration */
#define REG_CORE_DIGITAL_SENSOR_COMMS12 0x000003C0 /* ADMW_CORE Digital Sensor Communication Clock Configuration */
#define REG_CORE_DIGITAL_SENSOR_COMMS13 0x00000400 /* ADMW_CORE Digital Sensor Communication Clock Configuration */
#define REG_CORE_DIGITAL_SENSOR_COMMS14 0x00000440 /* ADMW_CORE Digital Sensor Communication Clock Configuration */
#define REG_CORE_DIGITAL_SENSOR_COMMS15 0x00000480 /* ADMW_CORE Digital Sensor Communication Clock Configuration */
#define REG_CORE_DIGITAL_SENSOR_COMMSn(i) (REG_CORE_DIGITAL_SENSOR_COMMS0 + ((i) * 64))
#define REG_CORE_DIGITAL_SENSOR_COMMSn_COUNT 16
#define REG_CORE_DIGITAL_SENSOR_COMMAND1n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command1[n] */
#define REG_CORE_DIGITAL_SENSOR_COMMAND10_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND10 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND11_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND11 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND12_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND12 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND13_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND13 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND14_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND14 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND15_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND15 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND16_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND16 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND17_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND17 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND18_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND18 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND19_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND19 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND110_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND110 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND111_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND111 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND112_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND112 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND113_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND113 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND114_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND114 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND115_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND115 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND10 0x000000C2 /* ADMW_CORE Sensor Configuration Command1 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND11 0x00000102 /* ADMW_CORE Sensor Configuration Command1 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND12 0x00000142 /* ADMW_CORE Sensor Configuration Command1 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND13 0x00000182 /* ADMW_CORE Sensor Configuration Command1 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND14 0x000001C2 /* ADMW_CORE Sensor Configuration Command1 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND15 0x00000202 /* ADMW_CORE Sensor Configuration Command1 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND16 0x00000242 /* ADMW_CORE Sensor Configuration Command1 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND17 0x00000282 /* ADMW_CORE Sensor Configuration Command1 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND18 0x000002C2 /* ADMW_CORE Sensor Configuration Command1 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND19 0x00000302 /* ADMW_CORE Sensor Configuration Command1 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND110 0x00000342 /* ADMW_CORE Sensor Configuration Command1 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND111 0x00000382 /* ADMW_CORE Sensor Configuration Command1 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND112 0x000003C2 /* ADMW_CORE Sensor Configuration Command1 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND113 0x00000402 /* ADMW_CORE Sensor Configuration Command1 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND114 0x00000442 /* ADMW_CORE Sensor Configuration Command1 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND115 0x00000482 /* ADMW_CORE Sensor Configuration Command1 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND1n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND10 + ((i) * 64))
#define REG_CORE_DIGITAL_SENSOR_COMMAND1n_COUNT 16
#define REG_CORE_DIGITAL_SENSOR_COMMAND2n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command2[n] */
#define REG_CORE_DIGITAL_SENSOR_COMMAND20_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND20 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND21_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND21 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND22_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND22 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND23_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND23 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND24_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND24 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND25_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND25 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND26_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND26 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND27_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND27 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND28_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND28 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND29_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND29 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND210_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND210 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND211_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND211 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND212_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND212 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND213_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND213 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND214_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND214 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND215_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND215 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND20 0x000000C3 /* ADMW_CORE Sensor Configuration Command2 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND21 0x00000103 /* ADMW_CORE Sensor Configuration Command2 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND22 0x00000143 /* ADMW_CORE Sensor Configuration Command2 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND23 0x00000183 /* ADMW_CORE Sensor Configuration Command2 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND24 0x000001C3 /* ADMW_CORE Sensor Configuration Command2 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND25 0x00000203 /* ADMW_CORE Sensor Configuration Command2 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND26 0x00000243 /* ADMW_CORE Sensor Configuration Command2 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND27 0x00000283 /* ADMW_CORE Sensor Configuration Command2 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND28 0x000002C3 /* ADMW_CORE Sensor Configuration Command2 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND29 0x00000303 /* ADMW_CORE Sensor Configuration Command2 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND210 0x00000343 /* ADMW_CORE Sensor Configuration Command2 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND211 0x00000383 /* ADMW_CORE Sensor Configuration Command2 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND212 0x000003C3 /* ADMW_CORE Sensor Configuration Command2 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND213 0x00000403 /* ADMW_CORE Sensor Configuration Command2 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND214 0x00000443 /* ADMW_CORE Sensor Configuration Command2 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND215 0x00000483 /* ADMW_CORE Sensor Configuration Command2 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND2n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND20 + ((i) * 64))
#define REG_CORE_DIGITAL_SENSOR_COMMAND2n_COUNT 16
#define REG_CORE_DIGITAL_SENSOR_COMMAND3n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command3[n] */
#define REG_CORE_DIGITAL_SENSOR_COMMAND30_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND30 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND31_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND31 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND32_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND32 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND33_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND33 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND34_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND34 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND35_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND35 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND36_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND36 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND37_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND37 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND38_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND38 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND39_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND39 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND310_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND310 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND311_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND311 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND312_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND312 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND313_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND313 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND314_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND314 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND315_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND315 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND30 0x000000C4 /* ADMW_CORE Sensor Configuration Command3 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND31 0x00000104 /* ADMW_CORE Sensor Configuration Command3 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND32 0x00000144 /* ADMW_CORE Sensor Configuration Command3 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND33 0x00000184 /* ADMW_CORE Sensor Configuration Command3 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND34 0x000001C4 /* ADMW_CORE Sensor Configuration Command3 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND35 0x00000204 /* ADMW_CORE Sensor Configuration Command3 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND36 0x00000244 /* ADMW_CORE Sensor Configuration Command3 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND37 0x00000284 /* ADMW_CORE Sensor Configuration Command3 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND38 0x000002C4 /* ADMW_CORE Sensor Configuration Command3 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND39 0x00000304 /* ADMW_CORE Sensor Configuration Command3 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND310 0x00000344 /* ADMW_CORE Sensor Configuration Command3 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND311 0x00000384 /* ADMW_CORE Sensor Configuration Command3 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND312 0x000003C4 /* ADMW_CORE Sensor Configuration Command3 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND313 0x00000404 /* ADMW_CORE Sensor Configuration Command3 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND314 0x00000444 /* ADMW_CORE Sensor Configuration Command3 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND315 0x00000484 /* ADMW_CORE Sensor Configuration Command3 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND3n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND30 + ((i) * 64))
#define REG_CORE_DIGITAL_SENSOR_COMMAND3n_COUNT 16
#define REG_CORE_DIGITAL_SENSOR_COMMAND4n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command4[n] */
#define REG_CORE_DIGITAL_SENSOR_COMMAND40_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND40 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND41_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND41 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND42_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND42 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND43_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND43 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND44_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND44 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND45_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND45 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND46_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND46 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND47_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND47 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND48_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND48 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND49_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND49 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND410_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND410 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND411_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND411 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND412_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND412 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND413_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND413 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND414_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND414 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND415_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND415 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND40 0x000000C5 /* ADMW_CORE Sensor Configuration Command4 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND41 0x00000105 /* ADMW_CORE Sensor Configuration Command4 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND42 0x00000145 /* ADMW_CORE Sensor Configuration Command4 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND43 0x00000185 /* ADMW_CORE Sensor Configuration Command4 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND44 0x000001C5 /* ADMW_CORE Sensor Configuration Command4 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND45 0x00000205 /* ADMW_CORE Sensor Configuration Command4 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND46 0x00000245 /* ADMW_CORE Sensor Configuration Command4 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND47 0x00000285 /* ADMW_CORE Sensor Configuration Command4 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND48 0x000002C5 /* ADMW_CORE Sensor Configuration Command4 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND49 0x00000305 /* ADMW_CORE Sensor Configuration Command4 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND410 0x00000345 /* ADMW_CORE Sensor Configuration Command4 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND411 0x00000385 /* ADMW_CORE Sensor Configuration Command4 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND412 0x000003C5 /* ADMW_CORE Sensor Configuration Command4 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND413 0x00000405 /* ADMW_CORE Sensor Configuration Command4 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND414 0x00000445 /* ADMW_CORE Sensor Configuration Command4 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND415 0x00000485 /* ADMW_CORE Sensor Configuration Command4 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND4n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND40 + ((i) * 64))
#define REG_CORE_DIGITAL_SENSOR_COMMAND4n_COUNT 16
#define REG_CORE_DIGITAL_SENSOR_COMMAND5n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command5[n] */
#define REG_CORE_DIGITAL_SENSOR_COMMAND50_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND50 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND51_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND51 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND52_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND52 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND53_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND53 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND54_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND54 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND55_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND55 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND56_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND56 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND57_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND57 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND58_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND58 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND59_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND59 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND510_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND510 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND511_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND511 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND512_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND512 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND513_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND513 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND514_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND514 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND515_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND515 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND50 0x000000C6 /* ADMW_CORE Sensor Configuration Command5 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND51 0x00000106 /* ADMW_CORE Sensor Configuration Command5 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND52 0x00000146 /* ADMW_CORE Sensor Configuration Command5 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND53 0x00000186 /* ADMW_CORE Sensor Configuration Command5 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND54 0x000001C6 /* ADMW_CORE Sensor Configuration Command5 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND55 0x00000206 /* ADMW_CORE Sensor Configuration Command5 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND56 0x00000246 /* ADMW_CORE Sensor Configuration Command5 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND57 0x00000286 /* ADMW_CORE Sensor Configuration Command5 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND58 0x000002C6 /* ADMW_CORE Sensor Configuration Command5 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND59 0x00000306 /* ADMW_CORE Sensor Configuration Command5 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND510 0x00000346 /* ADMW_CORE Sensor Configuration Command5 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND511 0x00000386 /* ADMW_CORE Sensor Configuration Command5 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND512 0x000003C6 /* ADMW_CORE Sensor Configuration Command5 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND513 0x00000406 /* ADMW_CORE Sensor Configuration Command5 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND514 0x00000446 /* ADMW_CORE Sensor Configuration Command5 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND515 0x00000486 /* ADMW_CORE Sensor Configuration Command5 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND5n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND50 + ((i) * 64))
#define REG_CORE_DIGITAL_SENSOR_COMMAND5n_COUNT 16
#define REG_CORE_DIGITAL_SENSOR_COMMAND6n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command6[n] */
#define REG_CORE_DIGITAL_SENSOR_COMMAND60_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND60 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND61_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND61 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND62_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND62 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND63_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND63 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND64_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND64 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND65_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND65 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND66_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND66 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND67_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND67 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND68_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND68 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND69_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND69 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND610_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND610 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND611_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND611 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND612_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND612 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND613_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND613 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND614_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND614 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND615_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND615 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND60 0x000000C7 /* ADMW_CORE Sensor Configuration Command6 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND61 0x00000107 /* ADMW_CORE Sensor Configuration Command6 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND62 0x00000147 /* ADMW_CORE Sensor Configuration Command6 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND63 0x00000187 /* ADMW_CORE Sensor Configuration Command6 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND64 0x000001C7 /* ADMW_CORE Sensor Configuration Command6 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND65 0x00000207 /* ADMW_CORE Sensor Configuration Command6 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND66 0x00000247 /* ADMW_CORE Sensor Configuration Command6 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND67 0x00000287 /* ADMW_CORE Sensor Configuration Command6 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND68 0x000002C7 /* ADMW_CORE Sensor Configuration Command6 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND69 0x00000307 /* ADMW_CORE Sensor Configuration Command6 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND610 0x00000347 /* ADMW_CORE Sensor Configuration Command6 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND611 0x00000387 /* ADMW_CORE Sensor Configuration Command6 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND612 0x000003C7 /* ADMW_CORE Sensor Configuration Command6 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND613 0x00000407 /* ADMW_CORE Sensor Configuration Command6 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND614 0x00000447 /* ADMW_CORE Sensor Configuration Command6 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND615 0x00000487 /* ADMW_CORE Sensor Configuration Command6 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND6n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND60 + ((i) * 64))
#define REG_CORE_DIGITAL_SENSOR_COMMAND6n_COUNT 16
#define REG_CORE_DIGITAL_SENSOR_COMMAND7n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command7[n] */
#define REG_CORE_DIGITAL_SENSOR_COMMAND70_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND70 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND71_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND71 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND72_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND72 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND73_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND73 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND74_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND74 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND75_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND75 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND76_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND76 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND77_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND77 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND78_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND78 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND79_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND79 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND710_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND710 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND711_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND711 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND712_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND712 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND713_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND713 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND714_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND714 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND715_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND715 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND70 0x000000C8 /* ADMW_CORE Sensor Configuration Command7 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND71 0x00000108 /* ADMW_CORE Sensor Configuration Command7 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND72 0x00000148 /* ADMW_CORE Sensor Configuration Command7 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND73 0x00000188 /* ADMW_CORE Sensor Configuration Command7 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND74 0x000001C8 /* ADMW_CORE Sensor Configuration Command7 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND75 0x00000208 /* ADMW_CORE Sensor Configuration Command7 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND76 0x00000248 /* ADMW_CORE Sensor Configuration Command7 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND77 0x00000288 /* ADMW_CORE Sensor Configuration Command7 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND78 0x000002C8 /* ADMW_CORE Sensor Configuration Command7 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND79 0x00000308 /* ADMW_CORE Sensor Configuration Command7 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND710 0x00000348 /* ADMW_CORE Sensor Configuration Command7 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND711 0x00000388 /* ADMW_CORE Sensor Configuration Command7 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND712 0x000003C8 /* ADMW_CORE Sensor Configuration Command7 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND713 0x00000408 /* ADMW_CORE Sensor Configuration Command7 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND714 0x00000448 /* ADMW_CORE Sensor Configuration Command7 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND715 0x00000488 /* ADMW_CORE Sensor Configuration Command7 */
#define REG_CORE_DIGITAL_SENSOR_COMMAND7n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND70 + ((i) * 64))
#define REG_CORE_DIGITAL_SENSOR_COMMAND7n_COUNT 16
#define REG_CORE_DIGITAL_SENSOR_READ_CMD1n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd1[n] */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD10_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD10 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD11_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD11 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD12_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD12 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD13_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD13 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD14_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD14 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD15_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD15 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD16_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD16 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD17_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD17 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD18_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD18 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD19_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD19 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD110_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD110 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD111_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD111 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD112_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD112 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD113_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD113 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD114_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD114 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD115_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD115 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD10 0x000000C9 /* ADMW_CORE Sensor Read Command1 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD11 0x00000109 /* ADMW_CORE Sensor Read Command1 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD12 0x00000149 /* ADMW_CORE Sensor Read Command1 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD13 0x00000189 /* ADMW_CORE Sensor Read Command1 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD14 0x000001C9 /* ADMW_CORE Sensor Read Command1 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD15 0x00000209 /* ADMW_CORE Sensor Read Command1 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD16 0x00000249 /* ADMW_CORE Sensor Read Command1 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD17 0x00000289 /* ADMW_CORE Sensor Read Command1 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD18 0x000002C9 /* ADMW_CORE Sensor Read Command1 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD19 0x00000309 /* ADMW_CORE Sensor Read Command1 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD110 0x00000349 /* ADMW_CORE Sensor Read Command1 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD111 0x00000389 /* ADMW_CORE Sensor Read Command1 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD112 0x000003C9 /* ADMW_CORE Sensor Read Command1 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD113 0x00000409 /* ADMW_CORE Sensor Read Command1 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD114 0x00000449 /* ADMW_CORE Sensor Read Command1 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD115 0x00000489 /* ADMW_CORE Sensor Read Command1 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD1n(i) (REG_CORE_DIGITAL_SENSOR_READ_CMD10 + ((i) * 64))
#define REG_CORE_DIGITAL_SENSOR_READ_CMD1n_COUNT 16
#define REG_CORE_DIGITAL_SENSOR_READ_CMD2n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd2[n] */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD20_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD20 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD21_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD21 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD22_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD22 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD23_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD23 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD24_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD24 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD25_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD25 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD26_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD26 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD27_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD27 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD28_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD28 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD29_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD29 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD210_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD210 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD211_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD211 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD212_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD212 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD213_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD213 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD214_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD214 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD215_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD215 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD20 0x000000CA /* ADMW_CORE Sensor Read Command2 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD21 0x0000010A /* ADMW_CORE Sensor Read Command2 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD22 0x0000014A /* ADMW_CORE Sensor Read Command2 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD23 0x0000018A /* ADMW_CORE Sensor Read Command2 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD24 0x000001CA /* ADMW_CORE Sensor Read Command2 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD25 0x0000020A /* ADMW_CORE Sensor Read Command2 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD26 0x0000024A /* ADMW_CORE Sensor Read Command2 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD27 0x0000028A /* ADMW_CORE Sensor Read Command2 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD28 0x000002CA /* ADMW_CORE Sensor Read Command2 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD29 0x0000030A /* ADMW_CORE Sensor Read Command2 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD210 0x0000034A /* ADMW_CORE Sensor Read Command2 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD211 0x0000038A /* ADMW_CORE Sensor Read Command2 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD212 0x000003CA /* ADMW_CORE Sensor Read Command2 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD213 0x0000040A /* ADMW_CORE Sensor Read Command2 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD214 0x0000044A /* ADMW_CORE Sensor Read Command2 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD215 0x0000048A /* ADMW_CORE Sensor Read Command2 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD2n(i) (REG_CORE_DIGITAL_SENSOR_READ_CMD20 + ((i) * 64))
#define REG_CORE_DIGITAL_SENSOR_READ_CMD2n_COUNT 16
#define REG_CORE_DIGITAL_SENSOR_READ_CMD3n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd3[n] */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD30_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD30 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD31_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD31 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD32_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD32 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD33_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD33 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD34_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD34 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD35_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD35 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD36_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD36 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD37_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD37 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD38_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD38 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD39_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD39 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD310_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD310 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD311_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD311 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD312_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD312 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD313_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD313 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD314_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD314 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD315_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD315 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD30 0x000000CB /* ADMW_CORE Sensor Read Command3 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD31 0x0000010B /* ADMW_CORE Sensor Read Command3 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD32 0x0000014B /* ADMW_CORE Sensor Read Command3 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD33 0x0000018B /* ADMW_CORE Sensor Read Command3 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD34 0x000001CB /* ADMW_CORE Sensor Read Command3 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD35 0x0000020B /* ADMW_CORE Sensor Read Command3 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD36 0x0000024B /* ADMW_CORE Sensor Read Command3 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD37 0x0000028B /* ADMW_CORE Sensor Read Command3 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD38 0x000002CB /* ADMW_CORE Sensor Read Command3 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD39 0x0000030B /* ADMW_CORE Sensor Read Command3 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD310 0x0000034B /* ADMW_CORE Sensor Read Command3 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD311 0x0000038B /* ADMW_CORE Sensor Read Command3 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD312 0x000003CB /* ADMW_CORE Sensor Read Command3 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD313 0x0000040B /* ADMW_CORE Sensor Read Command3 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD314 0x0000044B /* ADMW_CORE Sensor Read Command3 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD315 0x0000048B /* ADMW_CORE Sensor Read Command3 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD3n(i) (REG_CORE_DIGITAL_SENSOR_READ_CMD30 + ((i) * 64))
#define REG_CORE_DIGITAL_SENSOR_READ_CMD3n_COUNT 16
#define REG_CORE_DIGITAL_SENSOR_READ_CMD4n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd4[n] */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD40_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD40 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD41_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD41 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD42_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD42 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD43_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD43 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD44_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD44 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD45_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD45 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD46_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD46 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD47_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD47 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD48_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD48 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD49_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD49 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD410_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD410 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD411_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD411 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD412_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD412 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD413_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD413 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD414_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD414 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD415_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD415 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD40 0x000000CC /* ADMW_CORE Sensor Read Command4 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD41 0x0000010C /* ADMW_CORE Sensor Read Command4 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD42 0x0000014C /* ADMW_CORE Sensor Read Command4 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD43 0x0000018C /* ADMW_CORE Sensor Read Command4 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD44 0x000001CC /* ADMW_CORE Sensor Read Command4 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD45 0x0000020C /* ADMW_CORE Sensor Read Command4 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD46 0x0000024C /* ADMW_CORE Sensor Read Command4 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD47 0x0000028C /* ADMW_CORE Sensor Read Command4 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD48 0x000002CC /* ADMW_CORE Sensor Read Command4 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD49 0x0000030C /* ADMW_CORE Sensor Read Command4 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD410 0x0000034C /* ADMW_CORE Sensor Read Command4 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD411 0x0000038C /* ADMW_CORE Sensor Read Command4 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD412 0x000003CC /* ADMW_CORE Sensor Read Command4 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD413 0x0000040C /* ADMW_CORE Sensor Read Command4 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD414 0x0000044C /* ADMW_CORE Sensor Read Command4 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD415 0x0000048C /* ADMW_CORE Sensor Read Command4 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD4n(i) (REG_CORE_DIGITAL_SENSOR_READ_CMD40 + ((i) * 64))
#define REG_CORE_DIGITAL_SENSOR_READ_CMD4n_COUNT 16
#define REG_CORE_DIGITAL_SENSOR_READ_CMD5n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd5[n] */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD50_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD50 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD51_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD51 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD52_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD52 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD53_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD53 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD54_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD54 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD55_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD55 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD56_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD56 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD57_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD57 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD58_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD58 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD59_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD59 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD510_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD510 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD511_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD511 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD512_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD512 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD513_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD513 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD514_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD514 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD515_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD515 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD50 0x000000CD /* ADMW_CORE Sensor Read Command5 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD51 0x0000010D /* ADMW_CORE Sensor Read Command5 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD52 0x0000014D /* ADMW_CORE Sensor Read Command5 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD53 0x0000018D /* ADMW_CORE Sensor Read Command5 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD54 0x000001CD /* ADMW_CORE Sensor Read Command5 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD55 0x0000020D /* ADMW_CORE Sensor Read Command5 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD56 0x0000024D /* ADMW_CORE Sensor Read Command5 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD57 0x0000028D /* ADMW_CORE Sensor Read Command5 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD58 0x000002CD /* ADMW_CORE Sensor Read Command5 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD59 0x0000030D /* ADMW_CORE Sensor Read Command5 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD510 0x0000034D /* ADMW_CORE Sensor Read Command5 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD511 0x0000038D /* ADMW_CORE Sensor Read Command5 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD512 0x000003CD /* ADMW_CORE Sensor Read Command5 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD513 0x0000040D /* ADMW_CORE Sensor Read Command5 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD514 0x0000044D /* ADMW_CORE Sensor Read Command5 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD515 0x0000048D /* ADMW_CORE Sensor Read Command5 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD5n(i) (REG_CORE_DIGITAL_SENSOR_READ_CMD50 + ((i) * 64))
#define REG_CORE_DIGITAL_SENSOR_READ_CMD5n_COUNT 16
#define REG_CORE_DIGITAL_SENSOR_READ_CMD6n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd6[n] */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD60_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD60 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD61_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD61 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD62_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD62 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD63_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD63 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD64_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD64 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD65_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD65 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD66_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD66 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD67_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD67 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD68_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD68 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD69_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD69 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD610_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD610 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD611_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD611 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD612_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD612 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD613_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD613 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD614_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD614 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD615_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD615 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD60 0x000000CE /* ADMW_CORE Sensor Read Command6 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD61 0x0000010E /* ADMW_CORE Sensor Read Command6 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD62 0x0000014E /* ADMW_CORE Sensor Read Command6 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD63 0x0000018E /* ADMW_CORE Sensor Read Command6 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD64 0x000001CE /* ADMW_CORE Sensor Read Command6 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD65 0x0000020E /* ADMW_CORE Sensor Read Command6 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD66 0x0000024E /* ADMW_CORE Sensor Read Command6 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD67 0x0000028E /* ADMW_CORE Sensor Read Command6 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD68 0x000002CE /* ADMW_CORE Sensor Read Command6 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD69 0x0000030E /* ADMW_CORE Sensor Read Command6 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD610 0x0000034E /* ADMW_CORE Sensor Read Command6 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD611 0x0000038E /* ADMW_CORE Sensor Read Command6 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD612 0x000003CE /* ADMW_CORE Sensor Read Command6 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD613 0x0000040E /* ADMW_CORE Sensor Read Command6 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD614 0x0000044E /* ADMW_CORE Sensor Read Command6 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD615 0x0000048E /* ADMW_CORE Sensor Read Command6 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD6n(i) (REG_CORE_DIGITAL_SENSOR_READ_CMD60 + ((i) * 64))
#define REG_CORE_DIGITAL_SENSOR_READ_CMD6n_COUNT 16
#define REG_CORE_DIGITAL_SENSOR_READ_CMD7n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd7[n] */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD70_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD70 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD71_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD71 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD72_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD72 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD73_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD73 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD74_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD74 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD75_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD75 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD76_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD76 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD77_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD77 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD78_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD78 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD79_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD79 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD710_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD710 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD711_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD711 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD712_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD712 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD713_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD713 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD714_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD714 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD715_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD715 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD70 0x000000CF /* ADMW_CORE Sensor Read Command7 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD71 0x0000010F /* ADMW_CORE Sensor Read Command7 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD72 0x0000014F /* ADMW_CORE Sensor Read Command7 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD73 0x0000018F /* ADMW_CORE Sensor Read Command7 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD74 0x000001CF /* ADMW_CORE Sensor Read Command7 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD75 0x0000020F /* ADMW_CORE Sensor Read Command7 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD76 0x0000024F /* ADMW_CORE Sensor Read Command7 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD77 0x0000028F /* ADMW_CORE Sensor Read Command7 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD78 0x000002CF /* ADMW_CORE Sensor Read Command7 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD79 0x0000030F /* ADMW_CORE Sensor Read Command7 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD710 0x0000034F /* ADMW_CORE Sensor Read Command7 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD711 0x0000038F /* ADMW_CORE Sensor Read Command7 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD712 0x000003CF /* ADMW_CORE Sensor Read Command7 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD713 0x0000040F /* ADMW_CORE Sensor Read Command7 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD714 0x0000044F /* ADMW_CORE Sensor Read Command7 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD715 0x0000048F /* ADMW_CORE Sensor Read Command7 */
#define REG_CORE_DIGITAL_SENSOR_READ_CMD7n(i) (REG_CORE_DIGITAL_SENSOR_READ_CMD70 + ((i) * 64))
#define REG_CORE_DIGITAL_SENSOR_READ_CMD7n_COUNT 16
/* ============================================================================================================================
ADMW_CORE Register BitMasks, Positions & Enumerations
============================================================================================================================ */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_COMMAND Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_COMMAND_SPECIAL_COMMAND 0 /* Special Command */
#define BITM_CORE_COMMAND_SPECIAL_COMMAND 0x000000FF /* Special Command */
#define ENUM_CORE_COMMAND_NOP 0x00000000 /* Special_Command: No Command */
#define ENUM_CORE_COMMAND_CONVERT 0x00000001 /* Special_Command: Start ADC Conversions */
#define ENUM_CORE_COMMAND_CONVERT_WITH_RAW 0x00000002 /* Special_Command: Start Conversions with Added RAW ADC Data */
#define ENUM_CORE_COMMAND_RUN_DIAGNOSTICS 0x00000003 /* Special_Command: Initiate a Diagnostics Cycle */
#define ENUM_CORE_COMMAND_SELF_CALIBRATION 0x00000004 /* Special_Command: Initiate a Self-Calibration Cycle */
#define ENUM_CORE_COMMAND_LATCH_CONFIG 0x00000007 /* Special_Command: Latch Configuration. */
#define ENUM_CORE_COMMAND_LOAD_LUT 0x00000008 /* Special_Command: Load LUT from FLASH */
#define ENUM_CORE_COMMAND_SAVE_LUT 0x00000009 /* Special_Command: Save LUT to FLASH */
#define ENUM_CORE_COMMAND_SYSTEM_CHECK 0x0000000A /* Special_Command: Full Suite of Measurement Diagnostics */
#define ENUM_CORE_COMMAND_CONVERT_FFT 0x0000000B /* Special_Command: Perform FFTs on Selected Channel(s) */
#define ENUM_CORE_COMMAND_ERASE_EXTERNAL_FLASH 0x00000010 /* Special_Command: Erase Contents of External Flash */
#define ENUM_CORE_COMMAND_POWER_DOWN 0x00000014 /* Special_Command: Enter Low Power State */
#define ENUM_CORE_COMMAND_LOAD_CONFIG_1 0x00000018 /* Special_Command: Load Registers with Configuration#1 from FLASH */
#define ENUM_CORE_COMMAND_SAVE_CONFIG_1 0x00000019 /* Special_Command: Store Current Registers to FLASH Configuration#1 */
#define ENUM_CORE_COMMAND_LOAD_CONFIG_2 0x0000001A /* Special_Command: Load Registers with Configuration#2 from FLASH */
#define ENUM_CORE_COMMAND_SAVE_CONFIG_2 0x0000001B /* Special_Command: Store Current Registers to FLASH Configuration#2 */
#define ENUM_CORE_COMMAND_LOAD_CONFIG_3 0x0000001C /* Special_Command: Load Registers with Configuration#3 from FLASH */
#define ENUM_CORE_COMMAND_SAVE_CONFIG_3 0x0000001D /* Special_Command: Store Current Registers to FLASH Configuration#3 */
#define ENUM_CORE_COMMAND_LOAD_CONFIG_4 0x0000001E /* Special_Command: Load Registers with Configuration#4 from FLASH */
#define ENUM_CORE_COMMAND_SAVE_CONFIG_4 0x0000001F /* Special_Command: Store Current Registers to FLASH Configuration#4 */
#define ENUM_CORE_COMMAND_CALIBRATE_DIGITAL 0x00000020 /* Special_Command: Performs a Calibration of Digital Sensor, if Supported & Enabled. */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_MODE Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_MODE_EXT_FLASH_STORE 7 /* Indicates If Measurement Data Should Be Stored in Flash */
#define BITP_CORE_MODE_FFT_MODE 5 /* Indicates Single or Multiple Sequence of FFTs */
#define BITP_CORE_MODE_CALIBRATION_METHOD 4 /* Indicates If Calibration is Required on 'Latch' Command */
#define BITP_CORE_MODE_DRDY_MODE 2 /* Indicates Behavior of DRDY with Respect to FIFO State */
#define BITP_CORE_MODE_CONVERSION_MODE 0 /* Conversion Mode */
#define BITM_CORE_MODE_EXT_FLASH_STORE 0x00000080 /* Indicates If Measurement Data Should Be Stored in Flash */
#define BITM_CORE_MODE_FFT_MODE 0x00000020 /* Indicates Single or Multiple Sequence of FFTs */
#define BITM_CORE_MODE_CALIBRATION_METHOD 0x00000010 /* Indicates If Calibration is Required on 'Latch' Command */
#define BITM_CORE_MODE_DRDY_MODE 0x0000000C /* Indicates Behavior of DRDY with Respect to FIFO State */
#define BITM_CORE_MODE_CONVERSION_MODE 0x00000003 /* Conversion Mode */
#define ENUM_CORE_MODE_EXT_FLASH_NOT_USED 0x00000000 /* Ext_Flash_Store: Do Not Use External Flash */
#define ENUM_CORE_MODE_EXT_FLASH_USED 0x00000080 /* Ext_Flash_Store: Use External Flash */
#define ENUM_CORE_MODE_FFT_MODE_SINGLE 0x00000000 /* FFT_Mode: Perform Single Sequence of FFT(s) on Selected Channel(s) */
#define ENUM_CORE_MODE_FFT_MODE_CONTINUOUS 0x00000020 /* FFT_Mode: Perform Continuous Sequence of FFTs on Selected Channel(s) */
#define ENUM_CORE_MODE_NO_CAL 0x00000000 /* Calibration_Method: No Calibration Performed */
#define ENUM_CORE_MODE_DO_CAL 0x00000010 /* Calibration_Method: Calibration Performed */
#define ENUM_CORE_MODE_DRDY_PER_CONVERSION 0x00000000 /* Drdy_Mode: Data Ready Per Conversion */
#define ENUM_CORE_MODE_DRDY_PER_CYCLE 0x00000004 /* Drdy_Mode: Data Ready Per Cycle */
#define ENUM_CORE_MODE_DRDY_PER_FIFO_FILL 0x00000008 /* Drdy_Mode: Data Ready Per FIFO Fill / Multi-Cycle Burst */
#define ENUM_CORE_MODE_SINGLECYCLE 0x00000000 /* Conversion_Mode: Single Cycle */
#define ENUM_CORE_MODE_MULTICYCLE 0x00000001 /* Conversion_Mode: Multi Cycle */
#define ENUM_CORE_MODE_CONTINUOUS 0x00000002 /* Conversion_Mode: Continuous Conversion */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_POWER_CONFIG Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_POWER_CONFIG_POWER_MODE_ADC 0 /* ADC Power Mode */
#define BITM_CORE_POWER_CONFIG_POWER_MODE_ADC 0x00000003 /* ADC Power Mode */
#define ENUM_CORE_POWER_CONFIG_ADC_LOW_POWER 0x00000000 /* Power_Mode_ADC: ADC Low Power Mode */
#define ENUM_CORE_POWER_CONFIG_ADC_MID_POWER 0x00000001 /* Power_Mode_ADC: ADC Mid Power Mode */
#define ENUM_CORE_POWER_CONFIG_ADC_FULL_POWER 0x00000002 /* Power_Mode_ADC: ADC Full Power Mode */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_CYCLE_CONTROL Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_CYCLE_CONTROL_CYCLE_TIME_UNITS 14 /* Units for Cycle Time */
#define BITP_CORE_CYCLE_CONTROL_FILTER_SETTLING 13 /* Determines ADC Filter Settling in a Multi-Channel Sequence */
#define BITP_CORE_CYCLE_CONTROL_CYCLE_TYPE 12 /* Type of Measurement Cycle */
#define BITP_CORE_CYCLE_CONTROL_CYCLE_TIME 0 /* Duration of a Full Measurement Cycle */
#define BITM_CORE_CYCLE_CONTROL_CYCLE_TIME_UNITS 0x0000C000 /* Units for Cycle Time */
#define BITM_CORE_CYCLE_CONTROL_FILTER_SETTLING 0x00002000 /* Determines ADC Filter Settling in a Multi-Channel Sequence */
#define BITM_CORE_CYCLE_CONTROL_CYCLE_TYPE 0x00001000 /* Type of Measurement Cycle */
#define BITM_CORE_CYCLE_CONTROL_CYCLE_TIME 0x00000FFF /* Duration of a Full Measurement Cycle */
#define ENUM_CORE_CYCLE_CONTROL_MICROSECONDS 0x00000000 /* Cycle_Time_Units: Micro-Seconds */
#define ENUM_CORE_CYCLE_CONTROL_MILLISECONDS 0x00004000 /* Cycle_Time_Units: Milli-Seconds */
#define ENUM_CORE_CYCLE_CONTROL_SECONDS 0x00008000 /* Cycle_Time_Units: Seconds */
#define ENUM_CORE_CYCLE_CONTROL_FILTER_SETTLING_SETTLED 0x00000000 /* Filter_Settling: ADC Result Fully Settles for Every Output */
#define ENUM_CORE_CYCLE_CONTROL_FILTER_SETTLING_FAST 0x00002000 /* Filter_Settling: ADC Result Appears at Higher Update Rate for Consecutive Conversions */
#define ENUM_CORE_CYCLE_CONTROL_CYCLE_TYPE_SWITCH 0x00000000 /* Cycle_Type: Switch Channels After Every Conversion */
#define ENUM_CORE_CYCLE_CONTROL_CYCLE_TYPE_FULL 0x00001000 /* Cycle_Type: Perform Full Number Of Conversions On A Channel Consecutively */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_FIFO_NUM_CYCLES Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_FIFO_NUM_CYCLES_FIFO_NUM_CYCLES 0 /* How Many Cycles to Fill FIFO */
#define BITM_CORE_FIFO_NUM_CYCLES_FIFO_NUM_CYCLES 0x000000FF /* How Many Cycles to Fill FIFO */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_MULTI_CYCLE_REPEAT_INTERVAL Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_MULTI_CYCLE_REPEAT_INTERVAL_MULTI_CYCLE_REPEAT_INTERVAL 0 /* Defines Time Between Repetitions of Measurement Cycles. */
#define BITM_CORE_MULTI_CYCLE_REPEAT_INTERVAL_MULTI_CYCLE_REPEAT_INTERVAL 0x00FFFFFF /* Defines Time Between Repetitions of Measurement Cycles. */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_STATUS Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_STATUS_FIFO_ERROR 5 /* Indicates Error with FIFO */
#define BITP_CORE_STATUS_CMD_RUNNING 4 /* Indicates a Special Command is Active */
#define BITP_CORE_STATUS_DRDY 3 /* Indicates a New Sensor Result is Available to Be Read */
#define BITP_CORE_STATUS_ERROR 2 /* Indicates an Error */
#define BITP_CORE_STATUS_ALERT_ACTIVE 1 /* Indicates One or More Sensors Alerts are Active */
#define BITM_CORE_STATUS_FIFO_ERROR 0x00000020 /* Indicates Error with FIFO */
#define BITM_CORE_STATUS_CMD_RUNNING 0x00000010 /* Indicates a Special Command is Active */
#define BITM_CORE_STATUS_DRDY 0x00000008 /* Indicates a New Sensor Result is Available to Be Read */
#define BITM_CORE_STATUS_ERROR 0x00000004 /* Indicates an Error */
#define BITM_CORE_STATUS_ALERT_ACTIVE 0x00000002 /* Indicates One or More Sensors Alerts are Active */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DIAGNOSTICS_STATUS Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIAGNOSTICS_STATUS_DIAG_CALIBRATION_ERROR 13 /* Indicates Error During Internal Device Calibrations */
#define BITP_CORE_DIAGNOSTICS_STATUS_DIAG_CONVERSION_ERROR 12 /* Indicates Error During Internal ADC Conversions */
#define BITP_CORE_DIAGNOSTICS_STATUS_DIAG_SUPPLY_CAP_ERROR 3 /* Indicates Fault on Internal Supply Regulator Capacitor */
#define BITP_CORE_DIAGNOSTICS_STATUS_DIAG_SUPPLY_MONITOR_ERROR 2 /* Indicates Low Voltage on Internal Supply Voltages */
#define BITP_CORE_DIAGNOSTICS_STATUS_DIAG_COMMS_ERROR 1 /* Indicates Error on Internal Device Communications */
#define BITP_CORE_DIAGNOSTICS_STATUS_DIAG_CHECKSUM_ERROR 0 /* Indicates Error on Internal Checksum Calculations */
#define BITM_CORE_DIAGNOSTICS_STATUS_DIAG_CALIBRATION_ERROR 0x00002000 /* Indicates Error During Internal Device Calibrations */
#define BITM_CORE_DIAGNOSTICS_STATUS_DIAG_CONVERSION_ERROR 0x00001000 /* Indicates Error During Internal ADC Conversions */
#define BITM_CORE_DIAGNOSTICS_STATUS_DIAG_SUPPLY_CAP_ERROR 0x00000008 /* Indicates Fault on Internal Supply Regulator Capacitor */
#define BITM_CORE_DIAGNOSTICS_STATUS_DIAG_SUPPLY_MONITOR_ERROR 0x00000004 /* Indicates Low Voltage on Internal Supply Voltages */
#define BITM_CORE_DIAGNOSTICS_STATUS_DIAG_COMMS_ERROR 0x00000002 /* Indicates Error on Internal Device Communications */
#define BITM_CORE_DIAGNOSTICS_STATUS_DIAG_CHECKSUM_ERROR 0x00000001 /* Indicates Error on Internal Checksum Calculations */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_CHANNEL_ALERT_STATUS Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH15 15 /* Indicates Channel Alert is Active */
#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH14 14 /* Indicates Channel Alert is Active */
#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH13 13 /* Indicates Channel Alert is Active */
#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH12 12 /* Indicates Channel Alert is Active */
#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH11 11 /* Indicates Channel Alert is Active */
#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH10 10 /* Indicates Channel Alert is Active */
#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH9 9 /* Indicates Channel Alert is Active */
#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH8 8 /* Indicates Channel Alert is Active */
#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH7 7 /* Indicates Channel Alert is Active */
#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH6 6 /* Indicates Channel Alert is Active */
#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH5 5 /* Indicates Channel Alert is Active */
#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH4 4 /* Indicates Channel Alert is Active */
#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH3 3 /* Indicates Channel Alert is Active */
#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH2 2 /* Indicates Channel Alert is Active */
#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH1 1 /* Indicates Channel Alert is Active */
#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH0 0 /* Indicates Channel Alert is Active */
#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH15 0x00008000 /* Indicates Channel Alert is Active */
#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH14 0x00004000 /* Indicates Channel Alert is Active */
#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH13 0x00002000 /* Indicates Channel Alert is Active */
#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH12 0x00001000 /* Indicates Channel Alert is Active */
#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH11 0x00000800 /* Indicates Channel Alert is Active */
#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH10 0x00000400 /* Indicates Channel Alert is Active */
#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH9 0x00000200 /* Indicates Channel Alert is Active */
#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH8 0x00000100 /* Indicates Channel Alert is Active */
#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH7 0x00000080 /* Indicates Channel Alert is Active */
#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH6 0x00000040 /* Indicates Channel Alert is Active */
#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH5 0x00000020 /* Indicates Channel Alert is Active */
#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH4 0x00000010 /* Indicates Channel Alert is Active */
#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH3 0x00000008 /* Indicates Channel Alert is Active */
#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH2 0x00000004 /* Indicates Channel Alert is Active */
#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH1 0x00000002 /* Indicates Channel Alert is Active */
#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH0 0x00000001 /* Indicates Channel Alert is Active */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_ALERT_STATUS_2 Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_ALERT_STATUS_2_EXT_FLASH_ERROR 7 /* Indicates with External Flash Memory */
#define BITP_CORE_ALERT_STATUS_2_TEMPERATURE_ALARM_LO 6 /* Indicates Device Temperature Low Alarm */
#define BITP_CORE_ALERT_STATUS_2_TEMPERATURE_ALARM_HI 5 /* Indicates Device Temperature High Alarm */
#define BITP_CORE_ALERT_STATUS_2_TEMPERATURE_ALERT_LO 4 /* Indicates Device Temperature Low Alert */
#define BITP_CORE_ALERT_STATUS_2_TEMPERATURE_ALERT_HI 3 /* Indicates Device Temperature High Alert */
#define BITP_CORE_ALERT_STATUS_2_CONFIGURATION_ERROR 2 /* Indicates Error with Programmed Configuration */
#define BITP_CORE_ALERT_STATUS_2_LUT_ERROR 1 /* Indicates Error with One or More Look-Up-Tables */
#define BITM_CORE_ALERT_STATUS_2_EXT_FLASH_ERROR 0x00000080 /* Indicates with External Flash Memory */
#define BITM_CORE_ALERT_STATUS_2_TEMPERATURE_ALARM_LO 0x00000040 /* Indicates Device Temperature Low Alarm */
#define BITM_CORE_ALERT_STATUS_2_TEMPERATURE_ALARM_HI 0x00000020 /* Indicates Device Temperature High Alarm */
#define BITM_CORE_ALERT_STATUS_2_TEMPERATURE_ALERT_LO 0x00000010 /* Indicates Device Temperature Low Alert */
#define BITM_CORE_ALERT_STATUS_2_TEMPERATURE_ALERT_HI 0x00000008 /* Indicates Device Temperature High Alert */
#define BITM_CORE_ALERT_STATUS_2_CONFIGURATION_ERROR 0x00000004 /* Indicates Error with Programmed Configuration */
#define BITM_CORE_ALERT_STATUS_2_LUT_ERROR 0x00000002 /* Indicates Error with One or More Look-Up-Tables */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_ALERT_DETAIL_CH[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_ALERT_DETAIL_CH_COMP_NOT_READY 15 /* Indicates Compensation Channel Not Ready When Required */
#define BITP_CORE_ALERT_DETAIL_CH_SENSOR_NOT_READY 14 /* Indicates Digital Sensor Not Ready When Read */
#define BITP_CORE_ALERT_DETAIL_CH_CORRECTION_OVERRANGE 13 /* Indicates Result Larger Than LUT/Equation Range */
#define BITP_CORE_ALERT_DETAIL_CH_CORRECTION_UNDERRANGE 12 /* Indicates Result Less Than LUT/Equation Range */
#define BITP_CORE_ALERT_DETAIL_CH_OVER_VOLTAGE 11 /* Indicates Channel Over-Voltage */
#define BITP_CORE_ALERT_DETAIL_CH_UNDER_VOLTAGE 10 /* Indicates Channel Under-Voltage */
#define BITP_CORE_ALERT_DETAIL_CH_LUT_ERROR_CH 9 /* Indicates Error with Channel Look-Up-Table */
#define BITP_CORE_ALERT_DETAIL_CH_CONFIG_ERR 8 /* Indicates Configuration Error on Channel */
#define BITP_CORE_ALERT_DETAIL_CH_CALIBRATION_INVALID 7 /* Indicates Problem During Calibration of Channel */
#define BITP_CORE_ALERT_DETAIL_CH_REF_DETECT 6 /* Indicates Whether ADC Reference is Valid */
#define BITP_CORE_ALERT_DETAIL_CH_SENSOR_OPEN 5 /* Indicates Sensor Input is Open Circuit */
#define BITP_CORE_ALERT_DETAIL_CH_HIGH_LIMIT 4 /* Indicates Sensor Result is Greater Than High Limit */
#define BITP_CORE_ALERT_DETAIL_CH_LOW_LIMIT 3 /* Indicates Sensor Result is Less Than Low Limit */
#define BITP_CORE_ALERT_DETAIL_CH_OVER_RANGE 2 /* Indicates Channel Over-Range */
#define BITP_CORE_ALERT_DETAIL_CH_UNDER_RANGE 1 /* Indicates Channel Under-Range */
#define BITP_CORE_ALERT_DETAIL_CH_TIME_OUT 0 /* Indicates Time-Out Error from Digital Sensor */
#define BITM_CORE_ALERT_DETAIL_CH_COMP_NOT_READY 0x00008000 /* Indicates Compensation Channel Not Ready When Required */
#define BITM_CORE_ALERT_DETAIL_CH_SENSOR_NOT_READY 0x00004000 /* Indicates Digital Sensor Not Ready When Read */
#define BITM_CORE_ALERT_DETAIL_CH_CORRECTION_OVERRANGE 0x00002000 /* Indicates Result Larger Than LUT/Equation Range */
#define BITM_CORE_ALERT_DETAIL_CH_CORRECTION_UNDERRANGE 0x00001000 /* Indicates Result Less Than LUT/Equation Range */
#define BITM_CORE_ALERT_DETAIL_CH_OVER_VOLTAGE 0x00000800 /* Indicates Channel Over-Voltage */
#define BITM_CORE_ALERT_DETAIL_CH_UNDER_VOLTAGE 0x00000400 /* Indicates Channel Under-Voltage */
#define BITM_CORE_ALERT_DETAIL_CH_LUT_ERROR_CH 0x00000200 /* Indicates Error with Channel Look-Up-Table */
#define BITM_CORE_ALERT_DETAIL_CH_CONFIG_ERR 0x00000100 /* Indicates Configuration Error on Channel */
#define BITM_CORE_ALERT_DETAIL_CH_CALIBRATION_INVALID 0x00000080 /* Indicates Problem During Calibration of Channel */
#define BITM_CORE_ALERT_DETAIL_CH_REF_DETECT 0x00000040 /* Indicates Whether ADC Reference is Valid */
#define BITM_CORE_ALERT_DETAIL_CH_SENSOR_OPEN 0x00000020 /* Indicates Sensor Input is Open Circuit */
#define BITM_CORE_ALERT_DETAIL_CH_HIGH_LIMIT 0x00000010 /* Indicates Sensor Result is Greater Than High Limit */
#define BITM_CORE_ALERT_DETAIL_CH_LOW_LIMIT 0x00000008 /* Indicates Sensor Result is Less Than Low Limit */
#define BITM_CORE_ALERT_DETAIL_CH_OVER_RANGE 0x00000004 /* Indicates Channel Over-Range */
#define BITM_CORE_ALERT_DETAIL_CH_UNDER_RANGE 0x00000002 /* Indicates Channel Under-Range */
#define BITM_CORE_ALERT_DETAIL_CH_TIME_OUT 0x00000001 /* Indicates Time-Out Error from Digital Sensor */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_ERROR_CODE Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_ERROR_CODE_ERROR_CODE 0 /* Code Indicating Type of Error */
#define BITM_CORE_ERROR_CODE_ERROR_CODE 0x0000FFFF /* Code Indicating Type of Error */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_ALERT_CODE Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_ALERT_CODE_ALERT_CODE 0 /* Code Indicating Type of Alert */
#define BITM_CORE_ALERT_CODE_ALERT_CODE 0x0000FFFF /* Code Indicating Type of Alert */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_EXTERNAL_REFERENCE1 Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_EXTERNAL_REFERENCE1_EXT_REFIN1_VALUE 0 /* Refin1 Value */
#define BITM_CORE_EXTERNAL_REFERENCE1_EXT_REFIN1_VALUE 0xFFFFFFFF /* Refin1 Value */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_EXTERNAL_REFERENCE2 Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_EXTERNAL_REFERENCE2_EXT_REFIN2_VALUE 0 /* Refin2 Value */
#define BITM_CORE_EXTERNAL_REFERENCE2_EXT_REFIN2_VALUE 0xFFFFFFFF /* Refin2 Value */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DIAGNOSTICS_CONTROL Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIAGNOSTICS_CONTROL_TEMPERARURE_ALARM_ACTION 4 /* Determines Output in Response to Temperature Alarm */
#define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_OSD_FREQ 2 /* Diagnostics Open Sensor Detect Frequency */
#define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 1 /* Diagnostics Measure Enable */
#define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_GLOBAL_EN 0 /* Diagnostics Global Enable */
#define BITM_CORE_DIAGNOSTICS_CONTROL_TEMPERARURE_ALARM_ACTION 0x00000010 /* Determines Output in Response to Temperature Alarm */
#define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_OSD_FREQ 0x0000000C /* Diagnostics Open Sensor Detect Frequency */
#define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 0x00000002 /* Diagnostics Measure Enable */
#define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_GLOBAL_EN 0x00000001 /* Diagnostics Global Enable */
#define ENUM_CORE_DIAGNOSTICS_CONTROL_TEMPERATURE_ALARM_NAN 0x00000000 /* Temperarure_Alarm_Action: Sensor Output Equals Not-A-Number in Response to Temperature Alarm */
#define ENUM_CORE_DIAGNOSTICS_CONTROL_TEMPERATURE_ALARM_OUTPUT_ACTIVE 0x00000010 /* Temperarure_Alarm_Action: Sensor Output is not Clamped to Not-A-Number in Response to Temperature Alarm */
#define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_OFF 0x00000000 /* Diag_OSD_Freq: No Open-Circuit Detection During Measurement */
#define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_PER_1_CYCLE 0x00000004 /* Diag_OSD_Freq: Open-Circuit Detection Performed Once Per Measurement Cycle */
#define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_PER_100_CYCLES 0x00000008 /* Diag_OSD_Freq: Open-Circuit Detection Performed Once Per Hundred Measurement Cycles */
#define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_PER_1000_CYCLES 0x0000000C /* Diag_OSD_Freq: Open-Circuit Detection Performed Once Per Thousand Measurement Cycles */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DATA_FIFO Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DATA_FIFO_DATA_FIFO 0 /* Fifo Buffer of Sensor Results */
#define BITM_CORE_DATA_FIFO_DATA_FIFO 0x000000FF /* Fifo Buffer of Sensor Results */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DEBUG_CODE Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DEBUG_CODE_DEBUG_CODE 0 /* Additional Information on Source of Alert or Errors */
#define BITM_CORE_DEBUG_CODE_DEBUG_CODE 0xFFFFFFFF /* Additional Information on Source of Alert or Errors */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_FFT_CONFIG Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_FFT_CONFIG_FFT_NUM_CHANNELS 6 /* Indicates Number of Channels for FFT */
#define BITP_CORE_FFT_CONFIG_FFT_OUTPUT 4 /* Indicates FFT Output Format */
#define BITP_CORE_FFT_CONFIG_FFT_WINDOW 2 /* Indicates Window Type for FFT */
#define BITP_CORE_FFT_CONFIG_FFT_NUM_BINS 0 /* Indicates Number of Bins in FFT */
#define BITM_CORE_FFT_CONFIG_FFT_NUM_CHANNELS 0x000000C0 /* Indicates Number of Channels for FFT */
#define BITM_CORE_FFT_CONFIG_FFT_OUTPUT 0x00000030 /* Indicates FFT Output Format */
#define BITM_CORE_FFT_CONFIG_FFT_WINDOW 0x0000000C /* Indicates Window Type for FFT */
#define BITM_CORE_FFT_CONFIG_FFT_NUM_BINS 0x00000003 /* Indicates Number of Bins in FFT */
#define ENUM_CORE_FFT_CONFIG_FFT_CHANS_1 0x00000000 /* FFT_Num_Channels: One FFT Channel */
#define ENUM_CORE_FFT_CONFIG_FFT_CHANS_2 0x00000040 /* FFT_Num_Channels: Two FFT Channels */
#define ENUM_CORE_FFT_CONFIG_FFT_CHANS_3 0x00000080 /* FFT_Num_Channels: Three FFT Channels */
#define ENUM_CORE_FFT_CONFIG_FFT_CHANS_4 0x000000C0 /* FFT_Num_Channels: Four FFT Channels */
#define ENUM_CORE_FFT_CONFIG_FFT_OUTPUT_FULL 0x00000000 /* FFT_Output: N/2-Term Amplitude Response */
#define ENUM_CORE_FFT_CONFIG_FFT_OUTPUT_MAX16 0x00000010 /* FFT_Output: Bin-Number and Amplitude of 16 Highest Peaks of Amplitude Response */
#define ENUM_CORE_FFT_CONFIG_FFT_OUTPUT_FULL_WITH_RAW 0x00000020 /* FFT_Output: N/2-Term Amplitude Response Plus N Raw ADC Samples */
#define ENUM_CORE_FFT_CONFIG_FFT_WINDOW_NONE 0x00000000 /* FFT_Window: No Window */
#define ENUM_CORE_FFT_CONFIG_FFT_WINDOW_HANN 0x00000004 /* FFT_Window: Hann Window */
#define ENUM_CORE_FFT_CONFIG_FFT_WINDOW_BLACKMANN_HARRIS 0x00000008 /* FFT_Window: Blackman-Harris-Nuttall Window */
#define ENUM_CORE_FFT_CONFIG_FFT_WINDOW_TBD 0x0000000C /* FFT_Window: Reserved */
#define ENUM_CORE_FFT_CONFIG_FFT_BINS_256 0x00000000 /* FFT_Num_Bins: FFT Size 256 */
#define ENUM_CORE_FFT_CONFIG_FFT_BINS_512 0x00000001 /* FFT_Num_Bins: FFT Size 512 */
#define ENUM_CORE_FFT_CONFIG_FFT_BINS_1024 0x00000002 /* FFT_Num_Bins: FFT Size 1024 */
#define ENUM_CORE_FFT_CONFIG_FFT_BINS_2048 0x00000003 /* FFT_Num_Bins: FFT Size 2048 */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_ADVANCED_SENSOR_ACCESS Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_ADVANCED_SENSOR_ACCESS_ADVANCED_SENSOR_ACCESS 0 /* Write Specific Key Value to Access Advanced Sensors */
#define BITM_CORE_ADVANCED_SENSOR_ACCESS_ADVANCED_SENSOR_ACCESS 0x0000FFFF /* Write Specific Key Value to Access Advanced Sensors */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_LUT_SELECT Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_LUT_SELECT_LUT_RW 7 /* Read or Write LUT Data */
#define BITM_CORE_LUT_SELECT_LUT_RW 0x00000080 /* Read or Write LUT Data */
#define ENUM_CORE_LUT_SELECT_LUT_READ 0x00000000 /* LUT_RW: Read Addressed LUT Data */
#define ENUM_CORE_LUT_SELECT_LUT_WRITE 0x00000080 /* LUT_RW: Write Addressed LUT Data */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_LUT_OFFSET Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_LUT_OFFSET_LUT_OFFSET 0 /* Offset into Look-Up-Table */
#define BITM_CORE_LUT_OFFSET_LUT_OFFSET 0x00003FFF /* Offset into Look-Up-Table */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_LUT_DATA Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_LUT_DATA_LUT_DATA 0 /* Data Byte to Write to / Read from Look-Up-Table */
#define BITM_CORE_LUT_DATA_LUT_DATA 0x000000FF /* Data Byte to Write to / Read from Look-Up-Table */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_EXT_FLASH_INDEX Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_EXT_FLASH_INDEX_EXT_FLASH_INDEX 0 /* Start Position (Sample No.) for Retrieval of Ext. Flash Data */
#define BITM_CORE_EXT_FLASH_INDEX_EXT_FLASH_INDEX 0xFFFFFFFF /* Start Position (Sample No.) for Retrieval of Ext. Flash Data */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_EXT_FLASH_SAMPLE_COUNT Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_EXT_FLASH_SAMPLE_COUNT_EXT_FLASH_SAMPLE_COUNT 0 /* Indicates How Many Samples Stored in External Flash */
#define BITM_CORE_EXT_FLASH_SAMPLE_COUNT_EXT_FLASH_SAMPLE_COUNT 0xFFFFFFFF /* Indicates How Many Samples Stored in External Flash */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_EXT_FLASH_DATA Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_EXT_FLASH_DATA_EXT_FLASH_DATA 0 /* Data Read Back from External Flash */
#define BITM_CORE_EXT_FLASH_DATA_EXT_FLASH_DATA 0x000000FF /* Data Read Back from External Flash */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_REVISION Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_REVISION_REV_MAJOR 24 /* Major Revision Information */
#define BITP_CORE_REVISION_REV_MINOR 16 /* Minor Revision Information */
#define BITP_CORE_REVISION_REV_PATCH 0 /* Patch Revision Information */
#define BITM_CORE_REVISION_REV_MAJOR 0xFF000000 /* Major Revision Information */
#define BITM_CORE_REVISION_REV_MINOR 0x00FF0000 /* Minor Revision Information */
#define BITM_CORE_REVISION_REV_PATCH 0x0000FFFF /* Patch Revision Information */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_CHANNEL_COUNT[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_CHANNEL_COUNT_CHANNEL_ENABLE 7 /* Enable Channel in Measurement Cycle */
#define BITP_CORE_CHANNEL_COUNT_CHANNEL_COUNT 0 /* How Many Times Channel Should Appear in One Cycle */
#define BITM_CORE_CHANNEL_COUNT_CHANNEL_ENABLE 0x00000080 /* Enable Channel in Measurement Cycle */
#define BITM_CORE_CHANNEL_COUNT_CHANNEL_COUNT 0x0000007F /* How Many Times Channel Should Appear in One Cycle */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_CHANNEL_OPTIONS[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_CHANNEL_OPTIONS_FFT_ENABLE_CH 7 /* Indicates Channel to Be Used for FFT */
#define BITP_CORE_CHANNEL_OPTIONS_CHANNEL_PRIORITY 0 /* Indicates Priority or Position of This Channel in Sequence */
#define BITM_CORE_CHANNEL_OPTIONS_FFT_ENABLE_CH 0x00000080 /* Indicates Channel to Be Used for FFT */
#define BITM_CORE_CHANNEL_OPTIONS_CHANNEL_PRIORITY 0x0000000F /* Indicates Priority or Position of This Channel in Sequence */
#define ENUM_CORE_CHANNEL_OPTIONS_NO_FFT 0x00000000 /* FFT_Enable_Ch: FFT Will not be Performed on This Channel */
#define ENUM_CORE_CHANNEL_OPTIONS_DO_FFT 0x00000080 /* FFT_Enable_Ch: FFT Will be Performed on This Channel */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_SENSOR_TYPE[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_SENSOR_TYPE_SENSOR_TYPE 0 /* Sensor Type */
#define BITM_CORE_SENSOR_TYPE_SENSOR_TYPE 0x00000FFF /* Sensor Type */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_T_DEF_L1 0x00000000 /* Sensor_Type: Thermocouple T-Type Sensor Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_J_DEF_L1 0x00000001 /* Sensor_Type: Thermocouple J-Type Sensor Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_K_DEF_L1 0x00000002 /* Sensor_Type: Thermocouple K-Type Sensor Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_1_DEF_L2 0x00000008 /* Sensor_Type: Thermocouple Sensor 1 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_2_DEF_L2 0x00000009 /* Sensor_Type: Thermocouple Sensor 2 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_3_DEF_L2 0x0000000A /* Sensor_Type: Thermocouple Sensor 3 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_4_DEF_L2 0x0000000B /* Sensor_Type: Thermocouple Sensor 4 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_T_ADV_L1 0x00000010 /* Sensor_Type: Thermocouple T-Type Sensor Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_J_ADV_L1 0x00000011 /* Sensor_Type: Thermocouple J-Type Sensor Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_K_ADV_L1 0x00000012 /* Sensor_Type: Thermocouple K-Type Sensor Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_1_ADV_L2 0x00000018 /* Sensor_Type: Thermocouple Sensor 1 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_2_ADV_L2 0x00000019 /* Sensor_Type: Thermocouple Sensor 2 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_3_ADV_L2 0x0000001A /* Sensor_Type: Thermocouple Sensor 3 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_4_ADV_L2 0x0000001B /* Sensor_Type: Thermocouple Sensor 4 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT100_DEF_L1 0x00000020 /* Sensor_Type: RTD 2 Wire PT100 Sensor Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT1000_DEF_L1 0x00000021 /* Sensor_Type: RTD 2 Wire PT1000 Sensor Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_1_DEF_L2 0x00000028 /* Sensor_Type: RTD 2 Wire Sensor 1 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_2_DEF_L2 0x00000029 /* Sensor_Type: RTD 2 Wire Sensor 2 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_3_DEF_L2 0x0000002A /* Sensor_Type: RTD 2 Wire Sensor 3 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_4_DEF_L2 0x0000002B /* Sensor_Type: RTD 2 Wire Sensor 4 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT100_ADV_L1 0x00000030 /* Sensor_Type: RTD 2 Wire PT100 Sensor Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT1000_ADV_L1 0x00000031 /* Sensor_Type: RTD 2 Wire PT1000 Sensor Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_1_ADV_L2 0x00000038 /* Sensor_Type: RTD 2 Wire Sensor 1 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_2_ADV_L2 0x00000039 /* Sensor_Type: RTD 2 Wire Sensor 2 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_3_ADV_L2 0x0000003A /* Sensor_Type: RTD 2 Wire Sensor 3 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_4_ADV_L2 0x0000003B /* Sensor_Type: RTD 2 Wire Sensor 4 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT100_DEF_L1 0x00000040 /* Sensor_Type: RTD 3 Wire PT100 Sensor Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT1000_DEF_L1 0x00000041 /* Sensor_Type: RTD 3 Wire PT1000 Sensor Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_1_DEF_L2 0x00000048 /* Sensor_Type: RTD 3 Wire Sensor 1 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_2_DEF_L2 0x00000049 /* Sensor_Type: RTD 3 Wire Sensor 2 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_3_DEF_L2 0x0000004A /* Sensor_Type: RTD 3 Wire Sensor 3 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_4_DEF_L2 0x0000004B /* Sensor_Type: RTD 3 Wire Sensor 4 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT100_ADV_L1 0x00000050 /* Sensor_Type: RTD 3 Wire PT100 Sensor Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT1000_ADV_L1 0x00000051 /* Sensor_Type: RTD 3 Wire PT1000 Sensor Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_1_ADV_L2 0x00000058 /* Sensor_Type: RTD 3 Wire Sensor 1 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_2_ADV_L2 0x00000059 /* Sensor_Type: RTD 3 Wire Sensor 2 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_3_ADV_L2 0x0000005A /* Sensor_Type: RTD 3 Wire Sensor 3 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_4_ADV_L2 0x0000005B /* Sensor_Type: RTD 3 Wire Sensor 4 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT100_DEF_L1 0x00000060 /* Sensor_Type: RTD 4 Wire PT100 Sensor Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT1000_DEF_L1 0x00000061 /* Sensor_Type: RTD 4 Wire PT1000 Sensor Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_1_DEF_L2 0x00000068 /* Sensor_Type: RTD 4 Wire Sensor 1 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_2_DEF_L2 0x00000069 /* Sensor_Type: RTD 4 Wire Sensor 2 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_3_DEF_L2 0x0000006A /* Sensor_Type: RTD 4 Wire Sensor 3 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_4_DEF_L2 0x0000006B /* Sensor_Type: RTD 4 Wire Sensor 4 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT100_ADV_L1 0x00000070 /* Sensor_Type: RTD 4 Wire PT100 Sensor Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT1000_ADV_L1 0x00000071 /* Sensor_Type: RTD 4 Wire PT1000 Sensor Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_1_ADV_L2 0x00000078 /* Sensor_Type: RTD 4 Wire Sensor 1 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_2_ADV_L2 0x00000079 /* Sensor_Type: RTD 4 Wire Sensor 2 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_3_ADV_L2 0x0000007A /* Sensor_Type: RTD 4 Wire Sensor 3 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_4_ADV_L2 0x0000007B /* Sensor_Type: RTD 4 Wire Sensor 4 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_A_10K_DEF_L1 0x00000080 /* Sensor_Type: Thermistor Type A 10kOhm Sensor Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_B_10K_DEF_L1 0x00000081 /* Sensor_Type: Thermistor Type B 10kOhm Sensor Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_1_DEF_L2 0x00000088 /* Sensor_Type: Thermistor Sensor 1 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_2_DEF_L2 0x00000089 /* Sensor_Type: Thermistor Sensor 2 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_3_DEF_L2 0x0000008A /* Sensor_Type: Thermistor Sensor 3 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_4_DEF_L2 0x0000008B /* Sensor_Type: Thermistor Sensor 4 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_A_10K_ADV_L1 0x00000090 /* Sensor_Type: Thermistor Type A 10kOhm Sensor Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_B_10K_ADV_L1 0x00000091 /* Sensor_Type: Thermistor Type B 10kOhm Sensor Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_1_ADV_L2 0x00000098 /* Sensor_Type: Thermistor Sensor 1 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_2_ADV_L2 0x00000099 /* Sensor_Type: Thermistor Sensor 2 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_3_ADV_L2 0x0000009A /* Sensor_Type: Thermistor Sensor 3 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_4_ADV_L2 0x0000009B /* Sensor_Type: Thermistor Sensor 4 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_1_DEF_L2 0x000000A8 /* Sensor_Type: Bridge 4 Wire Sensor 1 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_2_DEF_L2 0x000000A9 /* Sensor_Type: Bridge 4 Wire Sensor 2 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_3_DEF_L2 0x000000AA /* Sensor_Type: Bridge 4 Wire Sensor 3 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_4_DEF_L2 0x000000AB /* Sensor_Type: Bridge 4 Wire Sensor 4 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_1_ADV_L2 0x000000B8 /* Sensor_Type: Bridge 4 Wire Sensor 1 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_2_ADV_L2 0x000000B9 /* Sensor_Type: Bridge 4 Wire Sensor 2 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_3_ADV_L2 0x000000BA /* Sensor_Type: Bridge 4 Wire Sensor 2 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_4_ADV_L2 0x000000BB /* Sensor_Type: Bridge 4 Wire Sensor 2 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_1_DEF_L2 0x000000C8 /* Sensor_Type: Bridge 6 Wire Sensor 1 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_2_DEF_L2 0x000000C9 /* Sensor_Type: Bridge 6 Wire Sensor 2 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_3_DEF_L2 0x000000CA /* Sensor_Type: Bridge 6 Wire Sensor 3 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_4_DEF_L2 0x000000CB /* Sensor_Type: Bridge 6 Wire Sensor 4 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_1_ADV_L2 0x000000D8 /* Sensor_Type: Bridge 6 Wire Sensor 1 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_2_ADV_L2 0x000000D9 /* Sensor_Type: Bridge 6 Wire Sensor 2 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_3_ADV_L2 0x000000DA /* Sensor_Type: Bridge 6 Wire Sensor 3 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_4_ADV_L2 0x000000DB /* Sensor_Type: Bridge 6 Wire Sensor 4 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_DIODE_2C_TYPEA_DEF_L1 0x000000E0 /* Sensor_Type: Diode 2 Current Type A Sensor Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_DIODE_3C_TYPEA_DEF_L1 0x000000E1 /* Sensor_Type: Diode 3 Current Type A Sensor Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_DIODE_2C_1_DEF_L2 0x000000E8 /* Sensor_Type: Diode 2 Current Sensor 1 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_DIODE_3C_1_DEF_L2 0x000000E9 /* Sensor_Type: Diode 3 Current Sensor 1 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_DIODE_2C_TYPEA_ADV_L1 0x000000F0 /* Sensor_Type: Diode 2 Current Type A Sensor Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_DIODE_3C_TYPEA_ADV_L1 0x000000F1 /* Sensor_Type: Diode 3 Current Type A Sensor Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_DIODE_2C_1_ADV_L2 0x000000F8 /* Sensor_Type: Diode 2 Current Sensor 1 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_DIODE_3C_1_ADV_L2 0x000000F9 /* Sensor_Type: Diode 3 Current Sensor 1 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_MICROPHONE_A_DEF_L1 0x00000100 /* Sensor_Type: Microphone With No External Amplifier Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_MICROPHONE_B_DEF_L1 0x00000101 /* Sensor_Type: Microphone With External Amplifier Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_MICROPHONE_1_DEF_L2 0x00000108 /* Sensor_Type: Microphone With No External Amplifier Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_MICROPHONE_2_DEF_L2 0x00000109 /* Sensor_Type: Microphone With External Amplifier Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_MICROPHONE_A_ADV_L1 0x00000110 /* Sensor_Type: Microphone With No External Amplifier Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_MICROPHONE_B_ADV_L1 0x00000111 /* Sensor_Type: Microphone With External Amplifier Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_MICROPHONE_1_ADV_L2 0x00000116 /* Sensor_Type: Microphone With No External Amplifier Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_MICROPHONE_2_ADV_L2 0x00000117 /* Sensor_Type: Microphone With External Amplifier Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_VOLTAGE 0x00000200 /* Sensor_Type: Voltage Input */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_VOLTAGE_PRESSURE_A_DEF_L1 0x00000220 /* Sensor_Type: Voltage Output Pressure Sensor A Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_VOLTAGE_PRESSURE_B_DEF_L1 0x00000221 /* Sensor_Type: Voltage Output Pressure Sensor B Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_VOLTAGE_PRESSURE_1_DEF_L2 0x00000228 /* Sensor_Type: Voltage Output Pressure Sensor 1 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_VOLTAGE_PRESSURE_2_DEF_L2 0x00000229 /* Sensor_Type: Voltage Output Pressure Sensor 2 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_VOLTAGE_PRESSURE_A_ADV_L1 0x00000230 /* Sensor_Type: Voltage Output Pressure Sensor A Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_VOLTAGE_PRESSURE_B_ADV_L1 0x00000231 /* Sensor_Type: Voltage Output Pressure Sensor B Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_VOLTAGE_PRESSURE_1_ADV_L2 0x00000238 /* Sensor_Type: Voltage Output Pressure Sensor 1 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_VOLTAGE_PRESSURE_2_ADV_L2 0x00000239 /* Sensor_Type: Voltage Output Pressure Sensor 2 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_CURRENT 0x00000300 /* Sensor_Type: Current Input */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_CURRENT_PRESSURE_A_DEF_L1 0x00000320 /* Sensor_Type: Current Output Pressure Sensor A Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_CURRENT_PRESSURE_1_DEF_L2 0x00000328 /* Sensor_Type: Current Output Pressure Sensor 1 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_CURRENT_PRESSURE_2_DEF_L2 0x00000329 /* Sensor_Type: Current Output Pressure Sensor 2 Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_CURRENT_PRESSURE_A_ADV_L1 0x00000330 /* Sensor_Type: Current Output Pressure Sensor A Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_CURRENT_PRESSURE_1_ADV_L2 0x00000338 /* Sensor_Type: Current Output Pressure Sensor 1 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_CURRENT_PRESSURE_2_ADV_L2 0x00000339 /* Sensor_Type: Current Output Pressure Sensor 2 Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_I2C_PRESSURE_A_DEF_L1 0x00000800 /* Sensor_Type: I2C Pressure Sensor A Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_I2C_PRESSURE_B_DEF_L1 0x00000801 /* Sensor_Type: I2C Pressure Sensor B Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_I2C_PRESSURE_A_DEF_L2 0x00000808 /* Sensor_Type: I2C Pressure Sensor A Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_I2C_PRESSURE_B_DEF_L2 0x00000809 /* Sensor_Type: I2C Pressure Sensor B Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_I2C_PRESSURE_A_ADV_L1 0x00000810 /* Sensor_Type: I2C Pressure Sensor A Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_I2C_PRESSURE_B_ADV_L1 0x00000811 /* Sensor_Type: I2C Pressure Sensor B Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_I2C_PRESSURE_A_ADV_L2 0x00000818 /* Sensor_Type: I2C Pressure Sensor A Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_I2C_PRESSURE_B_ADV_L2 0x00000819 /* Sensor_Type: I2C Pressure Sensor B Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_I2C_HUMIDITY_A_DEF_L1 0x00000840 /* Sensor_Type: I2C Humidity Sensor A Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_I2C_HUMIDITY_B_DEF_L1 0x00000841 /* Sensor_Type: I2C Humidity Sensor B Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_I2C_HUMIDITY_A_DEF_L2 0x00000848 /* Sensor_Type: I2C Humidity Sensor A Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_I2C_HUMIDITY_B_DEF_L2 0x00000849 /* Sensor_Type: I2C Humidity Sensor B Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_I2C_HUMIDITY_A_ADV_L1 0x00000850 /* Sensor_Type: I2C Humidity Sensor A Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_I2C_HUMIDITY_B_ADV_L1 0x00000851 /* Sensor_Type: I2C Humidity Sensor B Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_I2C_HUMIDITY_A_ADV_L2 0x00000858 /* Sensor_Type: I2C Humidity Sensor A Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_I2C_HUMIDITY_B_ADV_L2 0x00000859 /* Sensor_Type: I2C Humidity Sensor B Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_I2C_AMBIENTLIGHT_A_DEF_L1 0x00000880 /* Sensor_Type: I2C Ambient Light Sensor A Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_I2C_AMBIENTLIGHT_A_DEF_L2 0x00000888 /* Sensor_Type: I2C Ambient Light Sensor A Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_I2C_AMBIENTLIGHT_A_ADV_L1 0x00000890 /* Sensor_Type: I2C Ambient Light Sensor A Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_I2C_AMBIENTLIGHT_A_ADV_L2 0x00000898 /* Sensor_Type: I2C Ambient Light Sensor A Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_SPI_PRESSURE_A_DEF_L1 0x00000C00 /* Sensor_Type: SPI Pressure Sensor A Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_SPI_PRESSURE_A_DEF_L2 0x00000C08 /* Sensor_Type: SPI Pressure Sensor A Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_SPI_PRESSURE_A_ADV_L1 0x00000C10 /* Sensor_Type: SPI Pressure Sensor A Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_SPI_PRESSURE_A_ADV_L2 0x00000C18 /* Sensor_Type: SPI Pressure Sensor A Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_SPI_HUMIDITY_A_DEF_L1 0x00000C40 /* Sensor_Type: SPI Humidity Sensor A Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_SPI_HUMIDITY_B_DEF_L1 0x00000C41 /* Sensor_Type: SPI Humidity Sensor B Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_SPI_HUMIDITY_A_DEF_L2 0x00000C48 /* Sensor_Type: SPI Humidity Sensor A Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_SPI_HUMIDITY_B_DEF_L2 0x00000C49 /* Sensor_Type: SPI Humidity Sensor B Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_SPI_HUMIDITY_A_ADV_L1 0x00000C50 /* Sensor_Type: SPI Humidity Sensor A Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_SPI_HUMIDITY_B_ADV_L1 0x00000C51 /* Sensor_Type: SPI Humidity Sensor B Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_SPI_HUMIDITY_A_ADV_L2 0x00000C58 /* Sensor_Type: SPI Humidity Sensor A Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_SPI_HUMIDITY_B_ADV_L2 0x00000C59 /* Sensor_Type: SPI Humidity Sensor B Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_SPI_ACCELEROMETER_A_DEF_L1 0x00000C80 /* Sensor_Type: SPI Accelerometer Sensor A 3-Axis Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_SPI_ACCELEROMETER_B_DEF_L1 0x00000C81 /* Sensor_Type: SPI Accelerometer Sensor B 3-Axis Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_SPI_ACCELEROMETER_A_DEF_L2 0x00000C88 /* Sensor_Type: SPI Accelerometer Sensor A 3-Axis Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_SPI_ACCELEROMETER_B_DEF_L2 0x00000C89 /* Sensor_Type: SPI Accelerometer Sensor B 3-Axis Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_SPI_ACCELEROMETER_A_ADV_L1 0x00000C90 /* Sensor_Type: SPI Accelerometer Sensor A 3-Axis Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_SPI_ACCELEROMETER_B_ADV_L1 0x00000C91 /* Sensor_Type: SPI Accelerometer Sensor B 3-Axis Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_SPI_ACCELEROMETER_A_ADV_L2 0x00000C98 /* Sensor_Type: SPI Accelerometer Sensor A 3-Axis Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_SPI_ACCELEROMETER_B_ADV_L2 0x00000C99 /* Sensor_Type: SPI Accelerometer Sensor B 3-Axis Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_UART_CO2_A_DEF_L1 0x00000E00 /* Sensor_Type: UART CO2 Sensor A Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_UART_CO2_B_DEF_L1 0x00000E01 /* Sensor_Type: UART CO2 Sensor B Defined Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_UART_CO2_A_DEF_L2 0x00000E08 /* Sensor_Type: UART CO2 Sensor A Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_UART_CO2_B_DEF_L2 0x00000E09 /* Sensor_Type: UART CO2 Sensor B Defined Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_UART_CO2_A_ADV_L1 0x00000E10 /* Sensor_Type: UART CO2 Sensor A Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_UART_CO2_B_ADV_L1 0x00000E11 /* Sensor_Type: UART CO2 Sensor B Advanced Level 1 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_UART_CO2_A_ADV_L2 0x00000E18 /* Sensor_Type: UART CO2 Sensor A Advanced Level 2 */
#define ENUM_CORE_SENSOR_TYPE_SENSOR_UART_CO2_B_ADV_L2 0x00000E19 /* Sensor_Type: UART CO2 Sensor B Advanced Level 2 */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_SENSOR_DETAILS[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_SENSOR_DETAILS_COMPENSATION_DISABLE 31 /* Indicates Compensation Data Should Not Be Used */
#define BITP_CORE_SENSOR_DETAILS_AVERAGING 28 /* Number of ADC Results to Average */
#define BITP_CORE_SENSOR_DETAILS_PGA_GAIN 24 /* PGA Gain */
#define BITP_CORE_SENSOR_DETAILS_REFERENCE_SELECT 20 /* Reference Selection */
#define BITP_CORE_SENSOR_DETAILS_VBIAS 19 /* Controls ADC Vbias Output */
#define BITP_CORE_SENSOR_DETAILS_REFERENCE_BUFFER_DISABLE 18 /* Enable or Disable ADC Reference Buffer */
#define BITP_CORE_SENSOR_DETAILS_DO_NOT_PUBLISH 17 /* Do Not Publish Channel Result */
#define BITP_CORE_SENSOR_DETAILS_UNITY_LUT_SELECT 16 /* Selects Unity Transfer Function Instead of Sensor Default */
#define BITP_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL 4 /* Indicates Which Channel is Used to Compensate Sensor Result */
#define BITP_CORE_SENSOR_DETAILS_MEASUREMENT_UNITS 0 /* Units of Sensor Measurement */
#define BITM_CORE_SENSOR_DETAILS_COMPENSATION_DISABLE 0x80000000 /* Indicates Compensation Data Should Not Be Used */
#define BITM_CORE_SENSOR_DETAILS_AVERAGING 0x70000000 /* Number of ADC Results to Average */
#define BITM_CORE_SENSOR_DETAILS_PGA_GAIN 0x07000000 /* PGA Gain */
#define BITM_CORE_SENSOR_DETAILS_REFERENCE_SELECT 0x00F00000 /* Reference Selection */
#define BITM_CORE_SENSOR_DETAILS_VBIAS 0x00080000 /* Controls ADC Vbias Output */
#define BITM_CORE_SENSOR_DETAILS_REFERENCE_BUFFER_DISABLE 0x00040000 /* Enable or Disable ADC Reference Buffer */
#define BITM_CORE_SENSOR_DETAILS_DO_NOT_PUBLISH 0x00020000 /* Do Not Publish Channel Result */
#define BITM_CORE_SENSOR_DETAILS_UNITY_LUT_SELECT 0x00010000 /* Selects Unity Transfer Function Instead of Sensor Default */
#define BITM_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL 0x000000F0 /* Indicates Which Channel is Used to Compensate Sensor Result */
#define BITM_CORE_SENSOR_DETAILS_MEASUREMENT_UNITS 0x0000000F /* Units of Sensor Measurement */
#define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_1 0x00000000 /* PGA_Gain: Gain of 1 */
#define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_2 0x01000000 /* PGA_Gain: Gain of 2 */
#define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_4 0x02000000 /* PGA_Gain: Gain of 4 */
#define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_8 0x03000000 /* PGA_Gain: Gain of 8 */
#define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_16 0x04000000 /* PGA_Gain: Gain of 16 */
#define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_32 0x05000000 /* PGA_Gain: Gain of 32 */
#define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_64 0x06000000 /* PGA_Gain: Gain of 64 */
#define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_128 0x07000000 /* PGA_Gain: Gain of 128 */
#define ENUM_CORE_SENSOR_DETAILS_REF_INT 0x00000000 /* Reference_Select: Internal Reference */
#define ENUM_CORE_SENSOR_DETAILS_REF_AVDD 0x00100000 /* Reference_Select: AVDD */
#define ENUM_CORE_SENSOR_DETAILS_REF_VEXT1 0x00200000 /* Reference_Select: External Voltage on Refin1 */
#define ENUM_CORE_SENSOR_DETAILS_REF_VEXT2 0x00300000 /* Reference_Select: External Voltage on Refin2 */
#define ENUM_CORE_SENSOR_DETAILS_REF_RINT1 0x00400000 /* Reference_Select: Internal Resistor1 */
#define ENUM_CORE_SENSOR_DETAILS_REF_RINT2 0x00500000 /* Reference_Select: Internal Resistor2 */
#define ENUM_CORE_SENSOR_DETAILS_REF_REXT1 0x00600000 /* Reference_Select: External Resistor on Refin1 */
#define ENUM_CORE_SENSOR_DETAILS_REF_REXT2 0x00700000 /* Reference_Select: External Resistor on Refin2 */
#define ENUM_CORE_SENSOR_DETAILS_REF_EXC 0x00800000 /* Reference_Select: Bridge Excitation Voltage */
#define ENUM_CORE_SENSOR_DETAILS_UNITS_UNSPECIFIED 0x00000000 /* Measurement_Units: Not Specified */
#define ENUM_CORE_SENSOR_DETAILS_UNITS_RESERVED 0x00000001 /* Measurement_Units: Reserved */
#define ENUM_CORE_SENSOR_DETAILS_UNITS_DEGC 0x00000002 /* Measurement_Units: Degrees C */
#define ENUM_CORE_SENSOR_DETAILS_UNITS_DEGF 0x00000003 /* Measurement_Units: Degrees F */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_CHANNEL_EXCITATION[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_CHANNEL_EXCITATION_IOUT_DONT_SWAP_3WIRE 7 /* Indicates 3-Wire Excitation Currents Should Not Be Swapped */
#define BITP_CORE_CHANNEL_EXCITATION_IOUT_DIODE_RATIO 5 /* Modify Current Ratios Used for Diode Sensor */
#define BITP_CORE_CHANNEL_EXCITATION_IOUT_EXCITATION_CURRENT 0 /* Current Source Value */
#define BITM_CORE_CHANNEL_EXCITATION_IOUT_DONT_SWAP_3WIRE 0x00000080 /* Indicates 3-Wire Excitation Currents Should Not Be Swapped */
#define BITM_CORE_CHANNEL_EXCITATION_IOUT_DIODE_RATIO 0x00000020 /* Modify Current Ratios Used for Diode Sensor */
#define BITM_CORE_CHANNEL_EXCITATION_IOUT_EXCITATION_CURRENT 0x00000007 /* Current Source Value */
#define ENUM_CORE_CHANNEL_EXCITATION_IOUT_DIODE_DEFAULT 0x00000000 /* IOUT_Diode_Ratio: Default Excitation Current Ratios */
#define ENUM_CORE_CHANNEL_EXCITATION_IOUT_DIODE_MAX 0x00000020 /* IOUT_Diode_Ratio: Higher Excitation Current Ratios */
#define ENUM_CORE_CHANNEL_EXCITATION_IEXC_OFF 0x00000000 /* IOUT_Excitation_Current: Disabled */
#define ENUM_CORE_CHANNEL_EXCITATION_IEXC_50UA 0x00000001 /* IOUT_Excitation_Current: 50 \mu;A */
#define ENUM_CORE_CHANNEL_EXCITATION_IEXC_100UA 0x00000002 /* IOUT_Excitation_Current: 100 \mu;A */
#define ENUM_CORE_CHANNEL_EXCITATION_IEXC_250UA 0x00000003 /* IOUT_Excitation_Current: 250 \mu;A */
#define ENUM_CORE_CHANNEL_EXCITATION_IEXC_500UA 0x00000004 /* IOUT_Excitation_Current: 500 \mu;A */
#define ENUM_CORE_CHANNEL_EXCITATION_IEXC_750UA 0x00000005 /* IOUT_Excitation_Current: 750 \mu;A */
#define ENUM_CORE_CHANNEL_EXCITATION_IEXC_1000UA 0x00000006 /* IOUT_Excitation_Current: 1000 \mu;A */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_SETTLING_TIME[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_SETTLING_TIME_SETTLING_TIME_UNITS 14 /* Units for Settling Time */
#define BITP_CORE_SETTLING_TIME_SETTLING_TIME 0 /* Settling Time to Allow When Switching to Channel */
#define BITM_CORE_SETTLING_TIME_SETTLING_TIME_UNITS 0x0000C000 /* Units for Settling Time */
#define BITM_CORE_SETTLING_TIME_SETTLING_TIME 0x00003FFF /* Settling Time to Allow When Switching to Channel */
#define ENUM_CORE_SETTLING_TIME_MICROSECONDS 0x00000000 /* Settling_Time_Units: Micro-Seconds */
#define ENUM_CORE_SETTLING_TIME_MILLISECONDS 0x00004000 /* Settling_Time_Units: Milli-Seconds */
#define ENUM_CORE_SETTLING_TIME_SECONDS 0x00008000 /* Settling_Time_Units: Seconds */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_FILTER_SELECT[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_FILTER_SELECT_ADC_FILTER_TYPE 11 /* ADC Digital Filter Type */
#define BITP_CORE_FILTER_SELECT_ADC_FS 0 /* ADC Digital Filter Select */
#define BITM_CORE_FILTER_SELECT_ADC_FILTER_TYPE 0x0000F800 /* ADC Digital Filter Type */
#define BITM_CORE_FILTER_SELECT_ADC_FS 0x000007FF /* ADC Digital Filter Select */
#define ENUM_CORE_FILTER_SELECT_FILTER_FIR_25SPS 0x00000000 /* ADC_Filter_Type: FIR Filter 25 SPS */
#define ENUM_CORE_FILTER_SELECT_FILTER_FIR_20SPS 0x00000800 /* ADC_Filter_Type: FIR Filter 20 SPS */
#define ENUM_CORE_FILTER_SELECT_FILTER_SINC4 0x00001000 /* ADC_Filter_Type: Sinc4 Filter */
#define ENUM_CORE_FILTER_SELECT_FILTER_TBD 0x00001800 /* ADC_Filter_Type: TBD Filter */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_HIGH_THRESHOLD_LIMIT[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_HIGH_THRESHOLD_LIMIT_HIGH_THRESHOLD 0 /* Upper Limit for Sensor Alert Comparison */
#define BITM_CORE_HIGH_THRESHOLD_LIMIT_HIGH_THRESHOLD 0xFFFFFFFF /* Upper Limit for Sensor Alert Comparison */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_LOW_THRESHOLD_LIMIT[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_LOW_THRESHOLD_LIMIT_LOW_THRESHOLD 0 /* Lower Limit for Sensor Alert Comparison */
#define BITM_CORE_LOW_THRESHOLD_LIMIT_LOW_THRESHOLD 0xFFFFFFFF /* Lower Limit for Sensor Alert Comparison */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_SENSOR_OFFSET[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_SENSOR_OFFSET_SENSOR_OFFSET 0 /* Sensor Offset Adjustment */
#define BITM_CORE_SENSOR_OFFSET_SENSOR_OFFSET 0xFFFFFFFF /* Sensor Offset Adjustment */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_SENSOR_GAIN[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_SENSOR_GAIN_SENSOR_GAIN 0 /* Sensor Gain Adjustment */
#define BITM_CORE_SENSOR_GAIN_SENSOR_GAIN 0xFFFFFFFF /* Sensor Gain Adjustment */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_ALERT_CODE_CH[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_ALERT_CODE_CH_ALERT_CODE_CH 0 /* Per-Channel Code Indicating Type of Alert */
#define BITM_CORE_ALERT_CODE_CH_ALERT_CODE_CH 0x0000FFFF /* Per-Channel Code Indicating Type of Alert */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_CHANNEL_SKIP[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_CHANNEL_SKIP_CHANNEL_SKIP 0 /* Indicates If Channel Will Skip Some Measurement Cycles */
#define BITM_CORE_CHANNEL_SKIP_CHANNEL_SKIP 0x000000FF /* Indicates If Channel Will Skip Some Measurement Cycles */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_SENSOR_PARAMETER[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_SENSOR_PARAMETER_SENSOR_PARAMETER 0 /* Sensor Parameter Adjustment */
#define BITM_CORE_SENSOR_PARAMETER_SENSOR_PARAMETER 0xFFFFFFFF /* Sensor Parameter Adjustment */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_CALIBRATION_PARAMETER[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_CALIBRATION_PARAMETER_CALIBRATION_PARAMETER_ENABLE 24 /* Enables Use of Calibration_Parameter */
#define BITP_CORE_CALIBRATION_PARAMETER_CALIBRATION_PARAMETER 0 /* Calibration Parameter Value */
#define BITM_CORE_CALIBRATION_PARAMETER_CALIBRATION_PARAMETER_ENABLE 0x01000000 /* Enables Use of Calibration_Parameter */
#define BITM_CORE_CALIBRATION_PARAMETER_CALIBRATION_PARAMETER 0x00FFFFFF /* Calibration Parameter Value */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DIGITAL_SENSOR_CONFIG[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_DATA_BITS 11 /* Number of Relevant Data Bits */
#define BITP_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_READ_BYTES 8 /* Number of Bytes to Read from the Sensor */
#define BITP_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_BIT_OFFSET 4 /* Data Bit Offset, Relative to Alignment */
#define BITP_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_LEFT_ALIGNED 3 /* Data Alignment Within the Data Frame */
#define BITP_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_LITTLE_ENDIAN 2 /* Data Endianness of Sensor Result */
#define BITP_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_CODING 0 /* Data Encoding of Sensor Result */
#define BITM_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_DATA_BITS 0x0000F800 /* Number of Relevant Data Bits */
#define BITM_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_READ_BYTES 0x00000700 /* Number of Bytes to Read from the Sensor */
#define BITM_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_BIT_OFFSET 0x000000F0 /* Data Bit Offset, Relative to Alignment */
#define BITM_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_LEFT_ALIGNED 0x00000008 /* Data Alignment Within the Data Frame */
#define BITM_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_LITTLE_ENDIAN 0x00000004 /* Data Endianness of Sensor Result */
#define BITM_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_CODING 0x00000003 /* Data Encoding of Sensor Result */
#define ENUM_CORE_DIGITAL_SENSOR_CONFIG_CODING_NONE 0x00000000 /* Digital_Sensor_Coding: None/Invalid */
#define ENUM_CORE_DIGITAL_SENSOR_CONFIG_CODING_UNIPOLAR 0x00000001 /* Digital_Sensor_Coding: Unipolar */
#define ENUM_CORE_DIGITAL_SENSOR_CONFIG_CODING_TWOS_COMPL 0x00000002 /* Digital_Sensor_Coding: Twos Complement */
#define ENUM_CORE_DIGITAL_SENSOR_CONFIG_CODING_OFFSET_BINARY 0x00000003 /* Digital_Sensor_Coding: Offset Binary */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DIGITAL_SENSOR_ADDRESS[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIGITAL_SENSOR_ADDRESS_DIGITAL_SENSOR_ADDRESS 0 /* I2C Address or Write Address Command for SPI Sensor */
#define BITM_CORE_DIGITAL_SENSOR_ADDRESS_DIGITAL_SENSOR_ADDRESS 0x000000FF /* I2C Address or Write Address Command for SPI Sensor */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DIGITAL_SENSOR_NUM_CMDS[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIGITAL_SENSOR_NUM_CMDS_DIGITAL_SENSOR_NUM_READ_CMDS 4 /* Number of Read Commands for Digital Sensor */
#define BITP_CORE_DIGITAL_SENSOR_NUM_CMDS_DIGITAL_SENSOR_NUM_CFG_CMDS 0 /* Number of Configuration Commands for Digital Sensor */
#define BITM_CORE_DIGITAL_SENSOR_NUM_CMDS_DIGITAL_SENSOR_NUM_READ_CMDS 0x00000070 /* Number of Read Commands for Digital Sensor */
#define BITM_CORE_DIGITAL_SENSOR_NUM_CMDS_DIGITAL_SENSOR_NUM_CFG_CMDS 0x00000007 /* Number of Configuration Commands for Digital Sensor */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DIGITAL_SENSOR_COMMS[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIGITAL_SENSOR_COMMS_UART_MODE 12 /* Configuration for Sensor UART Protocol */
#define BITP_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE 10 /* Configuration for Sensor SPI Protocol */
#define BITP_CORE_DIGITAL_SENSOR_COMMS_UART_BAUD 7 /* Controls Baud Rate for UART Sensors */
#define BITP_CORE_DIGITAL_SENSOR_COMMS_I2C_CLOCK 5 /* Controls SCLK Frequency for I2C Sensors */
#define BITP_CORE_DIGITAL_SENSOR_COMMS_SPI_CLOCK 1 /* Controls Clock Frequency for SPI Sensors */
#define BITP_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_SENSOR_COMMS_EN 0 /* Enable Digital Sensor Comms Register Parameters */
#define BITM_CORE_DIGITAL_SENSOR_COMMS_UART_MODE 0x0000F000 /* Configuration for Sensor UART Protocol */
#define BITM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE 0x00000C00 /* Configuration for Sensor SPI Protocol */
#define BITM_CORE_DIGITAL_SENSOR_COMMS_UART_BAUD 0x00000380 /* Controls Baud Rate for UART Sensors */
#define BITM_CORE_DIGITAL_SENSOR_COMMS_I2C_CLOCK 0x00000060 /* Controls SCLK Frequency for I2C Sensors */
#define BITM_CORE_DIGITAL_SENSOR_COMMS_SPI_CLOCK 0x0000001E /* Controls Clock Frequency for SPI Sensors */
#define BITM_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_SENSOR_COMMS_EN 0x00000001 /* Enable Digital Sensor Comms Register Parameters */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8N1 0x00000000 /* Uart_Mode: 8 Data Bits No Parity 1 Stop Bit */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8N2 0x00001000 /* Uart_Mode: 8 Data Bits No Parity 2 Stop Bits */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8N3 0x00002000 /* Uart_Mode: 8 Data Bits No Parity 3 Stop Bits */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8E1 0x00004000 /* Uart_Mode: 8 Data Bits Even Parity 1 Stop Bit */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8E2 0x00005000 /* Uart_Mode: 8 Data Bits Even Parity 2 Stop Bits */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8E3 0x00006000 /* Uart_Mode: 8 Data Bits Even Parity 3 Stop Bits */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8O1 0x00008000 /* Uart_Mode: 8 Data Bits Odd Parity 1 Stop Bit */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8O2 0x00009000 /* Uart_Mode: 8 Data Bits Odd Parity 2 Stop Bits */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8O3 0x0000A000 /* Uart_Mode: 8 Data Bits Odd Parity 3 Stop Bits */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_0 0x00000000 /* SPI_Mode: Clock Polarity = 0 Clock Phase = 0 */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_1 0x00000400 /* SPI_Mode: Clock Polarity = 0 Clock Phase = 1 */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_2 0x00000800 /* SPI_Mode: Clock Polarity = 1 Clock Phase = 0 */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_3 0x00000C00 /* SPI_Mode: Clock Polarity = 1 Clock Phase = 1 */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_UART_115200 0x00000000 /* Uart_Baud: 115200 bps */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_UART_57600 0x00000080 /* Uart_Baud: 57600 bps */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_UART_38400 0x00000100 /* Uart_Baud: 38400 bps */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_UART_19200 0x00000180 /* Uart_Baud: 19200 bps */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_UART_9600 0x00000200 /* Uart_Baud: 9600 bps */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_UART_4800 0x00000280 /* Uart_Baud: 4800 bps */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_UART_2400 0x00000300 /* Uart_Baud: 2400 bps */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_UART_1200 0x00000380 /* Uart_Baud: 1200 bps */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_I2C_100K 0x00000000 /* I2C_Clock: 100kHz SCL */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_I2C_400K 0x00000020 /* I2C_Clock: 400kHz SCL */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_I2C_RESERVED1 0x00000040 /* I2C_Clock: Reserved */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_I2C_RESERVED2 0x00000060 /* I2C_Clock: Reserved */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_13MHZ 0x00000000 /* SPI_Clock: 13 MHz */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_6_5MHZ 0x00000002 /* SPI_Clock: 6.5 MHz */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_3_25MHZ 0x00000004 /* SPI_Clock: 3.25 MHz */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_1_625MHZ 0x00000006 /* SPI_Clock: 1.625 MHz */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_812KHZ 0x00000008 /* SPI_Clock: 812.5kHz */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_406KHZ 0x0000000A /* SPI_Clock: 406.2kHz */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_203KHZ 0x0000000C /* SPI_Clock: 203.1kHz */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_101KHZ 0x0000000E /* SPI_Clock: 101.5kHz */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_50KHZ 0x00000010 /* SPI_Clock: 50.8kHz */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_25KHZ 0x00000012 /* SPI_Clock: 25.4kHz */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_12KHZ 0x00000014 /* SPI_Clock: 12.7kHz */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_6KHZ 0x00000016 /* SPI_Clock: 6.3kHz */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_3KHZ 0x00000018 /* SPI_Clock: 3.2kHz */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_1_5KHZ 0x0000001A /* SPI_Clock: 1.58kHz */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_793HZ 0x0000001C /* SPI_Clock: 793Hz */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_396HZ 0x0000001E /* SPI_Clock: 396Hz */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_DEFAULT 0x00000000 /* Digital_Sensor_Comms_En: Default Parameters Used for Digital Sensor Communications */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_USER 0x00000001 /* Digital_Sensor_Comms_En: User Supplied Parameters Used for Digital Sensor Communications */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DIGITAL_SENSOR_COMMAND1[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIGITAL_SENSOR_COMMAND1_DIGITAL_SENSOR_COMMAND1 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */
#define BITM_CORE_DIGITAL_SENSOR_COMMAND1_DIGITAL_SENSOR_COMMAND1 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DIGITAL_SENSOR_COMMAND2[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIGITAL_SENSOR_COMMAND2_DIGITAL_SENSOR_COMMAND2 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */
#define BITM_CORE_DIGITAL_SENSOR_COMMAND2_DIGITAL_SENSOR_COMMAND2 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DIGITAL_SENSOR_COMMAND3[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIGITAL_SENSOR_COMMAND3_DIGITAL_SENSOR_COMMAND3 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */
#define BITM_CORE_DIGITAL_SENSOR_COMMAND3_DIGITAL_SENSOR_COMMAND3 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DIGITAL_SENSOR_COMMAND4[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIGITAL_SENSOR_COMMAND4_DIGITAL_SENSOR_COMMAND4 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */
#define BITM_CORE_DIGITAL_SENSOR_COMMAND4_DIGITAL_SENSOR_COMMAND4 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DIGITAL_SENSOR_COMMAND5[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIGITAL_SENSOR_COMMAND5_DIGITAL_SENSOR_COMMAND5 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */
#define BITM_CORE_DIGITAL_SENSOR_COMMAND5_DIGITAL_SENSOR_COMMAND5 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DIGITAL_SENSOR_COMMAND6[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIGITAL_SENSOR_COMMAND6_DIGITAL_SENSOR_COMMAND6 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */
#define BITM_CORE_DIGITAL_SENSOR_COMMAND6_DIGITAL_SENSOR_COMMAND6 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DIGITAL_SENSOR_COMMAND7[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIGITAL_SENSOR_COMMAND7_DIGITAL_SENSOR_COMMAND7 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */
#define BITM_CORE_DIGITAL_SENSOR_COMMAND7_DIGITAL_SENSOR_COMMAND7 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DIGITAL_SENSOR_READ_CMD1[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIGITAL_SENSOR_READ_CMD1_DIGITAL_SENSOR_READ_CMD1 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
#define BITM_CORE_DIGITAL_SENSOR_READ_CMD1_DIGITAL_SENSOR_READ_CMD1 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DIGITAL_SENSOR_READ_CMD2[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIGITAL_SENSOR_READ_CMD2_DIGITAL_SENSOR_READ_CMD2 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
#define BITM_CORE_DIGITAL_SENSOR_READ_CMD2_DIGITAL_SENSOR_READ_CMD2 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DIGITAL_SENSOR_READ_CMD3[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIGITAL_SENSOR_READ_CMD3_DIGITAL_SENSOR_READ_CMD3 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
#define BITM_CORE_DIGITAL_SENSOR_READ_CMD3_DIGITAL_SENSOR_READ_CMD3 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DIGITAL_SENSOR_READ_CMD4[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIGITAL_SENSOR_READ_CMD4_DIGITAL_SENSOR_READ_CMD4 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
#define BITM_CORE_DIGITAL_SENSOR_READ_CMD4_DIGITAL_SENSOR_READ_CMD4 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DIGITAL_SENSOR_READ_CMD5[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIGITAL_SENSOR_READ_CMD5_DIGITAL_SENSOR_READ_CMD5 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
#define BITM_CORE_DIGITAL_SENSOR_READ_CMD5_DIGITAL_SENSOR_READ_CMD5 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DIGITAL_SENSOR_READ_CMD6[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIGITAL_SENSOR_READ_CMD6_DIGITAL_SENSOR_READ_CMD6 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
#define BITM_CORE_DIGITAL_SENSOR_READ_CMD6_DIGITAL_SENSOR_READ_CMD6 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
/* -------------------------------------------------------------------------------------------------------------------------
ADMW_CORE_DIGITAL_SENSOR_READ_CMD7[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIGITAL_SENSOR_READ_CMD7_DIGITAL_SENSOR_READ_CMD7 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
#define BITM_CORE_DIGITAL_SENSOR_READ_CMD7_DIGITAL_SENSOR_READ_CMD7 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
#endif /* end ifndef _DEF1000_REGISTERS_H */