Vybhav Kadaba / Mbed OS EV-PRO-MW1001_Development_v11775

Minor changes to support ADMW FWv1.17.75

inc/admw1001/ADMW1001_REGISTERS_typedefs.h@43:e1789b7214cf, 2020-01-07 (annotated)

Committer:
Vkadaba
Date:
Tue Jan 07 05:45:58 2020 +0000
Revision:
43:e1789b7214cf
Parent:
36:54e2418e7620
Child:
44:94bdfaefddac
Added CycleTime units in seconds Added global scopes for .excitationState and .groundSwitch on mbed and added same on all config files

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Vkadaba 5:0728bde67bdb 1 /* ================================================================================
Vkadaba 32:52445bef314d 2
Vkadaba 32:52445bef314d 3 Created by :
Vkadaba 32:52445bef314d 4 Created on : 2019 Oct 08, 09:43 GMT Daylight Time
Vkadaba 5:0728bde67bdb 5
Vkadaba 5:0728bde67bdb 6 Project : ADMW1001_REGISTERS
Vkadaba 5:0728bde67bdb 7 File : ADMW1001_REGISTERS_typedefs.h
Vkadaba 5:0728bde67bdb 8 Description : C Register Structures
Vkadaba 5:0728bde67bdb 9
Vkadaba 32:52445bef314d 10 !! ADI Confidential !!
Vkadaba 32:52445bef314d 11 INTERNAL USE ONLY
Vkadaba 5:0728bde67bdb 12
Vkadaba 6:9d393a9677f4 13 Copyright (c) 2019 Analog Devices, Inc. All Rights Reserved.
Vkadaba 5:0728bde67bdb 14 This software is proprietary and confidential to Analog Devices, Inc. and
Vkadaba 5:0728bde67bdb 15 its licensors.
Vkadaba 5:0728bde67bdb 16
Vkadaba 5:0728bde67bdb 17 This file was auto-generated. Do not make local changes to this file.
Vkadaba 32:52445bef314d 18
Vkadaba 32:52445bef314d 19 Auto generation script information:
Vkadaba 32:52445bef314d 20 Script: C:\Program Files (x86)\Yoda-19.05.01\generators\inc\genHeaders
Vkadaba 32:52445bef314d 21 Last modified: 26-SEP-2017
Vkadaba 5:0728bde67bdb 22
Vkadaba 5:0728bde67bdb 23 ================================================================================ */
Vkadaba 5:0728bde67bdb 24
Vkadaba 5:0728bde67bdb 25 #ifndef _ADMW1001_REGISTERS_TYPEDEFS_H
Vkadaba 5:0728bde67bdb 26 #define _ADMW1001_REGISTERS_TYPEDEFS_H
Vkadaba 5:0728bde67bdb 27
Vkadaba 5:0728bde67bdb 28 /* pickup integer types */
Vkadaba 5:0728bde67bdb 29 #if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__))
Vkadaba 5:0728bde67bdb 30 #include <stdint.h>
Vkadaba 5:0728bde67bdb 31 #endif /* _LANGUAGE_C */
Vkadaba 5:0728bde67bdb 32
Vkadaba 5:0728bde67bdb 33 #if defined ( __CC_ARM )
Vkadaba 5:0728bde67bdb 34 #pragma push
Vkadaba 5:0728bde67bdb 35 #pragma anon_unions
Vkadaba 5:0728bde67bdb 36 #endif
Vkadaba 5:0728bde67bdb 37
Vkadaba 5:0728bde67bdb 38 /** @defgroup Interface_Config_A Interface Configuration A (Interface_Config_A) Register
Vkadaba 5:0728bde67bdb 39 * Interface Configuration A (Interface_Config_A) Register.
Vkadaba 5:0728bde67bdb 40 * @{
Vkadaba 5:0728bde67bdb 41 */
Vkadaba 5:0728bde67bdb 42
Vkadaba 5:0728bde67bdb 43 /* =========================================================================
Vkadaba 5:0728bde67bdb 44 *! \enum ADMW_SPI_Interface_Config_A_Addr_Ascension
Vkadaba 5:0728bde67bdb 45 *! \brief Determines Sequential Addressing Behavior (Addr_Ascension) Enumerations
Vkadaba 5:0728bde67bdb 46 * ========================================================================= */
Vkadaba 5:0728bde67bdb 47 typedef enum
Vkadaba 5:0728bde67bdb 48 {
Vkadaba 5:0728bde67bdb 49 SPI_INTERFACE_CONFIG_A_DESCEND = 0, /**< Address accessed is decremented by one for each data byte when streaming */
Vkadaba 5:0728bde67bdb 50 SPI_INTERFACE_CONFIG_A_ASCEND = 1 /**< Address accessed is incremented by one for each data byte when streaming */
Vkadaba 5:0728bde67bdb 51 } ADMW_SPI_Interface_Config_A_Addr_Ascension;
Vkadaba 5:0728bde67bdb 52
Vkadaba 5:0728bde67bdb 53
Vkadaba 5:0728bde67bdb 54 /* ==========================================================================
Vkadaba 5:0728bde67bdb 55 *! \struct ADMW_SPI_Interface_Config_A_Struct
Vkadaba 5:0728bde67bdb 56 *! \brief Interface Configuration A Register bit field structure
Vkadaba 5:0728bde67bdb 57 * ========================================================================== */
Vkadaba 8:2f2775c34640 58 typedef struct _ADMW_SPI_Interface_Config_A_t {
Vkadaba 5:0728bde67bdb 59 union {
Vkadaba 5:0728bde67bdb 60 struct {
Vkadaba 32:52445bef314d 61 uint8_t SW_ResetX : 1; /**< Second of Two of the SW_RESET Bits. */
Vkadaba 5:0728bde67bdb 62 uint8_t reserved1 : 3;
Vkadaba 32:52445bef314d 63 uint8_t SDO_Enable : 1; /**< Serial Data Output Pin Enable */
Vkadaba 5:0728bde67bdb 64 uint8_t Addr_Ascension : 1; /**< Determines Sequential Addressing Behavior */
Vkadaba 5:0728bde67bdb 65 uint8_t reserved6 : 1;
Vkadaba 32:52445bef314d 66 uint8_t SW_Reset : 1; /**< First of Two of the SW_RESET Bits. */
Vkadaba 5:0728bde67bdb 67 };
Vkadaba 5:0728bde67bdb 68 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 69 };
Vkadaba 5:0728bde67bdb 70 } ADMW_SPI_Interface_Config_A_t;
Vkadaba 5:0728bde67bdb 71
Vkadaba 5:0728bde67bdb 72 /*@}*/
Vkadaba 5:0728bde67bdb 73
Vkadaba 5:0728bde67bdb 74 /** @defgroup Interface_Config_B Interface Configuration B (Interface_Config_B) Register
Vkadaba 5:0728bde67bdb 75 * Interface Configuration B (Interface_Config_B) Register.
Vkadaba 5:0728bde67bdb 76 * @{
Vkadaba 5:0728bde67bdb 77 */
Vkadaba 5:0728bde67bdb 78
Vkadaba 5:0728bde67bdb 79 /* =========================================================================
Vkadaba 5:0728bde67bdb 80 *! \enum ADMW_SPI_Interface_Config_B_Single_Inst
Vkadaba 5:0728bde67bdb 81 *! \brief Select Streaming or Single Instruction Mode (Single_Inst) Enumerations
Vkadaba 5:0728bde67bdb 82 * ========================================================================= */
Vkadaba 5:0728bde67bdb 83 typedef enum
Vkadaba 5:0728bde67bdb 84 {
Vkadaba 5:0728bde67bdb 85 SPI_INTERFACE_CONFIG_B_STREAMING_MODE = 0, /**< Streaming mode is enabled */
Vkadaba 5:0728bde67bdb 86 SPI_INTERFACE_CONFIG_B_SINGLE_INSTRUCTION_MODE = 1 /**< Single Instruction mode is enabled */
Vkadaba 5:0728bde67bdb 87 } ADMW_SPI_Interface_Config_B_Single_Inst;
Vkadaba 5:0728bde67bdb 88
Vkadaba 5:0728bde67bdb 89
Vkadaba 5:0728bde67bdb 90 /* ==========================================================================
Vkadaba 5:0728bde67bdb 91 *! \struct ADMW_SPI_Interface_Config_B_Struct
Vkadaba 5:0728bde67bdb 92 *! \brief Interface Configuration B Register bit field structure
Vkadaba 5:0728bde67bdb 93 * ========================================================================== */
Vkadaba 8:2f2775c34640 94 typedef struct _ADMW_SPI_Interface_Config_B_t {
Vkadaba 5:0728bde67bdb 95 union {
Vkadaba 5:0728bde67bdb 96 struct {
Vkadaba 5:0728bde67bdb 97 uint8_t reserved0 : 7;
Vkadaba 5:0728bde67bdb 98 uint8_t Single_Inst : 1; /**< Select Streaming or Single Instruction Mode */
Vkadaba 5:0728bde67bdb 99 };
Vkadaba 5:0728bde67bdb 100 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 101 };
Vkadaba 5:0728bde67bdb 102 } ADMW_SPI_Interface_Config_B_t;
Vkadaba 5:0728bde67bdb 103
Vkadaba 5:0728bde67bdb 104 /*@}*/
Vkadaba 5:0728bde67bdb 105
Vkadaba 5:0728bde67bdb 106 /** @defgroup Chip_Type Chip Type (Chip_Type) Register
Vkadaba 5:0728bde67bdb 107 * Chip Type (Chip_Type) Register.
Vkadaba 5:0728bde67bdb 108 * @{
Vkadaba 5:0728bde67bdb 109 */
Vkadaba 5:0728bde67bdb 110
Vkadaba 5:0728bde67bdb 111 /* ==========================================================================
Vkadaba 5:0728bde67bdb 112 *! \struct ADMW_SPI_Chip_Type_Struct
Vkadaba 5:0728bde67bdb 113 *! \brief Chip Type Register bit field structure
Vkadaba 5:0728bde67bdb 114 * ========================================================================== */
Vkadaba 8:2f2775c34640 115 typedef struct _ADMW_SPI_Chip_Type_t {
Vkadaba 5:0728bde67bdb 116 union {
Vkadaba 5:0728bde67bdb 117 struct {
Vkadaba 5:0728bde67bdb 118 uint8_t Chip_Type : 4; /**< Precision ADC */
Vkadaba 5:0728bde67bdb 119 uint8_t reserved4 : 4;
Vkadaba 5:0728bde67bdb 120 };
Vkadaba 5:0728bde67bdb 121 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 122 };
Vkadaba 5:0728bde67bdb 123 } ADMW_SPI_Chip_Type_t;
Vkadaba 5:0728bde67bdb 124
Vkadaba 5:0728bde67bdb 125 /*@}*/
Vkadaba 5:0728bde67bdb 126
Vkadaba 5:0728bde67bdb 127 /** @defgroup Product_ID_L Product ID Low (Product_ID_L) Register
Vkadaba 5:0728bde67bdb 128 * Product ID Low (Product_ID_L) Register.
Vkadaba 5:0728bde67bdb 129 * @{
Vkadaba 5:0728bde67bdb 130 */
Vkadaba 5:0728bde67bdb 131
Vkadaba 5:0728bde67bdb 132 /* ==========================================================================
Vkadaba 5:0728bde67bdb 133 *! \struct ADMW_SPI_Product_ID_L_Struct
Vkadaba 5:0728bde67bdb 134 *! \brief Product ID Low Register bit field structure
Vkadaba 5:0728bde67bdb 135 * ========================================================================== */
Vkadaba 8:2f2775c34640 136 typedef struct _ADMW_SPI_Product_ID_L_t {
Vkadaba 5:0728bde67bdb 137 union {
Vkadaba 5:0728bde67bdb 138 struct {
Vkadaba 32:52445bef314d 139 uint8_t Product_ID_Trim_Bits : 4; /**< These Bits Vary on Die Configured for Multiple Generics */
Vkadaba 32:52445bef314d 140 uint8_t Product_ID_Fixed_Bits : 4; /**< Product_ID_Fixed_Bits[3:0] These Bits are Fixed on Die Configured for Multiple Generics */
Vkadaba 5:0728bde67bdb 141 };
Vkadaba 5:0728bde67bdb 142 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 143 };
Vkadaba 5:0728bde67bdb 144 } ADMW_SPI_Product_ID_L_t;
Vkadaba 5:0728bde67bdb 145
Vkadaba 5:0728bde67bdb 146 /*@}*/
Vkadaba 5:0728bde67bdb 147
Vkadaba 5:0728bde67bdb 148 /** @defgroup Product_ID_H Product ID High (Product_ID_H) Register
Vkadaba 5:0728bde67bdb 149 * Product ID High (Product_ID_H) Register.
Vkadaba 5:0728bde67bdb 150 * @{
Vkadaba 5:0728bde67bdb 151 */
Vkadaba 5:0728bde67bdb 152
Vkadaba 5:0728bde67bdb 153 /* ==========================================================================
Vkadaba 5:0728bde67bdb 154 *! \struct ADMW_SPI_Product_ID_H_Struct
Vkadaba 5:0728bde67bdb 155 *! \brief Product ID High Register bit field structure
Vkadaba 5:0728bde67bdb 156 * ========================================================================== */
Vkadaba 8:2f2775c34640 157 typedef struct _ADMW_SPI_Product_ID_H_t {
Vkadaba 5:0728bde67bdb 158 union {
Vkadaba 5:0728bde67bdb 159 struct {
Vkadaba 32:52445bef314d 160 uint8_t Product_ID_Fixed_Bits : 8; /**< Product_ID_Fixed_Bits[11:4] These Bits are Fixed on Die Configured for Multiple Generics */
Vkadaba 5:0728bde67bdb 161 };
Vkadaba 5:0728bde67bdb 162 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 163 };
Vkadaba 5:0728bde67bdb 164 } ADMW_SPI_Product_ID_H_t;
Vkadaba 5:0728bde67bdb 165
Vkadaba 5:0728bde67bdb 166 /*@}*/
Vkadaba 5:0728bde67bdb 167
Vkadaba 5:0728bde67bdb 168 /** @defgroup Chip_Grade Chip Grade (Chip_Grade) Register
Vkadaba 5:0728bde67bdb 169 * Chip Grade (Chip_Grade) Register.
Vkadaba 5:0728bde67bdb 170 * @{
Vkadaba 5:0728bde67bdb 171 */
Vkadaba 5:0728bde67bdb 172
Vkadaba 5:0728bde67bdb 173 /* ==========================================================================
Vkadaba 5:0728bde67bdb 174 *! \struct ADMW_SPI_Chip_Grade_Struct
Vkadaba 5:0728bde67bdb 175 *! \brief Chip Grade Register bit field structure
Vkadaba 5:0728bde67bdb 176 * ========================================================================== */
Vkadaba 8:2f2775c34640 177 typedef struct _ADMW_SPI_Chip_Grade_t {
Vkadaba 5:0728bde67bdb 178 union {
Vkadaba 5:0728bde67bdb 179 struct {
Vkadaba 32:52445bef314d 180 uint8_t Device_Revision : 4; /**< Device Hardware Revision */
Vkadaba 32:52445bef314d 181 uint8_t Grade : 4; /**< Device Performance Grade */
Vkadaba 5:0728bde67bdb 182 };
Vkadaba 5:0728bde67bdb 183 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 184 };
Vkadaba 5:0728bde67bdb 185 } ADMW_SPI_Chip_Grade_t;
Vkadaba 5:0728bde67bdb 186
Vkadaba 5:0728bde67bdb 187 /*@}*/
Vkadaba 5:0728bde67bdb 188
Vkadaba 5:0728bde67bdb 189 /** @defgroup Scratch_Pad Scratch Pad (Scratch_Pad) Register
Vkadaba 5:0728bde67bdb 190 * Scratch Pad (Scratch_Pad) Register.
Vkadaba 5:0728bde67bdb 191 * @{
Vkadaba 5:0728bde67bdb 192 */
Vkadaba 5:0728bde67bdb 193
Vkadaba 5:0728bde67bdb 194 /* ==========================================================================
Vkadaba 5:0728bde67bdb 195 *! \struct ADMW_SPI_Scratch_Pad_Struct
Vkadaba 5:0728bde67bdb 196 *! \brief Scratch Pad Register bit field structure
Vkadaba 5:0728bde67bdb 197 * ========================================================================== */
Vkadaba 8:2f2775c34640 198 typedef struct _ADMW_SPI_Scratch_Pad_t {
Vkadaba 5:0728bde67bdb 199 union {
Vkadaba 5:0728bde67bdb 200 struct {
Vkadaba 5:0728bde67bdb 201 uint8_t Scratch_Value : 8; /**< Software Scratchpad */
Vkadaba 5:0728bde67bdb 202 };
Vkadaba 5:0728bde67bdb 203 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 204 };
Vkadaba 5:0728bde67bdb 205 } ADMW_SPI_Scratch_Pad_t;
Vkadaba 5:0728bde67bdb 206
Vkadaba 5:0728bde67bdb 207 /*@}*/
Vkadaba 5:0728bde67bdb 208
Vkadaba 5:0728bde67bdb 209 /** @defgroup SPI_Revision SPI Revision (SPI_Revision) Register
Vkadaba 5:0728bde67bdb 210 * SPI Revision (SPI_Revision) Register.
Vkadaba 5:0728bde67bdb 211 * @{
Vkadaba 5:0728bde67bdb 212 */
Vkadaba 5:0728bde67bdb 213
Vkadaba 5:0728bde67bdb 214 /* =========================================================================
Vkadaba 5:0728bde67bdb 215 *! \enum ADMW_SPI_SPI_Revision_Version
Vkadaba 5:0728bde67bdb 216 *! \brief SPI Version (Version) Enumerations
Vkadaba 5:0728bde67bdb 217 * ========================================================================= */
Vkadaba 5:0728bde67bdb 218 typedef enum
Vkadaba 5:0728bde67bdb 219 {
Vkadaba 5:0728bde67bdb 220 SPI_SPI_REVISION_REV1_0 = 2 /**< Revision 1.0 */
Vkadaba 5:0728bde67bdb 221 } ADMW_SPI_SPI_Revision_Version;
Vkadaba 5:0728bde67bdb 222
Vkadaba 5:0728bde67bdb 223
Vkadaba 5:0728bde67bdb 224 /* =========================================================================
Vkadaba 5:0728bde67bdb 225 *! \enum ADMW_SPI_SPI_Revision_SPI_Type
Vkadaba 5:0728bde67bdb 226 *! \brief Always Reads as 0x2 (SPI_Type) Enumerations
Vkadaba 5:0728bde67bdb 227 * ========================================================================= */
Vkadaba 5:0728bde67bdb 228 typedef enum
Vkadaba 5:0728bde67bdb 229 {
Vkadaba 32:52445bef314d 230 SPI_SPI_REVISION_ADI_SPI = 0, /**< ADI_SPI */
Vkadaba 32:52445bef314d 231 SPI_SPI_REVISION_LPT_SPI = 2 /**< LPT_SPI */
Vkadaba 5:0728bde67bdb 232 } ADMW_SPI_SPI_Revision_SPI_Type;
Vkadaba 5:0728bde67bdb 233
Vkadaba 5:0728bde67bdb 234
Vkadaba 5:0728bde67bdb 235 /* ==========================================================================
Vkadaba 5:0728bde67bdb 236 *! \struct ADMW_SPI_SPI_Revision_Struct
Vkadaba 5:0728bde67bdb 237 *! \brief SPI Revision Register bit field structure
Vkadaba 5:0728bde67bdb 238 * ========================================================================== */
Vkadaba 8:2f2775c34640 239 typedef struct _ADMW_SPI_SPI_Revision_t {
Vkadaba 5:0728bde67bdb 240 union {
Vkadaba 5:0728bde67bdb 241 struct {
Vkadaba 5:0728bde67bdb 242 uint8_t Version : 6; /**< SPI Version */
Vkadaba 5:0728bde67bdb 243 uint8_t SPI_Type : 2; /**< Always Reads as 0x2 */
Vkadaba 5:0728bde67bdb 244 };
Vkadaba 5:0728bde67bdb 245 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 246 };
Vkadaba 5:0728bde67bdb 247 } ADMW_SPI_SPI_Revision_t;
Vkadaba 5:0728bde67bdb 248
Vkadaba 5:0728bde67bdb 249 /*@}*/
Vkadaba 5:0728bde67bdb 250
Vkadaba 5:0728bde67bdb 251 /** @defgroup Vendor_L Vendor ID Low (Vendor_L) Register
Vkadaba 5:0728bde67bdb 252 * Vendor ID Low (Vendor_L) Register.
Vkadaba 5:0728bde67bdb 253 * @{
Vkadaba 5:0728bde67bdb 254 */
Vkadaba 5:0728bde67bdb 255
Vkadaba 5:0728bde67bdb 256 /* ==========================================================================
Vkadaba 5:0728bde67bdb 257 *! \struct ADMW_SPI_Vendor_L_Struct
Vkadaba 5:0728bde67bdb 258 *! \brief Vendor ID Low Register bit field structure
Vkadaba 5:0728bde67bdb 259 * ========================================================================== */
Vkadaba 8:2f2775c34640 260 typedef struct _ADMW_SPI_Vendor_L_t {
Vkadaba 5:0728bde67bdb 261 union {
Vkadaba 5:0728bde67bdb 262 struct {
Vkadaba 5:0728bde67bdb 263 uint8_t VID : 8; /**< VID[7:0] Analog Devices Vendor ID */
Vkadaba 5:0728bde67bdb 264 };
Vkadaba 5:0728bde67bdb 265 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 266 };
Vkadaba 5:0728bde67bdb 267 } ADMW_SPI_Vendor_L_t;
Vkadaba 5:0728bde67bdb 268
Vkadaba 5:0728bde67bdb 269 /*@}*/
Vkadaba 5:0728bde67bdb 270
Vkadaba 5:0728bde67bdb 271 /** @defgroup Vendor_H Vendor ID High (Vendor_H) Register
Vkadaba 5:0728bde67bdb 272 * Vendor ID High (Vendor_H) Register.
Vkadaba 5:0728bde67bdb 273 * @{
Vkadaba 5:0728bde67bdb 274 */
Vkadaba 5:0728bde67bdb 275
Vkadaba 5:0728bde67bdb 276 /* ==========================================================================
Vkadaba 5:0728bde67bdb 277 *! \struct ADMW_SPI_Vendor_H_Struct
Vkadaba 5:0728bde67bdb 278 *! \brief Vendor ID High Register bit field structure
Vkadaba 5:0728bde67bdb 279 * ========================================================================== */
Vkadaba 8:2f2775c34640 280 typedef struct _ADMW_SPI_Vendor_H_t {
Vkadaba 5:0728bde67bdb 281 union {
Vkadaba 5:0728bde67bdb 282 struct {
Vkadaba 5:0728bde67bdb 283 uint8_t VID : 8; /**< VID[15:8] Analog Devices Vendor ID */
Vkadaba 5:0728bde67bdb 284 };
Vkadaba 5:0728bde67bdb 285 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 286 };
Vkadaba 5:0728bde67bdb 287 } ADMW_SPI_Vendor_H_t;
Vkadaba 5:0728bde67bdb 288
Vkadaba 5:0728bde67bdb 289 /*@}*/
Vkadaba 5:0728bde67bdb 290
Vkadaba 5:0728bde67bdb 291 /** @defgroup Stream_Mode Stream Mode (Stream_Mode) Register
Vkadaba 5:0728bde67bdb 292 * Stream Mode (Stream_Mode) Register.
Vkadaba 5:0728bde67bdb 293 * @{
Vkadaba 5:0728bde67bdb 294 */
Vkadaba 5:0728bde67bdb 295
Vkadaba 5:0728bde67bdb 296 /* ==========================================================================
Vkadaba 5:0728bde67bdb 297 *! \struct ADMW_SPI_Stream_Mode_Struct
Vkadaba 5:0728bde67bdb 298 *! \brief Stream Mode Register bit field structure
Vkadaba 5:0728bde67bdb 299 * ========================================================================== */
Vkadaba 8:2f2775c34640 300 typedef struct _ADMW_SPI_Stream_Mode_t {
Vkadaba 5:0728bde67bdb 301 union {
Vkadaba 5:0728bde67bdb 302 struct {
Vkadaba 32:52445bef314d 303 uint8_t Loop_Count : 8; /**< Set the Data Byte Count Before Looping to Start Address */
Vkadaba 5:0728bde67bdb 304 };
Vkadaba 5:0728bde67bdb 305 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 306 };
Vkadaba 5:0728bde67bdb 307 } ADMW_SPI_Stream_Mode_t;
Vkadaba 5:0728bde67bdb 308
Vkadaba 5:0728bde67bdb 309 /*@}*/
Vkadaba 5:0728bde67bdb 310
Vkadaba 5:0728bde67bdb 311 /** @defgroup Transfer_Config Transfer Config (Transfer_Config) Register
Vkadaba 5:0728bde67bdb 312 * Transfer Config (Transfer_Config) Register.
Vkadaba 5:0728bde67bdb 313 * @{
Vkadaba 5:0728bde67bdb 314 */
Vkadaba 5:0728bde67bdb 315
Vkadaba 5:0728bde67bdb 316 /* =========================================================================
Vkadaba 5:0728bde67bdb 317 *! \enum ADMW_SPI_Transfer_Config_Stream_Mode
Vkadaba 32:52445bef314d 318 *! \brief When Streaming, Control Master to Slave Transfer (Stream_Mode) Enumerations
Vkadaba 5:0728bde67bdb 319 * ========================================================================= */
Vkadaba 5:0728bde67bdb 320 typedef enum
Vkadaba 5:0728bde67bdb 321 {
Vkadaba 6:9d393a9677f4 322 SPI_TRANSFER_CONFIG_UPDATE_ON_WRITE = 0, /**< Transfers after each byte/mulit-byte register */
Vkadaba 6:9d393a9677f4 323 SPI_TRANSFER_CONFIG_UPDATE_ON_ADDRESS_LOOP = 1 /**< Transfers when address loops */
Vkadaba 5:0728bde67bdb 324 } ADMW_SPI_Transfer_Config_Stream_Mode;
Vkadaba 5:0728bde67bdb 325
Vkadaba 5:0728bde67bdb 326
Vkadaba 5:0728bde67bdb 327 /* ==========================================================================
Vkadaba 5:0728bde67bdb 328 *! \struct ADMW_SPI_Transfer_Config_Struct
Vkadaba 5:0728bde67bdb 329 *! \brief Transfer Config Register bit field structure
Vkadaba 5:0728bde67bdb 330 * ========================================================================== */
Vkadaba 8:2f2775c34640 331 typedef struct _ADMW_SPI_Transfer_Config_t {
Vkadaba 5:0728bde67bdb 332 union {
Vkadaba 5:0728bde67bdb 333 struct {
Vkadaba 5:0728bde67bdb 334 uint8_t reserved0 : 1;
Vkadaba 32:52445bef314d 335 uint8_t Stream_Mode : 1; /**< When Streaming, Control Master to Slave Transfer */
Vkadaba 5:0728bde67bdb 336 uint8_t reserved2 : 6;
Vkadaba 5:0728bde67bdb 337 };
Vkadaba 5:0728bde67bdb 338 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 339 };
Vkadaba 5:0728bde67bdb 340 } ADMW_SPI_Transfer_Config_t;
Vkadaba 5:0728bde67bdb 341
Vkadaba 5:0728bde67bdb 342 /*@}*/
Vkadaba 5:0728bde67bdb 343
Vkadaba 5:0728bde67bdb 344 /** @defgroup Interface_Config_C Interface Configuration C (Interface_Config_C) Register
Vkadaba 5:0728bde67bdb 345 * Interface Configuration C (Interface_Config_C) Register.
Vkadaba 5:0728bde67bdb 346 * @{
Vkadaba 5:0728bde67bdb 347 */
Vkadaba 5:0728bde67bdb 348
Vkadaba 5:0728bde67bdb 349 /* =========================================================================
Vkadaba 5:0728bde67bdb 350 *! \enum ADMW_SPI_Interface_Config_C_Strict_Register_Access
Vkadaba 32:52445bef314d 351 *! \brief Multibyte Registers Must Be Read or Written in Full (Strict_Register_Access) Enumerations
Vkadaba 5:0728bde67bdb 352 * ========================================================================= */
Vkadaba 5:0728bde67bdb 353 typedef enum
Vkadaba 5:0728bde67bdb 354 {
Vkadaba 6:9d393a9677f4 355 SPI_INTERFACE_CONFIG_C_NORMAL_ACCESS = 0, /**< Normal mode, no access restrictions */
Vkadaba 6:9d393a9677f4 356 SPI_INTERFACE_CONFIG_C_STRICT_ACCESS = 1 /**< Strict mode, multi-byte registers require all bytes read/written */
Vkadaba 5:0728bde67bdb 357 } ADMW_SPI_Interface_Config_C_Strict_Register_Access;
Vkadaba 5:0728bde67bdb 358
Vkadaba 5:0728bde67bdb 359
Vkadaba 5:0728bde67bdb 360 /* =========================================================================
Vkadaba 5:0728bde67bdb 361 *! \enum ADMW_SPI_Interface_Config_C_CRC_Enable
Vkadaba 5:0728bde67bdb 362 *! \brief CRC Enable (CRC_Enable) Enumerations
Vkadaba 5:0728bde67bdb 363 * ========================================================================= */
Vkadaba 5:0728bde67bdb 364 typedef enum
Vkadaba 5:0728bde67bdb 365 {
Vkadaba 6:9d393a9677f4 366 SPI_INTERFACE_CONFIG_C_DISABLED = 0, /**< CRC Disabled */
Vkadaba 6:9d393a9677f4 367 SPI_INTERFACE_CONFIG_C_ENABLED = 1 /**< CRC Enabled */
Vkadaba 5:0728bde67bdb 368 } ADMW_SPI_Interface_Config_C_CRC_Enable;
Vkadaba 5:0728bde67bdb 369
Vkadaba 5:0728bde67bdb 370
Vkadaba 5:0728bde67bdb 371 /* ==========================================================================
Vkadaba 5:0728bde67bdb 372 *! \struct ADMW_SPI_Interface_Config_C_Struct
Vkadaba 5:0728bde67bdb 373 *! \brief Interface Configuration C Register bit field structure
Vkadaba 5:0728bde67bdb 374 * ========================================================================== */
Vkadaba 8:2f2775c34640 375 typedef struct _ADMW_SPI_Interface_Config_C_t {
Vkadaba 5:0728bde67bdb 376 union {
Vkadaba 5:0728bde67bdb 377 struct {
Vkadaba 5:0728bde67bdb 378 uint8_t CRC_EnableB : 2; /**< Inverted CRC Enable */
Vkadaba 5:0728bde67bdb 379 uint8_t reserved2 : 2;
Vkadaba 32:52445bef314d 380 uint8_t Send_Status : 1; /**< Sends Status in 4-Wire Mode When Enabled */
Vkadaba 32:52445bef314d 381 uint8_t Strict_Register_Access : 1; /**< Multibyte Registers Must Be Read or Written in Full */
Vkadaba 5:0728bde67bdb 382 uint8_t CRC_Enable : 2; /**< CRC Enable */
Vkadaba 5:0728bde67bdb 383 };
Vkadaba 5:0728bde67bdb 384 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 385 };
Vkadaba 5:0728bde67bdb 386 } ADMW_SPI_Interface_Config_C_t;
Vkadaba 5:0728bde67bdb 387
Vkadaba 5:0728bde67bdb 388 /*@}*/
Vkadaba 5:0728bde67bdb 389
Vkadaba 5:0728bde67bdb 390 /** @defgroup Interface_Status_A Interface Status A (Interface_Status_A) Register
Vkadaba 5:0728bde67bdb 391 * Interface Status A (Interface_Status_A) Register.
Vkadaba 5:0728bde67bdb 392 * @{
Vkadaba 5:0728bde67bdb 393 */
Vkadaba 5:0728bde67bdb 394
Vkadaba 5:0728bde67bdb 395 /* ==========================================================================
Vkadaba 5:0728bde67bdb 396 *! \struct ADMW_SPI_Interface_Status_A_Struct
Vkadaba 5:0728bde67bdb 397 *! \brief Interface Status A Register bit field structure
Vkadaba 5:0728bde67bdb 398 * ========================================================================== */
Vkadaba 8:2f2775c34640 399 typedef struct _ADMW_SPI_Interface_Status_A_t {
Vkadaba 5:0728bde67bdb 400 union {
Vkadaba 5:0728bde67bdb 401 struct {
Vkadaba 32:52445bef314d 402 uint8_t Address_Invalid_Error : 1; /**< Attempt to Read/Write Nonexistent Register Address */
Vkadaba 5:0728bde67bdb 403 uint8_t Register_Partial_Access_Error : 1; /**< Set When Fewer Than Expected Number of Bytes Read/Written */
Vkadaba 32:52445bef314d 404 uint8_t Wr_To_Rd_Only_Reg_Error : 1; /**< Write to Read Only Register Attempted */
Vkadaba 5:0728bde67bdb 405 uint8_t CRC_Error : 1; /**< Invalid/No CRC Received */
Vkadaba 5:0728bde67bdb 406 uint8_t Clock_Count_Error : 1; /**< Incorrect Number of Clocks Detected in a Transaction */
Vkadaba 5:0728bde67bdb 407 uint8_t reserved5 : 2;
Vkadaba 5:0728bde67bdb 408 uint8_t Not_Ready_Error : 1; /**< Device Not Ready for Transaction */
Vkadaba 5:0728bde67bdb 409 };
Vkadaba 5:0728bde67bdb 410 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 411 };
Vkadaba 5:0728bde67bdb 412 } ADMW_SPI_Interface_Status_A_t;
Vkadaba 5:0728bde67bdb 413
Vkadaba 5:0728bde67bdb 414 /*@}*/
Vkadaba 5:0728bde67bdb 415
Vkadaba 32:52445bef314d 416 /** @defgroup Command Special Command Register (Command) Register
Vkadaba 32:52445bef314d 417 * Special Command Register (Command) Register.
Vkadaba 5:0728bde67bdb 418 * @{
Vkadaba 5:0728bde67bdb 419 */
Vkadaba 5:0728bde67bdb 420
Vkadaba 5:0728bde67bdb 421 /* =========================================================================
Vkadaba 8:2f2775c34640 422 *! \enum ADMW_CORE_Command_Special_Command
Vkadaba 5:0728bde67bdb 423 *! \brief Special Command (Special_Command) Enumerations
Vkadaba 5:0728bde67bdb 424 * ========================================================================= */
Vkadaba 5:0728bde67bdb 425 typedef enum
Vkadaba 5:0728bde67bdb 426 {
Vkadaba 32:52445bef314d 427 CORE_COMMAND_NOP = 0, /**< No command */
Vkadaba 32:52445bef314d 428 CORE_COMMAND_CONVERT = 1, /**< Start ADC conversions */
Vkadaba 32:52445bef314d 429 CORE_COMMAND_CONVERT_WITH_RAW = 2, /**< Start conversions with added raw ADC data */
Vkadaba 32:52445bef314d 430 CORE_COMMAND_LATCH_CONFIG = 7, /**< Latch configuration. */
Vkadaba 32:52445bef314d 431 CORE_COMMAND_LOAD_LUT = 8, /**< Load LUT from flash */
Vkadaba 32:52445bef314d 432 CORE_COMMAND_SAVE_LUT = 9, /**< Save LUT to flash */
Vkadaba 32:52445bef314d 433 CORE_COMMAND_POWER_DOWN = 20, /**< Enter Low Power State */
Vkadaba 32:52445bef314d 434 CORE_COMMAND_LOAD_CONFIG_1 = 24, /**< Load registers with configuration from flash */
Vkadaba 32:52445bef314d 435 CORE_COMMAND_SAVE_CONFIG_1 = 25 /**< Store current registers to flash configuration */
Vkadaba 8:2f2775c34640 436 } ADMW_CORE_Command_Special_Command;
Vkadaba 5:0728bde67bdb 437
Vkadaba 5:0728bde67bdb 438
Vkadaba 5:0728bde67bdb 439 /* ==========================================================================
Vkadaba 8:2f2775c34640 440 *! \struct ADMW_CORE_Command_Struct
Vkadaba 5:0728bde67bdb 441 *! \brief Special Command Register bit field structure
Vkadaba 5:0728bde67bdb 442 * ========================================================================== */
Vkadaba 8:2f2775c34640 443 typedef struct _ADMW_CORE_Command_t {
Vkadaba 5:0728bde67bdb 444 union {
Vkadaba 5:0728bde67bdb 445 struct {
Vkadaba 5:0728bde67bdb 446 uint8_t Special_Command : 8; /**< Special Command */
Vkadaba 5:0728bde67bdb 447 };
Vkadaba 5:0728bde67bdb 448 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 449 };
Vkadaba 8:2f2775c34640 450 } ADMW_CORE_Command_t;
Vkadaba 5:0728bde67bdb 451
Vkadaba 5:0728bde67bdb 452 /*@}*/
Vkadaba 5:0728bde67bdb 453
Vkadaba 5:0728bde67bdb 454 /** @defgroup Mode Operating Mode and DRDY Control (Mode) Register
Vkadaba 5:0728bde67bdb 455 * Operating Mode and DRDY Control (Mode) Register.
Vkadaba 5:0728bde67bdb 456 * @{
Vkadaba 5:0728bde67bdb 457 */
Vkadaba 5:0728bde67bdb 458
Vkadaba 5:0728bde67bdb 459 /* =========================================================================
Vkadaba 8:2f2775c34640 460 *! \enum ADMW_CORE_Mode_Conversion_Mode
Vkadaba 5:0728bde67bdb 461 *! \brief Conversion Mode (Conversion_Mode) Enumerations
Vkadaba 5:0728bde67bdb 462 * ========================================================================= */
Vkadaba 5:0728bde67bdb 463 typedef enum
Vkadaba 5:0728bde67bdb 464 {
Vkadaba 32:52445bef314d 465 CORE_MODE_SINGLECYCLE = 0, /**< Single cycle conversion mode. A cycle is completed every time a convert command is issued */
Vkadaba 32:52445bef314d 466 CORE_MODE_RESERVED = 1, /**< Reserved for future use */
Vkadaba 32:52445bef314d 467 CORE_MODE_CONTINUOUS = 2 /**< Continuous conversion mode. A cycle is started repeatedly at time specified in cycle time */
Vkadaba 8:2f2775c34640 468 } ADMW_CORE_Mode_Conversion_Mode;
Vkadaba 5:0728bde67bdb 469
Vkadaba 5:0728bde67bdb 470
Vkadaba 5:0728bde67bdb 471 /* =========================================================================
Vkadaba 8:2f2775c34640 472 *! \enum ADMW_CORE_Mode_Drdy_Mode
Vkadaba 32:52445bef314d 473 *! \brief Indicates Behavior of DRDY Pin (Drdy_Mode) Enumerations
Vkadaba 5:0728bde67bdb 474 * ========================================================================= */
Vkadaba 5:0728bde67bdb 475 typedef enum
Vkadaba 5:0728bde67bdb 476 {
Vkadaba 32:52445bef314d 477 CORE_MODE_DRDY_PER_CONVERSION = 0, /**< Data ready per conversion */
Vkadaba 32:52445bef314d 478 CORE_MODE_DRDY_PER_CYCLE = 1 /**< Data ready per cycle */
Vkadaba 8:2f2775c34640 479 } ADMW_CORE_Mode_Drdy_Mode;
Vkadaba 5:0728bde67bdb 480
Vkadaba 5:0728bde67bdb 481
Vkadaba 5:0728bde67bdb 482 /* ==========================================================================
Vkadaba 8:2f2775c34640 483 *! \struct ADMW_CORE_Mode_Struct
Vkadaba 5:0728bde67bdb 484 *! \brief Operating Mode and DRDY Control Register bit field structure
Vkadaba 5:0728bde67bdb 485 * ========================================================================== */
Vkadaba 8:2f2775c34640 486 typedef struct _ADMW_CORE_Mode_t {
Vkadaba 5:0728bde67bdb 487 union {
Vkadaba 5:0728bde67bdb 488 struct {
Vkadaba 5:0728bde67bdb 489 uint8_t Conversion_Mode : 2; /**< Conversion Mode */
Vkadaba 32:52445bef314d 490 uint8_t Drdy_Mode : 2; /**< Indicates Behavior of DRDY Pin */
Vkadaba 6:9d393a9677f4 491 uint8_t reserved4 : 4;
Vkadaba 5:0728bde67bdb 492 };
Vkadaba 5:0728bde67bdb 493 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 494 };
Vkadaba 8:2f2775c34640 495 } ADMW_CORE_Mode_t;
Vkadaba 5:0728bde67bdb 496
Vkadaba 5:0728bde67bdb 497 /*@}*/
Vkadaba 5:0728bde67bdb 498
Vkadaba 32:52445bef314d 499 /** @defgroup Power_Config Power Configuration (Power_Config) Register
Vkadaba 32:52445bef314d 500 * Power Configuration (Power_Config) Register.
Vkadaba 5:0728bde67bdb 501 * @{
Vkadaba 5:0728bde67bdb 502 */
Vkadaba 5:0728bde67bdb 503
Vkadaba 5:0728bde67bdb 504 /* =========================================================================
Vkadaba 8:2f2775c34640 505 *! \enum ADMW_CORE_Power_Config_Power_Mode_MCU
Vkadaba 6:9d393a9677f4 506 *! \brief MCU Power Mode (Power_Mode_MCU) Enumerations
Vkadaba 5:0728bde67bdb 507 * ========================================================================= */
Vkadaba 5:0728bde67bdb 508 typedef enum
Vkadaba 5:0728bde67bdb 509 {
Vkadaba 32:52445bef314d 510 CORE_POWER_CONFIG_ACTIVE_MODE = 0, /**< ADMW1001 is fully power up and ready to convert */
Vkadaba 32:52445bef314d 511 CORE_POWER_CONFIG_HIBERNATION = 1 /**< Lowest power mode. wakeup pin required to enter active mode. SPI powered down */
Vkadaba 8:2f2775c34640 512 } ADMW_CORE_Power_Config_Power_Mode_MCU;
Vkadaba 5:0728bde67bdb 513
Vkadaba 5:0728bde67bdb 514
Vkadaba 5:0728bde67bdb 515 /* ==========================================================================
Vkadaba 8:2f2775c34640 516 *! \struct ADMW_CORE_Power_Config_Struct
Vkadaba 32:52445bef314d 517 *! \brief Power Configuration Register bit field structure
Vkadaba 5:0728bde67bdb 518 * ========================================================================== */
Vkadaba 8:2f2775c34640 519 typedef struct _ADMW_CORE_Power_Config_t {
Vkadaba 5:0728bde67bdb 520 union {
Vkadaba 5:0728bde67bdb 521 struct {
Vkadaba 6:9d393a9677f4 522 uint8_t Power_Mode_MCU : 1; /**< MCU Power Mode */
Vkadaba 6:9d393a9677f4 523 uint8_t reserved1 : 7;
Vkadaba 5:0728bde67bdb 524 };
Vkadaba 5:0728bde67bdb 525 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 526 };
Vkadaba 8:2f2775c34640 527 } ADMW_CORE_Power_Config_t;
Vkadaba 5:0728bde67bdb 528
Vkadaba 5:0728bde67bdb 529 /*@}*/
Vkadaba 5:0728bde67bdb 530
Vkadaba 5:0728bde67bdb 531 /** @defgroup Cycle_Control Measurement Cycle (Cycle_Control) Register
Vkadaba 5:0728bde67bdb 532 * Measurement Cycle (Cycle_Control) Register.
Vkadaba 5:0728bde67bdb 533 * @{
Vkadaba 5:0728bde67bdb 534 */
Vkadaba 5:0728bde67bdb 535
Vkadaba 5:0728bde67bdb 536 /* =========================================================================
Vkadaba 43:e1789b7214cf 537 *! \enum ADMW_CORE_Cycle_Control_GND_SW_CTRL
Vkadaba 43:e1789b7214cf 538 *! \brief Ground Switch Cycle Control (GND_SW_CTRL) Enumerations
Vkadaba 43:e1789b7214cf 539 * ========================================================================= */
Vkadaba 43:e1789b7214cf 540 typedef enum
Vkadaba 43:e1789b7214cf 541 {
Vkadaba 43:e1789b7214cf 542 CORE_CYCLE_CONTROL_CLOSE_SW = 0, /**< Ground Switch Closed */
Vkadaba 43:e1789b7214cf 543 CORE_CYCLE_CONTROL_CYCLE_SW = 1 /**< Ground Switch Opens outside of measurement cycle to conserve power */
Vkadaba 43:e1789b7214cf 544 } ADMW_CORE_Cycle_Control_GND_SW_CTRL;
Vkadaba 43:e1789b7214cf 545
Vkadaba 43:e1789b7214cf 546 /* =========================================================================
Vkadaba 8:2f2775c34640 547 *! \enum ADMW_CORE_Cycle_Control_Vbias
Vkadaba 8:2f2775c34640 548 *! \brief Voltage Bias Global Enable (Vbias) Enumerations
Vkadaba 8:2f2775c34640 549 * ========================================================================= */
Vkadaba 8:2f2775c34640 550 typedef enum
Vkadaba 8:2f2775c34640 551 {
Vkadaba 32:52445bef314d 552 CORE_CYCLE_CONTROL_VBIAS_DISABLE = 0, /**< Vbias disabled */
Vkadaba 32:52445bef314d 553 CORE_CYCLE_CONTROL_VBIAS_ENABLE = 1 /**< Enable Vbias output for the duration of a cycle */
Vkadaba 8:2f2775c34640 554 } ADMW_CORE_Cycle_Control_Vbias;
Vkadaba 8:2f2775c34640 555
Vkadaba 8:2f2775c34640 556
Vkadaba 8:2f2775c34640 557 /* =========================================================================
Vkadaba 8:2f2775c34640 558 *! \enum ADMW_CORE_Cycle_Control_Cycle_Time_Units
Vkadaba 5:0728bde67bdb 559 *! \brief Units for Cycle Time (Cycle_Time_Units) Enumerations
Vkadaba 5:0728bde67bdb 560 * ========================================================================= */
Vkadaba 5:0728bde67bdb 561 typedef enum
Vkadaba 5:0728bde67bdb 562 {
Vkadaba 32:52445bef314d 563 CORE_CYCLE_CONTROL_MILLISECONDS = 0, /**< Milli-seconds */
Vkadaba 8:2f2775c34640 564 CORE_CYCLE_CONTROL_SECONDS = 1 /**< Seconds */
Vkadaba 8:2f2775c34640 565 } ADMW_CORE_Cycle_Control_Cycle_Time_Units;
Vkadaba 5:0728bde67bdb 566
Vkadaba 43:e1789b7214cf 567 /* =========================================================================
Vkadaba 43:e1789b7214cf 568 *! \enum ADMW_CORE_Cycle_Control_PST_MEAS_EXC_CTRL
Vkadaba 43:e1789b7214cf 569 *! \brief Disable Current Sources After Measurement Completes (PST_MEAS_EXC_CTRL) Enumerations
Vkadaba 43:e1789b7214cf 570 * ========================================================================= */
Vkadaba 43:e1789b7214cf 571 typedef enum
Vkadaba 43:e1789b7214cf 572 {
Vkadaba 43:e1789b7214cf 573 CORE_CYCLE_CONTROL_POWERCYCLE = 0, /**< */
Vkadaba 43:e1789b7214cf 574 CORE_CYCLE_CONTROL_ALWAYSON = 1 /**< */
Vkadaba 43:e1789b7214cf 575 } ADMW_CORE_Cycle_Control_PST_MEAS_EXC_CTRL;
Vkadaba 5:0728bde67bdb 576
Vkadaba 5:0728bde67bdb 577 /* ==========================================================================
Vkadaba 8:2f2775c34640 578 *! \struct ADMW_CORE_Cycle_Control_Struct
Vkadaba 5:0728bde67bdb 579 *! \brief Measurement Cycle Register bit field structure
Vkadaba 5:0728bde67bdb 580 * ========================================================================== */
Vkadaba 8:2f2775c34640 581 typedef struct _ADMW_CORE_Cycle_Control_t {
Vkadaba 5:0728bde67bdb 582 union {
Vkadaba 5:0728bde67bdb 583 struct {
Vkadaba 32:52445bef314d 584 uint16_t Cycle_Time : 12; /**< Time Between Measurement Cycles */
Vkadaba 43:e1789b7214cf 585 uint16_t GND_SW_CTRL : 1; /**< Ground Switch Cycle Control */
Vkadaba 8:2f2775c34640 586 uint16_t Vbias : 1; /**< Voltage Bias Global Enable */
Vkadaba 32:52445bef314d 587 uint16_t Cycle_Time_Units : 1; /**< Units for Cycle Time */
Vkadaba 43:e1789b7214cf 588 uint16_t PST_MEAS_EXC_CTRL : 1; /**< Disable Current Sources After Measurement Completes */
Vkadaba 5:0728bde67bdb 589 };
Vkadaba 5:0728bde67bdb 590 uint16_t VALUE16;
Vkadaba 5:0728bde67bdb 591 };
Vkadaba 8:2f2775c34640 592 } ADMW_CORE_Cycle_Control_t;
Vkadaba 5:0728bde67bdb 593
Vkadaba 5:0728bde67bdb 594 /*@}*/
Vkadaba 5:0728bde67bdb 595
Vkadaba 32:52445bef314d 596 /** @defgroup Fifo_Num_Cycles Number of Measurement Cycles to Store in FIFO (Fifo_Num_Cycles) Register
Vkadaba 32:52445bef314d 597 * Number of Measurement Cycles to Store in FIFO (Fifo_Num_Cycles) Register.
Vkadaba 32:52445bef314d 598 * @{
Vkadaba 32:52445bef314d 599 */
Vkadaba 32:52445bef314d 600
Vkadaba 32:52445bef314d 601 /* ==========================================================================
Vkadaba 32:52445bef314d 602 *! \struct ADMW_CORE_Fifo_Num_Cycles_Struct
Vkadaba 32:52445bef314d 603 *! \brief Number of Measurement Cycles to Store in FIFO Register bit field structure
Vkadaba 32:52445bef314d 604 * ========================================================================== */
Vkadaba 32:52445bef314d 605 typedef struct _ADMW_CORE_Fifo_Num_Cycles_t {
Vkadaba 32:52445bef314d 606 union {
Vkadaba 32:52445bef314d 607 struct {
Vkadaba 32:52445bef314d 608 uint8_t Fifo_Num_Cycles : 8; /**< Number of Cycles to Fill the FIFO */
Vkadaba 32:52445bef314d 609 };
Vkadaba 32:52445bef314d 610 uint8_t VALUE8;
Vkadaba 32:52445bef314d 611 };
Vkadaba 32:52445bef314d 612 } ADMW_CORE_Fifo_Num_Cycles_t;
Vkadaba 32:52445bef314d 613
Vkadaba 32:52445bef314d 614 /*@}*/
Vkadaba 32:52445bef314d 615
Vkadaba 5:0728bde67bdb 616 /** @defgroup Status General Status (Status) Register
Vkadaba 5:0728bde67bdb 617 * General Status (Status) Register.
Vkadaba 5:0728bde67bdb 618 * @{
Vkadaba 5:0728bde67bdb 619 */
Vkadaba 5:0728bde67bdb 620
Vkadaba 5:0728bde67bdb 621 /* ==========================================================================
Vkadaba 8:2f2775c34640 622 *! \struct ADMW_CORE_Status_Struct
Vkadaba 5:0728bde67bdb 623 *! \brief General Status Register bit field structure
Vkadaba 5:0728bde67bdb 624 * ========================================================================== */
Vkadaba 8:2f2775c34640 625 typedef struct _ADMW_CORE_Status_t {
Vkadaba 5:0728bde67bdb 626 union {
Vkadaba 5:0728bde67bdb 627 struct {
Vkadaba 32:52445bef314d 628 uint8_t Configuration_Error : 1; /**< Indicates Error with Programmed Configuration */
Vkadaba 32:52445bef314d 629 uint8_t Alert_Active : 1; /**< Indicates One or More Sensor Alerts Active */
Vkadaba 32:52445bef314d 630 uint8_t Error : 1; /**< Indicates an Error */
Vkadaba 32:52445bef314d 631 uint8_t Drdy : 1; /**< Indicates New Sensor Result Available to Read */
Vkadaba 32:52445bef314d 632 uint8_t Cmd_Running : 1; /**< Indicates Special Command Active */
Vkadaba 32:52445bef314d 633 uint8_t FIFO_Error : 1; /**< Indicates Error with FIFO */
Vkadaba 32:52445bef314d 634 uint8_t Diag_Checksum_Error : 1; /**< Indicates Error on Internal Checksum Calculations */
Vkadaba 32:52445bef314d 635 uint8_t LUT_Error : 1; /**< Indicates Error with One or More Lookup Tables */
Vkadaba 5:0728bde67bdb 636 };
Vkadaba 5:0728bde67bdb 637 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 638 };
Vkadaba 8:2f2775c34640 639 } ADMW_CORE_Status_t;
Vkadaba 5:0728bde67bdb 640
Vkadaba 5:0728bde67bdb 641 /*@}*/
Vkadaba 5:0728bde67bdb 642
Vkadaba 5:0728bde67bdb 643 /** @defgroup Channel_Alert_Status Alert Status Summary (Channel_Alert_Status) Register
Vkadaba 5:0728bde67bdb 644 * Alert Status Summary (Channel_Alert_Status) Register.
Vkadaba 5:0728bde67bdb 645 * @{
Vkadaba 5:0728bde67bdb 646 */
Vkadaba 5:0728bde67bdb 647
Vkadaba 5:0728bde67bdb 648 /* ==========================================================================
Vkadaba 8:2f2775c34640 649 *! \struct ADMW_CORE_Channel_Alert_Status_Struct
Vkadaba 5:0728bde67bdb 650 *! \brief Alert Status Summary Register bit field structure
Vkadaba 5:0728bde67bdb 651 * ========================================================================== */
Vkadaba 8:2f2775c34640 652 typedef struct _ADMW_CORE_Channel_Alert_Status_t {
Vkadaba 5:0728bde67bdb 653 union {
Vkadaba 5:0728bde67bdb 654 struct {
Vkadaba 32:52445bef314d 655 uint16_t Alert_Ch0 : 1; /**< Indicates Channel 0 Alert Active */
Vkadaba 32:52445bef314d 656 uint16_t Alert_Ch1 : 1; /**< Indicates Channel 1 Alert Active */
Vkadaba 32:52445bef314d 657 uint16_t Alert_Ch2 : 1; /**< Indicates Channel 2 Alert Active */
Vkadaba 32:52445bef314d 658 uint16_t Alert_Ch3 : 1; /**< Indicates Channel 3 Alert Active */
Vkadaba 32:52445bef314d 659 uint16_t Alert_Ch4 : 1; /**< Indicates Channel 4 Alert Active */
Vkadaba 32:52445bef314d 660 uint16_t Alert_Ch5 : 1; /**< Indicates Channel 5Alert Active */
Vkadaba 32:52445bef314d 661 uint16_t Alert_Ch6 : 1; /**< Indicates Channel 6 Alert Active */
Vkadaba 32:52445bef314d 662 uint16_t Alert_Ch7 : 1; /**< Indicates Channel 7 Alert Active */
Vkadaba 32:52445bef314d 663 uint16_t Alert_Ch8 : 1; /**< Indicates Channel 8 Alert Active */
Vkadaba 32:52445bef314d 664 uint16_t Alert_Ch9 : 1; /**< Indicates Channel 9 Alert Active */
Vkadaba 32:52445bef314d 665 uint16_t Alert_Ch10 : 1; /**< Indicates Channel 10 Alert Active */
Vkadaba 32:52445bef314d 666 uint16_t Alert_Ch11 : 1; /**< Indicates Channel 11 Alert Active */
Vkadaba 32:52445bef314d 667 uint16_t Alert_Ch12 : 1; /**< Indicates Channel 12 Alert Active */
Vkadaba 32:52445bef314d 668 uint16_t reserved13 : 3;
Vkadaba 5:0728bde67bdb 669 };
Vkadaba 5:0728bde67bdb 670 uint16_t VALUE16;
Vkadaba 5:0728bde67bdb 671 };
Vkadaba 8:2f2775c34640 672 } ADMW_CORE_Channel_Alert_Status_t;
Vkadaba 5:0728bde67bdb 673
Vkadaba 5:0728bde67bdb 674 /*@}*/
Vkadaba 5:0728bde67bdb 675
Vkadaba 32:52445bef314d 676 /** @defgroup Alert_Detail_Ch Detailed Channel Error Information (Alert_Detail_Ch) Register
Vkadaba 32:52445bef314d 677 * Detailed Channel Error Information (Alert_Detail_Ch) Register.
Vkadaba 5:0728bde67bdb 678 * @{
Vkadaba 5:0728bde67bdb 679 */
Vkadaba 5:0728bde67bdb 680
Vkadaba 5:0728bde67bdb 681 /* ==========================================================================
Vkadaba 8:2f2775c34640 682 *! \struct ADMW_CORE_Alert_Detail_Ch_Struct
Vkadaba 32:52445bef314d 683 *! \brief Detailed Channel Error Information Register bit field structure
Vkadaba 5:0728bde67bdb 684 * ========================================================================== */
Vkadaba 8:2f2775c34640 685 typedef struct _ADMW_CORE_Alert_Detail_Ch_t {
Vkadaba 5:0728bde67bdb 686 union {
Vkadaba 5:0728bde67bdb 687 struct {
Vkadaba 32:52445bef314d 688 uint16_t Result_Valid : 1; /**< Set If a Result is Valid */
Vkadaba 32:52445bef314d 689 uint16_t ADC_Near_Overrange : 1; /**< Indicates If the ADC is Near Overrange */
Vkadaba 32:52445bef314d 690 uint16_t Sensor_UnderRange : 1; /**< Indicates If the Sensor is Underrange */
Vkadaba 32:52445bef314d 691 uint16_t Sensor_OverRange : 1; /**< Indicates If the Sensor is Overrange */
Vkadaba 32:52445bef314d 692 uint16_t CJ_Soft_Fault : 1; /**< Cold Junction Soft Fault */
Vkadaba 32:52445bef314d 693 uint16_t CJ_Hard_Fault : 1; /**< Cold Junction Hard Fault */
Vkadaba 32:52445bef314d 694 uint16_t ADC_Input_OverRange : 1; /**< Indicates the ADC Input is Overrange */
Vkadaba 32:52445bef314d 695 uint16_t Sensor_HardFault : 1; /**< Indicates Sensor Hard Fault */
Vkadaba 32:52445bef314d 696 uint16_t reserved8 : 8;
Vkadaba 5:0728bde67bdb 697 };
Vkadaba 5:0728bde67bdb 698 uint16_t VALUE16;
Vkadaba 5:0728bde67bdb 699 };
Vkadaba 8:2f2775c34640 700 } ADMW_CORE_Alert_Detail_Ch_t;
Vkadaba 5:0728bde67bdb 701
Vkadaba 5:0728bde67bdb 702 /*@}*/
Vkadaba 5:0728bde67bdb 703
Vkadaba 5:0728bde67bdb 704 /** @defgroup Error_Code Code Indicating Source of Error (Error_Code) Register
Vkadaba 5:0728bde67bdb 705 * Code Indicating Source of Error (Error_Code) Register.
Vkadaba 5:0728bde67bdb 706 * @{
Vkadaba 5:0728bde67bdb 707 */
Vkadaba 5:0728bde67bdb 708
Vkadaba 5:0728bde67bdb 709 /* ==========================================================================
Vkadaba 8:2f2775c34640 710 *! \struct ADMW_CORE_Error_Code_Struct
Vkadaba 5:0728bde67bdb 711 *! \brief Code Indicating Source of Error Register bit field structure
Vkadaba 5:0728bde67bdb 712 * ========================================================================== */
Vkadaba 8:2f2775c34640 713 typedef struct _ADMW_CORE_Error_Code_t {
Vkadaba 5:0728bde67bdb 714 union {
Vkadaba 5:0728bde67bdb 715 struct {
Vkadaba 5:0728bde67bdb 716 uint16_t Error_Code : 16; /**< Code Indicating Type of Error */
Vkadaba 5:0728bde67bdb 717 };
Vkadaba 5:0728bde67bdb 718 uint16_t VALUE16;
Vkadaba 5:0728bde67bdb 719 };
Vkadaba 8:2f2775c34640 720 } ADMW_CORE_Error_Code_t;
Vkadaba 5:0728bde67bdb 721
Vkadaba 5:0728bde67bdb 722 /*@}*/
Vkadaba 5:0728bde67bdb 723
Vkadaba 32:52445bef314d 724 /** @defgroup External_Reference_Resistor External Reference Resistor Value (External_Reference_Resistor) Register
Vkadaba 32:52445bef314d 725 * External Reference Resistor Value (External_Reference_Resistor) Register.
Vkadaba 5:0728bde67bdb 726 * @{
Vkadaba 5:0728bde67bdb 727 */
Vkadaba 5:0728bde67bdb 728
Vkadaba 5:0728bde67bdb 729 /* ==========================================================================
Vkadaba 8:2f2775c34640 730 *! \struct ADMW_CORE_External_Reference_Resistor_Struct
Vkadaba 32:52445bef314d 731 *! \brief External Reference Resistor Value Register bit field structure
Vkadaba 5:0728bde67bdb 732 * ========================================================================== */
Vkadaba 8:2f2775c34640 733 typedef struct _ADMW_CORE_External_Reference_Resistor_t {
Vkadaba 5:0728bde67bdb 734 union {
Vkadaba 5:0728bde67bdb 735 struct {
Vkadaba 32:52445bef314d 736 float Ext_Refin1_Value; /**< External Reference Resistor Value */
Vkadaba 5:0728bde67bdb 737 };
Vkadaba 5:0728bde67bdb 738 float VALUE32;
Vkadaba 5:0728bde67bdb 739 };
Vkadaba 8:2f2775c34640 740 } ADMW_CORE_External_Reference_Resistor_t;
Vkadaba 5:0728bde67bdb 741
Vkadaba 5:0728bde67bdb 742 /*@}*/
Vkadaba 5:0728bde67bdb 743
Vkadaba 36:54e2418e7620 744 /** @defgroup External_Voltage_Reference External Reference Information (External_Voltage_Reference) Register
Vkadaba 36:54e2418e7620 745 * External Reference Information (External_Voltage_Reference) Register.
Vkadaba 36:54e2418e7620 746 * @{
Vkadaba 36:54e2418e7620 747 */
Vkadaba 36:54e2418e7620 748
Vkadaba 36:54e2418e7620 749 /* ==========================================================================
Vkadaba 36:54e2418e7620 750 *! \struct ADMW_CORE_External_Voltage_Reference_Struct
Vkadaba 36:54e2418e7620 751 *! \brief External Reference Information Register bit field structure
Vkadaba 36:54e2418e7620 752 * ========================================================================== */
Vkadaba 36:54e2418e7620 753 typedef struct _ADMW_CORE_External_Voltage_Reference_t {
Vkadaba 36:54e2418e7620 754 union {
Vkadaba 36:54e2418e7620 755 struct {
Vkadaba 36:54e2418e7620 756 float Ext_Refin2_Value; /**< Reference Input Value */
Vkadaba 36:54e2418e7620 757 };
Vkadaba 36:54e2418e7620 758 float VALUE32;
Vkadaba 36:54e2418e7620 759 };
Vkadaba 36:54e2418e7620 760 } ADMW_CORE_External_Voltage_Reference_t;
Vkadaba 36:54e2418e7620 761
Vkadaba 36:54e2418e7620 762 /*@}*/
Vkadaba 43:e1789b7214cf 763
Vkadaba 43:e1789b7214cf 764 /** @defgroup AVDD_Voltage AVDD Voltage (AVDD_Voltage) Register
Vkadaba 43:e1789b7214cf 765 * AVDD Voltage (AVDD_Voltage) Register.
Vkadaba 43:e1789b7214cf 766 * @{
Vkadaba 43:e1789b7214cf 767 */
Vkadaba 43:e1789b7214cf 768
Vkadaba 43:e1789b7214cf 769 /* ==========================================================================
Vkadaba 43:e1789b7214cf 770 *! \struct ADMW_CORE_AVDD_Voltage_Struct
Vkadaba 43:e1789b7214cf 771 *! \brief AVDD Voltage Register bit field structure
Vkadaba 43:e1789b7214cf 772 * ========================================================================== */
Vkadaba 43:e1789b7214cf 773 typedef struct _ADMW_CORE_AVDD_Voltage_t {
Vkadaba 43:e1789b7214cf 774 union {
Vkadaba 43:e1789b7214cf 775 struct {
Vkadaba 43:e1789b7214cf 776 float Avdd_Voltage; /**< AVDD Voltage */
Vkadaba 43:e1789b7214cf 777 };
Vkadaba 43:e1789b7214cf 778 float VALUE32;
Vkadaba 43:e1789b7214cf 779 };
Vkadaba 43:e1789b7214cf 780 } ADMW_CORE_AVDD_Voltage_t;
Vkadaba 43:e1789b7214cf 781
Vkadaba 43:e1789b7214cf 782 /*@}*/
Vkadaba 43:e1789b7214cf 783
Vkadaba 5:0728bde67bdb 784 /** @defgroup Diagnostics_Control Diagnostic Control (Diagnostics_Control) Register
Vkadaba 5:0728bde67bdb 785 * Diagnostic Control (Diagnostics_Control) Register.
Vkadaba 5:0728bde67bdb 786 * @{
Vkadaba 5:0728bde67bdb 787 */
Vkadaba 5:0728bde67bdb 788
Vkadaba 5:0728bde67bdb 789 /* =========================================================================
Vkadaba 8:2f2775c34640 790 *! \enum ADMW_CORE_Diagnostics_Control_Diag_OSD_Freq
Vkadaba 5:0728bde67bdb 791 *! \brief Diagnostics Open Sensor Detect Frequency (Diag_OSD_Freq) Enumerations
Vkadaba 5:0728bde67bdb 792 * ========================================================================= */
Vkadaba 5:0728bde67bdb 793 typedef enum
Vkadaba 5:0728bde67bdb 794 {
Vkadaba 32:52445bef314d 795 CORE_DIAGNOSTICS_CONTROL_OCD_OFF = 0, /**< No Open-Circuit Detection During Measurement */
Vkadaba 32:52445bef314d 796 CORE_DIAGNOSTICS_CONTROL_OCD_PER_1_CYCLE = 1, /**< Open-Circuit Detection Performed Once Per Measurement Cycle */
Vkadaba 32:52445bef314d 797 CORE_DIAGNOSTICS_CONTROL_OCD_PER_10_CYCLES = 2, /**< Open-Circuit Detection Performed Once Per Ten Measurement Cycles */
Vkadaba 32:52445bef314d 798 CORE_DIAGNOSTICS_CONTROL_OCD_PER_100_CYCLES = 3 /**< Open-Circuit Detection Performed Once Per Hundred Measurement Cycles */
Vkadaba 8:2f2775c34640 799 } ADMW_CORE_Diagnostics_Control_Diag_OSD_Freq;
Vkadaba 5:0728bde67bdb 800
Vkadaba 5:0728bde67bdb 801
Vkadaba 5:0728bde67bdb 802 /* ==========================================================================
Vkadaba 8:2f2775c34640 803 *! \struct ADMW_CORE_Diagnostics_Control_Struct
Vkadaba 5:0728bde67bdb 804 *! \brief Diagnostic Control Register bit field structure
Vkadaba 5:0728bde67bdb 805 * ========================================================================== */
Vkadaba 8:2f2775c34640 806 typedef struct _ADMW_CORE_Diagnostics_Control_t {
Vkadaba 5:0728bde67bdb 807 union {
Vkadaba 5:0728bde67bdb 808 struct {
Vkadaba 32:52445bef314d 809 uint8_t Diag_Meas_En : 1; /**< Diagnostics Measure Enable */
Vkadaba 32:52445bef314d 810 uint8_t Diag_OSD_Freq : 2; /**< Diagnostics Open Sensor Detect Frequency */
Vkadaba 32:52445bef314d 811 uint8_t reserved3 : 5;
Vkadaba 5:0728bde67bdb 812 };
Vkadaba 32:52445bef314d 813 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 814 };
Vkadaba 8:2f2775c34640 815 } ADMW_CORE_Diagnostics_Control_t;
Vkadaba 5:0728bde67bdb 816
Vkadaba 5:0728bde67bdb 817 /*@}*/
Vkadaba 5:0728bde67bdb 818
Vkadaba 5:0728bde67bdb 819 /** @defgroup Data_FIFO FIFO Buffer of Sensor Results (Data_FIFO) Register
Vkadaba 5:0728bde67bdb 820 * FIFO Buffer of Sensor Results (Data_FIFO) Register.
Vkadaba 5:0728bde67bdb 821 * @{
Vkadaba 5:0728bde67bdb 822 */
Vkadaba 5:0728bde67bdb 823
Vkadaba 5:0728bde67bdb 824 /* ==========================================================================
Vkadaba 8:2f2775c34640 825 *! \struct ADMW_CORE_Data_FIFO_Struct
Vkadaba 5:0728bde67bdb 826 *! \brief FIFO Buffer of Sensor Results Register bit field structure
Vkadaba 5:0728bde67bdb 827 * ========================================================================== */
Vkadaba 8:2f2775c34640 828 typedef struct _ADMW_CORE_Data_FIFO_t {
Vkadaba 5:0728bde67bdb 829 union {
Vkadaba 5:0728bde67bdb 830 struct {
Vkadaba 32:52445bef314d 831 uint8_t Data_Fifo : 8; /**< FIFO Buffer of Sensor Results */
Vkadaba 5:0728bde67bdb 832 };
Vkadaba 5:0728bde67bdb 833 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 834 };
Vkadaba 8:2f2775c34640 835 } ADMW_CORE_Data_FIFO_t;
Vkadaba 5:0728bde67bdb 836
Vkadaba 5:0728bde67bdb 837 /*@}*/
Vkadaba 5:0728bde67bdb 838
Vkadaba 5:0728bde67bdb 839 /** @defgroup Debug_Code Additional Information on Source of Alert or Errors (Debug_Code) Register
Vkadaba 5:0728bde67bdb 840 * Additional Information on Source of Alert or Errors (Debug_Code) Register.
Vkadaba 5:0728bde67bdb 841 * @{
Vkadaba 5:0728bde67bdb 842 */
Vkadaba 5:0728bde67bdb 843
Vkadaba 5:0728bde67bdb 844 /* ==========================================================================
Vkadaba 8:2f2775c34640 845 *! \struct ADMW_CORE_Debug_Code_Struct
Vkadaba 5:0728bde67bdb 846 *! \brief Additional Information on Source of Alert or Errors Register bit field structure
Vkadaba 5:0728bde67bdb 847 * ========================================================================== */
Vkadaba 8:2f2775c34640 848 typedef struct _ADMW_CORE_Debug_Code_t {
Vkadaba 5:0728bde67bdb 849 union {
Vkadaba 5:0728bde67bdb 850 struct {
Vkadaba 5:0728bde67bdb 851 uint32_t Debug_Code : 32; /**< Additional Information on Source of Alert or Errors */
Vkadaba 5:0728bde67bdb 852 };
Vkadaba 5:0728bde67bdb 853 uint32_t VALUE32;
Vkadaba 5:0728bde67bdb 854 };
Vkadaba 8:2f2775c34640 855 } ADMW_CORE_Debug_Code_t;
Vkadaba 5:0728bde67bdb 856
Vkadaba 5:0728bde67bdb 857 /*@}*/
Vkadaba 5:0728bde67bdb 858
Vkadaba 32:52445bef314d 859 /** @defgroup Test_Reg_Access Allows Access to Test (Hidden) Registers and Features (Test_Reg_Access) Register
Vkadaba 32:52445bef314d 860 * Allows Access to Test (Hidden) Registers and Features (Test_Reg_Access) Register.
Vkadaba 5:0728bde67bdb 861 * @{
Vkadaba 5:0728bde67bdb 862 */
Vkadaba 5:0728bde67bdb 863
Vkadaba 5:0728bde67bdb 864 /* ==========================================================================
Vkadaba 32:52445bef314d 865 *! \struct ADMW_CORE_Test_Reg_Access_Struct
Vkadaba 32:52445bef314d 866 *! \brief Allows Access to Test (Hidden) Registers and Features Register bit field structure
Vkadaba 5:0728bde67bdb 867 * ========================================================================== */
Vkadaba 32:52445bef314d 868 typedef struct _ADMW_CORE_Test_Reg_Access_t {
Vkadaba 5:0728bde67bdb 869 union {
Vkadaba 5:0728bde67bdb 870 struct {
Vkadaba 32:52445bef314d 871 uint16_t Test_Access : 16; /**< Test Register Access. Specific Write Sequence Required */
Vkadaba 5:0728bde67bdb 872 };
Vkadaba 5:0728bde67bdb 873 uint16_t VALUE16;
Vkadaba 5:0728bde67bdb 874 };
Vkadaba 32:52445bef314d 875 } ADMW_CORE_Test_Reg_Access_t;
Vkadaba 5:0728bde67bdb 876
Vkadaba 5:0728bde67bdb 877 /*@}*/
Vkadaba 5:0728bde67bdb 878
Vkadaba 32:52445bef314d 879 /** @defgroup LUT_Select LUT Read/Write Strobe (LUT_Select) Register
Vkadaba 32:52445bef314d 880 * LUT Read/Write Strobe (LUT_Select) Register.
Vkadaba 5:0728bde67bdb 881 * @{
Vkadaba 5:0728bde67bdb 882 */
Vkadaba 5:0728bde67bdb 883
Vkadaba 5:0728bde67bdb 884 /* =========================================================================
Vkadaba 8:2f2775c34640 885 *! \enum ADMW_CORE_LUT_Select_LUT_RW
Vkadaba 5:0728bde67bdb 886 *! \brief Read or Write LUT Data (LUT_RW) Enumerations
Vkadaba 5:0728bde67bdb 887 * ========================================================================= */
Vkadaba 5:0728bde67bdb 888 typedef enum
Vkadaba 5:0728bde67bdb 889 {
Vkadaba 32:52445bef314d 890 CORE_LUT_SELECT_LUT_READ = 0, /**< Read addressed LUT data */
Vkadaba 32:52445bef314d 891 CORE_LUT_SELECT_LUT_WRITE = 1 /**< Write addressed LUT data */
Vkadaba 8:2f2775c34640 892 } ADMW_CORE_LUT_Select_LUT_RW;
Vkadaba 5:0728bde67bdb 893
Vkadaba 5:0728bde67bdb 894
Vkadaba 5:0728bde67bdb 895 /* ==========================================================================
Vkadaba 8:2f2775c34640 896 *! \struct ADMW_CORE_LUT_Select_Struct
Vkadaba 32:52445bef314d 897 *! \brief LUT Read/Write Strobe Register bit field structure
Vkadaba 5:0728bde67bdb 898 * ========================================================================== */
Vkadaba 8:2f2775c34640 899 typedef struct _ADMW_CORE_LUT_Select_t {
Vkadaba 5:0728bde67bdb 900 union {
Vkadaba 5:0728bde67bdb 901 struct {
Vkadaba 5:0728bde67bdb 902 uint8_t reserved0 : 7;
Vkadaba 5:0728bde67bdb 903 uint8_t LUT_RW : 1; /**< Read or Write LUT Data */
Vkadaba 5:0728bde67bdb 904 };
Vkadaba 5:0728bde67bdb 905 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 906 };
Vkadaba 8:2f2775c34640 907 } ADMW_CORE_LUT_Select_t;
Vkadaba 5:0728bde67bdb 908
Vkadaba 5:0728bde67bdb 909 /*@}*/
Vkadaba 5:0728bde67bdb 910
Vkadaba 5:0728bde67bdb 911 /** @defgroup LUT_Offset Offset into Selected LUT (LUT_Offset) Register
Vkadaba 5:0728bde67bdb 912 * Offset into Selected LUT (LUT_Offset) Register.
Vkadaba 5:0728bde67bdb 913 * @{
Vkadaba 5:0728bde67bdb 914 */
Vkadaba 5:0728bde67bdb 915
Vkadaba 5:0728bde67bdb 916 /* ==========================================================================
Vkadaba 8:2f2775c34640 917 *! \struct ADMW_CORE_LUT_Offset_Struct
Vkadaba 5:0728bde67bdb 918 *! \brief Offset into Selected LUT Register bit field structure
Vkadaba 5:0728bde67bdb 919 * ========================================================================== */
Vkadaba 8:2f2775c34640 920 typedef struct _ADMW_CORE_LUT_Offset_t {
Vkadaba 5:0728bde67bdb 921 union {
Vkadaba 5:0728bde67bdb 922 struct {
Vkadaba 32:52445bef314d 923 uint16_t LUT_Offset : 14; /**< Offset into the Lookup Table */
Vkadaba 5:0728bde67bdb 924 uint16_t reserved14 : 2;
Vkadaba 5:0728bde67bdb 925 };
Vkadaba 5:0728bde67bdb 926 uint16_t VALUE16;
Vkadaba 5:0728bde67bdb 927 };
Vkadaba 8:2f2775c34640 928 } ADMW_CORE_LUT_Offset_t;
Vkadaba 5:0728bde67bdb 929
Vkadaba 5:0728bde67bdb 930 /*@}*/
Vkadaba 5:0728bde67bdb 931
Vkadaba 5:0728bde67bdb 932 /** @defgroup LUT_Data Data to Read/Write from Addressed LUT Entry (LUT_Data) Register
Vkadaba 5:0728bde67bdb 933 * Data to Read/Write from Addressed LUT Entry (LUT_Data) Register.
Vkadaba 5:0728bde67bdb 934 * @{
Vkadaba 5:0728bde67bdb 935 */
Vkadaba 5:0728bde67bdb 936
Vkadaba 5:0728bde67bdb 937 /* ==========================================================================
Vkadaba 8:2f2775c34640 938 *! \struct ADMW_CORE_LUT_Data_Struct
Vkadaba 5:0728bde67bdb 939 *! \brief Data to Read/Write from Addressed LUT Entry Register bit field structure
Vkadaba 5:0728bde67bdb 940 * ========================================================================== */
Vkadaba 8:2f2775c34640 941 typedef struct _ADMW_CORE_LUT_Data_t {
Vkadaba 5:0728bde67bdb 942 union {
Vkadaba 5:0728bde67bdb 943 struct {
Vkadaba 32:52445bef314d 944 uint8_t LUT_Data : 8; /**< Data Byte to Write to and Read from the Lookup Table */
Vkadaba 5:0728bde67bdb 945 };
Vkadaba 5:0728bde67bdb 946 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 947 };
Vkadaba 8:2f2775c34640 948 } ADMW_CORE_LUT_Data_t;
Vkadaba 5:0728bde67bdb 949
Vkadaba 5:0728bde67bdb 950 /*@}*/
Vkadaba 5:0728bde67bdb 951
Vkadaba 5:0728bde67bdb 952 /** @defgroup Revision Hardware, Firmware Revision (Revision) Register
Vkadaba 5:0728bde67bdb 953 * Hardware, Firmware Revision (Revision) Register.
Vkadaba 5:0728bde67bdb 954 * @{
Vkadaba 5:0728bde67bdb 955 */
Vkadaba 5:0728bde67bdb 956
Vkadaba 5:0728bde67bdb 957 /* ==========================================================================
Vkadaba 8:2f2775c34640 958 *! \struct ADMW_CORE_Revision_Struct
Vkadaba 5:0728bde67bdb 959 *! \brief Hardware, Firmware Revision Register bit field structure
Vkadaba 5:0728bde67bdb 960 * ========================================================================== */
Vkadaba 8:2f2775c34640 961 typedef struct _ADMW_CORE_Revision_t {
Vkadaba 5:0728bde67bdb 962 union {
Vkadaba 5:0728bde67bdb 963 struct {
Vkadaba 5:0728bde67bdb 964 uint32_t Rev_Patch : 16; /**< Patch Revision Information */
Vkadaba 5:0728bde67bdb 965 uint32_t Rev_Minor : 8; /**< Minor Revision Information */
Vkadaba 5:0728bde67bdb 966 uint32_t Rev_Major : 8; /**< Major Revision Information */
Vkadaba 5:0728bde67bdb 967 };
Vkadaba 5:0728bde67bdb 968 uint32_t VALUE32;
Vkadaba 5:0728bde67bdb 969 };
Vkadaba 8:2f2775c34640 970 } ADMW_CORE_Revision_t;
Vkadaba 5:0728bde67bdb 971
Vkadaba 5:0728bde67bdb 972 /*@}*/
Vkadaba 5:0728bde67bdb 973
Vkadaba 5:0728bde67bdb 974 /** @defgroup Channel_Count Number of Channel Occurrences per Measurement Cycle (Channel_Count) Register
Vkadaba 5:0728bde67bdb 975 * Number of Channel Occurrences per Measurement Cycle (Channel_Count) Register.
Vkadaba 5:0728bde67bdb 976 * @{
Vkadaba 5:0728bde67bdb 977 */
Vkadaba 5:0728bde67bdb 978
Vkadaba 5:0728bde67bdb 979 /* ==========================================================================
Vkadaba 8:2f2775c34640 980 *! \struct ADMW_CORE_Channel_Count_Struct
Vkadaba 5:0728bde67bdb 981 *! \brief Number of Channel Occurrences per Measurement Cycle Register bit field structure
Vkadaba 5:0728bde67bdb 982 * ========================================================================== */
Vkadaba 8:2f2775c34640 983 typedef struct _ADMW_CORE_Channel_Count_t {
Vkadaba 5:0728bde67bdb 984 union {
Vkadaba 5:0728bde67bdb 985 struct {
Vkadaba 32:52445bef314d 986 uint8_t Channel_Count : 7; /**< How Many Times Channel Appears in One Cycle */
Vkadaba 5:0728bde67bdb 987 uint8_t Channel_Enable : 1; /**< Enable Channel in Measurement Cycle */
Vkadaba 5:0728bde67bdb 988 };
Vkadaba 5:0728bde67bdb 989 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 990 };
Vkadaba 8:2f2775c34640 991 } ADMW_CORE_Channel_Count_t;
Vkadaba 5:0728bde67bdb 992
Vkadaba 5:0728bde67bdb 993 /*@}*/
Vkadaba 5:0728bde67bdb 994
Vkadaba 32:52445bef314d 995 /** @defgroup Channel_Options Position of Channel Within Sequence (Channel_Options) Register
Vkadaba 32:52445bef314d 996 * Position of Channel Within Sequence (Channel_Options) Register.
Vkadaba 5:0728bde67bdb 997 * @{
Vkadaba 5:0728bde67bdb 998 */
Vkadaba 5:0728bde67bdb 999
Vkadaba 5:0728bde67bdb 1000 /* ==========================================================================
Vkadaba 8:2f2775c34640 1001 *! \struct ADMW_CORE_Channel_Options_Struct
Vkadaba 32:52445bef314d 1002 *! \brief Position of Channel Within Sequence Register bit field structure
Vkadaba 5:0728bde67bdb 1003 * ========================================================================== */
Vkadaba 8:2f2775c34640 1004 typedef struct _ADMW_CORE_Channel_Options_t {
Vkadaba 5:0728bde67bdb 1005 union {
Vkadaba 5:0728bde67bdb 1006 struct {
Vkadaba 5:0728bde67bdb 1007 uint8_t Channel_Priority : 4; /**< Indicates Priority or Position of This Channel in Sequence */
Vkadaba 6:9d393a9677f4 1008 uint8_t reserved4 : 4;
Vkadaba 5:0728bde67bdb 1009 };
Vkadaba 5:0728bde67bdb 1010 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 1011 };
Vkadaba 8:2f2775c34640 1012 } ADMW_CORE_Channel_Options_t;
Vkadaba 5:0728bde67bdb 1013
Vkadaba 5:0728bde67bdb 1014 /*@}*/
Vkadaba 5:0728bde67bdb 1015
Vkadaba 5:0728bde67bdb 1016 /** @defgroup Sensor_Type Sensor Select (Sensor_Type) Register
Vkadaba 5:0728bde67bdb 1017 * Sensor Select (Sensor_Type) Register.
Vkadaba 5:0728bde67bdb 1018 * @{
Vkadaba 5:0728bde67bdb 1019 */
Vkadaba 5:0728bde67bdb 1020
Vkadaba 5:0728bde67bdb 1021 /* =========================================================================
Vkadaba 8:2f2775c34640 1022 *! \enum ADMW_CORE_Sensor_Type_Sensor_Type
Vkadaba 5:0728bde67bdb 1023 *! \brief Sensor Type (Sensor_Type) Enumerations
Vkadaba 5:0728bde67bdb 1024 * ========================================================================= */
Vkadaba 5:0728bde67bdb 1025 typedef enum
Vkadaba 5:0728bde67bdb 1026 {
Vkadaba 32:52445bef314d 1027 CORE_SENSOR_TYPE_THERMOCOUPLE_T = 0, /**< Thermocouple T-Type sensor */
Vkadaba 32:52445bef314d 1028 CORE_SENSOR_TYPE_THERMOCOUPLE_J = 1, /**< Thermocouple J-Type Sensor */
Vkadaba 32:52445bef314d 1029 CORE_SENSOR_TYPE_THERMOCOUPLE_K = 2, /**< Thermocouple K-Type Sensor */
Vkadaba 32:52445bef314d 1030 CORE_SENSOR_TYPE_RTD_2W_PT100 = 32, /**< RTD 2 wire PT100 sensor */
Vkadaba 32:52445bef314d 1031 CORE_SENSOR_TYPE_RTD_2W_PT1000 = 33, /**< RTD 2 wire PT1000 sensor */
Vkadaba 32:52445bef314d 1032 CORE_SENSOR_TYPE_RTD_3W_PT100 = 64, /**< RTD 3 wire PT100 sensor */
Vkadaba 32:52445bef314d 1033 CORE_SENSOR_TYPE_RTD_3W_PT1000 = 65, /**< RTD 3 wire PT1000 sensor */
Vkadaba 32:52445bef314d 1034 CORE_SENSOR_TYPE_RTD_4W_PT100 = 96, /**< RTD 4 wire PT100 sensor */
Vkadaba 32:52445bef314d 1035 CORE_SENSOR_TYPE_RTD_4W_PT1000 = 97, /**< RTD 4 wire PT1000 sensor */
Vkadaba 32:52445bef314d 1036 CORE_SENSOR_TYPE_BRIDGE_4W = 169, /**< Bridge 4 wire sensor */
Vkadaba 32:52445bef314d 1037 CORE_SENSOR_TYPE_CUSTOM1 = 1024, /**< Custom1 */
Vkadaba 32:52445bef314d 1038 CORE_SENSOR_TYPE_I2C_HUMIDITY_B = 2113, /**< I2C humidity sensor B */
Vkadaba 32:52445bef314d 1039 CORE_SENSOR_TYPE_SENSOR_RESERVED_1 = 4064, /**< RESERVED. NOT TO BE USED */
Vkadaba 32:52445bef314d 1040 CORE_SENSOR_TYPE_SENSOR_RESERVED_2 = 4095 /**< RESERVED. NOT TO BE USED */
Vkadaba 8:2f2775c34640 1041 } ADMW_CORE_Sensor_Type_Sensor_Type;
Vkadaba 5:0728bde67bdb 1042
Vkadaba 5:0728bde67bdb 1043
Vkadaba 5:0728bde67bdb 1044 /* ==========================================================================
Vkadaba 8:2f2775c34640 1045 *! \struct ADMW_CORE_Sensor_Type_Struct
Vkadaba 5:0728bde67bdb 1046 *! \brief Sensor Select Register bit field structure
Vkadaba 5:0728bde67bdb 1047 * ========================================================================== */
Vkadaba 8:2f2775c34640 1048 typedef struct _ADMW_CORE_Sensor_Type_t {
Vkadaba 5:0728bde67bdb 1049 union {
Vkadaba 5:0728bde67bdb 1050 struct {
Vkadaba 5:0728bde67bdb 1051 uint16_t Sensor_Type : 12; /**< Sensor Type */
Vkadaba 5:0728bde67bdb 1052 uint16_t reserved12 : 4;
Vkadaba 5:0728bde67bdb 1053 };
Vkadaba 5:0728bde67bdb 1054 uint16_t VALUE16;
Vkadaba 5:0728bde67bdb 1055 };
Vkadaba 8:2f2775c34640 1056 } ADMW_CORE_Sensor_Type_t;
Vkadaba 5:0728bde67bdb 1057
Vkadaba 5:0728bde67bdb 1058 /*@}*/
Vkadaba 5:0728bde67bdb 1059
Vkadaba 5:0728bde67bdb 1060 /** @defgroup Sensor_Details Sensor Details (Sensor_Details) Register
Vkadaba 5:0728bde67bdb 1061 * Sensor Details (Sensor_Details) Register.
Vkadaba 5:0728bde67bdb 1062 * @{
Vkadaba 5:0728bde67bdb 1063 */
Vkadaba 5:0728bde67bdb 1064
Vkadaba 5:0728bde67bdb 1065 /* =========================================================================
Vkadaba 8:2f2775c34640 1066 *! \enum ADMW_CORE_Sensor_Details_Measurement_Units
Vkadaba 5:0728bde67bdb 1067 *! \brief Units of Sensor Measurement (Measurement_Units) Enumerations
Vkadaba 5:0728bde67bdb 1068 * ========================================================================= */
Vkadaba 5:0728bde67bdb 1069 typedef enum
Vkadaba 5:0728bde67bdb 1070 {
Vkadaba 5:0728bde67bdb 1071 CORE_SENSOR_DETAILS_UNITS_UNSPECIFIED = 0, /**< Not Specified */
Vkadaba 5:0728bde67bdb 1072 CORE_SENSOR_DETAILS_UNITS_RESERVED = 1, /**< Reserved */
Vkadaba 5:0728bde67bdb 1073 CORE_SENSOR_DETAILS_UNITS_DEGC = 2, /**< Degrees C */
Vkadaba 5:0728bde67bdb 1074 CORE_SENSOR_DETAILS_UNITS_DEGF = 3 /**< Degrees F */
Vkadaba 8:2f2775c34640 1075 } ADMW_CORE_Sensor_Details_Measurement_Units;
Vkadaba 8:2f2775c34640 1076
Vkadaba 5:0728bde67bdb 1077
Vkadaba 6:9d393a9677f4 1078 /* =========================================================================
Vkadaba 6:9d393a9677f4 1079 *! \enum ADMW_CORE_Sensor_Details_LUT_Select
Vkadaba 6:9d393a9677f4 1080 *! \brief Lookup Table Select (LUT_Select) Enumerations
Vkadaba 6:9d393a9677f4 1081 * ========================================================================= */
Vkadaba 6:9d393a9677f4 1082 typedef enum
Vkadaba 6:9d393a9677f4 1083 {
Vkadaba 32:52445bef314d 1084 CORE_SENSOR_DETAILS_LUT_DEFAULT = 0, /**< Default lookup table for selected sensor type */
Vkadaba 32:52445bef314d 1085 CORE_SENSOR_DETAILS_LUT_UNITY = 1, /**< Unity lookup table. 1:1 mapping from input to output */
Vkadaba 32:52445bef314d 1086 CORE_SENSOR_DETAILS_LUT_CUSTOM = 2, /**< User defined custom lookup table. */
Vkadaba 6:9d393a9677f4 1087 CORE_SENSOR_DETAILS_LUT_RESERVED = 3 /**< Reserved */
Vkadaba 8:2f2775c34640 1088 } ADMW_CORE_Sensor_Details_LUT_Select;
Vkadaba 6:9d393a9677f4 1089
Vkadaba 6:9d393a9677f4 1090
Vkadaba 6:9d393a9677f4 1091 /* =========================================================================
Vkadaba 8:2f2775c34640 1092 *! \enum ADMW_CORE_Sensor_Details_Reference_Select
Vkadaba 5:0728bde67bdb 1093 *! \brief Reference Selection (Reference_Select) Enumerations
Vkadaba 5:0728bde67bdb 1094 * ========================================================================= */
Vkadaba 5:0728bde67bdb 1095 typedef enum
Vkadaba 5:0728bde67bdb 1096 {
Vkadaba 32:52445bef314d 1097 CORE_SENSOR_DETAILS_REF_VINT = 0, /**< Internal voltage reference (1.2V) */
Vkadaba 32:52445bef314d 1098 CORE_SENSOR_DETAILS_REF_VEXT1 = 1, /**< External voltage reference applied to VERF+ and VREF- */
Vkadaba 32:52445bef314d 1099 CORE_SENSOR_DETAILS_REF_AVDD = 3 /**< AVDD supply internally used as reference */
Vkadaba 8:2f2775c34640 1100 } ADMW_CORE_Sensor_Details_Reference_Select;
Vkadaba 5:0728bde67bdb 1101
Vkadaba 5:0728bde67bdb 1102
Vkadaba 5:0728bde67bdb 1103 /* =========================================================================
Vkadaba 8:2f2775c34640 1104 *! \enum ADMW_CORE_Sensor_Details_PGA_Gain
Vkadaba 5:0728bde67bdb 1105 *! \brief PGA Gain (PGA_Gain) Enumerations
Vkadaba 5:0728bde67bdb 1106 * ========================================================================= */
Vkadaba 5:0728bde67bdb 1107 typedef enum
Vkadaba 5:0728bde67bdb 1108 {
Vkadaba 5:0728bde67bdb 1109 CORE_SENSOR_DETAILS_PGA_GAIN_1 = 0, /**< Gain of 1 */
Vkadaba 5:0728bde67bdb 1110 CORE_SENSOR_DETAILS_PGA_GAIN_2 = 1, /**< Gain of 2 */
Vkadaba 5:0728bde67bdb 1111 CORE_SENSOR_DETAILS_PGA_GAIN_4 = 2, /**< Gain of 4 */
Vkadaba 5:0728bde67bdb 1112 CORE_SENSOR_DETAILS_PGA_GAIN_8 = 3, /**< Gain of 8 */
Vkadaba 5:0728bde67bdb 1113 CORE_SENSOR_DETAILS_PGA_GAIN_16 = 4, /**< Gain of 16 */
Vkadaba 5:0728bde67bdb 1114 CORE_SENSOR_DETAILS_PGA_GAIN_32 = 5, /**< Gain of 32 */
Vkadaba 5:0728bde67bdb 1115 CORE_SENSOR_DETAILS_PGA_GAIN_64 = 6, /**< Gain of 64 */
Vkadaba 5:0728bde67bdb 1116 CORE_SENSOR_DETAILS_PGA_GAIN_128 = 7 /**< Gain of 128 */
Vkadaba 8:2f2775c34640 1117 } ADMW_CORE_Sensor_Details_PGA_Gain;
Vkadaba 5:0728bde67bdb 1118
Vkadaba 5:0728bde67bdb 1119
Vkadaba 6:9d393a9677f4 1120 /* =========================================================================
Vkadaba 8:2f2775c34640 1121 *! \enum ADMW_CORE_Sensor_Details_RTD_Curve
Vkadaba 32:52445bef314d 1122 *! \brief Select RTD Curve for Linearization (RTD_Curve) Enumerations
Vkadaba 6:9d393a9677f4 1123 * ========================================================================= */
Vkadaba 6:9d393a9677f4 1124 typedef enum
Vkadaba 6:9d393a9677f4 1125 {
Vkadaba 32:52445bef314d 1126 CORE_SENSOR_DETAILS_EUROPEAN_CURVE = 0, /**< European curve */
Vkadaba 32:52445bef314d 1127 CORE_SENSOR_DETAILS_AMERICAN_CURVE = 1, /**< American curve */
Vkadaba 32:52445bef314d 1128 CORE_SENSOR_DETAILS_JAPANESE_CURVE = 2, /**< Japanese curve */
Vkadaba 32:52445bef314d 1129 CORE_SENSOR_DETAILS_ITS90_CURVE = 3 /**< ITS-90 curve */
Vkadaba 8:2f2775c34640 1130 } ADMW_CORE_Sensor_Details_RTD_Curve;
Vkadaba 6:9d393a9677f4 1131
Vkadaba 6:9d393a9677f4 1132
Vkadaba 5:0728bde67bdb 1133 /* ==========================================================================
Vkadaba 8:2f2775c34640 1134 *! \struct ADMW_CORE_Sensor_Details_Struct
Vkadaba 5:0728bde67bdb 1135 *! \brief Sensor Details Register bit field structure
Vkadaba 5:0728bde67bdb 1136 * ========================================================================== */
Vkadaba 8:2f2775c34640 1137 typedef struct _ADMW_CORE_Sensor_Details_t {
Vkadaba 5:0728bde67bdb 1138 union {
Vkadaba 5:0728bde67bdb 1139 struct {
Vkadaba 5:0728bde67bdb 1140 uint32_t Measurement_Units : 4; /**< Units of Sensor Measurement */
Vkadaba 32:52445bef314d 1141 uint32_t Compensation_Channel : 4; /**< Indicates Which Channel Used to Compensate the Sensor Result */
Vkadaba 8:2f2775c34640 1142 uint32_t reserved8 : 7;
Vkadaba 8:2f2775c34640 1143 uint32_t LUT_Select : 2; /**< Lookup Table Select */
Vkadaba 5:0728bde67bdb 1144 uint32_t Do_Not_Publish : 1; /**< Do Not Publish Channel Result */
Vkadaba 8:2f2775c34640 1145 uint32_t reserved18 : 2;
Vkadaba 6:9d393a9677f4 1146 uint32_t Reference_Select : 4; /**< Reference Selection */
Vkadaba 6:9d393a9677f4 1147 uint32_t PGA_Gain : 3; /**< PGA Gain */
Vkadaba 32:52445bef314d 1148 uint32_t RTD_Curve : 2; /**< Select RTD Curve for Linearization */
Vkadaba 6:9d393a9677f4 1149 uint32_t reserved29 : 2;
Vkadaba 32:52445bef314d 1150 uint32_t Compensation_Disable : 1; /**< This Bit Indicates Compensation Data Must Not Be Used */
Vkadaba 5:0728bde67bdb 1151 };
Vkadaba 5:0728bde67bdb 1152 uint32_t VALUE32;
Vkadaba 5:0728bde67bdb 1153 };
Vkadaba 8:2f2775c34640 1154 } ADMW_CORE_Sensor_Details_t;
Vkadaba 5:0728bde67bdb 1155
Vkadaba 5:0728bde67bdb 1156 /*@}*/
Vkadaba 5:0728bde67bdb 1157
Vkadaba 5:0728bde67bdb 1158 /** @defgroup Channel_Excitation Excitation Current (Channel_Excitation) Register
Vkadaba 5:0728bde67bdb 1159 * Excitation Current (Channel_Excitation) Register.
Vkadaba 5:0728bde67bdb 1160 * @{
Vkadaba 5:0728bde67bdb 1161 */
Vkadaba 5:0728bde67bdb 1162
Vkadaba 5:0728bde67bdb 1163 /* =========================================================================
Vkadaba 8:2f2775c34640 1164 *! \enum ADMW_CORE_Channel_Excitation_IOUT_Excitation_Current
Vkadaba 5:0728bde67bdb 1165 *! \brief Current Source Value (IOUT_Excitation_Current) Enumerations
Vkadaba 5:0728bde67bdb 1166 * ========================================================================= */
Vkadaba 5:0728bde67bdb 1167 typedef enum
Vkadaba 5:0728bde67bdb 1168 {
Vkadaba 32:52445bef314d 1169 CORE_CHANNEL_EXCITATION_NONE = 0, /**< Excitation Current Disabled */
Vkadaba 32:52445bef314d 1170 CORE_CHANNEL_EXCITATION_RESERVED = 1, /**< Reserved */
Vkadaba 32:52445bef314d 1171 CORE_CHANNEL_EXCITATION_IEXC_10UA = 2, /**< 10 \mu;A */
Vkadaba 32:52445bef314d 1172 CORE_CHANNEL_EXCITATION_RESERVED2 = 3, /**< Reserved */
Vkadaba 32:52445bef314d 1173 CORE_CHANNEL_EXCITATION_IEXC_50UA = 4, /**< 50 \mu;A */
Vkadaba 32:52445bef314d 1174 CORE_CHANNEL_EXCITATION_IEXC_100UA = 5, /**< 100 \mu;A */
Vkadaba 32:52445bef314d 1175 CORE_CHANNEL_EXCITATION_IEXC_250UA = 6, /**< 250 \mu;A */
Vkadaba 32:52445bef314d 1176 CORE_CHANNEL_EXCITATION_IEXC_500UA = 7, /**< 500 \mu;A */
Vkadaba 32:52445bef314d 1177 CORE_CHANNEL_EXCITATION_IEXC_1000UA = 8, /**< 1000 \mu;A */
Vkadaba 32:52445bef314d 1178 CORE_CHANNEL_EXCITATION_EXTERNAL = 15 /**< External current sourced */
Vkadaba 8:2f2775c34640 1179 } ADMW_CORE_Channel_Excitation_IOUT_Excitation_Current;
Vkadaba 5:0728bde67bdb 1180
Vkadaba 5:0728bde67bdb 1181
Vkadaba 5:0728bde67bdb 1182 /* ==========================================================================
Vkadaba 8:2f2775c34640 1183 *! \struct ADMW_CORE_Channel_Excitation_Struct
Vkadaba 5:0728bde67bdb 1184 *! \brief Excitation Current Register bit field structure
Vkadaba 5:0728bde67bdb 1185 * ========================================================================== */
Vkadaba 8:2f2775c34640 1186 typedef struct _ADMW_CORE_Channel_Excitation_t {
Vkadaba 5:0728bde67bdb 1187 union {
Vkadaba 5:0728bde67bdb 1188 struct {
Vkadaba 6:9d393a9677f4 1189 uint16_t IOUT_Excitation_Current : 4; /**< Current Source Value */
Vkadaba 32:52445bef314d 1190 uint16_t reserved4 : 12;
Vkadaba 5:0728bde67bdb 1191 };
Vkadaba 6:9d393a9677f4 1192 uint16_t VALUE16;
Vkadaba 5:0728bde67bdb 1193 };
Vkadaba 8:2f2775c34640 1194 } ADMW_CORE_Channel_Excitation_t;
Vkadaba 5:0728bde67bdb 1195
Vkadaba 5:0728bde67bdb 1196 /*@}*/
Vkadaba 5:0728bde67bdb 1197
Vkadaba 5:0728bde67bdb 1198 /** @defgroup Settling_Time Settling Time (Settling_Time) Register
Vkadaba 5:0728bde67bdb 1199 * Settling Time (Settling_Time) Register.
Vkadaba 5:0728bde67bdb 1200 * @{
Vkadaba 5:0728bde67bdb 1201 */
Vkadaba 5:0728bde67bdb 1202
Vkadaba 5:0728bde67bdb 1203 /* =========================================================================
Vkadaba 8:2f2775c34640 1204 *! \enum ADMW_CORE_Settling_Time_Settling_Time_Units
Vkadaba 5:0728bde67bdb 1205 *! \brief Units for Settling Time (Settling_Time_Units) Enumerations
Vkadaba 5:0728bde67bdb 1206 * ========================================================================= */
Vkadaba 5:0728bde67bdb 1207 typedef enum
Vkadaba 5:0728bde67bdb 1208 {
Vkadaba 32:52445bef314d 1209 CORE_SETTLING_TIME_MICROSECONDS = 0, /**< Micro-seconds */
Vkadaba 32:52445bef314d 1210 CORE_SETTLING_TIME_MILLISECONDS = 1, /**< Milli-seconds */
Vkadaba 32:52445bef314d 1211 CORE_SETTLING_TIME_SECONDS = 2, /**< Seconds */
Vkadaba 32:52445bef314d 1212 CORE_SETTLING_TIME_UNDEFINED = 3 /**< Undefined */
Vkadaba 8:2f2775c34640 1213 } ADMW_CORE_Settling_Time_Settling_Time_Units;
Vkadaba 5:0728bde67bdb 1214
Vkadaba 5:0728bde67bdb 1215
Vkadaba 5:0728bde67bdb 1216 /* ==========================================================================
Vkadaba 8:2f2775c34640 1217 *! \struct ADMW_CORE_Settling_Time_Struct
Vkadaba 5:0728bde67bdb 1218 *! \brief Settling Time Register bit field structure
Vkadaba 5:0728bde67bdb 1219 * ========================================================================== */
Vkadaba 8:2f2775c34640 1220 typedef struct _ADMW_CORE_Settling_Time_t {
Vkadaba 5:0728bde67bdb 1221 union {
Vkadaba 5:0728bde67bdb 1222 struct {
Vkadaba 5:0728bde67bdb 1223 uint16_t Settling_Time : 14; /**< Settling Time to Allow When Switching to Channel */
Vkadaba 5:0728bde67bdb 1224 uint16_t Settling_Time_Units : 2; /**< Units for Settling Time */
Vkadaba 5:0728bde67bdb 1225 };
Vkadaba 5:0728bde67bdb 1226 uint16_t VALUE16;
Vkadaba 5:0728bde67bdb 1227 };
Vkadaba 8:2f2775c34640 1228 } ADMW_CORE_Settling_Time_t;
Vkadaba 5:0728bde67bdb 1229
Vkadaba 5:0728bde67bdb 1230 /*@}*/
Vkadaba 5:0728bde67bdb 1231
Vkadaba 32:52445bef314d 1232 /** @defgroup Measurement_Setup ADC Measurement Setup (Measurement_Setup) Register
Vkadaba 32:52445bef314d 1233 * ADC Measurement Setup (Measurement_Setup) Register.
Vkadaba 5:0728bde67bdb 1234 * @{
Vkadaba 5:0728bde67bdb 1235 */
Vkadaba 5:0728bde67bdb 1236
Vkadaba 5:0728bde67bdb 1237 /* =========================================================================
Vkadaba 8:2f2775c34640 1238 *! \enum ADMW_CORE_Measurement_Setup_NOTCH_EN_2
Vkadaba 6:9d393a9677f4 1239 *! \brief Enable Notch 2 Filter Mode (NOTCH_EN_2) Enumerations
Vkadaba 6:9d393a9677f4 1240 * ========================================================================= */
Vkadaba 6:9d393a9677f4 1241 typedef enum
Vkadaba 6:9d393a9677f4 1242 {
Vkadaba 32:52445bef314d 1243 CORE_MEASUREMENT_SETUP_NOTCH_DIS = 0, /**< Disable notch filter */
Vkadaba 32:52445bef314d 1244 CORE_MEASUREMENT_SETUP_NOTCH_EN = 1 /**< Enable notch 2 filter option. */
Vkadaba 8:2f2775c34640 1245 } ADMW_CORE_Measurement_Setup_NOTCH_EN_2;
Vkadaba 6:9d393a9677f4 1246
Vkadaba 8:2f2775c34640 1247 /* =========================================================================
Vkadaba 8:2f2775c34640 1248 *! \enum ADMW_CORE_Measurement_Setup_Chop_Mode
Vkadaba 6:9d393a9677f4 1249 *! \brief Enabled and Disable Chop Mode (Chop_Mode) Enumerations
Vkadaba 6:9d393a9677f4 1250 * ========================================================================= */
Vkadaba 6:9d393a9677f4 1251 typedef enum
Vkadaba 6:9d393a9677f4 1252 {
Vkadaba 32:52445bef314d 1253 CORE_MEASUREMENT_SETUP_DISABLE_CHOP = 0, /**< ADC front end chopping disabled */
Vkadaba 32:52445bef314d 1254 CORE_MEASUREMENT_SETUP_HW_CHOP = 1, /**< Hardware chopping enabled */
Vkadaba 32:52445bef314d 1255 CORE_MEASUREMENT_SETUP_SW_CHOP = 2, /**< SW chop enabled */
Vkadaba 32:52445bef314d 1256 CORE_MEASUREMENT_SETUP_HW_SW_CHOP = 3 /**< Hardware and software chop enabled */
Vkadaba 8:2f2775c34640 1257 } ADMW_CORE_Measurement_Setup_Chop_Mode;
Vkadaba 6:9d393a9677f4 1258
Vkadaba 6:9d393a9677f4 1259
Vkadaba 6:9d393a9677f4 1260 /* =========================================================================
Vkadaba 8:2f2775c34640 1261 *! \enum ADMW_CORE_Measurement_Setup_ADC_Filter_Type
Vkadaba 5:0728bde67bdb 1262 *! \brief ADC Digital Filter Type (ADC_Filter_Type) Enumerations
Vkadaba 5:0728bde67bdb 1263 * ========================================================================= */
Vkadaba 5:0728bde67bdb 1264 typedef enum
Vkadaba 5:0728bde67bdb 1265 {
Vkadaba 32:52445bef314d 1266 CORE_MEASUREMENT_SETUP_ENABLE_SINC4 = 0, /**< Enabled SINC4 filter */
Vkadaba 32:52445bef314d 1267 CORE_MEASUREMENT_SETUP_ENABLE_SINC3 = 1 /**< Enabled SINC3 filter */
Vkadaba 8:2f2775c34640 1268 } ADMW_CORE_Measurement_Setup_ADC_Filter_Type;
Vkadaba 6:9d393a9677f4 1269
Vkadaba 6:9d393a9677f4 1270
Vkadaba 6:9d393a9677f4 1271 /* =========================================================================
Vkadaba 8:2f2775c34640 1272 *! \enum ADMW_CORE_Measurement_Setup_Buffer_Bypass
Vkadaba 8:2f2775c34640 1273 *! \brief Disable Buffers (Buffer_Bypass) Enumerations
Vkadaba 8:2f2775c34640 1274 * ========================================================================= */
Vkadaba 8:2f2775c34640 1275 typedef enum
Vkadaba 8:2f2775c34640 1276 {
Vkadaba 32:52445bef314d 1277 CORE_MEASUREMENT_SETUP_BUFFERS_ENABLED = 0, /**< Input buffers enabled */
Vkadaba 32:52445bef314d 1278 CORE_MEASUREMENT_SETUP_BUFFERS_DISABLED = 1 /**< Input buffers disabled */
Vkadaba 8:2f2775c34640 1279 } ADMW_CORE_Measurement_Setup_Buffer_Bypass;
Vkadaba 5:0728bde67bdb 1280
Vkadaba 5:0728bde67bdb 1281
Vkadaba 5:0728bde67bdb 1282 /* ==========================================================================
Vkadaba 8:2f2775c34640 1283 *! \struct ADMW_CORE_Measurement_Setup_Struct
Vkadaba 32:52445bef314d 1284 *! \brief ADC Measurement Setup Register bit field structure
Vkadaba 5:0728bde67bdb 1285 * ========================================================================== */
Vkadaba 8:2f2775c34640 1286 typedef struct _ADMW_CORE_Measurement_Setup_t {
Vkadaba 5:0728bde67bdb 1287 union {
Vkadaba 5:0728bde67bdb 1288 struct {
Vkadaba 32:52445bef314d 1289 uint32_t ADC_SF : 7; /**< ADC Digital Filter Speed */
Vkadaba 32:52445bef314d 1290 uint32_t reserved7 : 1;
Vkadaba 32:52445bef314d 1291 uint32_t NOTCH_EN_2 : 1; /**< Enable Notch 2 Filter Mode */
Vkadaba 43:e1789b7214cf 1292 uint32_t reserved9 : 1;
Vkadaba 43:e1789b7214cf 1293 uint32_t Chop_Mode : 2; /**< Enabled and Disable Chop Mode */
Vkadaba 43:e1789b7214cf 1294 uint32_t ADC_Filter_Type : 1; /**< ADC Digital Filter Type */
Vkadaba 43:e1789b7214cf 1295 uint32_t reserved13 : 2;
Vkadaba 43:e1789b7214cf 1296 uint32_t Buffer_Bypass : 1; /**< Disable Buffers */
Vkadaba 43:e1789b7214cf 1297 uint32_t reserved16 : 16;
Vkadaba 5:0728bde67bdb 1298 };
Vkadaba 5:0728bde67bdb 1299 uint32_t VALUE32;
Vkadaba 5:0728bde67bdb 1300 };
Vkadaba 8:2f2775c34640 1301 } ADMW_CORE_Measurement_Setup_t;
Vkadaba 5:0728bde67bdb 1302
Vkadaba 5:0728bde67bdb 1303 /*@}*/
Vkadaba 5:0728bde67bdb 1304
Vkadaba 5:0728bde67bdb 1305 /** @defgroup High_Threshold_Limit High Threshold (High_Threshold_Limit) Register
Vkadaba 5:0728bde67bdb 1306 * High Threshold (High_Threshold_Limit) Register.
Vkadaba 5:0728bde67bdb 1307 * @{
Vkadaba 5:0728bde67bdb 1308 */
Vkadaba 5:0728bde67bdb 1309
Vkadaba 5:0728bde67bdb 1310 /* ==========================================================================
Vkadaba 8:2f2775c34640 1311 *! \struct ADMW_CORE_High_Threshold_Limit_Struct
Vkadaba 5:0728bde67bdb 1312 *! \brief High Threshold Register bit field structure
Vkadaba 5:0728bde67bdb 1313 * ========================================================================== */
Vkadaba 8:2f2775c34640 1314 typedef struct _ADMW_CORE_High_Threshold_Limit_t {
Vkadaba 5:0728bde67bdb 1315 union {
Vkadaba 5:0728bde67bdb 1316 struct {
Vkadaba 5:0728bde67bdb 1317 float High_Threshold; /**< Upper Limit for Sensor Alert Comparison */
Vkadaba 5:0728bde67bdb 1318 };
Vkadaba 5:0728bde67bdb 1319 float VALUE32;
Vkadaba 5:0728bde67bdb 1320 };
Vkadaba 8:2f2775c34640 1321 } ADMW_CORE_High_Threshold_Limit_t;
Vkadaba 5:0728bde67bdb 1322
Vkadaba 5:0728bde67bdb 1323 /*@}*/
Vkadaba 5:0728bde67bdb 1324
Vkadaba 5:0728bde67bdb 1325 /** @defgroup Low_Threshold_Limit Low Threshold (Low_Threshold_Limit) Register
Vkadaba 5:0728bde67bdb 1326 * Low Threshold (Low_Threshold_Limit) Register.
Vkadaba 5:0728bde67bdb 1327 * @{
Vkadaba 5:0728bde67bdb 1328 */
Vkadaba 5:0728bde67bdb 1329
Vkadaba 5:0728bde67bdb 1330 /* ==========================================================================
Vkadaba 8:2f2775c34640 1331 *! \struct ADMW_CORE_Low_Threshold_Limit_Struct
Vkadaba 5:0728bde67bdb 1332 *! \brief Low Threshold Register bit field structure
Vkadaba 5:0728bde67bdb 1333 * ========================================================================== */
Vkadaba 8:2f2775c34640 1334 typedef struct _ADMW_CORE_Low_Threshold_Limit_t {
Vkadaba 5:0728bde67bdb 1335 union {
Vkadaba 5:0728bde67bdb 1336 struct {
Vkadaba 5:0728bde67bdb 1337 float Low_Threshold; /**< Lower Limit for Sensor Alert Comparison */
Vkadaba 5:0728bde67bdb 1338 };
Vkadaba 5:0728bde67bdb 1339 float VALUE32;
Vkadaba 5:0728bde67bdb 1340 };
Vkadaba 8:2f2775c34640 1341 } ADMW_CORE_Low_Threshold_Limit_t;
Vkadaba 5:0728bde67bdb 1342
Vkadaba 5:0728bde67bdb 1343 /*@}*/
Vkadaba 5:0728bde67bdb 1344
Vkadaba 5:0728bde67bdb 1345 /** @defgroup Sensor_Offset Sensor Offset Adjustment (Sensor_Offset) Register
Vkadaba 5:0728bde67bdb 1346 * Sensor Offset Adjustment (Sensor_Offset) Register.
Vkadaba 5:0728bde67bdb 1347 * @{
Vkadaba 5:0728bde67bdb 1348 */
Vkadaba 5:0728bde67bdb 1349
Vkadaba 5:0728bde67bdb 1350 /* ==========================================================================
Vkadaba 8:2f2775c34640 1351 *! \struct ADMW_CORE_Sensor_Offset_Struct
Vkadaba 5:0728bde67bdb 1352 *! \brief Sensor Offset Adjustment Register bit field structure
Vkadaba 5:0728bde67bdb 1353 * ========================================================================== */
Vkadaba 8:2f2775c34640 1354 typedef struct _ADMW_CORE_Sensor_Offset_t {
Vkadaba 5:0728bde67bdb 1355 union {
Vkadaba 5:0728bde67bdb 1356 struct {
Vkadaba 5:0728bde67bdb 1357 float Sensor_Offset; /**< Sensor Offset Adjustment */
Vkadaba 5:0728bde67bdb 1358 };
Vkadaba 5:0728bde67bdb 1359 float VALUE32;
Vkadaba 5:0728bde67bdb 1360 };
Vkadaba 8:2f2775c34640 1361 } ADMW_CORE_Sensor_Offset_t;
Vkadaba 5:0728bde67bdb 1362
Vkadaba 5:0728bde67bdb 1363 /*@}*/
Vkadaba 5:0728bde67bdb 1364
Vkadaba 5:0728bde67bdb 1365 /** @defgroup Sensor_Gain Sensor Gain Adjustment (Sensor_Gain) Register
Vkadaba 5:0728bde67bdb 1366 * Sensor Gain Adjustment (Sensor_Gain) Register.
Vkadaba 5:0728bde67bdb 1367 * @{
Vkadaba 5:0728bde67bdb 1368 */
Vkadaba 5:0728bde67bdb 1369
Vkadaba 5:0728bde67bdb 1370 /* ==========================================================================
Vkadaba 8:2f2775c34640 1371 *! \struct ADMW_CORE_Sensor_Gain_Struct
Vkadaba 5:0728bde67bdb 1372 *! \brief Sensor Gain Adjustment Register bit field structure
Vkadaba 5:0728bde67bdb 1373 * ========================================================================== */
Vkadaba 8:2f2775c34640 1374 typedef struct _ADMW_CORE_Sensor_Gain_t {
Vkadaba 5:0728bde67bdb 1375 union {
Vkadaba 5:0728bde67bdb 1376 struct {
Vkadaba 5:0728bde67bdb 1377 float Sensor_Gain; /**< Sensor Gain Adjustment */
Vkadaba 5:0728bde67bdb 1378 };
Vkadaba 5:0728bde67bdb 1379 float VALUE32;
Vkadaba 5:0728bde67bdb 1380 };
Vkadaba 8:2f2775c34640 1381 } ADMW_CORE_Sensor_Gain_t;
Vkadaba 5:0728bde67bdb 1382
Vkadaba 5:0728bde67bdb 1383 /*@}*/
Vkadaba 5:0728bde67bdb 1384
Vkadaba 5:0728bde67bdb 1385 /** @defgroup Channel_Skip Indicates If Channel Will Skip Some Measurement Cycles (Channel_Skip) Register
Vkadaba 5:0728bde67bdb 1386 * Indicates If Channel Will Skip Some Measurement Cycles (Channel_Skip) Register.
Vkadaba 5:0728bde67bdb 1387 * @{
Vkadaba 5:0728bde67bdb 1388 */
Vkadaba 5:0728bde67bdb 1389
Vkadaba 5:0728bde67bdb 1390 /* ==========================================================================
Vkadaba 8:2f2775c34640 1391 *! \struct ADMW_CORE_Channel_Skip_Struct
Vkadaba 5:0728bde67bdb 1392 *! \brief Indicates If Channel Will Skip Some Measurement Cycles Register bit field structure
Vkadaba 5:0728bde67bdb 1393 * ========================================================================== */
Vkadaba 8:2f2775c34640 1394 typedef struct _ADMW_CORE_Channel_Skip_t {
Vkadaba 5:0728bde67bdb 1395 union {
Vkadaba 5:0728bde67bdb 1396 struct {
Vkadaba 5:0728bde67bdb 1397 uint16_t Channel_Skip : 8; /**< Indicates If Channel Will Skip Some Measurement Cycles */
Vkadaba 5:0728bde67bdb 1398 uint16_t reserved8 : 8;
Vkadaba 5:0728bde67bdb 1399 };
Vkadaba 5:0728bde67bdb 1400 uint16_t VALUE16;
Vkadaba 5:0728bde67bdb 1401 };
Vkadaba 8:2f2775c34640 1402 } ADMW_CORE_Channel_Skip_t;
Vkadaba 5:0728bde67bdb 1403
Vkadaba 5:0728bde67bdb 1404 /*@}*/
Vkadaba 5:0728bde67bdb 1405
Vkadaba 5:0728bde67bdb 1406 /** @defgroup Digital_Sensor_Config Digital Sensor Data Coding (Digital_Sensor_Config) Register
Vkadaba 5:0728bde67bdb 1407 * Digital Sensor Data Coding (Digital_Sensor_Config) Register.
Vkadaba 5:0728bde67bdb 1408 * @{
Vkadaba 5:0728bde67bdb 1409 */
Vkadaba 5:0728bde67bdb 1410
Vkadaba 5:0728bde67bdb 1411 /* =========================================================================
Vkadaba 8:2f2775c34640 1412 *! \enum ADMW_CORE_Digital_Sensor_Config_Digital_Sensor_Coding
Vkadaba 5:0728bde67bdb 1413 *! \brief Data Encoding of Sensor Result (Digital_Sensor_Coding) Enumerations
Vkadaba 5:0728bde67bdb 1414 * ========================================================================= */
Vkadaba 5:0728bde67bdb 1415 typedef enum
Vkadaba 5:0728bde67bdb 1416 {
Vkadaba 5:0728bde67bdb 1417 CORE_DIGITAL_SENSOR_CONFIG_CODING_NONE = 0, /**< None/Invalid */
Vkadaba 5:0728bde67bdb 1418 CORE_DIGITAL_SENSOR_CONFIG_CODING_UNIPOLAR = 1, /**< Unipolar */
Vkadaba 32:52445bef314d 1419 CORE_DIGITAL_SENSOR_CONFIG_CODING_TWOS_COMPL = 2, /**< Twos complement */
Vkadaba 32:52445bef314d 1420 CORE_DIGITAL_SENSOR_CONFIG_CODING_OFFSET_BINARY = 3 /**< Offset binary */
Vkadaba 8:2f2775c34640 1421 } ADMW_CORE_Digital_Sensor_Config_Digital_Sensor_Coding;
Vkadaba 5:0728bde67bdb 1422
Vkadaba 5:0728bde67bdb 1423
Vkadaba 5:0728bde67bdb 1424 /* ==========================================================================
Vkadaba 8:2f2775c34640 1425 *! \struct ADMW_CORE_Digital_Sensor_Config_Struct
Vkadaba 5:0728bde67bdb 1426 *! \brief Digital Sensor Data Coding Register bit field structure
Vkadaba 5:0728bde67bdb 1427 * ========================================================================== */
Vkadaba 8:2f2775c34640 1428 typedef struct _ADMW_CORE_Digital_Sensor_Config_t {
Vkadaba 5:0728bde67bdb 1429 union {
Vkadaba 5:0728bde67bdb 1430 struct {
Vkadaba 5:0728bde67bdb 1431 uint16_t Digital_Sensor_Coding : 2; /**< Data Encoding of Sensor Result */
Vkadaba 5:0728bde67bdb 1432 uint16_t Digital_Sensor_Little_Endian : 1; /**< Data Endianness of Sensor Result */
Vkadaba 5:0728bde67bdb 1433 uint16_t Digital_Sensor_Left_Aligned : 1; /**< Data Alignment Within the Data Frame */
Vkadaba 5:0728bde67bdb 1434 uint16_t Digital_Sensor_Bit_Offset : 4; /**< Data Bit Offset, Relative to Alignment */
Vkadaba 5:0728bde67bdb 1435 uint16_t Digital_Sensor_Read_Bytes : 3; /**< Number of Bytes to Read from the Sensor */
Vkadaba 5:0728bde67bdb 1436 uint16_t Digital_Sensor_Data_Bits : 5; /**< Number of Relevant Data Bits */
Vkadaba 5:0728bde67bdb 1437 };
Vkadaba 5:0728bde67bdb 1438 uint16_t VALUE16;
Vkadaba 5:0728bde67bdb 1439 };
Vkadaba 8:2f2775c34640 1440 } ADMW_CORE_Digital_Sensor_Config_t;
Vkadaba 5:0728bde67bdb 1441
Vkadaba 5:0728bde67bdb 1442 /*@}*/
Vkadaba 5:0728bde67bdb 1443
Vkadaba 5:0728bde67bdb 1444 /** @defgroup Digital_Sensor_Address Sensor Address (Digital_Sensor_Address) Register
Vkadaba 5:0728bde67bdb 1445 * Sensor Address (Digital_Sensor_Address) Register.
Vkadaba 5:0728bde67bdb 1446 * @{
Vkadaba 5:0728bde67bdb 1447 */
Vkadaba 5:0728bde67bdb 1448
Vkadaba 5:0728bde67bdb 1449 /* ==========================================================================
Vkadaba 8:2f2775c34640 1450 *! \struct ADMW_CORE_Digital_Sensor_Address_Struct
Vkadaba 5:0728bde67bdb 1451 *! \brief Sensor Address Register bit field structure
Vkadaba 5:0728bde67bdb 1452 * ========================================================================== */
Vkadaba 8:2f2775c34640 1453 typedef struct _ADMW_CORE_Digital_Sensor_Address_t {
Vkadaba 5:0728bde67bdb 1454 union {
Vkadaba 5:0728bde67bdb 1455 struct {
Vkadaba 5:0728bde67bdb 1456 uint8_t Digital_Sensor_Address : 8; /**< I2C Address or Write Address Command for SPI Sensor */
Vkadaba 5:0728bde67bdb 1457 };
Vkadaba 5:0728bde67bdb 1458 uint8_t VALUE8;
Vkadaba 5:0728bde67bdb 1459 };
Vkadaba 8:2f2775c34640 1460 } ADMW_CORE_Digital_Sensor_Address_t;
Vkadaba 5:0728bde67bdb 1461
Vkadaba 5:0728bde67bdb 1462 /*@}*/
Vkadaba 5:0728bde67bdb 1463
Vkadaba 5:0728bde67bdb 1464 /** @defgroup Digital_Sensor_Comms Digital Sensor Communication Clock Configuration (Digital_Sensor_Comms) Register
Vkadaba 5:0728bde67bdb 1465 * Digital Sensor Communication Clock Configuration (Digital_Sensor_Comms) Register.
Vkadaba 5:0728bde67bdb 1466 * @{
Vkadaba 5:0728bde67bdb 1467 */
Vkadaba 5:0728bde67bdb 1468
Vkadaba 5:0728bde67bdb 1469 /* =========================================================================
Vkadaba 8:2f2775c34640 1470 *! \enum ADMW_CORE_Digital_Sensor_Comms_Digital_Sensor_Comms_En
Vkadaba 32:52445bef314d 1471 *! \brief Enable Digital Sensor Communications Register Parameters (Digital_Sensor_Comms_En) Enumerations
Vkadaba 5:0728bde67bdb 1472 * ========================================================================= */
Vkadaba 5:0728bde67bdb 1473 typedef enum
Vkadaba 5:0728bde67bdb 1474 {
Vkadaba 32:52445bef314d 1475 CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_DEFAULT = 0, /**< Default parameters used for digital sensor communications */
Vkadaba 32:52445bef314d 1476 CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_USER = 1 /**< User supplied parameters used for digital sensor communications */
Vkadaba 8:2f2775c34640 1477 } ADMW_CORE_Digital_Sensor_Comms_Digital_Sensor_Comms_En;
Vkadaba 5:0728bde67bdb 1478
Vkadaba 5:0728bde67bdb 1479
Vkadaba 5:0728bde67bdb 1480 /* =========================================================================
Vkadaba 8:2f2775c34640 1481 *! \enum ADMW_CORE_Digital_Sensor_Comms_SPI_Clock
Vkadaba 5:0728bde67bdb 1482 *! \brief Controls Clock Frequency for SPI Sensors (SPI_Clock) Enumerations
Vkadaba 5:0728bde67bdb 1483 * ========================================================================= */
Vkadaba 5:0728bde67bdb 1484 typedef enum
Vkadaba 5:0728bde67bdb 1485 {
Vkadaba 8:2f2775c34640 1486 CORE_DIGITAL_SENSOR_COMMS_SPI_8MHZ = 0, /**< 8MHz */
Vkadaba 8:2f2775c34640 1487 CORE_DIGITAL_SENSOR_COMMS_SPI_4MHZ = 1, /**< 4MHz */
Vkadaba 8:2f2775c34640 1488 CORE_DIGITAL_SENSOR_COMMS_SPI_2MHZ = 2, /**< 2MHz */
Vkadaba 8:2f2775c34640 1489 CORE_DIGITAL_SENSOR_COMMS_SPI_1MHZ = 3, /**< 1MHz */
Vkadaba 8:2f2775c34640 1490 CORE_DIGITAL_SENSOR_COMMS_SPI_500KHZ = 4, /**< 500kHz */
Vkadaba 8:2f2775c34640 1491 CORE_DIGITAL_SENSOR_COMMS_SPI_250KHZ = 5, /**< 250kHz */
Vkadaba 8:2f2775c34640 1492 CORE_DIGITAL_SENSOR_COMMS_SPI_125KHZ = 6, /**< 125kHz */
Vkadaba 8:2f2775c34640 1493 CORE_DIGITAL_SENSOR_COMMS_SPI_62P5KHZ = 7, /**< 62.5kHz */
Vkadaba 8:2f2775c34640 1494 CORE_DIGITAL_SENSOR_COMMS_SPI_31P3KHZ = 8, /**< 31.25kHz */
Vkadaba 8:2f2775c34640 1495 CORE_DIGITAL_SENSOR_COMMS_SPI_15P6KHZ = 9, /**< 15.625kHz */
Vkadaba 8:2f2775c34640 1496 CORE_DIGITAL_SENSOR_COMMS_SPI_7P8KHZ = 10, /**< 7.8kHz */
Vkadaba 8:2f2775c34640 1497 CORE_DIGITAL_SENSOR_COMMS_SPI_3P9KHZ = 11, /**< 3.9kHz */
Vkadaba 8:2f2775c34640 1498 CORE_DIGITAL_SENSOR_COMMS_SPI_1P9KHZ = 12, /**< 1.95kHz */
Vkadaba 8:2f2775c34640 1499 CORE_DIGITAL_SENSOR_COMMS_SPI_977HZ = 13, /**< 977Hz */
Vkadaba 8:2f2775c34640 1500 CORE_DIGITAL_SENSOR_COMMS_SPI_488HZ = 14, /**< 488Hz */
Vkadaba 8:2f2775c34640 1501 CORE_DIGITAL_SENSOR_COMMS_SPI_244HZ = 15 /**< 244Hz */
Vkadaba 8:2f2775c34640 1502 } ADMW_CORE_Digital_Sensor_Comms_SPI_Clock;
Vkadaba 5:0728bde67bdb 1503
Vkadaba 5:0728bde67bdb 1504
Vkadaba 5:0728bde67bdb 1505 /* =========================================================================
Vkadaba 8:2f2775c34640 1506 *! \enum ADMW_CORE_Digital_Sensor_Comms_I2C_Clock
Vkadaba 5:0728bde67bdb 1507 *! \brief Controls SCLK Frequency for I2C Sensors (I2C_Clock) Enumerations
Vkadaba 5:0728bde67bdb 1508 * ========================================================================= */
Vkadaba 5:0728bde67bdb 1509 typedef enum
Vkadaba 5:0728bde67bdb 1510 {
Vkadaba 5:0728bde67bdb 1511 CORE_DIGITAL_SENSOR_COMMS_I2C_100K = 0, /**< 100kHz SCL */
Vkadaba 5:0728bde67bdb 1512 CORE_DIGITAL_SENSOR_COMMS_I2C_400K = 1, /**< 400kHz SCL */
Vkadaba 5:0728bde67bdb 1513 CORE_DIGITAL_SENSOR_COMMS_I2C_RESERVED1 = 2, /**< Reserved */
Vkadaba 5:0728bde67bdb 1514 CORE_DIGITAL_SENSOR_COMMS_I2C_RESERVED2 = 3 /**< Reserved */
Vkadaba 8:2f2775c34640 1515 } ADMW_CORE_Digital_Sensor_Comms_I2C_Clock;
Vkadaba 5:0728bde67bdb 1516
Vkadaba 5:0728bde67bdb 1517
Vkadaba 5:0728bde67bdb 1518 /* =========================================================================
Vkadaba 8:2f2775c34640 1519 *! \enum ADMW_CORE_Digital_Sensor_Comms_SPI_Mode
Vkadaba 5:0728bde67bdb 1520 *! \brief Configuration for Sensor SPI Protocol (SPI_Mode) Enumerations
Vkadaba 5:0728bde67bdb 1521 * ========================================================================= */
Vkadaba 5:0728bde67bdb 1522 typedef enum
Vkadaba 5:0728bde67bdb 1523 {
Vkadaba 32:52445bef314d 1524 CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_0 = 0, /**< Clock polarity = 0 Clock phase = 0 */
Vkadaba 32:52445bef314d 1525 CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_1 = 1, /**< Clock polarity = 0 Clock phase = 1 */
Vkadaba 32:52445bef314d 1526 CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_2 = 2, /**< Clock polarity = 1 Clock phase = 0 */
Vkadaba 32:52445bef314d 1527 CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_3 = 3 /**< Clock polarity = 1 Clock phase = 1 */
Vkadaba 8:2f2775c34640 1528 } ADMW_CORE_Digital_Sensor_Comms_SPI_Mode;
Vkadaba 5:0728bde67bdb 1529
Vkadaba 5:0728bde67bdb 1530
Vkadaba 5:0728bde67bdb 1531 /* ==========================================================================
Vkadaba 8:2f2775c34640 1532 *! \struct ADMW_CORE_Digital_Sensor_Comms_Struct
Vkadaba 5:0728bde67bdb 1533 *! \brief Digital Sensor Communication Clock Configuration Register bit field structure
Vkadaba 5:0728bde67bdb 1534 * ========================================================================== */
Vkadaba 8:2f2775c34640 1535 typedef struct _ADMW_CORE_Digital_Sensor_Comms_t {
Vkadaba 5:0728bde67bdb 1536 union {
Vkadaba 5:0728bde67bdb 1537 struct {
Vkadaba 32:52445bef314d 1538 uint16_t Digital_Sensor_Comms_En : 1; /**< Enable Digital Sensor Communications Register Parameters */
Vkadaba 5:0728bde67bdb 1539 uint16_t SPI_Clock : 4; /**< Controls Clock Frequency for SPI Sensors */
Vkadaba 5:0728bde67bdb 1540 uint16_t I2C_Clock : 2; /**< Controls SCLK Frequency for I2C Sensors */
Vkadaba 6:9d393a9677f4 1541 uint16_t reserved7 : 3;
Vkadaba 5:0728bde67bdb 1542 uint16_t SPI_Mode : 2; /**< Configuration for Sensor SPI Protocol */
Vkadaba 6:9d393a9677f4 1543 uint16_t reserved12 : 4;
Vkadaba 5:0728bde67bdb 1544 };
Vkadaba 5:0728bde67bdb 1545 uint16_t VALUE16;
Vkadaba 5:0728bde67bdb 1546 };
Vkadaba 8:2f2775c34640 1547 } ADMW_CORE_Digital_Sensor_Comms_t;
Vkadaba 5:0728bde67bdb 1548
Vkadaba 5:0728bde67bdb 1549 /*@}*/
Vkadaba 5:0728bde67bdb 1550
Vkadaba 5:0728bde67bdb 1551
Vkadaba 5:0728bde67bdb 1552 #if defined (__CC_ARM)
Vkadaba 5:0728bde67bdb 1553 #pragma pop
Vkadaba 5:0728bde67bdb 1554 #endif
Vkadaba 5:0728bde67bdb 1555
Vkadaba 5:0728bde67bdb 1556 #endif