Optimised fork of bikeNomad's WS2811 LED control library. Supports KL25Z and KL46Z
Fork of Multi_WS2811 by
Optimised to use far less RAM than the original.
Capable of running up to 8 strings of 240 LEDs each with plenty of RAM to spare on the KL46Z.
Should run at least three strings of 240 LEDs on the KL25Z (RAM limited)
WS2811.cpp@1:7b2d0ea091fb, 2014-04-01 (annotated)
- Committer:
- Tomo2k
- Date:
- Tue Apr 01 11:23:33 2014 +0000
- Revision:
- 1:7b2d0ea091fb
- Parent:
- 0:a8535703f23b
- Child:
- 2:1c2c9c8788a8
Added support for FRDM-KL46Z
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bikeNomad | 0:a8535703f23b | 1 | // 800 KHz WS2811 driver driving potentially many LED strings. |
bikeNomad | 0:a8535703f23b | 2 | // Uses 3-phase DMA |
bikeNomad | 0:a8535703f23b | 3 | // 16K SRAM less stack, etc. |
bikeNomad | 0:a8535703f23b | 4 | // |
bikeNomad | 0:a8535703f23b | 5 | // Per LED: 3 bytes (malloc'd) for RGB data |
bikeNomad | 0:a8535703f23b | 6 | // |
bikeNomad | 0:a8535703f23b | 7 | // Per LED strip / per LED |
bikeNomad | 0:a8535703f23b | 8 | // 96 bytes (static) for bit data |
bikeNomad | 0:a8535703f23b | 9 | // + 96 bytes (static) for ones data |
bikeNomad | 0:a8535703f23b | 10 | // = 192 bytes |
bikeNomad | 0:a8535703f23b | 11 | // |
bikeNomad | 0:a8535703f23b | 12 | // 40 LEDs max per string = 7680 bytes static |
bikeNomad | 0:a8535703f23b | 13 | // |
bikeNomad | 0:a8535703f23b | 14 | // 40 LEDs: 7680 + 40*3 = 7800 bytes |
bikeNomad | 0:a8535703f23b | 15 | // 80 LEDs: 7680 + 80*3 = 7920 bytes |
bikeNomad | 0:a8535703f23b | 16 | |
Tomo2k | 1:7b2d0ea091fb | 17 | #if defined(TARGET_KL25Z) |
bikeNomad | 0:a8535703f23b | 18 | #include "MKL25Z4.h" |
Tomo2k | 1:7b2d0ea091fb | 19 | #elif defined(TARGET_KL46Z) |
Tomo2k | 1:7b2d0ea091fb | 20 | #include "MKL46Z4.h" |
Tomo2k | 1:7b2d0ea091fb | 21 | #endif |
Tomo2k | 1:7b2d0ea091fb | 22 | |
bikeNomad | 0:a8535703f23b | 23 | #include "LedStrip.h" |
bikeNomad | 0:a8535703f23b | 24 | #include "WS2811.h" |
bikeNomad | 0:a8535703f23b | 25 | |
bikeNomad | 0:a8535703f23b | 26 | // |
bikeNomad | 0:a8535703f23b | 27 | // Configuration |
bikeNomad | 0:a8535703f23b | 28 | // |
bikeNomad | 0:a8535703f23b | 29 | |
bikeNomad | 0:a8535703f23b | 30 | // Define MONITOR_TPM0_PWM as non-zero to monitor PWM timing on PTD0 and PTD1 |
bikeNomad | 0:a8535703f23b | 31 | // PTD0 TPM0/CH0 PWM_1 J2/06 |
bikeNomad | 0:a8535703f23b | 32 | // PTD1 TPM0/CH1 PWM_2 J2/12 (also LED_BLUE) |
bikeNomad | 0:a8535703f23b | 33 | #define MONITOR_TPM0_PWM 0 |
bikeNomad | 0:a8535703f23b | 34 | |
bikeNomad | 0:a8535703f23b | 35 | // define DEBUG_PIN to identify a pin in PORTD used for debug output |
bikeNomad | 0:a8535703f23b | 36 | // #define DEBUG_PIN 4 /* PTD4 debugOut */ |
bikeNomad | 0:a8535703f23b | 37 | |
bikeNomad | 0:a8535703f23b | 38 | #ifdef DEBUG_PIN |
bikeNomad | 0:a8535703f23b | 39 | #define DEBUG 1 |
bikeNomad | 0:a8535703f23b | 40 | #endif |
bikeNomad | 0:a8535703f23b | 41 | |
bikeNomad | 0:a8535703f23b | 42 | #if DEBUG |
bikeNomad | 0:a8535703f23b | 43 | #define DEBUG_MASK (1<<DEBUG_PIN) |
bikeNomad | 0:a8535703f23b | 44 | #define RESET_DEBUG (IO_GPIO->PDOR &= ~DEBUG_MASK) |
bikeNomad | 0:a8535703f23b | 45 | #define SET_DEBUG (IO_GPIO->PDOR |= DEBUG_MASK) |
bikeNomad | 0:a8535703f23b | 46 | #else |
bikeNomad | 0:a8535703f23b | 47 | #define DEBUG_MASK 0 |
bikeNomad | 0:a8535703f23b | 48 | #define RESET_DEBUG (void)0 |
bikeNomad | 0:a8535703f23b | 49 | #define SET_DEBUG (void)0 |
bikeNomad | 0:a8535703f23b | 50 | #endif |
bikeNomad | 0:a8535703f23b | 51 | |
bikeNomad | 0:a8535703f23b | 52 | static PORT_Type volatile * const IO_PORT = PORTD; |
bikeNomad | 0:a8535703f23b | 53 | static GPIO_Type volatile * const IO_GPIO = PTD; |
bikeNomad | 0:a8535703f23b | 54 | |
bikeNomad | 0:a8535703f23b | 55 | // 48 MHz clock, no prescaling. |
bikeNomad | 0:a8535703f23b | 56 | #define NSEC_TO_TICKS(nsec) ((nsec)*48/1000) |
bikeNomad | 0:a8535703f23b | 57 | #define USEC_TO_TICKS(usec) ((usec)*48) |
bikeNomad | 0:a8535703f23b | 58 | static const uint32_t CLK_NSEC = 1250; |
bikeNomad | 0:a8535703f23b | 59 | static const uint32_t tpm_period = NSEC_TO_TICKS(CLK_NSEC); |
bikeNomad | 0:a8535703f23b | 60 | static const uint32_t tpm_p0_period = NSEC_TO_TICKS(250); |
bikeNomad | 0:a8535703f23b | 61 | static const uint32_t tpm_p1_period = NSEC_TO_TICKS(650); |
bikeNomad | 0:a8535703f23b | 62 | static const uint32_t guardtime_period = USEC_TO_TICKS(55); // guardtime minimum 50 usec. |
bikeNomad | 0:a8535703f23b | 63 | |
bikeNomad | 0:a8535703f23b | 64 | enum DMA_MUX_SRC { |
bikeNomad | 0:a8535703f23b | 65 | DMA_MUX_SRC_TPM0_CH_0 = 24, |
bikeNomad | 0:a8535703f23b | 66 | DMA_MUX_SRC_TPM0_CH_1, |
bikeNomad | 0:a8535703f23b | 67 | DMA_MUX_SRC_TPM0_Overflow = 54, |
bikeNomad | 0:a8535703f23b | 68 | }; |
bikeNomad | 0:a8535703f23b | 69 | |
bikeNomad | 0:a8535703f23b | 70 | enum DMA_CHAN { |
bikeNomad | 0:a8535703f23b | 71 | DMA_CHAN_START = 0, |
bikeNomad | 0:a8535703f23b | 72 | DMA_CHAN_0_LOW = 1, |
bikeNomad | 0:a8535703f23b | 73 | DMA_CHAN_1_LOW = 2, |
bikeNomad | 0:a8535703f23b | 74 | N_DMA_CHANNELS |
bikeNomad | 0:a8535703f23b | 75 | }; |
bikeNomad | 0:a8535703f23b | 76 | |
bikeNomad | 0:a8535703f23b | 77 | volatile bool WS2811::dma_done = true; |
bikeNomad | 0:a8535703f23b | 78 | |
bikeNomad | 0:a8535703f23b | 79 | // class static |
bikeNomad | 0:a8535703f23b | 80 | bool WS2811::initialized = false; |
bikeNomad | 0:a8535703f23b | 81 | |
bikeNomad | 0:a8535703f23b | 82 | // class static |
bikeNomad | 0:a8535703f23b | 83 | uint32_t WS2811::enabledPins = 0; |
bikeNomad | 0:a8535703f23b | 84 | |
bikeNomad | 0:a8535703f23b | 85 | #define WORD_ALIGNED __attribute__ ((aligned(4))) |
bikeNomad | 0:a8535703f23b | 86 | |
bikeNomad | 0:a8535703f23b | 87 | #define DMA_LEADING_ZEROS 2 |
bikeNomad | 0:a8535703f23b | 88 | #define BITS_PER_RGB 24 |
bikeNomad | 0:a8535703f23b | 89 | #define DMA_TRAILING_ZEROS 1 |
bikeNomad | 0:a8535703f23b | 90 | |
bikeNomad | 0:a8535703f23b | 91 | static struct { |
bikeNomad | 0:a8535703f23b | 92 | uint32_t start_t1_low[ DMA_LEADING_ZEROS ]; |
bikeNomad | 0:a8535703f23b | 93 | uint32_t dmaWords[ BITS_PER_RGB * MAX_LEDS_PER_STRIP ]; |
bikeNomad | 0:a8535703f23b | 94 | uint32_t trailing_zeros_1[ DMA_TRAILING_ZEROS ]; |
bikeNomad | 0:a8535703f23b | 95 | |
bikeNomad | 0:a8535703f23b | 96 | uint32_t start_t0_high[ DMA_LEADING_ZEROS - 1 ]; |
bikeNomad | 0:a8535703f23b | 97 | uint32_t allOnes[ BITS_PER_RGB * MAX_LEDS_PER_STRIP ]; |
bikeNomad | 0:a8535703f23b | 98 | uint32_t trailing_zeros_2[ DMA_TRAILING_ZEROS + 1 ]; |
bikeNomad | 0:a8535703f23b | 99 | } dmaData WORD_ALIGNED; |
bikeNomad | 0:a8535703f23b | 100 | |
bikeNomad | 0:a8535703f23b | 101 | // class static |
bikeNomad | 0:a8535703f23b | 102 | void WS2811::hw_init() |
bikeNomad | 0:a8535703f23b | 103 | { |
bikeNomad | 0:a8535703f23b | 104 | if (initialized) return; |
bikeNomad | 0:a8535703f23b | 105 | |
bikeNomad | 0:a8535703f23b | 106 | dma_data_init(); |
bikeNomad | 0:a8535703f23b | 107 | clock_init(); |
bikeNomad | 0:a8535703f23b | 108 | dma_init(); |
bikeNomad | 0:a8535703f23b | 109 | io_init(); |
bikeNomad | 0:a8535703f23b | 110 | tpm_init(); |
bikeNomad | 0:a8535703f23b | 111 | |
bikeNomad | 0:a8535703f23b | 112 | initialized = true; |
bikeNomad | 0:a8535703f23b | 113 | |
bikeNomad | 0:a8535703f23b | 114 | SET_DEBUG; |
bikeNomad | 0:a8535703f23b | 115 | RESET_DEBUG; |
bikeNomad | 0:a8535703f23b | 116 | } |
bikeNomad | 0:a8535703f23b | 117 | |
bikeNomad | 0:a8535703f23b | 118 | // class static |
bikeNomad | 0:a8535703f23b | 119 | void WS2811::dma_data_init() |
bikeNomad | 0:a8535703f23b | 120 | { |
bikeNomad | 0:a8535703f23b | 121 | memset(dmaData.allOnes, 0xFF, sizeof(dmaData.allOnes)); |
bikeNomad | 0:a8535703f23b | 122 | |
bikeNomad | 0:a8535703f23b | 123 | #if DEBUG |
bikeNomad | 0:a8535703f23b | 124 | for (unsigned i = 0; i < BITS_PER_RGB * MAX_LEDS_PER_STRIP; i++) |
bikeNomad | 0:a8535703f23b | 125 | dmaData.dmaWords[i] = DEBUG_MASK; |
bikeNomad | 0:a8535703f23b | 126 | #endif |
bikeNomad | 0:a8535703f23b | 127 | } |
bikeNomad | 0:a8535703f23b | 128 | |
bikeNomad | 0:a8535703f23b | 129 | // class static |
bikeNomad | 0:a8535703f23b | 130 | |
bikeNomad | 0:a8535703f23b | 131 | /// Enable PORTD, DMA and TPM0 clocking |
bikeNomad | 0:a8535703f23b | 132 | void WS2811::clock_init() |
bikeNomad | 0:a8535703f23b | 133 | { |
bikeNomad | 0:a8535703f23b | 134 | SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK; |
bikeNomad | 0:a8535703f23b | 135 | SIM->SCGC6 |= SIM_SCGC6_DMAMUX_MASK | SIM_SCGC6_TPM0_MASK; // Enable clock to DMA mux and TPM0 |
bikeNomad | 0:a8535703f23b | 136 | SIM->SCGC7 |= SIM_SCGC7_DMA_MASK; // Enable clock to DMA |
bikeNomad | 0:a8535703f23b | 137 | |
bikeNomad | 0:a8535703f23b | 138 | SIM->SOPT2 |= SIM_SOPT2_TPMSRC(1); // Clock source: MCGFLLCLK or MCGPLLCLK |
bikeNomad | 0:a8535703f23b | 139 | } |
bikeNomad | 0:a8535703f23b | 140 | |
bikeNomad | 0:a8535703f23b | 141 | // class static |
bikeNomad | 0:a8535703f23b | 142 | |
bikeNomad | 0:a8535703f23b | 143 | /// Configure GPIO output pins |
bikeNomad | 0:a8535703f23b | 144 | void WS2811::io_init() |
bikeNomad | 0:a8535703f23b | 145 | { |
bikeNomad | 0:a8535703f23b | 146 | uint32_t m = 1; |
bikeNomad | 0:a8535703f23b | 147 | for (uint32_t i = 0; i < 32; i++) { |
bikeNomad | 0:a8535703f23b | 148 | // set up each pin |
bikeNomad | 0:a8535703f23b | 149 | if (m & enabledPins) { |
bikeNomad | 0:a8535703f23b | 150 | IO_PORT->PCR[i] = PORT_PCR_MUX(1) // GPIO |
bikeNomad | 0:a8535703f23b | 151 | | PORT_PCR_DSE_MASK; // high drive strength |
bikeNomad | 0:a8535703f23b | 152 | } |
bikeNomad | 0:a8535703f23b | 153 | m <<= 1; |
bikeNomad | 0:a8535703f23b | 154 | } |
bikeNomad | 0:a8535703f23b | 155 | |
bikeNomad | 0:a8535703f23b | 156 | IO_GPIO->PDDR |= enabledPins; // set as outputs |
bikeNomad | 0:a8535703f23b | 157 | |
bikeNomad | 0:a8535703f23b | 158 | #if MONITOR_TPM0_PWM |
bikeNomad | 0:a8535703f23b | 159 | // PTD0 CH0 monitor: TPM0, high drive strength |
bikeNomad | 0:a8535703f23b | 160 | IO_PORT->PCR[0] = PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK; |
bikeNomad | 0:a8535703f23b | 161 | // PTD1 CH1 monitor: TPM0, high drive strength |
bikeNomad | 0:a8535703f23b | 162 | IO_PORT->PCR[1] = PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK; |
bikeNomad | 0:a8535703f23b | 163 | IO_GPIO->PDDR |= 3; // set as outputs |
bikeNomad | 0:a8535703f23b | 164 | IO_GPIO->PDOR &= ~(enabledPins | 3); // initially low |
bikeNomad | 0:a8535703f23b | 165 | #else |
bikeNomad | 0:a8535703f23b | 166 | IO_GPIO->PDOR &= ~enabledPins; // initially low |
bikeNomad | 0:a8535703f23b | 167 | #endif |
bikeNomad | 0:a8535703f23b | 168 | |
bikeNomad | 0:a8535703f23b | 169 | #if DEBUG |
bikeNomad | 0:a8535703f23b | 170 | IO_PORT->PCR[DEBUG_PIN] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK; |
bikeNomad | 0:a8535703f23b | 171 | IO_GPIO->PDDR |= DEBUG_MASK; |
bikeNomad | 0:a8535703f23b | 172 | IO_GPIO->PDOR &= ~DEBUG_MASK; |
bikeNomad | 0:a8535703f23b | 173 | #endif |
bikeNomad | 0:a8535703f23b | 174 | } |
bikeNomad | 0:a8535703f23b | 175 | |
bikeNomad | 0:a8535703f23b | 176 | // class static |
bikeNomad | 0:a8535703f23b | 177 | |
bikeNomad | 0:a8535703f23b | 178 | /// Configure DMA and DMAMUX |
bikeNomad | 0:a8535703f23b | 179 | void WS2811::dma_init() |
bikeNomad | 0:a8535703f23b | 180 | { |
bikeNomad | 0:a8535703f23b | 181 | // reset DMAMUX |
bikeNomad | 0:a8535703f23b | 182 | DMAMUX0->CHCFG[DMA_CHAN_START] = 0; |
bikeNomad | 0:a8535703f23b | 183 | DMAMUX0->CHCFG[DMA_CHAN_0_LOW] = 0; |
bikeNomad | 0:a8535703f23b | 184 | DMAMUX0->CHCFG[DMA_CHAN_1_LOW] = 0; |
bikeNomad | 0:a8535703f23b | 185 | |
bikeNomad | 0:a8535703f23b | 186 | // wire our DMA event sources into the first three DMA channels |
bikeNomad | 0:a8535703f23b | 187 | // t=0: all enabled outputs go high on TPM0 overflow |
bikeNomad | 0:a8535703f23b | 188 | DMAMUX0->CHCFG[DMA_CHAN_START] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(DMA_MUX_SRC_TPM0_Overflow); |
bikeNomad | 0:a8535703f23b | 189 | // t=tpm_p0_period: all of the 0 bits go low. |
bikeNomad | 0:a8535703f23b | 190 | DMAMUX0->CHCFG[DMA_CHAN_0_LOW] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(DMA_MUX_SRC_TPM0_CH_0); |
bikeNomad | 0:a8535703f23b | 191 | // t=tpm_p1_period: all outputs go low. |
bikeNomad | 0:a8535703f23b | 192 | DMAMUX0->CHCFG[DMA_CHAN_1_LOW] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(DMA_MUX_SRC_TPM0_CH_1); |
bikeNomad | 0:a8535703f23b | 193 | |
bikeNomad | 0:a8535703f23b | 194 | NVIC_SetVector(DMA0_IRQn, (uint32_t)&DMA0_IRQHandler); |
bikeNomad | 0:a8535703f23b | 195 | NVIC_EnableIRQ(DMA0_IRQn); |
bikeNomad | 0:a8535703f23b | 196 | } |
bikeNomad | 0:a8535703f23b | 197 | |
bikeNomad | 0:a8535703f23b | 198 | // class static |
bikeNomad | 0:a8535703f23b | 199 | |
bikeNomad | 0:a8535703f23b | 200 | /// Configure TPM0 to do two different PWM periods at 800kHz rate |
bikeNomad | 0:a8535703f23b | 201 | void WS2811::tpm_init() |
bikeNomad | 0:a8535703f23b | 202 | { |
bikeNomad | 0:a8535703f23b | 203 | // set up TPM0 for proper period (800 kHz = 1.25 usec ±600nsec) |
bikeNomad | 0:a8535703f23b | 204 | TPM_Type volatile *tpm = TPM0; |
bikeNomad | 0:a8535703f23b | 205 | tpm->SC = TPM_SC_DMA_MASK // enable DMA |
bikeNomad | 0:a8535703f23b | 206 | | TPM_SC_TOF_MASK // reset TOF flag if set |
bikeNomad | 0:a8535703f23b | 207 | | TPM_SC_CMOD(0) // disable clocks |
bikeNomad | 0:a8535703f23b | 208 | | TPM_SC_PS(0); // 48MHz / 1 = 48MHz clock |
bikeNomad | 0:a8535703f23b | 209 | tpm->MOD = tpm_period - 1; // 48MHz / 800kHz |
bikeNomad | 0:a8535703f23b | 210 | |
bikeNomad | 0:a8535703f23b | 211 | // No Interrupts; High True pulses on Edge Aligned PWM |
bikeNomad | 0:a8535703f23b | 212 | tpm->CONTROLS[0].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK | TPM_CnSC_DMA_MASK; |
bikeNomad | 0:a8535703f23b | 213 | tpm->CONTROLS[1].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK | TPM_CnSC_DMA_MASK; |
bikeNomad | 0:a8535703f23b | 214 | |
bikeNomad | 0:a8535703f23b | 215 | // set TPM0 channel 0 for 0.35 usec (±150nsec) (0 code) |
bikeNomad | 0:a8535703f23b | 216 | // 1.25 usec * 1/3 = 417 nsec |
bikeNomad | 0:a8535703f23b | 217 | tpm->CONTROLS[0].CnV = tpm_p0_period; |
bikeNomad | 0:a8535703f23b | 218 | |
bikeNomad | 0:a8535703f23b | 219 | // set TPM0 channel 1 for 0.7 usec (±150nsec) (1 code) |
bikeNomad | 0:a8535703f23b | 220 | // 1.25 usec * 2/3 = 833 nsec |
bikeNomad | 0:a8535703f23b | 221 | tpm->CONTROLS[1].CnV = tpm_p1_period; |
bikeNomad | 0:a8535703f23b | 222 | |
bikeNomad | 0:a8535703f23b | 223 | NVIC_SetVector(TPM0_IRQn, (uint32_t)&TPM0_IRQHandler); |
bikeNomad | 0:a8535703f23b | 224 | NVIC_EnableIRQ(TPM0_IRQn); |
bikeNomad | 0:a8535703f23b | 225 | } |
bikeNomad | 0:a8535703f23b | 226 | |
bikeNomad | 0:a8535703f23b | 227 | WS2811::WS2811(unsigned n, unsigned pinNumber) |
bikeNomad | 0:a8535703f23b | 228 | : LedStrip(n) |
bikeNomad | 0:a8535703f23b | 229 | , pinMask(1U << pinNumber) |
bikeNomad | 0:a8535703f23b | 230 | { |
bikeNomad | 0:a8535703f23b | 231 | enabledPins |= pinMask; |
bikeNomad | 0:a8535703f23b | 232 | initialized = false; |
bikeNomad | 0:a8535703f23b | 233 | } |
bikeNomad | 0:a8535703f23b | 234 | |
bikeNomad | 0:a8535703f23b | 235 | // class static |
bikeNomad | 0:a8535703f23b | 236 | void WS2811::startDMA() |
bikeNomad | 0:a8535703f23b | 237 | { |
bikeNomad | 0:a8535703f23b | 238 | hw_init(); |
bikeNomad | 0:a8535703f23b | 239 | |
bikeNomad | 0:a8535703f23b | 240 | wait_for_dma_done(); |
bikeNomad | 0:a8535703f23b | 241 | dma_done = false; |
bikeNomad | 0:a8535703f23b | 242 | |
bikeNomad | 0:a8535703f23b | 243 | DMA_Type volatile * dma = DMA0; |
bikeNomad | 0:a8535703f23b | 244 | TPM_Type volatile *tpm = TPM0; |
bikeNomad | 0:a8535703f23b | 245 | uint32_t nBytes = sizeof(dmaData.start_t1_low) |
bikeNomad | 0:a8535703f23b | 246 | + sizeof(dmaData.dmaWords) |
bikeNomad | 0:a8535703f23b | 247 | + sizeof(dmaData.trailing_zeros_1); |
bikeNomad | 0:a8535703f23b | 248 | |
bikeNomad | 0:a8535703f23b | 249 | tpm->SC = TPM_SC_DMA_MASK // enable DMA |
bikeNomad | 0:a8535703f23b | 250 | | TPM_SC_TOF_MASK // reset TOF flag if set |
bikeNomad | 0:a8535703f23b | 251 | | TPM_SC_CMOD(0) // disable clocks |
bikeNomad | 0:a8535703f23b | 252 | | TPM_SC_PS(0); // 48MHz / 1 = 48MHz clock |
bikeNomad | 0:a8535703f23b | 253 | tpm->MOD = tpm_period - 1; // 48MHz / 800kHz |
bikeNomad | 0:a8535703f23b | 254 | |
bikeNomad | 0:a8535703f23b | 255 | tpm->CNT = tpm_p0_period - 2 ; |
bikeNomad | 0:a8535703f23b | 256 | tpm->STATUS = 0xFFFFFFFF; |
bikeNomad | 0:a8535703f23b | 257 | |
bikeNomad | 0:a8535703f23b | 258 | dma->DMA[DMA_CHAN_START].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status |
bikeNomad | 0:a8535703f23b | 259 | dma->DMA[DMA_CHAN_0_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status |
bikeNomad | 0:a8535703f23b | 260 | dma->DMA[DMA_CHAN_1_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status |
bikeNomad | 0:a8535703f23b | 261 | |
bikeNomad | 0:a8535703f23b | 262 | // t=0: all outputs go high |
bikeNomad | 0:a8535703f23b | 263 | // triggered by TPM0_Overflow |
bikeNomad | 0:a8535703f23b | 264 | // source is one word of 0 then 24 x 0xffffffff, then another 0 word |
bikeNomad | 0:a8535703f23b | 265 | dma->DMA[DMA_CHAN_START].SAR = (uint32_t)(void*)dmaData.start_t0_high; |
bikeNomad | 0:a8535703f23b | 266 | dma->DMA[DMA_CHAN_START].DSR_BCR = DMA_DSR_BCR_BCR_MASK & nBytes; // length of transfer in bytes |
bikeNomad | 0:a8535703f23b | 267 | |
bikeNomad | 0:a8535703f23b | 268 | // t=tpm_p0_period: some outputs (the 0 bits) go low. |
bikeNomad | 0:a8535703f23b | 269 | // Triggered by TPM0_CH0 |
bikeNomad | 0:a8535703f23b | 270 | // Start 2 words before the actual data to avoid garbage pulses. |
bikeNomad | 0:a8535703f23b | 271 | dma->DMA[DMA_CHAN_0_LOW].SAR = (uint32_t)(void*)dmaData.start_t1_low; // set source address |
bikeNomad | 0:a8535703f23b | 272 | dma->DMA[DMA_CHAN_0_LOW].DSR_BCR = DMA_DSR_BCR_BCR_MASK & nBytes; // length of transfer in bytes |
bikeNomad | 0:a8535703f23b | 273 | |
bikeNomad | 0:a8535703f23b | 274 | // t=tpm_p1_period: all outputs go low. |
bikeNomad | 0:a8535703f23b | 275 | // Triggered by TPM0_CH1 |
bikeNomad | 0:a8535703f23b | 276 | // source is constant 0x00000000 (first word of dmaWords) |
bikeNomad | 0:a8535703f23b | 277 | dma->DMA[DMA_CHAN_1_LOW].SAR = (uint32_t)(void*)dmaData.start_t1_low; // set source address |
bikeNomad | 0:a8535703f23b | 278 | dma->DMA[DMA_CHAN_1_LOW].DSR_BCR = DMA_DSR_BCR_BCR_MASK & nBytes; // length of transfer in bytes |
bikeNomad | 0:a8535703f23b | 279 | |
bikeNomad | 0:a8535703f23b | 280 | dma->DMA[DMA_CHAN_0_LOW].DAR |
bikeNomad | 0:a8535703f23b | 281 | = dma->DMA[DMA_CHAN_1_LOW].DAR |
bikeNomad | 0:a8535703f23b | 282 | = dma->DMA[DMA_CHAN_START].DAR |
bikeNomad | 0:a8535703f23b | 283 | = (uint32_t)(void*)&IO_GPIO->PDOR; |
bikeNomad | 0:a8535703f23b | 284 | |
bikeNomad | 0:a8535703f23b | 285 | SET_DEBUG; |
bikeNomad | 0:a8535703f23b | 286 | |
bikeNomad | 0:a8535703f23b | 287 | dma->DMA[DMA_CHAN_0_LOW].DCR = DMA_DCR_EINT_MASK // enable interrupt on end of transfer |
bikeNomad | 0:a8535703f23b | 288 | | DMA_DCR_ERQ_MASK |
bikeNomad | 0:a8535703f23b | 289 | | DMA_DCR_D_REQ_MASK // clear ERQ on end of transfer |
bikeNomad | 0:a8535703f23b | 290 | | DMA_DCR_SINC_MASK // increment source each transfer |
bikeNomad | 0:a8535703f23b | 291 | | DMA_DCR_CS_MASK |
bikeNomad | 0:a8535703f23b | 292 | | DMA_DCR_SSIZE(0) // 32-bit source transfers |
bikeNomad | 0:a8535703f23b | 293 | | DMA_DCR_DSIZE(0); // 32-bit destination transfers |
bikeNomad | 0:a8535703f23b | 294 | |
bikeNomad | 0:a8535703f23b | 295 | dma->DMA[DMA_CHAN_1_LOW].DCR = DMA_DCR_EINT_MASK // enable interrupt on end of transfer |
bikeNomad | 0:a8535703f23b | 296 | | DMA_DCR_ERQ_MASK |
bikeNomad | 0:a8535703f23b | 297 | | DMA_DCR_D_REQ_MASK // clear ERQ on end of transfer |
bikeNomad | 0:a8535703f23b | 298 | | DMA_DCR_CS_MASK |
bikeNomad | 0:a8535703f23b | 299 | | DMA_DCR_SSIZE(0) // 32-bit source transfers |
bikeNomad | 0:a8535703f23b | 300 | | DMA_DCR_DSIZE(0); // 32-bit destination transfers |
bikeNomad | 0:a8535703f23b | 301 | |
bikeNomad | 0:a8535703f23b | 302 | dma->DMA[DMA_CHAN_START].DCR = DMA_DCR_EINT_MASK // enable interrupt on end of transfer |
bikeNomad | 0:a8535703f23b | 303 | | DMA_DCR_ERQ_MASK |
bikeNomad | 0:a8535703f23b | 304 | | DMA_DCR_D_REQ_MASK // clear ERQ on end of transfer |
bikeNomad | 0:a8535703f23b | 305 | | DMA_DCR_SINC_MASK // increment source each transfer |
bikeNomad | 0:a8535703f23b | 306 | | DMA_DCR_CS_MASK |
bikeNomad | 0:a8535703f23b | 307 | | DMA_DCR_SSIZE(0) // 32-bit source transfers |
bikeNomad | 0:a8535703f23b | 308 | | DMA_DCR_DSIZE(0); |
bikeNomad | 0:a8535703f23b | 309 | |
bikeNomad | 0:a8535703f23b | 310 | tpm->SC |= TPM_SC_CMOD(1); // enable internal clocking |
bikeNomad | 0:a8535703f23b | 311 | } |
bikeNomad | 0:a8535703f23b | 312 | |
bikeNomad | 0:a8535703f23b | 313 | void WS2811::writePixel(unsigned n, uint8_t *p) |
bikeNomad | 0:a8535703f23b | 314 | { |
bikeNomad | 0:a8535703f23b | 315 | uint32_t *dest = dmaData.dmaWords + n * BITS_PER_RGB; |
bikeNomad | 0:a8535703f23b | 316 | writeByte(*p++, pinMask, dest + 0); // G |
bikeNomad | 0:a8535703f23b | 317 | writeByte(*p++, pinMask, dest + 8); // R |
bikeNomad | 0:a8535703f23b | 318 | writeByte(*p, pinMask, dest + 16); // B |
bikeNomad | 0:a8535703f23b | 319 | } |
bikeNomad | 0:a8535703f23b | 320 | |
bikeNomad | 0:a8535703f23b | 321 | // class static |
bikeNomad | 0:a8535703f23b | 322 | void WS2811::writeByte(uint8_t byte, uint32_t mask, uint32_t *dest) |
bikeNomad | 0:a8535703f23b | 323 | { |
bikeNomad | 0:a8535703f23b | 324 | for (uint8_t bm = 0x80; bm; bm >>= 1) { |
bikeNomad | 0:a8535703f23b | 325 | // MSBit first |
bikeNomad | 0:a8535703f23b | 326 | if (byte & bm) |
bikeNomad | 0:a8535703f23b | 327 | *dest |= mask; |
bikeNomad | 0:a8535703f23b | 328 | else |
bikeNomad | 0:a8535703f23b | 329 | *dest &= ~mask; |
bikeNomad | 0:a8535703f23b | 330 | dest++; |
bikeNomad | 0:a8535703f23b | 331 | } |
bikeNomad | 0:a8535703f23b | 332 | } |
bikeNomad | 0:a8535703f23b | 333 | |
bikeNomad | 0:a8535703f23b | 334 | void WS2811::begin() |
bikeNomad | 0:a8535703f23b | 335 | { |
bikeNomad | 0:a8535703f23b | 336 | blank(); |
bikeNomad | 0:a8535703f23b | 337 | show(); |
bikeNomad | 0:a8535703f23b | 338 | } |
bikeNomad | 0:a8535703f23b | 339 | |
bikeNomad | 0:a8535703f23b | 340 | void WS2811::blank() |
bikeNomad | 0:a8535703f23b | 341 | { |
bikeNomad | 0:a8535703f23b | 342 | memset(pixels, 0x00, numPixelBytes()); |
bikeNomad | 0:a8535703f23b | 343 | |
bikeNomad | 0:a8535703f23b | 344 | #if DEBUG |
bikeNomad | 0:a8535703f23b | 345 | for (unsigned i = DMA_LEADING_ZEROS; i < DMA_LEADING_ZEROS + BITS_PER_RGB; i++) |
bikeNomad | 0:a8535703f23b | 346 | dmaData.dmaWords[i] = DEBUG_MASK; |
bikeNomad | 0:a8535703f23b | 347 | #else |
bikeNomad | 0:a8535703f23b | 348 | memset(dmaData.dmaWords, 0x00, sizeof(dmaData.dmaWords)); |
bikeNomad | 0:a8535703f23b | 349 | #endif |
bikeNomad | 0:a8535703f23b | 350 | } |
bikeNomad | 0:a8535703f23b | 351 | |
bikeNomad | 0:a8535703f23b | 352 | void WS2811::show() |
bikeNomad | 0:a8535703f23b | 353 | { |
bikeNomad | 0:a8535703f23b | 354 | |
bikeNomad | 0:a8535703f23b | 355 | uint16_t i, n = numPixels(); // 3 bytes per LED |
bikeNomad | 0:a8535703f23b | 356 | uint8_t *p = pixels; |
bikeNomad | 0:a8535703f23b | 357 | |
bikeNomad | 0:a8535703f23b | 358 | for (i=0; i<n; i++ ) { |
bikeNomad | 0:a8535703f23b | 359 | writePixel(i, p); |
bikeNomad | 0:a8535703f23b | 360 | p += 3; |
bikeNomad | 0:a8535703f23b | 361 | } |
bikeNomad | 0:a8535703f23b | 362 | } |
bikeNomad | 0:a8535703f23b | 363 | |
bikeNomad | 0:a8535703f23b | 364 | extern "C" void DMA0_IRQHandler() |
bikeNomad | 0:a8535703f23b | 365 | { |
bikeNomad | 0:a8535703f23b | 366 | DMA_Type volatile *dma = DMA0; |
bikeNomad | 0:a8535703f23b | 367 | TPM_Type volatile *tpm = TPM0; |
bikeNomad | 0:a8535703f23b | 368 | |
bikeNomad | 0:a8535703f23b | 369 | uint32_t db; |
bikeNomad | 0:a8535703f23b | 370 | |
bikeNomad | 0:a8535703f23b | 371 | db = dma->DMA[DMA_CHAN_0_LOW].DSR_BCR; |
bikeNomad | 0:a8535703f23b | 372 | if (db & DMA_DSR_BCR_DONE_MASK) { |
bikeNomad | 0:a8535703f23b | 373 | dma->DMA[DMA_CHAN_0_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status |
bikeNomad | 0:a8535703f23b | 374 | } |
bikeNomad | 0:a8535703f23b | 375 | |
bikeNomad | 0:a8535703f23b | 376 | db = dma->DMA[DMA_CHAN_1_LOW].DSR_BCR; |
bikeNomad | 0:a8535703f23b | 377 | if (db & DMA_DSR_BCR_DONE_MASK) { |
bikeNomad | 0:a8535703f23b | 378 | dma->DMA[DMA_CHAN_1_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status |
bikeNomad | 0:a8535703f23b | 379 | } |
bikeNomad | 0:a8535703f23b | 380 | |
bikeNomad | 0:a8535703f23b | 381 | db = dma->DMA[DMA_CHAN_START].DSR_BCR; |
bikeNomad | 0:a8535703f23b | 382 | if (db & DMA_DSR_BCR_DONE_MASK) { |
bikeNomad | 0:a8535703f23b | 383 | dma->DMA[DMA_CHAN_START].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status |
bikeNomad | 0:a8535703f23b | 384 | } |
bikeNomad | 0:a8535703f23b | 385 | |
bikeNomad | 0:a8535703f23b | 386 | tpm->SC = TPM_SC_TOF_MASK; // reset TOF flag; disable internal clocking |
bikeNomad | 0:a8535703f23b | 387 | |
bikeNomad | 0:a8535703f23b | 388 | SET_DEBUG; |
bikeNomad | 0:a8535703f23b | 389 | |
bikeNomad | 0:a8535703f23b | 390 | // set TPM0 to interrrupt after guardtime |
bikeNomad | 0:a8535703f23b | 391 | tpm->MOD = guardtime_period - 1; // 48MHz * 55 usec |
bikeNomad | 0:a8535703f23b | 392 | tpm->CNT = 0; |
bikeNomad | 0:a8535703f23b | 393 | tpm->SC = TPM_SC_PS(0) // 48MHz / 1 = 48MHz clock |
bikeNomad | 0:a8535703f23b | 394 | | TPM_SC_TOIE_MASK // enable interrupts |
bikeNomad | 0:a8535703f23b | 395 | | TPM_SC_CMOD(1); // and internal clocking |
bikeNomad | 0:a8535703f23b | 396 | } |
bikeNomad | 0:a8535703f23b | 397 | |
bikeNomad | 0:a8535703f23b | 398 | extern "C" void TPM0_IRQHandler() |
bikeNomad | 0:a8535703f23b | 399 | { |
bikeNomad | 0:a8535703f23b | 400 | TPM0->SC = 0; // disable internal clocking |
bikeNomad | 0:a8535703f23b | 401 | TPM0->SC = TPM_SC_TOF_MASK; |
bikeNomad | 0:a8535703f23b | 402 | RESET_DEBUG; |
bikeNomad | 0:a8535703f23b | 403 | WS2811::dma_done = true; |
bikeNomad | 0:a8535703f23b | 404 | } |