Richard Thompson / Multi_WS2811

Optimised fork of bikeNomad's WS2811 LED control library. Supports KL25Z and KL46Z

Dependents:   CubicHand

Fork of Multi_WS2811 by Ned Konz

Optimised to use far less RAM than the original.

Capable of running up to 8 strings of 240 LEDs each with plenty of RAM to spare on the KL46Z.

Should run at least three strings of 240 LEDs on the KL25Z (RAM limited)

WS2811.cpp@7:58623ad7f310, 2014-04-02 (annotated)

Committer:
Tomo2k
Date:
Wed Apr 02 13:22:25 2014 +0000
Revision:
7:58623ad7f310
Parent:
6:3b5b8a367f40 
Updated comments, parameter names and added example usage

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Tomo2k 6:3b5b8a367f40 1 // 800 KHz WS2811 driver driving up to eight LED strips.
bikeNomad 0:a8535703f23b 2 // Uses 3-phase DMA
bikeNomad 0:a8535703f23b 3
Tomo2k 1:7b2d0ea091fb 4 #if defined(TARGET_KL25Z)
bikeNomad 0:a8535703f23b 5 #include "MKL25Z4.h"
Tomo2k 1:7b2d0ea091fb 6 #elif defined(TARGET_KL46Z)
Tomo2k 1:7b2d0ea091fb 7 #include "MKL46Z4.h"
Tomo2k 1:7b2d0ea091fb 8 #endif
Tomo2k 1:7b2d0ea091fb 9
bikeNomad 0:a8535703f23b 10 #include "LedStrip.h"
bikeNomad 0:a8535703f23b 11 #include "WS2811.h"
bikeNomad 0:a8535703f23b 12
bikeNomad 0:a8535703f23b 13 //
bikeNomad 0:a8535703f23b 14 // Configuration
bikeNomad 0:a8535703f23b 15 //
bikeNomad 0:a8535703f23b 16
bikeNomad 0:a8535703f23b 17 // Define MONITOR_TPM0_PWM as non-zero to monitor PWM timing on PTD0 and PTD1
bikeNomad 0:a8535703f23b 18 // PTD0 TPM0/CH0 PWM_1 J2/06
bikeNomad 0:a8535703f23b 19 // PTD1 TPM0/CH1 PWM_2 J2/12 (also LED_BLUE)
bikeNomad 0:a8535703f23b 20 #define MONITOR_TPM0_PWM 0
bikeNomad 0:a8535703f23b 21
bikeNomad 0:a8535703f23b 22 // define DEBUG_PIN to identify a pin in PORTD used for debug output
bikeNomad 0:a8535703f23b 23 // #define DEBUG_PIN 4 /* PTD4 debugOut */
bikeNomad 0:a8535703f23b 24
bikeNomad 0:a8535703f23b 25 #ifdef DEBUG_PIN
bikeNomad 0:a8535703f23b 26 #define DEBUG 1
bikeNomad 0:a8535703f23b 27 #endif
bikeNomad 0:a8535703f23b 28
bikeNomad 0:a8535703f23b 29 #if DEBUG
bikeNomad 0:a8535703f23b 30 #define DEBUG_MASK (1<<DEBUG_PIN)
bikeNomad 0:a8535703f23b 31 #define RESET_DEBUG (IO_GPIO->PDOR &= ~DEBUG_MASK)
bikeNomad 0:a8535703f23b 32 #define SET_DEBUG (IO_GPIO->PDOR |= DEBUG_MASK)
bikeNomad 0:a8535703f23b 33 #else
bikeNomad 0:a8535703f23b 34 #define DEBUG_MASK 0
bikeNomad 0:a8535703f23b 35 #define RESET_DEBUG (void)0
bikeNomad 0:a8535703f23b 36 #define SET_DEBUG (void)0
bikeNomad 0:a8535703f23b 37 #endif
bikeNomad 0:a8535703f23b 38
bikeNomad 0:a8535703f23b 39 static PORT_Type volatile * const IO_PORT = PORTD;
bikeNomad 0:a8535703f23b 40 static GPIO_Type volatile * const IO_GPIO = PTD;
bikeNomad 0:a8535703f23b 41
bikeNomad 0:a8535703f23b 42 // 48 MHz clock, no prescaling.
bikeNomad 0:a8535703f23b 43 #define NSEC_TO_TICKS(nsec) ((nsec)*48/1000)
bikeNomad 0:a8535703f23b 44 #define USEC_TO_TICKS(usec) ((usec)*48)
bikeNomad 0:a8535703f23b 45 static const uint32_t CLK_NSEC = 1250;
bikeNomad 0:a8535703f23b 46 static const uint32_t tpm_period = NSEC_TO_TICKS(CLK_NSEC);
bikeNomad 0:a8535703f23b 47 static const uint32_t tpm_p0_period = NSEC_TO_TICKS(250);
bikeNomad 0:a8535703f23b 48 static const uint32_t tpm_p1_period = NSEC_TO_TICKS(650);
bikeNomad 0:a8535703f23b 49 static const uint32_t guardtime_period = USEC_TO_TICKS(55); // guardtime minimum 50 usec.
bikeNomad 0:a8535703f23b 50
bikeNomad 0:a8535703f23b 51 enum DMA_MUX_SRC {
bikeNomad 0:a8535703f23b 52 DMA_MUX_SRC_TPM0_CH_0 = 24,
bikeNomad 0:a8535703f23b 53 DMA_MUX_SRC_TPM0_CH_1,
bikeNomad 0:a8535703f23b 54 DMA_MUX_SRC_TPM0_Overflow = 54,
bikeNomad 0:a8535703f23b 55 };
bikeNomad 0:a8535703f23b 56
bikeNomad 0:a8535703f23b 57 enum DMA_CHAN {
bikeNomad 0:a8535703f23b 58 DMA_CHAN_START = 0,
bikeNomad 0:a8535703f23b 59 DMA_CHAN_0_LOW = 1,
bikeNomad 0:a8535703f23b 60 DMA_CHAN_1_LOW = 2,
bikeNomad 0:a8535703f23b 61 N_DMA_CHANNELS
bikeNomad 0:a8535703f23b 62 };
bikeNomad 0:a8535703f23b 63
bikeNomad 0:a8535703f23b 64 volatile bool WS2811::dma_done = true;
bikeNomad 0:a8535703f23b 65
bikeNomad 0:a8535703f23b 66 // class static
bikeNomad 0:a8535703f23b 67 bool WS2811::initialized = false;
bikeNomad 0:a8535703f23b 68
bikeNomad 0:a8535703f23b 69 // class static
bikeNomad 0:a8535703f23b 70 uint32_t WS2811::enabledPins = 0;
bikeNomad 0:a8535703f23b 71
bikeNomad 0:a8535703f23b 72 #define WORD_ALIGNED __attribute__ ((aligned(4)))
Tomo2k 2:1c2c9c8788a8 73 #define BYTE_ALIGNED __attribute__ ((aligned(1)))
bikeNomad 0:a8535703f23b 74
bikeNomad 0:a8535703f23b 75 #define DMA_LEADING_ZEROS 2
bikeNomad 0:a8535703f23b 76 #define BITS_PER_RGB 24
bikeNomad 0:a8535703f23b 77 #define DMA_TRAILING_ZEROS 1
bikeNomad 0:a8535703f23b 78
bikeNomad 0:a8535703f23b 79 static struct {
Tomo2k 2:1c2c9c8788a8 80 uint8_t start_t1_low[ DMA_LEADING_ZEROS ];
Tomo2k 2:1c2c9c8788a8 81 uint8_t dmaWords[ BITS_PER_RGB * MAX_LEDS_PER_STRIP ];
Tomo2k 2:1c2c9c8788a8 82 uint8_t trailing_zeros_1[ DMA_TRAILING_ZEROS ];
bikeNomad 0:a8535703f23b 83
Tomo2k 2:1c2c9c8788a8 84 uint8_t start_t0_high[ DMA_LEADING_ZEROS - 1 ];
Tomo2k 2:1c2c9c8788a8 85 uint8_t allOnes[ BITS_PER_RGB * MAX_LEDS_PER_STRIP ];
Tomo2k 2:1c2c9c8788a8 86 uint8_t trailing_zeros_2[ DMA_TRAILING_ZEROS + 1 ];
Tomo2k 2:1c2c9c8788a8 87 } dmaData BYTE_ALIGNED;
bikeNomad 0:a8535703f23b 88
bikeNomad 0:a8535703f23b 89 // class static
bikeNomad 0:a8535703f23b 90 void WS2811::hw_init()
bikeNomad 0:a8535703f23b 91 {
bikeNomad 0:a8535703f23b 92 if (initialized) return;
bikeNomad 0:a8535703f23b 93
bikeNomad 0:a8535703f23b 94 dma_data_init();
bikeNomad 0:a8535703f23b 95 clock_init();
bikeNomad 0:a8535703f23b 96 dma_init();
bikeNomad 0:a8535703f23b 97 io_init();
bikeNomad 0:a8535703f23b 98 tpm_init();
bikeNomad 0:a8535703f23b 99
bikeNomad 0:a8535703f23b 100 initialized = true;
bikeNomad 0:a8535703f23b 101
bikeNomad 0:a8535703f23b 102 SET_DEBUG;
bikeNomad 0:a8535703f23b 103 RESET_DEBUG;
bikeNomad 0:a8535703f23b 104 }
bikeNomad 0:a8535703f23b 105
bikeNomad 0:a8535703f23b 106 // class static
bikeNomad 0:a8535703f23b 107 void WS2811::dma_data_init()
bikeNomad 0:a8535703f23b 108 {
bikeNomad 0:a8535703f23b 109 memset(dmaData.allOnes, 0xFF, sizeof(dmaData.allOnes));
bikeNomad 0:a8535703f23b 110
bikeNomad 0:a8535703f23b 111 #if DEBUG
bikeNomad 0:a8535703f23b 112 for (unsigned i = 0; i < BITS_PER_RGB * MAX_LEDS_PER_STRIP; i++)
bikeNomad 0:a8535703f23b 113 dmaData.dmaWords[i] = DEBUG_MASK;
bikeNomad 0:a8535703f23b 114 #endif
bikeNomad 0:a8535703f23b 115 }
bikeNomad 0:a8535703f23b 116
bikeNomad 0:a8535703f23b 117 // class static
bikeNomad 0:a8535703f23b 118
bikeNomad 0:a8535703f23b 119 /// Enable PORTD, DMA and TPM0 clocking
bikeNomad 0:a8535703f23b 120 void WS2811::clock_init()
bikeNomad 0:a8535703f23b 121 {
bikeNomad 0:a8535703f23b 122 SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK;
bikeNomad 0:a8535703f23b 123 SIM->SCGC6 |= SIM_SCGC6_DMAMUX_MASK | SIM_SCGC6_TPM0_MASK; // Enable clock to DMA mux and TPM0
bikeNomad 0:a8535703f23b 124 SIM->SCGC7 |= SIM_SCGC7_DMA_MASK; // Enable clock to DMA
bikeNomad 0:a8535703f23b 125
bikeNomad 0:a8535703f23b 126 SIM->SOPT2 |= SIM_SOPT2_TPMSRC(1); // Clock source: MCGFLLCLK or MCGPLLCLK
bikeNomad 0:a8535703f23b 127 }
bikeNomad 0:a8535703f23b 128
bikeNomad 0:a8535703f23b 129 // class static
bikeNomad 0:a8535703f23b 130
bikeNomad 0:a8535703f23b 131 /// Configure GPIO output pins
bikeNomad 0:a8535703f23b 132 void WS2811::io_init()
bikeNomad 0:a8535703f23b 133 {
bikeNomad 0:a8535703f23b 134 uint32_t m = 1;
bikeNomad 0:a8535703f23b 135 for (uint32_t i = 0; i < 32; i++) {
bikeNomad 0:a8535703f23b 136 // set up each pin
bikeNomad 0:a8535703f23b 137 if (m & enabledPins) {
bikeNomad 0:a8535703f23b 138 IO_PORT->PCR[i] = PORT_PCR_MUX(1) // GPIO
bikeNomad 0:a8535703f23b 139 | PORT_PCR_DSE_MASK; // high drive strength
bikeNomad 0:a8535703f23b 140 }
bikeNomad 0:a8535703f23b 141 m <<= 1;
bikeNomad 0:a8535703f23b 142 }
bikeNomad 0:a8535703f23b 143
bikeNomad 0:a8535703f23b 144 IO_GPIO->PDDR |= enabledPins; // set as outputs
bikeNomad 0:a8535703f23b 145
bikeNomad 0:a8535703f23b 146 #if MONITOR_TPM0_PWM
bikeNomad 0:a8535703f23b 147 // PTD0 CH0 monitor: TPM0, high drive strength
bikeNomad 0:a8535703f23b 148 IO_PORT->PCR[0] = PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK;
bikeNomad 0:a8535703f23b 149 // PTD1 CH1 monitor: TPM0, high drive strength
bikeNomad 0:a8535703f23b 150 IO_PORT->PCR[1] = PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK;
bikeNomad 0:a8535703f23b 151 IO_GPIO->PDDR |= 3; // set as outputs
bikeNomad 0:a8535703f23b 152 IO_GPIO->PDOR &= ~(enabledPins | 3); // initially low
bikeNomad 0:a8535703f23b 153 #else
bikeNomad 0:a8535703f23b 154 IO_GPIO->PDOR &= ~enabledPins; // initially low
bikeNomad 0:a8535703f23b 155 #endif
bikeNomad 0:a8535703f23b 156
bikeNomad 0:a8535703f23b 157 #if DEBUG
bikeNomad 0:a8535703f23b 158 IO_PORT->PCR[DEBUG_PIN] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
bikeNomad 0:a8535703f23b 159 IO_GPIO->PDDR |= DEBUG_MASK;
bikeNomad 0:a8535703f23b 160 IO_GPIO->PDOR &= ~DEBUG_MASK;
bikeNomad 0:a8535703f23b 161 #endif
bikeNomad 0:a8535703f23b 162 }
bikeNomad 0:a8535703f23b 163
bikeNomad 0:a8535703f23b 164 // class static
bikeNomad 0:a8535703f23b 165
bikeNomad 0:a8535703f23b 166 /// Configure DMA and DMAMUX
bikeNomad 0:a8535703f23b 167 void WS2811::dma_init()
bikeNomad 0:a8535703f23b 168 {
bikeNomad 0:a8535703f23b 169 // reset DMAMUX
bikeNomad 0:a8535703f23b 170 DMAMUX0->CHCFG[DMA_CHAN_START] = 0;
bikeNomad 0:a8535703f23b 171 DMAMUX0->CHCFG[DMA_CHAN_0_LOW] = 0;
bikeNomad 0:a8535703f23b 172 DMAMUX0->CHCFG[DMA_CHAN_1_LOW] = 0;
bikeNomad 0:a8535703f23b 173
bikeNomad 0:a8535703f23b 174 // wire our DMA event sources into the first three DMA channels
bikeNomad 0:a8535703f23b 175 // t=0: all enabled outputs go high on TPM0 overflow
bikeNomad 0:a8535703f23b 176 DMAMUX0->CHCFG[DMA_CHAN_START] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(DMA_MUX_SRC_TPM0_Overflow);
bikeNomad 0:a8535703f23b 177 // t=tpm_p0_period: all of the 0 bits go low.
bikeNomad 0:a8535703f23b 178 DMAMUX0->CHCFG[DMA_CHAN_0_LOW] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(DMA_MUX_SRC_TPM0_CH_0);
bikeNomad 0:a8535703f23b 179 // t=tpm_p1_period: all outputs go low.
bikeNomad 0:a8535703f23b 180 DMAMUX0->CHCFG[DMA_CHAN_1_LOW] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(DMA_MUX_SRC_TPM0_CH_1);
bikeNomad 0:a8535703f23b 181
bikeNomad 0:a8535703f23b 182 NVIC_SetVector(DMA0_IRQn, (uint32_t)&DMA0_IRQHandler);
bikeNomad 0:a8535703f23b 183 NVIC_EnableIRQ(DMA0_IRQn);
bikeNomad 0:a8535703f23b 184 }
bikeNomad 0:a8535703f23b 185
bikeNomad 0:a8535703f23b 186 // class static
bikeNomad 0:a8535703f23b 187
bikeNomad 0:a8535703f23b 188 /// Configure TPM0 to do two different PWM periods at 800kHz rate
bikeNomad 0:a8535703f23b 189 void WS2811::tpm_init()
bikeNomad 0:a8535703f23b 190 {
bikeNomad 0:a8535703f23b 191 // set up TPM0 for proper period (800 kHz = 1.25 usec ±600nsec)
bikeNomad 0:a8535703f23b 192 TPM_Type volatile *tpm = TPM0;
bikeNomad 0:a8535703f23b 193 tpm->SC = TPM_SC_DMA_MASK // enable DMA
bikeNomad 0:a8535703f23b 194 | TPM_SC_TOF_MASK // reset TOF flag if set
bikeNomad 0:a8535703f23b 195 | TPM_SC_CMOD(0) // disable clocks
bikeNomad 0:a8535703f23b 196 | TPM_SC_PS(0); // 48MHz / 1 = 48MHz clock
bikeNomad 0:a8535703f23b 197 tpm->MOD = tpm_period - 1; // 48MHz / 800kHz
bikeNomad 0:a8535703f23b 198
bikeNomad 0:a8535703f23b 199 // No Interrupts; High True pulses on Edge Aligned PWM
bikeNomad 0:a8535703f23b 200 tpm->CONTROLS[0].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK | TPM_CnSC_DMA_MASK;
bikeNomad 0:a8535703f23b 201 tpm->CONTROLS[1].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK | TPM_CnSC_DMA_MASK;
bikeNomad 0:a8535703f23b 202
bikeNomad 0:a8535703f23b 203 // set TPM0 channel 0 for 0.35 usec (±150nsec) (0 code)
bikeNomad 0:a8535703f23b 204 // 1.25 usec * 1/3 = 417 nsec
bikeNomad 0:a8535703f23b 205 tpm->CONTROLS[0].CnV = tpm_p0_period;
bikeNomad 0:a8535703f23b 206
bikeNomad 0:a8535703f23b 207 // set TPM0 channel 1 for 0.7 usec (±150nsec) (1 code)
bikeNomad 0:a8535703f23b 208 // 1.25 usec * 2/3 = 833 nsec
bikeNomad 0:a8535703f23b 209 tpm->CONTROLS[1].CnV = tpm_p1_period;
bikeNomad 0:a8535703f23b 210
bikeNomad 0:a8535703f23b 211 NVIC_SetVector(TPM0_IRQn, (uint32_t)&TPM0_IRQHandler);
bikeNomad 0:a8535703f23b 212 NVIC_EnableIRQ(TPM0_IRQn);
bikeNomad 0:a8535703f23b 213 }
bikeNomad 0:a8535703f23b 214
Tomo2k 7:58623ad7f310 215 WS2811::WS2811(uint16_t pixelCount, uint8_t pinNumber)
Tomo2k 7:58623ad7f310 216 : LedStrip(pixelCount)
bikeNomad 0:a8535703f23b 217 , pinMask(1U << pinNumber)
bikeNomad 0:a8535703f23b 218 {
bikeNomad 0:a8535703f23b 219 enabledPins |= pinMask;
bikeNomad 0:a8535703f23b 220 initialized = false;
bikeNomad 0:a8535703f23b 221 }
bikeNomad 0:a8535703f23b 222
bikeNomad 0:a8535703f23b 223 // class static
bikeNomad 0:a8535703f23b 224 void WS2811::startDMA()
bikeNomad 0:a8535703f23b 225 {
bikeNomad 0:a8535703f23b 226 hw_init();
Tomo2k 7:58623ad7f310 227
bikeNomad 0:a8535703f23b 228 wait_for_dma_done();
bikeNomad 0:a8535703f23b 229 dma_done = false;
bikeNomad 0:a8535703f23b 230
bikeNomad 0:a8535703f23b 231 DMA_Type volatile * dma = DMA0;
bikeNomad 0:a8535703f23b 232 TPM_Type volatile *tpm = TPM0;
bikeNomad 0:a8535703f23b 233 uint32_t nBytes = sizeof(dmaData.start_t1_low)
bikeNomad 0:a8535703f23b 234 + sizeof(dmaData.dmaWords)
bikeNomad 0:a8535703f23b 235 + sizeof(dmaData.trailing_zeros_1);
bikeNomad 0:a8535703f23b 236
bikeNomad 0:a8535703f23b 237 tpm->SC = TPM_SC_DMA_MASK // enable DMA
bikeNomad 0:a8535703f23b 238 | TPM_SC_TOF_MASK // reset TOF flag if set
bikeNomad 0:a8535703f23b 239 | TPM_SC_CMOD(0) // disable clocks
bikeNomad 0:a8535703f23b 240 | TPM_SC_PS(0); // 48MHz / 1 = 48MHz clock
bikeNomad 0:a8535703f23b 241 tpm->MOD = tpm_period - 1; // 48MHz / 800kHz
bikeNomad 0:a8535703f23b 242
bikeNomad 0:a8535703f23b 243 tpm->CNT = tpm_p0_period - 2 ;
bikeNomad 0:a8535703f23b 244 tpm->STATUS = 0xFFFFFFFF;
bikeNomad 0:a8535703f23b 245
bikeNomad 0:a8535703f23b 246 dma->DMA[DMA_CHAN_START].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
bikeNomad 0:a8535703f23b 247 dma->DMA[DMA_CHAN_0_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
bikeNomad 0:a8535703f23b 248 dma->DMA[DMA_CHAN_1_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
bikeNomad 0:a8535703f23b 249
bikeNomad 0:a8535703f23b 250 // t=0: all outputs go high
bikeNomad 0:a8535703f23b 251 // triggered by TPM0_Overflow
bikeNomad 0:a8535703f23b 252 // source is one word of 0 then 24 x 0xffffffff, then another 0 word
bikeNomad 0:a8535703f23b 253 dma->DMA[DMA_CHAN_START].SAR = (uint32_t)(void*)dmaData.start_t0_high;
bikeNomad 0:a8535703f23b 254 dma->DMA[DMA_CHAN_START].DSR_BCR = DMA_DSR_BCR_BCR_MASK & nBytes; // length of transfer in bytes
bikeNomad 0:a8535703f23b 255
bikeNomad 0:a8535703f23b 256 // t=tpm_p0_period: some outputs (the 0 bits) go low.
bikeNomad 0:a8535703f23b 257 // Triggered by TPM0_CH0
bikeNomad 0:a8535703f23b 258 // Start 2 words before the actual data to avoid garbage pulses.
bikeNomad 0:a8535703f23b 259 dma->DMA[DMA_CHAN_0_LOW].SAR = (uint32_t)(void*)dmaData.start_t1_low; // set source address
bikeNomad 0:a8535703f23b 260 dma->DMA[DMA_CHAN_0_LOW].DSR_BCR = DMA_DSR_BCR_BCR_MASK & nBytes; // length of transfer in bytes
bikeNomad 0:a8535703f23b 261
bikeNomad 0:a8535703f23b 262 // t=tpm_p1_period: all outputs go low.
bikeNomad 0:a8535703f23b 263 // Triggered by TPM0_CH1
bikeNomad 0:a8535703f23b 264 // source is constant 0x00000000 (first word of dmaWords)
bikeNomad 0:a8535703f23b 265 dma->DMA[DMA_CHAN_1_LOW].SAR = (uint32_t)(void*)dmaData.start_t1_low; // set source address
bikeNomad 0:a8535703f23b 266 dma->DMA[DMA_CHAN_1_LOW].DSR_BCR = DMA_DSR_BCR_BCR_MASK & nBytes; // length of transfer in bytes
bikeNomad 0:a8535703f23b 267
bikeNomad 0:a8535703f23b 268 dma->DMA[DMA_CHAN_0_LOW].DAR
bikeNomad 0:a8535703f23b 269 = dma->DMA[DMA_CHAN_1_LOW].DAR
bikeNomad 0:a8535703f23b 270 = dma->DMA[DMA_CHAN_START].DAR
bikeNomad 0:a8535703f23b 271 = (uint32_t)(void*)&IO_GPIO->PDOR;
bikeNomad 0:a8535703f23b 272
bikeNomad 0:a8535703f23b 273 SET_DEBUG;
bikeNomad 0:a8535703f23b 274
bikeNomad 0:a8535703f23b 275 dma->DMA[DMA_CHAN_0_LOW].DCR = DMA_DCR_EINT_MASK // enable interrupt on end of transfer
bikeNomad 0:a8535703f23b 276 | DMA_DCR_ERQ_MASK
bikeNomad 0:a8535703f23b 277 | DMA_DCR_D_REQ_MASK // clear ERQ on end of transfer
bikeNomad 0:a8535703f23b 278 | DMA_DCR_SINC_MASK // increment source each transfer
bikeNomad 0:a8535703f23b 279 | DMA_DCR_CS_MASK
Tomo2k 2:1c2c9c8788a8 280 | DMA_DCR_SSIZE(1) // 8-bit source transfers
Tomo2k 2:1c2c9c8788a8 281 | DMA_DCR_DSIZE(1); // 8-bit destination transfers
bikeNomad 0:a8535703f23b 282
bikeNomad 0:a8535703f23b 283 dma->DMA[DMA_CHAN_1_LOW].DCR = DMA_DCR_EINT_MASK // enable interrupt on end of transfer
bikeNomad 0:a8535703f23b 284 | DMA_DCR_ERQ_MASK
bikeNomad 0:a8535703f23b 285 | DMA_DCR_D_REQ_MASK // clear ERQ on end of transfer
bikeNomad 0:a8535703f23b 286 | DMA_DCR_CS_MASK
Tomo2k 2:1c2c9c8788a8 287 | DMA_DCR_SSIZE(1) // 8-bit source transfers
Tomo2k 2:1c2c9c8788a8 288 | DMA_DCR_DSIZE(1); // 8-bit destination transfers
bikeNomad 0:a8535703f23b 289
bikeNomad 0:a8535703f23b 290 dma->DMA[DMA_CHAN_START].DCR = DMA_DCR_EINT_MASK // enable interrupt on end of transfer
bikeNomad 0:a8535703f23b 291 | DMA_DCR_ERQ_MASK
bikeNomad 0:a8535703f23b 292 | DMA_DCR_D_REQ_MASK // clear ERQ on end of transfer
bikeNomad 0:a8535703f23b 293 | DMA_DCR_SINC_MASK // increment source each transfer
bikeNomad 0:a8535703f23b 294 | DMA_DCR_CS_MASK
Tomo2k 2:1c2c9c8788a8 295 | DMA_DCR_SSIZE(1) // 8-bit source transfers
Tomo2k 2:1c2c9c8788a8 296 | DMA_DCR_DSIZE(1);
bikeNomad 0:a8535703f23b 297
bikeNomad 0:a8535703f23b 298 tpm->SC |= TPM_SC_CMOD(1); // enable internal clocking
bikeNomad 0:a8535703f23b 299 }
bikeNomad 0:a8535703f23b 300
bikeNomad 0:a8535703f23b 301 void WS2811::writePixel(unsigned n, uint8_t *p)
bikeNomad 0:a8535703f23b 302 {
Tomo2k 2:1c2c9c8788a8 303 uint8_t *dest = dmaData.dmaWords + n * BITS_PER_RGB;
bikeNomad 0:a8535703f23b 304 writeByte(*p++, pinMask, dest + 0); // G
bikeNomad 0:a8535703f23b 305 writeByte(*p++, pinMask, dest + 8); // R
bikeNomad 0:a8535703f23b 306 writeByte(*p, pinMask, dest + 16); // B
bikeNomad 0:a8535703f23b 307 }
bikeNomad 0:a8535703f23b 308
bikeNomad 0:a8535703f23b 309 // class static
Tomo2k 2:1c2c9c8788a8 310 void WS2811::writeByte(uint8_t byte, uint32_t mask, uint8_t *dest)
bikeNomad 0:a8535703f23b 311 {
bikeNomad 0:a8535703f23b 312 for (uint8_t bm = 0x80; bm; bm >>= 1) {
bikeNomad 0:a8535703f23b 313 // MSBit first
bikeNomad 0:a8535703f23b 314 if (byte & bm)
bikeNomad 0:a8535703f23b 315 *dest |= mask;
bikeNomad 0:a8535703f23b 316 else
bikeNomad 0:a8535703f23b 317 *dest &= ~mask;
bikeNomad 0:a8535703f23b 318 dest++;
bikeNomad 0:a8535703f23b 319 }
bikeNomad 0:a8535703f23b 320 }
bikeNomad 0:a8535703f23b 321
bikeNomad 0:a8535703f23b 322 void WS2811::begin()
bikeNomad 0:a8535703f23b 323 {
bikeNomad 0:a8535703f23b 324 blank();
bikeNomad 0:a8535703f23b 325 show();
bikeNomad 0:a8535703f23b 326 }
bikeNomad 0:a8535703f23b 327
bikeNomad 0:a8535703f23b 328 void WS2811::blank()
bikeNomad 0:a8535703f23b 329 {
bikeNomad 0:a8535703f23b 330 memset(pixels, 0x00, numPixelBytes());
bikeNomad 0:a8535703f23b 331
bikeNomad 0:a8535703f23b 332 #if DEBUG
bikeNomad 0:a8535703f23b 333 for (unsigned i = DMA_LEADING_ZEROS; i < DMA_LEADING_ZEROS + BITS_PER_RGB; i++)
bikeNomad 0:a8535703f23b 334 dmaData.dmaWords[i] = DEBUG_MASK;
bikeNomad 0:a8535703f23b 335 #else
bikeNomad 0:a8535703f23b 336 memset(dmaData.dmaWords, 0x00, sizeof(dmaData.dmaWords));
bikeNomad 0:a8535703f23b 337 #endif
bikeNomad 0:a8535703f23b 338 }
bikeNomad 0:a8535703f23b 339
bikeNomad 0:a8535703f23b 340 void WS2811::show()
bikeNomad 0:a8535703f23b 341 {
bikeNomad 0:a8535703f23b 342
bikeNomad 0:a8535703f23b 343 uint16_t i, n = numPixels(); // 3 bytes per LED
bikeNomad 0:a8535703f23b 344 uint8_t *p = pixels;
bikeNomad 0:a8535703f23b 345
bikeNomad 0:a8535703f23b 346 for (i=0; i<n; i++ ) {
bikeNomad 0:a8535703f23b 347 writePixel(i, p);
bikeNomad 0:a8535703f23b 348 p += 3;
bikeNomad 0:a8535703f23b 349 }
bikeNomad 0:a8535703f23b 350 }
bikeNomad 0:a8535703f23b 351
bikeNomad 0:a8535703f23b 352 extern "C" void DMA0_IRQHandler()
bikeNomad 0:a8535703f23b 353 {
bikeNomad 0:a8535703f23b 354 DMA_Type volatile *dma = DMA0;
bikeNomad 0:a8535703f23b 355 TPM_Type volatile *tpm = TPM0;
bikeNomad 0:a8535703f23b 356
bikeNomad 0:a8535703f23b 357 uint32_t db;
bikeNomad 0:a8535703f23b 358
bikeNomad 0:a8535703f23b 359 db = dma->DMA[DMA_CHAN_0_LOW].DSR_BCR;
bikeNomad 0:a8535703f23b 360 if (db & DMA_DSR_BCR_DONE_MASK) {
bikeNomad 0:a8535703f23b 361 dma->DMA[DMA_CHAN_0_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
bikeNomad 0:a8535703f23b 362 }
bikeNomad 0:a8535703f23b 363
bikeNomad 0:a8535703f23b 364 db = dma->DMA[DMA_CHAN_1_LOW].DSR_BCR;
bikeNomad 0:a8535703f23b 365 if (db & DMA_DSR_BCR_DONE_MASK) {
bikeNomad 0:a8535703f23b 366 dma->DMA[DMA_CHAN_1_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
bikeNomad 0:a8535703f23b 367 }
bikeNomad 0:a8535703f23b 368
bikeNomad 0:a8535703f23b 369 db = dma->DMA[DMA_CHAN_START].DSR_BCR;
bikeNomad 0:a8535703f23b 370 if (db & DMA_DSR_BCR_DONE_MASK) {
bikeNomad 0:a8535703f23b 371 dma->DMA[DMA_CHAN_START].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
bikeNomad 0:a8535703f23b 372 }
bikeNomad 0:a8535703f23b 373
bikeNomad 0:a8535703f23b 374 tpm->SC = TPM_SC_TOF_MASK; // reset TOF flag; disable internal clocking
bikeNomad 0:a8535703f23b 375
bikeNomad 0:a8535703f23b 376 SET_DEBUG;
bikeNomad 0:a8535703f23b 377
bikeNomad 0:a8535703f23b 378 // set TPM0 to interrrupt after guardtime
bikeNomad 0:a8535703f23b 379 tpm->MOD = guardtime_period - 1; // 48MHz * 55 usec
bikeNomad 0:a8535703f23b 380 tpm->CNT = 0;
bikeNomad 0:a8535703f23b 381 tpm->SC = TPM_SC_PS(0) // 48MHz / 1 = 48MHz clock
bikeNomad 0:a8535703f23b 382 | TPM_SC_TOIE_MASK // enable interrupts
bikeNomad 0:a8535703f23b 383 | TPM_SC_CMOD(1); // and internal clocking
bikeNomad 0:a8535703f23b 384 }
bikeNomad 0:a8535703f23b 385
bikeNomad 0:a8535703f23b 386 extern "C" void TPM0_IRQHandler()
bikeNomad 0:a8535703f23b 387 {
bikeNomad 0:a8535703f23b 388 TPM0->SC = 0; // disable internal clocking
Tomo2k 7:58623ad7f310 389 TPM0->SC = TPM_SC_TOF_MASK;
bikeNomad 0:a8535703f23b 390 RESET_DEBUG;
bikeNomad 0:a8535703f23b 391 WS2811::dma_done = true;
bikeNomad 0:a8535703f23b 392 }