ARM

Committer:
Toby_Chen
Date:
Sat Oct 14 12:58:38 2017 +0000
Revision:
0:f266ca250f98
TRAY+

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Toby_Chen 0:f266ca250f98 1 /*
Toby_Chen 0:f266ca250f98 2 * MFRC522.cpp - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
Toby_Chen 0:f266ca250f98 3 * _Please_ see the comments in MFRC522.h - they give useful hints and background.
Toby_Chen 0:f266ca250f98 4 * Released into the public domain.
Toby_Chen 0:f266ca250f98 5 */
Toby_Chen 0:f266ca250f98 6
Toby_Chen 0:f266ca250f98 7 #include "MFRC522.h"
Toby_Chen 0:f266ca250f98 8
Toby_Chen 0:f266ca250f98 9 static const char* const _TypeNamePICC[] =
Toby_Chen 0:f266ca250f98 10 {
Toby_Chen 0:f266ca250f98 11 "Unknown type",
Toby_Chen 0:f266ca250f98 12 "PICC compliant with ISO/IEC 14443-4",
Toby_Chen 0:f266ca250f98 13 "PICC compliant with ISO/IEC 18092 (NFC)",
Toby_Chen 0:f266ca250f98 14 "MIFARE Mini, 320 bytes",
Toby_Chen 0:f266ca250f98 15 "MIFARE 1KB",
Toby_Chen 0:f266ca250f98 16 "MIFARE 4KB",
Toby_Chen 0:f266ca250f98 17 "MIFARE Ultralight or Ultralight C",
Toby_Chen 0:f266ca250f98 18 "MIFARE Plus",
Toby_Chen 0:f266ca250f98 19 "MIFARE TNP3XXX",
Toby_Chen 0:f266ca250f98 20
Toby_Chen 0:f266ca250f98 21 /* not complete UID */
Toby_Chen 0:f266ca250f98 22 "SAK indicates UID is not complete"
Toby_Chen 0:f266ca250f98 23 };
Toby_Chen 0:f266ca250f98 24
Toby_Chen 0:f266ca250f98 25 static const char* const _ErrorMessage[] =
Toby_Chen 0:f266ca250f98 26 {
Toby_Chen 0:f266ca250f98 27 "Unknown error",
Toby_Chen 0:f266ca250f98 28 "Success",
Toby_Chen 0:f266ca250f98 29 "Error in communication",
Toby_Chen 0:f266ca250f98 30 "Collision detected",
Toby_Chen 0:f266ca250f98 31 "Timeout in communication",
Toby_Chen 0:f266ca250f98 32 "A buffer is not big enough",
Toby_Chen 0:f266ca250f98 33 "Internal error in the code, should not happen",
Toby_Chen 0:f266ca250f98 34 "Invalid argument",
Toby_Chen 0:f266ca250f98 35 "The CRC_A does not match",
Toby_Chen 0:f266ca250f98 36 "A MIFARE PICC responded with NAK"
Toby_Chen 0:f266ca250f98 37 };
Toby_Chen 0:f266ca250f98 38
Toby_Chen 0:f266ca250f98 39 #define MFRC522_MaxPICCs (sizeof(_TypeNamePICC)/sizeof(_TypeNamePICC[0]))
Toby_Chen 0:f266ca250f98 40 #define MFRC522_MaxError (sizeof(_ErrorMessage)/sizeof(_ErrorMessage[0]))
Toby_Chen 0:f266ca250f98 41
Toby_Chen 0:f266ca250f98 42 /////////////////////////////////////////////////////////////////////////////////////
Toby_Chen 0:f266ca250f98 43 // Functions for setting up the driver
Toby_Chen 0:f266ca250f98 44 /////////////////////////////////////////////////////////////////////////////////////
Toby_Chen 0:f266ca250f98 45
Toby_Chen 0:f266ca250f98 46 /**
Toby_Chen 0:f266ca250f98 47 * Constructor.
Toby_Chen 0:f266ca250f98 48 * Prepares the output pins.
Toby_Chen 0:f266ca250f98 49 */
Toby_Chen 0:f266ca250f98 50 MFRC522::MFRC522(PinName mosi,
Toby_Chen 0:f266ca250f98 51 PinName miso,
Toby_Chen 0:f266ca250f98 52 PinName sclk,
Toby_Chen 0:f266ca250f98 53 PinName cs,
Toby_Chen 0:f266ca250f98 54 PinName reset) : m_SPI(mosi, miso, sclk), m_CS(cs), m_RESET(reset)
Toby_Chen 0:f266ca250f98 55 {
Toby_Chen 0:f266ca250f98 56 /* Configure SPI bus */
Toby_Chen 0:f266ca250f98 57 m_SPI.format(8, 0);
Toby_Chen 0:f266ca250f98 58 m_SPI.frequency(8000000);
Toby_Chen 0:f266ca250f98 59
Toby_Chen 0:f266ca250f98 60 /* Release SPI-CS pin */
Toby_Chen 0:f266ca250f98 61 m_CS = 1;
Toby_Chen 0:f266ca250f98 62
Toby_Chen 0:f266ca250f98 63 /* Release RESET pin */
Toby_Chen 0:f266ca250f98 64 m_RESET = 1;
Toby_Chen 0:f266ca250f98 65 } // End constructor
Toby_Chen 0:f266ca250f98 66
Toby_Chen 0:f266ca250f98 67
Toby_Chen 0:f266ca250f98 68 /**
Toby_Chen 0:f266ca250f98 69 * Destructor.
Toby_Chen 0:f266ca250f98 70 */
Toby_Chen 0:f266ca250f98 71 MFRC522::~MFRC522()
Toby_Chen 0:f266ca250f98 72 {
Toby_Chen 0:f266ca250f98 73
Toby_Chen 0:f266ca250f98 74 }
Toby_Chen 0:f266ca250f98 75
Toby_Chen 0:f266ca250f98 76
Toby_Chen 0:f266ca250f98 77 /////////////////////////////////////////////////////////////////////////////////////
Toby_Chen 0:f266ca250f98 78 // Basic interface functions for communicating with the MFRC522
Toby_Chen 0:f266ca250f98 79 /////////////////////////////////////////////////////////////////////////////////////
Toby_Chen 0:f266ca250f98 80
Toby_Chen 0:f266ca250f98 81 /**
Toby_Chen 0:f266ca250f98 82 * Writes a byte to the specified register in the MFRC522 chip.
Toby_Chen 0:f266ca250f98 83 * The interface is described in the datasheet section 8.1.2.
Toby_Chen 0:f266ca250f98 84 */
Toby_Chen 0:f266ca250f98 85 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t value)
Toby_Chen 0:f266ca250f98 86 {
Toby_Chen 0:f266ca250f98 87 m_CS = 0; /* Select SPI Chip MFRC522 */
Toby_Chen 0:f266ca250f98 88
Toby_Chen 0:f266ca250f98 89 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
Toby_Chen 0:f266ca250f98 90 (void) m_SPI.write(reg & 0x7E);
Toby_Chen 0:f266ca250f98 91 (void) m_SPI.write(value);
Toby_Chen 0:f266ca250f98 92
Toby_Chen 0:f266ca250f98 93 m_CS = 1; /* Release SPI Chip MFRC522 */
Toby_Chen 0:f266ca250f98 94 } // End PCD_WriteRegister()
Toby_Chen 0:f266ca250f98 95
Toby_Chen 0:f266ca250f98 96 /**
Toby_Chen 0:f266ca250f98 97 * Writes a number of bytes to the specified register in the MFRC522 chip.
Toby_Chen 0:f266ca250f98 98 * The interface is described in the datasheet section 8.1.2.
Toby_Chen 0:f266ca250f98 99 */
Toby_Chen 0:f266ca250f98 100 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t count, uint8_t *values)
Toby_Chen 0:f266ca250f98 101 {
Toby_Chen 0:f266ca250f98 102 m_CS = 0; /* Select SPI Chip MFRC522 */
Toby_Chen 0:f266ca250f98 103
Toby_Chen 0:f266ca250f98 104 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
Toby_Chen 0:f266ca250f98 105 (void) m_SPI.write(reg & 0x7E);
Toby_Chen 0:f266ca250f98 106 for (uint8_t index = 0; index < count; index++)
Toby_Chen 0:f266ca250f98 107 {
Toby_Chen 0:f266ca250f98 108 (void) m_SPI.write(values[index]);
Toby_Chen 0:f266ca250f98 109 }
Toby_Chen 0:f266ca250f98 110
Toby_Chen 0:f266ca250f98 111 m_CS = 1; /* Release SPI Chip MFRC522 */
Toby_Chen 0:f266ca250f98 112 } // End PCD_WriteRegister()
Toby_Chen 0:f266ca250f98 113
Toby_Chen 0:f266ca250f98 114 /**
Toby_Chen 0:f266ca250f98 115 * Reads a byte from the specified register in the MFRC522 chip.
Toby_Chen 0:f266ca250f98 116 * The interface is described in the datasheet section 8.1.2.
Toby_Chen 0:f266ca250f98 117 */
Toby_Chen 0:f266ca250f98 118 uint8_t MFRC522::PCD_ReadRegister(uint8_t reg)
Toby_Chen 0:f266ca250f98 119 {
Toby_Chen 0:f266ca250f98 120 uint8_t value;
Toby_Chen 0:f266ca250f98 121 m_CS = 0; /* Select SPI Chip MFRC522 */
Toby_Chen 0:f266ca250f98 122
Toby_Chen 0:f266ca250f98 123 // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
Toby_Chen 0:f266ca250f98 124 (void) m_SPI.write(0x80 | reg);
Toby_Chen 0:f266ca250f98 125
Toby_Chen 0:f266ca250f98 126 // Read the value back. Send 0 to stop reading.
Toby_Chen 0:f266ca250f98 127 value = m_SPI.write(0);
Toby_Chen 0:f266ca250f98 128
Toby_Chen 0:f266ca250f98 129 m_CS = 1; /* Release SPI Chip MFRC522 */
Toby_Chen 0:f266ca250f98 130
Toby_Chen 0:f266ca250f98 131 return value;
Toby_Chen 0:f266ca250f98 132 } // End PCD_ReadRegister()
Toby_Chen 0:f266ca250f98 133
Toby_Chen 0:f266ca250f98 134 /**
Toby_Chen 0:f266ca250f98 135 * Reads a number of bytes from the specified register in the MFRC522 chip.
Toby_Chen 0:f266ca250f98 136 * The interface is described in the datasheet section 8.1.2.
Toby_Chen 0:f266ca250f98 137 */
Toby_Chen 0:f266ca250f98 138 void MFRC522::PCD_ReadRegister(uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign)
Toby_Chen 0:f266ca250f98 139 {
Toby_Chen 0:f266ca250f98 140 if (count == 0) { return; }
Toby_Chen 0:f266ca250f98 141
Toby_Chen 0:f266ca250f98 142 uint8_t address = 0x80 | reg; // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
Toby_Chen 0:f266ca250f98 143 uint8_t index = 0; // Index in values array.
Toby_Chen 0:f266ca250f98 144
Toby_Chen 0:f266ca250f98 145 m_CS = 0; /* Select SPI Chip MFRC522 */
Toby_Chen 0:f266ca250f98 146 count--; // One read is performed outside of the loop
Toby_Chen 0:f266ca250f98 147 (void) m_SPI.write(address); // Tell MFRC522 which address we want to read
Toby_Chen 0:f266ca250f98 148
Toby_Chen 0:f266ca250f98 149 while (index < count)
Toby_Chen 0:f266ca250f98 150 {
Toby_Chen 0:f266ca250f98 151 if ((index == 0) && rxAlign) // Only update bit positions rxAlign..7 in values[0]
Toby_Chen 0:f266ca250f98 152 {
Toby_Chen 0:f266ca250f98 153 // Create bit mask for bit positions rxAlign..7
Toby_Chen 0:f266ca250f98 154 uint8_t mask = 0;
Toby_Chen 0:f266ca250f98 155 for (uint8_t i = rxAlign; i <= 7; i++)
Toby_Chen 0:f266ca250f98 156 {
Toby_Chen 0:f266ca250f98 157 mask |= (1 << i);
Toby_Chen 0:f266ca250f98 158 }
Toby_Chen 0:f266ca250f98 159
Toby_Chen 0:f266ca250f98 160 // Read value and tell that we want to read the same address again.
Toby_Chen 0:f266ca250f98 161 uint8_t value = m_SPI.write(address);
Toby_Chen 0:f266ca250f98 162
Toby_Chen 0:f266ca250f98 163 // Apply mask to both current value of values[0] and the new data in value.
Toby_Chen 0:f266ca250f98 164 values[0] = (values[index] & ~mask) | (value & mask);
Toby_Chen 0:f266ca250f98 165 }
Toby_Chen 0:f266ca250f98 166 else
Toby_Chen 0:f266ca250f98 167 {
Toby_Chen 0:f266ca250f98 168 // Read value and tell that we want to read the same address again.
Toby_Chen 0:f266ca250f98 169 values[index] = m_SPI.write(address);
Toby_Chen 0:f266ca250f98 170 }
Toby_Chen 0:f266ca250f98 171
Toby_Chen 0:f266ca250f98 172 index++;
Toby_Chen 0:f266ca250f98 173 }
Toby_Chen 0:f266ca250f98 174
Toby_Chen 0:f266ca250f98 175 values[index] = m_SPI.write(0); // Read the final byte. Send 0 to stop reading.
Toby_Chen 0:f266ca250f98 176
Toby_Chen 0:f266ca250f98 177 m_CS = 1; /* Release SPI Chip MFRC522 */
Toby_Chen 0:f266ca250f98 178 } // End PCD_ReadRegister()
Toby_Chen 0:f266ca250f98 179
Toby_Chen 0:f266ca250f98 180 /**
Toby_Chen 0:f266ca250f98 181 * Sets the bits given in mask in register reg.
Toby_Chen 0:f266ca250f98 182 */
Toby_Chen 0:f266ca250f98 183 void MFRC522::PCD_SetRegisterBits(uint8_t reg, uint8_t mask)
Toby_Chen 0:f266ca250f98 184 {
Toby_Chen 0:f266ca250f98 185 uint8_t tmp = PCD_ReadRegister(reg);
Toby_Chen 0:f266ca250f98 186 PCD_WriteRegister(reg, tmp | mask); // set bit mask
Toby_Chen 0:f266ca250f98 187 } // End PCD_SetRegisterBitMask()
Toby_Chen 0:f266ca250f98 188
Toby_Chen 0:f266ca250f98 189 /**
Toby_Chen 0:f266ca250f98 190 * Clears the bits given in mask from register reg.
Toby_Chen 0:f266ca250f98 191 */
Toby_Chen 0:f266ca250f98 192 void MFRC522::PCD_ClrRegisterBits(uint8_t reg, uint8_t mask)
Toby_Chen 0:f266ca250f98 193 {
Toby_Chen 0:f266ca250f98 194 uint8_t tmp = PCD_ReadRegister(reg);
Toby_Chen 0:f266ca250f98 195 PCD_WriteRegister(reg, tmp & (~mask)); // clear bit mask
Toby_Chen 0:f266ca250f98 196 } // End PCD_ClearRegisterBitMask()
Toby_Chen 0:f266ca250f98 197
Toby_Chen 0:f266ca250f98 198
Toby_Chen 0:f266ca250f98 199 /**
Toby_Chen 0:f266ca250f98 200 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
Toby_Chen 0:f266ca250f98 201 */
Toby_Chen 0:f266ca250f98 202 uint8_t MFRC522::PCD_CalculateCRC(uint8_t *data, uint8_t length, uint8_t *result)
Toby_Chen 0:f266ca250f98 203 {
Toby_Chen 0:f266ca250f98 204 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
Toby_Chen 0:f266ca250f98 205 PCD_WriteRegister(DivIrqReg, 0x04); // Clear the CRCIRq interrupt request bit
Toby_Chen 0:f266ca250f98 206 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
Toby_Chen 0:f266ca250f98 207 PCD_WriteRegister(FIFODataReg, length, data); // Write data to the FIFO
Toby_Chen 0:f266ca250f98 208 PCD_WriteRegister(CommandReg, PCD_CalcCRC); // Start the calculation
Toby_Chen 0:f266ca250f98 209
Toby_Chen 0:f266ca250f98 210 // Wait for the CRC calculation to complete. Each iteration of the while-loop takes 17.73us.
Toby_Chen 0:f266ca250f98 211 uint16_t i = 5000;
Toby_Chen 0:f266ca250f98 212 uint8_t n;
Toby_Chen 0:f266ca250f98 213 while (1)
Toby_Chen 0:f266ca250f98 214 {
Toby_Chen 0:f266ca250f98 215 n = PCD_ReadRegister(DivIrqReg); // DivIrqReg[7..0] bits are: Set2 reserved reserved MfinActIRq reserved CRCIRq reserved reserved
Toby_Chen 0:f266ca250f98 216 if (n & 0x04)
Toby_Chen 0:f266ca250f98 217 {
Toby_Chen 0:f266ca250f98 218 // CRCIRq bit set - calculation done
Toby_Chen 0:f266ca250f98 219 break;
Toby_Chen 0:f266ca250f98 220 }
Toby_Chen 0:f266ca250f98 221
Toby_Chen 0:f266ca250f98 222 if (--i == 0)
Toby_Chen 0:f266ca250f98 223 {
Toby_Chen 0:f266ca250f98 224 // The emergency break. We will eventually terminate on this one after 89ms.
Toby_Chen 0:f266ca250f98 225 // Communication with the MFRC522 might be down.
Toby_Chen 0:f266ca250f98 226 return STATUS_TIMEOUT;
Toby_Chen 0:f266ca250f98 227 }
Toby_Chen 0:f266ca250f98 228 }
Toby_Chen 0:f266ca250f98 229
Toby_Chen 0:f266ca250f98 230 // Stop calculating CRC for new content in the FIFO.
Toby_Chen 0:f266ca250f98 231 PCD_WriteRegister(CommandReg, PCD_Idle);
Toby_Chen 0:f266ca250f98 232
Toby_Chen 0:f266ca250f98 233 // Transfer the result from the registers to the result buffer
Toby_Chen 0:f266ca250f98 234 result[0] = PCD_ReadRegister(CRCResultRegL);
Toby_Chen 0:f266ca250f98 235 result[1] = PCD_ReadRegister(CRCResultRegH);
Toby_Chen 0:f266ca250f98 236 return STATUS_OK;
Toby_Chen 0:f266ca250f98 237 } // End PCD_CalculateCRC()
Toby_Chen 0:f266ca250f98 238
Toby_Chen 0:f266ca250f98 239
Toby_Chen 0:f266ca250f98 240 /////////////////////////////////////////////////////////////////////////////////////
Toby_Chen 0:f266ca250f98 241 // Functions for manipulating the MFRC522
Toby_Chen 0:f266ca250f98 242 /////////////////////////////////////////////////////////////////////////////////////
Toby_Chen 0:f266ca250f98 243
Toby_Chen 0:f266ca250f98 244 /**
Toby_Chen 0:f266ca250f98 245 * Initializes the MFRC522 chip.
Toby_Chen 0:f266ca250f98 246 */
Toby_Chen 0:f266ca250f98 247 void MFRC522::PCD_Init()
Toby_Chen 0:f266ca250f98 248 {
Toby_Chen 0:f266ca250f98 249 /* Reset MFRC522 */
Toby_Chen 0:f266ca250f98 250 m_RESET = 0;
Toby_Chen 0:f266ca250f98 251 wait_ms(10);
Toby_Chen 0:f266ca250f98 252 m_RESET = 1;
Toby_Chen 0:f266ca250f98 253
Toby_Chen 0:f266ca250f98 254 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
Toby_Chen 0:f266ca250f98 255 wait_ms(50);
Toby_Chen 0:f266ca250f98 256
Toby_Chen 0:f266ca250f98 257 // When communicating with a PICC we need a timeout if something goes wrong.
Toby_Chen 0:f266ca250f98 258 // f_timer = 13.56 MHz / (2*TPreScaler+1) where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo].
Toby_Chen 0:f266ca250f98 259 // TPrescaler_Hi are the four low bits in TModeReg. TPrescaler_Lo is TPrescalerReg.
Toby_Chen 0:f266ca250f98 260 PCD_WriteRegister(TModeReg, 0x80); // TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds
Toby_Chen 0:f266ca250f98 261 PCD_WriteRegister(TPrescalerReg, 0xA9); // TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25us.
Toby_Chen 0:f266ca250f98 262 PCD_WriteRegister(TReloadRegH, 0x03); // Reload timer with 0x3E8 = 1000, ie 25ms before timeout.
Toby_Chen 0:f266ca250f98 263 PCD_WriteRegister(TReloadRegL, 0xE8);
Toby_Chen 0:f266ca250f98 264
Toby_Chen 0:f266ca250f98 265 PCD_WriteRegister(TxASKReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
Toby_Chen 0:f266ca250f98 266 PCD_WriteRegister(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
Toby_Chen 0:f266ca250f98 267
Toby_Chen 0:f266ca250f98 268 PCD_WriteRegister(RFCfgReg, (0x07<<4)); // Set Rx Gain to max
Toby_Chen 0:f266ca250f98 269
Toby_Chen 0:f266ca250f98 270 PCD_AntennaOn(); // Enable the antenna driver pins TX1 and TX2 (they were disabled by the reset)
Toby_Chen 0:f266ca250f98 271 } // End PCD_Init()
Toby_Chen 0:f266ca250f98 272
Toby_Chen 0:f266ca250f98 273 /**
Toby_Chen 0:f266ca250f98 274 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
Toby_Chen 0:f266ca250f98 275 */
Toby_Chen 0:f266ca250f98 276 void MFRC522::PCD_Reset()
Toby_Chen 0:f266ca250f98 277 {
Toby_Chen 0:f266ca250f98 278 PCD_WriteRegister(CommandReg, PCD_SoftReset); // Issue the SoftReset command.
Toby_Chen 0:f266ca250f98 279 // The datasheet does not mention how long the SoftRest command takes to complete.
Toby_Chen 0:f266ca250f98 280 // But the MFRC522 might have been in soft power-down mode (triggered by bit 4 of CommandReg)
Toby_Chen 0:f266ca250f98 281 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
Toby_Chen 0:f266ca250f98 282 wait_ms(50);
Toby_Chen 0:f266ca250f98 283
Toby_Chen 0:f266ca250f98 284 // Wait for the PowerDown bit in CommandReg to be cleared
Toby_Chen 0:f266ca250f98 285 while (PCD_ReadRegister(CommandReg) & (1<<4))
Toby_Chen 0:f266ca250f98 286 {
Toby_Chen 0:f266ca250f98 287 // PCD still restarting - unlikely after waiting 50ms, but better safe than sorry.
Toby_Chen 0:f266ca250f98 288 }
Toby_Chen 0:f266ca250f98 289 } // End PCD_Reset()
Toby_Chen 0:f266ca250f98 290
Toby_Chen 0:f266ca250f98 291 /**
Toby_Chen 0:f266ca250f98 292 * Turns the antenna on by enabling pins TX1 and TX2.
Toby_Chen 0:f266ca250f98 293 * After a reset these pins disabled.
Toby_Chen 0:f266ca250f98 294 */
Toby_Chen 0:f266ca250f98 295 void MFRC522::PCD_AntennaOn()
Toby_Chen 0:f266ca250f98 296 {
Toby_Chen 0:f266ca250f98 297 uint8_t value = PCD_ReadRegister(TxControlReg);
Toby_Chen 0:f266ca250f98 298 if ((value & 0x03) != 0x03)
Toby_Chen 0:f266ca250f98 299 {
Toby_Chen 0:f266ca250f98 300 PCD_WriteRegister(TxControlReg, value | 0x03);
Toby_Chen 0:f266ca250f98 301 }
Toby_Chen 0:f266ca250f98 302 } // End PCD_AntennaOn()
Toby_Chen 0:f266ca250f98 303
Toby_Chen 0:f266ca250f98 304 /////////////////////////////////////////////////////////////////////////////////////
Toby_Chen 0:f266ca250f98 305 // Functions for communicating with PICCs
Toby_Chen 0:f266ca250f98 306 /////////////////////////////////////////////////////////////////////////////////////
Toby_Chen 0:f266ca250f98 307
Toby_Chen 0:f266ca250f98 308 /**
Toby_Chen 0:f266ca250f98 309 * Executes the Transceive command.
Toby_Chen 0:f266ca250f98 310 * CRC validation can only be done if backData and backLen are specified.
Toby_Chen 0:f266ca250f98 311 */
Toby_Chen 0:f266ca250f98 312 uint8_t MFRC522::PCD_TransceiveData(uint8_t *sendData,
Toby_Chen 0:f266ca250f98 313 uint8_t sendLen,
Toby_Chen 0:f266ca250f98 314 uint8_t *backData,
Toby_Chen 0:f266ca250f98 315 uint8_t *backLen,
Toby_Chen 0:f266ca250f98 316 uint8_t *validBits,
Toby_Chen 0:f266ca250f98 317 uint8_t rxAlign,
Toby_Chen 0:f266ca250f98 318 bool checkCRC)
Toby_Chen 0:f266ca250f98 319 {
Toby_Chen 0:f266ca250f98 320 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
Toby_Chen 0:f266ca250f98 321 return PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, sendData, sendLen, backData, backLen, validBits, rxAlign, checkCRC);
Toby_Chen 0:f266ca250f98 322 } // End PCD_TransceiveData()
Toby_Chen 0:f266ca250f98 323
Toby_Chen 0:f266ca250f98 324 /**
Toby_Chen 0:f266ca250f98 325 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
Toby_Chen 0:f266ca250f98 326 * CRC validation can only be done if backData and backLen are specified.
Toby_Chen 0:f266ca250f98 327 */
Toby_Chen 0:f266ca250f98 328 uint8_t MFRC522::PCD_CommunicateWithPICC(uint8_t command,
Toby_Chen 0:f266ca250f98 329 uint8_t waitIRq,
Toby_Chen 0:f266ca250f98 330 uint8_t *sendData,
Toby_Chen 0:f266ca250f98 331 uint8_t sendLen,
Toby_Chen 0:f266ca250f98 332 uint8_t *backData,
Toby_Chen 0:f266ca250f98 333 uint8_t *backLen,
Toby_Chen 0:f266ca250f98 334 uint8_t *validBits,
Toby_Chen 0:f266ca250f98 335 uint8_t rxAlign,
Toby_Chen 0:f266ca250f98 336 bool checkCRC)
Toby_Chen 0:f266ca250f98 337 {
Toby_Chen 0:f266ca250f98 338 uint8_t n, _validBits = 0;
Toby_Chen 0:f266ca250f98 339 uint32_t i;
Toby_Chen 0:f266ca250f98 340
Toby_Chen 0:f266ca250f98 341 // Prepare values for BitFramingReg
Toby_Chen 0:f266ca250f98 342 uint8_t txLastBits = validBits ? *validBits : 0;
Toby_Chen 0:f266ca250f98 343 uint8_t bitFraming = (rxAlign << 4) + txLastBits; // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
Toby_Chen 0:f266ca250f98 344
Toby_Chen 0:f266ca250f98 345 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
Toby_Chen 0:f266ca250f98 346 PCD_WriteRegister(ComIrqReg, 0x7F); // Clear all seven interrupt request bits
Toby_Chen 0:f266ca250f98 347 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
Toby_Chen 0:f266ca250f98 348 PCD_WriteRegister(FIFODataReg, sendLen, sendData); // Write sendData to the FIFO
Toby_Chen 0:f266ca250f98 349 PCD_WriteRegister(BitFramingReg, bitFraming); // Bit adjustments
Toby_Chen 0:f266ca250f98 350 PCD_WriteRegister(CommandReg, command); // Execute the command
Toby_Chen 0:f266ca250f98 351 if (command == PCD_Transceive)
Toby_Chen 0:f266ca250f98 352 {
Toby_Chen 0:f266ca250f98 353 PCD_SetRegisterBits(BitFramingReg, 0x80); // StartSend=1, transmission of data starts
Toby_Chen 0:f266ca250f98 354 }
Toby_Chen 0:f266ca250f98 355
Toby_Chen 0:f266ca250f98 356 // Wait for the command to complete.
Toby_Chen 0:f266ca250f98 357 // In PCD_Init() we set the TAuto flag in TModeReg. This means the timer automatically starts when the PCD stops transmitting.
Toby_Chen 0:f266ca250f98 358 // Each iteration of the do-while-loop takes 17.86us.
Toby_Chen 0:f266ca250f98 359 i = 2000;
Toby_Chen 0:f266ca250f98 360 while (1)
Toby_Chen 0:f266ca250f98 361 {
Toby_Chen 0:f266ca250f98 362 n = PCD_ReadRegister(ComIrqReg); // ComIrqReg[7..0] bits are: Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
Toby_Chen 0:f266ca250f98 363 if (n & waitIRq)
Toby_Chen 0:f266ca250f98 364 { // One of the interrupts that signal success has been set.
Toby_Chen 0:f266ca250f98 365 break;
Toby_Chen 0:f266ca250f98 366 }
Toby_Chen 0:f266ca250f98 367
Toby_Chen 0:f266ca250f98 368 if (n & 0x01)
Toby_Chen 0:f266ca250f98 369 { // Timer interrupt - nothing received in 25ms
Toby_Chen 0:f266ca250f98 370 return STATUS_TIMEOUT;
Toby_Chen 0:f266ca250f98 371 }
Toby_Chen 0:f266ca250f98 372
Toby_Chen 0:f266ca250f98 373 if (--i == 0)
Toby_Chen 0:f266ca250f98 374 { // The emergency break. If all other condions fail we will eventually terminate on this one after 35.7ms. Communication with the MFRC522 might be down.
Toby_Chen 0:f266ca250f98 375 return STATUS_TIMEOUT;
Toby_Chen 0:f266ca250f98 376 }
Toby_Chen 0:f266ca250f98 377 }
Toby_Chen 0:f266ca250f98 378
Toby_Chen 0:f266ca250f98 379 // Stop now if any errors except collisions were detected.
Toby_Chen 0:f266ca250f98 380 uint8_t errorRegValue = PCD_ReadRegister(ErrorReg); // ErrorReg[7..0] bits are: WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr
Toby_Chen 0:f266ca250f98 381 if (errorRegValue & 0x13)
Toby_Chen 0:f266ca250f98 382 { // BufferOvfl ParityErr ProtocolErr
Toby_Chen 0:f266ca250f98 383 return STATUS_ERROR;
Toby_Chen 0:f266ca250f98 384 }
Toby_Chen 0:f266ca250f98 385
Toby_Chen 0:f266ca250f98 386 // If the caller wants data back, get it from the MFRC522.
Toby_Chen 0:f266ca250f98 387 if (backData && backLen)
Toby_Chen 0:f266ca250f98 388 {
Toby_Chen 0:f266ca250f98 389 n = PCD_ReadRegister(FIFOLevelReg); // Number of bytes in the FIFO
Toby_Chen 0:f266ca250f98 390 if (n > *backLen)
Toby_Chen 0:f266ca250f98 391 {
Toby_Chen 0:f266ca250f98 392 return STATUS_NO_ROOM;
Toby_Chen 0:f266ca250f98 393 }
Toby_Chen 0:f266ca250f98 394
Toby_Chen 0:f266ca250f98 395 *backLen = n; // Number of bytes returned
Toby_Chen 0:f266ca250f98 396 PCD_ReadRegister(FIFODataReg, n, backData, rxAlign); // Get received data from FIFO
Toby_Chen 0:f266ca250f98 397 _validBits = PCD_ReadRegister(ControlReg) & 0x07; // RxLastBits[2:0] indicates the number of valid bits in the last received byte. If this value is 000b, the whole byte is valid.
Toby_Chen 0:f266ca250f98 398 if (validBits)
Toby_Chen 0:f266ca250f98 399 {
Toby_Chen 0:f266ca250f98 400 *validBits = _validBits;
Toby_Chen 0:f266ca250f98 401 }
Toby_Chen 0:f266ca250f98 402 }
Toby_Chen 0:f266ca250f98 403
Toby_Chen 0:f266ca250f98 404 // Tell about collisions
Toby_Chen 0:f266ca250f98 405 if (errorRegValue & 0x08)
Toby_Chen 0:f266ca250f98 406 { // CollErr
Toby_Chen 0:f266ca250f98 407 return STATUS_COLLISION;
Toby_Chen 0:f266ca250f98 408 }
Toby_Chen 0:f266ca250f98 409
Toby_Chen 0:f266ca250f98 410 // Perform CRC_A validation if requested.
Toby_Chen 0:f266ca250f98 411 if (backData && backLen && checkCRC)
Toby_Chen 0:f266ca250f98 412 {
Toby_Chen 0:f266ca250f98 413 // In this case a MIFARE Classic NAK is not OK.
Toby_Chen 0:f266ca250f98 414 if ((*backLen == 1) && (_validBits == 4))
Toby_Chen 0:f266ca250f98 415 {
Toby_Chen 0:f266ca250f98 416 return STATUS_MIFARE_NACK;
Toby_Chen 0:f266ca250f98 417 }
Toby_Chen 0:f266ca250f98 418
Toby_Chen 0:f266ca250f98 419 // We need at least the CRC_A value and all 8 bits of the last byte must be received.
Toby_Chen 0:f266ca250f98 420 if ((*backLen < 2) || (_validBits != 0))
Toby_Chen 0:f266ca250f98 421 {
Toby_Chen 0:f266ca250f98 422 return STATUS_CRC_WRONG;
Toby_Chen 0:f266ca250f98 423 }
Toby_Chen 0:f266ca250f98 424
Toby_Chen 0:f266ca250f98 425 // Verify CRC_A - do our own calculation and store the control in controlBuffer.
Toby_Chen 0:f266ca250f98 426 uint8_t controlBuffer[2];
Toby_Chen 0:f266ca250f98 427 n = PCD_CalculateCRC(&backData[0], *backLen - 2, &controlBuffer[0]);
Toby_Chen 0:f266ca250f98 428 if (n != STATUS_OK)
Toby_Chen 0:f266ca250f98 429 {
Toby_Chen 0:f266ca250f98 430 return n;
Toby_Chen 0:f266ca250f98 431 }
Toby_Chen 0:f266ca250f98 432
Toby_Chen 0:f266ca250f98 433 if ((backData[*backLen - 2] != controlBuffer[0]) || (backData[*backLen - 1] != controlBuffer[1]))
Toby_Chen 0:f266ca250f98 434 {
Toby_Chen 0:f266ca250f98 435 return STATUS_CRC_WRONG;
Toby_Chen 0:f266ca250f98 436 }
Toby_Chen 0:f266ca250f98 437 }
Toby_Chen 0:f266ca250f98 438
Toby_Chen 0:f266ca250f98 439 return STATUS_OK;
Toby_Chen 0:f266ca250f98 440 } // End PCD_CommunicateWithPICC()
Toby_Chen 0:f266ca250f98 441
Toby_Chen 0:f266ca250f98 442 /*
Toby_Chen 0:f266ca250f98 443 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
Toby_Chen 0:f266ca250f98 444 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
Toby_Chen 0:f266ca250f98 445 */
Toby_Chen 0:f266ca250f98 446 uint8_t MFRC522::PICC_RequestA(uint8_t *bufferATQA, uint8_t *bufferSize)
Toby_Chen 0:f266ca250f98 447 {
Toby_Chen 0:f266ca250f98 448 return PICC_REQA_or_WUPA(PICC_CMD_REQA, bufferATQA, bufferSize);
Toby_Chen 0:f266ca250f98 449 } // End PICC_RequestA()
Toby_Chen 0:f266ca250f98 450
Toby_Chen 0:f266ca250f98 451 /**
Toby_Chen 0:f266ca250f98 452 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
Toby_Chen 0:f266ca250f98 453 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
Toby_Chen 0:f266ca250f98 454 */
Toby_Chen 0:f266ca250f98 455 uint8_t MFRC522::PICC_WakeupA(uint8_t *bufferATQA, uint8_t *bufferSize)
Toby_Chen 0:f266ca250f98 456 {
Toby_Chen 0:f266ca250f98 457 return PICC_REQA_or_WUPA(PICC_CMD_WUPA, bufferATQA, bufferSize);
Toby_Chen 0:f266ca250f98 458 } // End PICC_WakeupA()
Toby_Chen 0:f266ca250f98 459
Toby_Chen 0:f266ca250f98 460 /*
Toby_Chen 0:f266ca250f98 461 * Transmits REQA or WUPA commands.
Toby_Chen 0:f266ca250f98 462 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
Toby_Chen 0:f266ca250f98 463 */
Toby_Chen 0:f266ca250f98 464 uint8_t MFRC522::PICC_REQA_or_WUPA(uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize)
Toby_Chen 0:f266ca250f98 465 {
Toby_Chen 0:f266ca250f98 466 uint8_t validBits;
Toby_Chen 0:f266ca250f98 467 uint8_t status;
Toby_Chen 0:f266ca250f98 468
Toby_Chen 0:f266ca250f98 469 if (bufferATQA == NULL || *bufferSize < 2)
Toby_Chen 0:f266ca250f98 470 { // The ATQA response is 2 bytes long.
Toby_Chen 0:f266ca250f98 471 return STATUS_NO_ROOM;
Toby_Chen 0:f266ca250f98 472 }
Toby_Chen 0:f266ca250f98 473
Toby_Chen 0:f266ca250f98 474 // ValuesAfterColl=1 => Bits received after collision are cleared.
Toby_Chen 0:f266ca250f98 475 PCD_ClrRegisterBits(CollReg, 0x80);
Toby_Chen 0:f266ca250f98 476
Toby_Chen 0:f266ca250f98 477 // For REQA and WUPA we need the short frame format
Toby_Chen 0:f266ca250f98 478 // - transmit only 7 bits of the last (and only) byte. TxLastBits = BitFramingReg[2..0]
Toby_Chen 0:f266ca250f98 479 validBits = 7;
Toby_Chen 0:f266ca250f98 480
Toby_Chen 0:f266ca250f98 481 status = PCD_TransceiveData(&command, 1, bufferATQA, bufferSize, &validBits);
Toby_Chen 0:f266ca250f98 482 if (status != STATUS_OK)
Toby_Chen 0:f266ca250f98 483 {
Toby_Chen 0:f266ca250f98 484 return status;
Toby_Chen 0:f266ca250f98 485 }
Toby_Chen 0:f266ca250f98 486
Toby_Chen 0:f266ca250f98 487 if ((*bufferSize != 2) || (validBits != 0))
Toby_Chen 0:f266ca250f98 488 { // ATQA must be exactly 16 bits.
Toby_Chen 0:f266ca250f98 489 return STATUS_ERROR;
Toby_Chen 0:f266ca250f98 490 }
Toby_Chen 0:f266ca250f98 491
Toby_Chen 0:f266ca250f98 492 return STATUS_OK;
Toby_Chen 0:f266ca250f98 493 } // End PICC_REQA_or_WUPA()
Toby_Chen 0:f266ca250f98 494
Toby_Chen 0:f266ca250f98 495 /*
Toby_Chen 0:f266ca250f98 496 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
Toby_Chen 0:f266ca250f98 497 */
Toby_Chen 0:f266ca250f98 498 uint8_t MFRC522::PICC_Select(Uid *uid, uint8_t validBits)
Toby_Chen 0:f266ca250f98 499 {
Toby_Chen 0:f266ca250f98 500 bool uidComplete;
Toby_Chen 0:f266ca250f98 501 bool selectDone;
Toby_Chen 0:f266ca250f98 502 bool useCascadeTag;
Toby_Chen 0:f266ca250f98 503 uint8_t cascadeLevel = 1;
Toby_Chen 0:f266ca250f98 504 uint8_t result;
Toby_Chen 0:f266ca250f98 505 uint8_t count;
Toby_Chen 0:f266ca250f98 506 uint8_t index;
Toby_Chen 0:f266ca250f98 507 uint8_t uidIndex; // The first index in uid->uidByte[] that is used in the current Cascade Level.
Toby_Chen 0:f266ca250f98 508 uint8_t currentLevelKnownBits; // The number of known UID bits in the current Cascade Level.
Toby_Chen 0:f266ca250f98 509 uint8_t buffer[9]; // The SELECT/ANTICOLLISION commands uses a 7 byte standard frame + 2 bytes CRC_A
Toby_Chen 0:f266ca250f98 510 uint8_t bufferUsed; // The number of bytes used in the buffer, ie the number of bytes to transfer to the FIFO.
Toby_Chen 0:f266ca250f98 511 uint8_t rxAlign; // Used in BitFramingReg. Defines the bit position for the first bit received.
Toby_Chen 0:f266ca250f98 512 uint8_t txLastBits; // Used in BitFramingReg. The number of valid bits in the last transmitted byte.
Toby_Chen 0:f266ca250f98 513 uint8_t *responseBuffer;
Toby_Chen 0:f266ca250f98 514 uint8_t responseLength;
Toby_Chen 0:f266ca250f98 515
Toby_Chen 0:f266ca250f98 516 // Description of buffer structure:
Toby_Chen 0:f266ca250f98 517 // Byte 0: SEL Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3
Toby_Chen 0:f266ca250f98 518 // Byte 1: NVB Number of Valid Bits (in complete command, not just the UID): High nibble: complete bytes, Low nibble: Extra bits.
Toby_Chen 0:f266ca250f98 519 // Byte 2: UID-data or CT See explanation below. CT means Cascade Tag.
Toby_Chen 0:f266ca250f98 520 // Byte 3: UID-data
Toby_Chen 0:f266ca250f98 521 // Byte 4: UID-data
Toby_Chen 0:f266ca250f98 522 // Byte 5: UID-data
Toby_Chen 0:f266ca250f98 523 // Byte 6: BCC Block Check Character - XOR of bytes 2-5
Toby_Chen 0:f266ca250f98 524 // Byte 7: CRC_A
Toby_Chen 0:f266ca250f98 525 // Byte 8: CRC_A
Toby_Chen 0:f266ca250f98 526 // The BCC and CRC_A is only transmitted if we know all the UID bits of the current Cascade Level.
Toby_Chen 0:f266ca250f98 527 //
Toby_Chen 0:f266ca250f98 528 // Description of bytes 2-5: (Section 6.5.4 of the ISO/IEC 14443-3 draft: UID contents and cascade levels)
Toby_Chen 0:f266ca250f98 529 // UID size Cascade level Byte2 Byte3 Byte4 Byte5
Toby_Chen 0:f266ca250f98 530 // ======== ============= ===== ===== ===== =====
Toby_Chen 0:f266ca250f98 531 // 4 bytes 1 uid0 uid1 uid2 uid3
Toby_Chen 0:f266ca250f98 532 // 7 bytes 1 CT uid0 uid1 uid2
Toby_Chen 0:f266ca250f98 533 // 2 uid3 uid4 uid5 uid6
Toby_Chen 0:f266ca250f98 534 // 10 bytes 1 CT uid0 uid1 uid2
Toby_Chen 0:f266ca250f98 535 // 2 CT uid3 uid4 uid5
Toby_Chen 0:f266ca250f98 536 // 3 uid6 uid7 uid8 uid9
Toby_Chen 0:f266ca250f98 537
Toby_Chen 0:f266ca250f98 538 // Sanity checks
Toby_Chen 0:f266ca250f98 539 if (validBits > 80)
Toby_Chen 0:f266ca250f98 540 {
Toby_Chen 0:f266ca250f98 541 return STATUS_INVALID;
Toby_Chen 0:f266ca250f98 542 }
Toby_Chen 0:f266ca250f98 543
Toby_Chen 0:f266ca250f98 544 // Prepare MFRC522
Toby_Chen 0:f266ca250f98 545 // ValuesAfterColl=1 => Bits received after collision are cleared.
Toby_Chen 0:f266ca250f98 546 PCD_ClrRegisterBits(CollReg, 0x80);
Toby_Chen 0:f266ca250f98 547
Toby_Chen 0:f266ca250f98 548 // Repeat Cascade Level loop until we have a complete UID.
Toby_Chen 0:f266ca250f98 549 uidComplete = false;
Toby_Chen 0:f266ca250f98 550 while ( ! uidComplete)
Toby_Chen 0:f266ca250f98 551 {
Toby_Chen 0:f266ca250f98 552 // Set the Cascade Level in the SEL byte, find out if we need to use the Cascade Tag in byte 2.
Toby_Chen 0:f266ca250f98 553 switch (cascadeLevel)
Toby_Chen 0:f266ca250f98 554 {
Toby_Chen 0:f266ca250f98 555 case 1:
Toby_Chen 0:f266ca250f98 556 buffer[0] = PICC_CMD_SEL_CL1;
Toby_Chen 0:f266ca250f98 557 uidIndex = 0;
Toby_Chen 0:f266ca250f98 558 useCascadeTag = validBits && (uid->size > 4); // When we know that the UID has more than 4 bytes
Toby_Chen 0:f266ca250f98 559 break;
Toby_Chen 0:f266ca250f98 560
Toby_Chen 0:f266ca250f98 561 case 2:
Toby_Chen 0:f266ca250f98 562 buffer[0] = PICC_CMD_SEL_CL2;
Toby_Chen 0:f266ca250f98 563 uidIndex = 3;
Toby_Chen 0:f266ca250f98 564 useCascadeTag = validBits && (uid->size > 7); // When we know that the UID has more than 7 bytes
Toby_Chen 0:f266ca250f98 565 break;
Toby_Chen 0:f266ca250f98 566
Toby_Chen 0:f266ca250f98 567 case 3:
Toby_Chen 0:f266ca250f98 568 buffer[0] = PICC_CMD_SEL_CL3;
Toby_Chen 0:f266ca250f98 569 uidIndex = 6;
Toby_Chen 0:f266ca250f98 570 useCascadeTag = false; // Never used in CL3.
Toby_Chen 0:f266ca250f98 571 break;
Toby_Chen 0:f266ca250f98 572
Toby_Chen 0:f266ca250f98 573 default:
Toby_Chen 0:f266ca250f98 574 return STATUS_INTERNAL_ERROR;
Toby_Chen 0:f266ca250f98 575 //break;
Toby_Chen 0:f266ca250f98 576 }
Toby_Chen 0:f266ca250f98 577
Toby_Chen 0:f266ca250f98 578 // How many UID bits are known in this Cascade Level?
Toby_Chen 0:f266ca250f98 579 if(validBits > (8 * uidIndex))
Toby_Chen 0:f266ca250f98 580 {
Toby_Chen 0:f266ca250f98 581 currentLevelKnownBits = validBits - (8 * uidIndex);
Toby_Chen 0:f266ca250f98 582 }
Toby_Chen 0:f266ca250f98 583 else
Toby_Chen 0:f266ca250f98 584 {
Toby_Chen 0:f266ca250f98 585 currentLevelKnownBits = 0;
Toby_Chen 0:f266ca250f98 586 }
Toby_Chen 0:f266ca250f98 587
Toby_Chen 0:f266ca250f98 588 // Copy the known bits from uid->uidByte[] to buffer[]
Toby_Chen 0:f266ca250f98 589 index = 2; // destination index in buffer[]
Toby_Chen 0:f266ca250f98 590 if (useCascadeTag)
Toby_Chen 0:f266ca250f98 591 {
Toby_Chen 0:f266ca250f98 592 buffer[index++] = PICC_CMD_CT;
Toby_Chen 0:f266ca250f98 593 }
Toby_Chen 0:f266ca250f98 594
Toby_Chen 0:f266ca250f98 595 uint8_t bytesToCopy = currentLevelKnownBits / 8 + (currentLevelKnownBits % 8 ? 1 : 0); // The number of bytes needed to represent the known bits for this level.
Toby_Chen 0:f266ca250f98 596 if (bytesToCopy)
Toby_Chen 0:f266ca250f98 597 {
Toby_Chen 0:f266ca250f98 598 // Max 4 bytes in each Cascade Level. Only 3 left if we use the Cascade Tag
Toby_Chen 0:f266ca250f98 599 uint8_t maxBytes = useCascadeTag ? 3 : 4;
Toby_Chen 0:f266ca250f98 600 if (bytesToCopy > maxBytes)
Toby_Chen 0:f266ca250f98 601 {
Toby_Chen 0:f266ca250f98 602 bytesToCopy = maxBytes;
Toby_Chen 0:f266ca250f98 603 }
Toby_Chen 0:f266ca250f98 604
Toby_Chen 0:f266ca250f98 605 for (count = 0; count < bytesToCopy; count++)
Toby_Chen 0:f266ca250f98 606 {
Toby_Chen 0:f266ca250f98 607 buffer[index++] = uid->uidByte[uidIndex + count];
Toby_Chen 0:f266ca250f98 608 }
Toby_Chen 0:f266ca250f98 609 }
Toby_Chen 0:f266ca250f98 610
Toby_Chen 0:f266ca250f98 611 // Now that the data has been copied we need to include the 8 bits in CT in currentLevelKnownBits
Toby_Chen 0:f266ca250f98 612 if (useCascadeTag)
Toby_Chen 0:f266ca250f98 613 {
Toby_Chen 0:f266ca250f98 614 currentLevelKnownBits += 8;
Toby_Chen 0:f266ca250f98 615 }
Toby_Chen 0:f266ca250f98 616
Toby_Chen 0:f266ca250f98 617 // Repeat anti collision loop until we can transmit all UID bits + BCC and receive a SAK - max 32 iterations.
Toby_Chen 0:f266ca250f98 618 selectDone = false;
Toby_Chen 0:f266ca250f98 619 while ( ! selectDone)
Toby_Chen 0:f266ca250f98 620 {
Toby_Chen 0:f266ca250f98 621 // Find out how many bits and bytes to send and receive.
Toby_Chen 0:f266ca250f98 622 if (currentLevelKnownBits >= 32)
Toby_Chen 0:f266ca250f98 623 { // All UID bits in this Cascade Level are known. This is a SELECT.
Toby_Chen 0:f266ca250f98 624 //Serial.print("SELECT: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
Toby_Chen 0:f266ca250f98 625 buffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes
Toby_Chen 0:f266ca250f98 626
Toby_Chen 0:f266ca250f98 627 // Calulate BCC - Block Check Character
Toby_Chen 0:f266ca250f98 628 buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5];
Toby_Chen 0:f266ca250f98 629
Toby_Chen 0:f266ca250f98 630 // Calculate CRC_A
Toby_Chen 0:f266ca250f98 631 result = PCD_CalculateCRC(buffer, 7, &buffer[7]);
Toby_Chen 0:f266ca250f98 632 if (result != STATUS_OK)
Toby_Chen 0:f266ca250f98 633 {
Toby_Chen 0:f266ca250f98 634 return result;
Toby_Chen 0:f266ca250f98 635 }
Toby_Chen 0:f266ca250f98 636
Toby_Chen 0:f266ca250f98 637 txLastBits = 0; // 0 => All 8 bits are valid.
Toby_Chen 0:f266ca250f98 638 bufferUsed = 9;
Toby_Chen 0:f266ca250f98 639
Toby_Chen 0:f266ca250f98 640 // Store response in the last 3 bytes of buffer (BCC and CRC_A - not needed after tx)
Toby_Chen 0:f266ca250f98 641 responseBuffer = &buffer[6];
Toby_Chen 0:f266ca250f98 642 responseLength = 3;
Toby_Chen 0:f266ca250f98 643 }
Toby_Chen 0:f266ca250f98 644 else
Toby_Chen 0:f266ca250f98 645 { // This is an ANTICOLLISION.
Toby_Chen 0:f266ca250f98 646 //Serial.print("ANTICOLLISION: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
Toby_Chen 0:f266ca250f98 647 txLastBits = currentLevelKnownBits % 8;
Toby_Chen 0:f266ca250f98 648 count = currentLevelKnownBits / 8; // Number of whole bytes in the UID part.
Toby_Chen 0:f266ca250f98 649 index = 2 + count; // Number of whole bytes: SEL + NVB + UIDs
Toby_Chen 0:f266ca250f98 650 buffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits
Toby_Chen 0:f266ca250f98 651 bufferUsed = index + (txLastBits ? 1 : 0);
Toby_Chen 0:f266ca250f98 652
Toby_Chen 0:f266ca250f98 653 // Store response in the unused part of buffer
Toby_Chen 0:f266ca250f98 654 responseBuffer = &buffer[index];
Toby_Chen 0:f266ca250f98 655 responseLength = sizeof(buffer) - index;
Toby_Chen 0:f266ca250f98 656 }
Toby_Chen 0:f266ca250f98 657
Toby_Chen 0:f266ca250f98 658 // Set bit adjustments
Toby_Chen 0:f266ca250f98 659 rxAlign = txLastBits; // Having a seperate variable is overkill. But it makes the next line easier to read.
Toby_Chen 0:f266ca250f98 660 PCD_WriteRegister(BitFramingReg, (rxAlign << 4) + txLastBits); // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
Toby_Chen 0:f266ca250f98 661
Toby_Chen 0:f266ca250f98 662 // Transmit the buffer and receive the response.
Toby_Chen 0:f266ca250f98 663 result = PCD_TransceiveData(buffer, bufferUsed, responseBuffer, &responseLength, &txLastBits, rxAlign);
Toby_Chen 0:f266ca250f98 664 if (result == STATUS_COLLISION)
Toby_Chen 0:f266ca250f98 665 { // More than one PICC in the field => collision.
Toby_Chen 0:f266ca250f98 666 result = PCD_ReadRegister(CollReg); // CollReg[7..0] bits are: ValuesAfterColl reserved CollPosNotValid CollPos[4:0]
Toby_Chen 0:f266ca250f98 667 if (result & 0x20)
Toby_Chen 0:f266ca250f98 668 { // CollPosNotValid
Toby_Chen 0:f266ca250f98 669 return STATUS_COLLISION; // Without a valid collision position we cannot continue
Toby_Chen 0:f266ca250f98 670 }
Toby_Chen 0:f266ca250f98 671
Toby_Chen 0:f266ca250f98 672 uint8_t collisionPos = result & 0x1F; // Values 0-31, 0 means bit 32.
Toby_Chen 0:f266ca250f98 673 if (collisionPos == 0)
Toby_Chen 0:f266ca250f98 674 {
Toby_Chen 0:f266ca250f98 675 collisionPos = 32;
Toby_Chen 0:f266ca250f98 676 }
Toby_Chen 0:f266ca250f98 677
Toby_Chen 0:f266ca250f98 678 if (collisionPos <= currentLevelKnownBits)
Toby_Chen 0:f266ca250f98 679 { // No progress - should not happen
Toby_Chen 0:f266ca250f98 680 return STATUS_INTERNAL_ERROR;
Toby_Chen 0:f266ca250f98 681 }
Toby_Chen 0:f266ca250f98 682
Toby_Chen 0:f266ca250f98 683 // Choose the PICC with the bit set.
Toby_Chen 0:f266ca250f98 684 currentLevelKnownBits = collisionPos;
Toby_Chen 0:f266ca250f98 685 count = (currentLevelKnownBits - 1) % 8; // The bit to modify
Toby_Chen 0:f266ca250f98 686 index = 1 + (currentLevelKnownBits / 8) + (count ? 1 : 0); // First byte is index 0.
Toby_Chen 0:f266ca250f98 687 buffer[index] |= (1 << count);
Toby_Chen 0:f266ca250f98 688 }
Toby_Chen 0:f266ca250f98 689 else if (result != STATUS_OK)
Toby_Chen 0:f266ca250f98 690 {
Toby_Chen 0:f266ca250f98 691 return result;
Toby_Chen 0:f266ca250f98 692 }
Toby_Chen 0:f266ca250f98 693 else
Toby_Chen 0:f266ca250f98 694 { // STATUS_OK
Toby_Chen 0:f266ca250f98 695 if (currentLevelKnownBits >= 32)
Toby_Chen 0:f266ca250f98 696 { // This was a SELECT.
Toby_Chen 0:f266ca250f98 697 selectDone = true; // No more anticollision
Toby_Chen 0:f266ca250f98 698 // We continue below outside the while.
Toby_Chen 0:f266ca250f98 699 }
Toby_Chen 0:f266ca250f98 700 else
Toby_Chen 0:f266ca250f98 701 { // This was an ANTICOLLISION.
Toby_Chen 0:f266ca250f98 702 // We now have all 32 bits of the UID in this Cascade Level
Toby_Chen 0:f266ca250f98 703 currentLevelKnownBits = 32;
Toby_Chen 0:f266ca250f98 704 // Run loop again to do the SELECT.
Toby_Chen 0:f266ca250f98 705 }
Toby_Chen 0:f266ca250f98 706 }
Toby_Chen 0:f266ca250f98 707 } // End of while ( ! selectDone)
Toby_Chen 0:f266ca250f98 708
Toby_Chen 0:f266ca250f98 709 // We do not check the CBB - it was constructed by us above.
Toby_Chen 0:f266ca250f98 710
Toby_Chen 0:f266ca250f98 711 // Copy the found UID bytes from buffer[] to uid->uidByte[]
Toby_Chen 0:f266ca250f98 712 index = (buffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[]
Toby_Chen 0:f266ca250f98 713 bytesToCopy = (buffer[2] == PICC_CMD_CT) ? 3 : 4;
Toby_Chen 0:f266ca250f98 714 for (count = 0; count < bytesToCopy; count++)
Toby_Chen 0:f266ca250f98 715 {
Toby_Chen 0:f266ca250f98 716 uid->uidByte[uidIndex + count] = buffer[index++];
Toby_Chen 0:f266ca250f98 717 }
Toby_Chen 0:f266ca250f98 718
Toby_Chen 0:f266ca250f98 719 // Check response SAK (Select Acknowledge)
Toby_Chen 0:f266ca250f98 720 if (responseLength != 3 || txLastBits != 0)
Toby_Chen 0:f266ca250f98 721 { // SAK must be exactly 24 bits (1 byte + CRC_A).
Toby_Chen 0:f266ca250f98 722 return STATUS_ERROR;
Toby_Chen 0:f266ca250f98 723 }
Toby_Chen 0:f266ca250f98 724
Toby_Chen 0:f266ca250f98 725 // Verify CRC_A - do our own calculation and store the control in buffer[2..3] - those bytes are not needed anymore.
Toby_Chen 0:f266ca250f98 726 result = PCD_CalculateCRC(responseBuffer, 1, &buffer[2]);
Toby_Chen 0:f266ca250f98 727 if (result != STATUS_OK)
Toby_Chen 0:f266ca250f98 728 {
Toby_Chen 0:f266ca250f98 729 return result;
Toby_Chen 0:f266ca250f98 730 }
Toby_Chen 0:f266ca250f98 731
Toby_Chen 0:f266ca250f98 732 if ((buffer[2] != responseBuffer[1]) || (buffer[3] != responseBuffer[2]))
Toby_Chen 0:f266ca250f98 733 {
Toby_Chen 0:f266ca250f98 734 return STATUS_CRC_WRONG;
Toby_Chen 0:f266ca250f98 735 }
Toby_Chen 0:f266ca250f98 736
Toby_Chen 0:f266ca250f98 737 if (responseBuffer[0] & 0x04)
Toby_Chen 0:f266ca250f98 738 { // Cascade bit set - UID not complete yes
Toby_Chen 0:f266ca250f98 739 cascadeLevel++;
Toby_Chen 0:f266ca250f98 740 }
Toby_Chen 0:f266ca250f98 741 else
Toby_Chen 0:f266ca250f98 742 {
Toby_Chen 0:f266ca250f98 743 uidComplete = true;
Toby_Chen 0:f266ca250f98 744 uid->sak = responseBuffer[0];
Toby_Chen 0:f266ca250f98 745 }
Toby_Chen 0:f266ca250f98 746 } // End of while ( ! uidComplete)
Toby_Chen 0:f266ca250f98 747
Toby_Chen 0:f266ca250f98 748 // Set correct uid->size
Toby_Chen 0:f266ca250f98 749 uid->size = 3 * cascadeLevel + 1;
Toby_Chen 0:f266ca250f98 750
Toby_Chen 0:f266ca250f98 751 return STATUS_OK;
Toby_Chen 0:f266ca250f98 752 } // End PICC_Select()
Toby_Chen 0:f266ca250f98 753
Toby_Chen 0:f266ca250f98 754 /*
Toby_Chen 0:f266ca250f98 755 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
Toby_Chen 0:f266ca250f98 756 */
Toby_Chen 0:f266ca250f98 757 uint8_t MFRC522::PICC_HaltA()
Toby_Chen 0:f266ca250f98 758 {
Toby_Chen 0:f266ca250f98 759 uint8_t result;
Toby_Chen 0:f266ca250f98 760 uint8_t buffer[4];
Toby_Chen 0:f266ca250f98 761
Toby_Chen 0:f266ca250f98 762 // Build command buffer
Toby_Chen 0:f266ca250f98 763 buffer[0] = PICC_CMD_HLTA;
Toby_Chen 0:f266ca250f98 764 buffer[1] = 0;
Toby_Chen 0:f266ca250f98 765
Toby_Chen 0:f266ca250f98 766 // Calculate CRC_A
Toby_Chen 0:f266ca250f98 767 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
Toby_Chen 0:f266ca250f98 768 if (result == STATUS_OK)
Toby_Chen 0:f266ca250f98 769 {
Toby_Chen 0:f266ca250f98 770 // Send the command.
Toby_Chen 0:f266ca250f98 771 // The standard says:
Toby_Chen 0:f266ca250f98 772 // If the PICC responds with any modulation during a period of 1 ms after the end of the frame containing the
Toby_Chen 0:f266ca250f98 773 // HLTA command, this response shall be interpreted as 'not acknowledge'.
Toby_Chen 0:f266ca250f98 774 // We interpret that this way: Only STATUS_TIMEOUT is an success.
Toby_Chen 0:f266ca250f98 775 result = PCD_TransceiveData(buffer, sizeof(buffer), NULL, 0);
Toby_Chen 0:f266ca250f98 776 if (result == STATUS_TIMEOUT)
Toby_Chen 0:f266ca250f98 777 {
Toby_Chen 0:f266ca250f98 778 result = STATUS_OK;
Toby_Chen 0:f266ca250f98 779 }
Toby_Chen 0:f266ca250f98 780 else if (result == STATUS_OK)
Toby_Chen 0:f266ca250f98 781 { // That is ironically NOT ok in this case ;-)
Toby_Chen 0:f266ca250f98 782 result = STATUS_ERROR;
Toby_Chen 0:f266ca250f98 783 }
Toby_Chen 0:f266ca250f98 784 }
Toby_Chen 0:f266ca250f98 785
Toby_Chen 0:f266ca250f98 786 return result;
Toby_Chen 0:f266ca250f98 787 } // End PICC_HaltA()
Toby_Chen 0:f266ca250f98 788
Toby_Chen 0:f266ca250f98 789
Toby_Chen 0:f266ca250f98 790 /////////////////////////////////////////////////////////////////////////////////////
Toby_Chen 0:f266ca250f98 791 // Functions for communicating with MIFARE PICCs
Toby_Chen 0:f266ca250f98 792 /////////////////////////////////////////////////////////////////////////////////////
Toby_Chen 0:f266ca250f98 793
Toby_Chen 0:f266ca250f98 794 /*
Toby_Chen 0:f266ca250f98 795 * Executes the MFRC522 MFAuthent command.
Toby_Chen 0:f266ca250f98 796 */
Toby_Chen 0:f266ca250f98 797 uint8_t MFRC522::PCD_Authenticate(uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid)
Toby_Chen 0:f266ca250f98 798 {
Toby_Chen 0:f266ca250f98 799 uint8_t i, waitIRq = 0x10; // IdleIRq
Toby_Chen 0:f266ca250f98 800
Toby_Chen 0:f266ca250f98 801 // Build command buffer
Toby_Chen 0:f266ca250f98 802 uint8_t sendData[12];
Toby_Chen 0:f266ca250f98 803 sendData[0] = command;
Toby_Chen 0:f266ca250f98 804 sendData[1] = blockAddr;
Toby_Chen 0:f266ca250f98 805
Toby_Chen 0:f266ca250f98 806 for (i = 0; i < MF_KEY_SIZE; i++)
Toby_Chen 0:f266ca250f98 807 { // 6 key bytes
Toby_Chen 0:f266ca250f98 808 sendData[2+i] = key->keyByte[i];
Toby_Chen 0:f266ca250f98 809 }
Toby_Chen 0:f266ca250f98 810
Toby_Chen 0:f266ca250f98 811 for (i = 0; i < 4; i++)
Toby_Chen 0:f266ca250f98 812 { // The first 4 bytes of the UID
Toby_Chen 0:f266ca250f98 813 sendData[8+i] = uid->uidByte[i];
Toby_Chen 0:f266ca250f98 814 }
Toby_Chen 0:f266ca250f98 815
Toby_Chen 0:f266ca250f98 816 // Start the authentication.
Toby_Chen 0:f266ca250f98 817 return PCD_CommunicateWithPICC(PCD_MFAuthent, waitIRq, &sendData[0], sizeof(sendData));
Toby_Chen 0:f266ca250f98 818 } // End PCD_Authenticate()
Toby_Chen 0:f266ca250f98 819
Toby_Chen 0:f266ca250f98 820 /*
Toby_Chen 0:f266ca250f98 821 * Used to exit the PCD from its authenticated state.
Toby_Chen 0:f266ca250f98 822 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
Toby_Chen 0:f266ca250f98 823 */
Toby_Chen 0:f266ca250f98 824 void MFRC522::PCD_StopCrypto1()
Toby_Chen 0:f266ca250f98 825 {
Toby_Chen 0:f266ca250f98 826 // Clear MFCrypto1On bit
Toby_Chen 0:f266ca250f98 827 PCD_ClrRegisterBits(Status2Reg, 0x08); // Status2Reg[7..0] bits are: TempSensClear I2CForceHS reserved reserved MFCrypto1On ModemState[2:0]
Toby_Chen 0:f266ca250f98 828 } // End PCD_StopCrypto1()
Toby_Chen 0:f266ca250f98 829
Toby_Chen 0:f266ca250f98 830 /*
Toby_Chen 0:f266ca250f98 831 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
Toby_Chen 0:f266ca250f98 832 */
Toby_Chen 0:f266ca250f98 833 uint8_t MFRC522::MIFARE_Read(uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize)
Toby_Chen 0:f266ca250f98 834 {
Toby_Chen 0:f266ca250f98 835 uint8_t result = STATUS_NO_ROOM;
Toby_Chen 0:f266ca250f98 836
Toby_Chen 0:f266ca250f98 837 // Sanity check
Toby_Chen 0:f266ca250f98 838 if ((buffer == NULL) || (*bufferSize < 18))
Toby_Chen 0:f266ca250f98 839 {
Toby_Chen 0:f266ca250f98 840 return result;
Toby_Chen 0:f266ca250f98 841 }
Toby_Chen 0:f266ca250f98 842
Toby_Chen 0:f266ca250f98 843 // Build command buffer
Toby_Chen 0:f266ca250f98 844 buffer[0] = PICC_CMD_MF_READ;
Toby_Chen 0:f266ca250f98 845 buffer[1] = blockAddr;
Toby_Chen 0:f266ca250f98 846
Toby_Chen 0:f266ca250f98 847 // Calculate CRC_A
Toby_Chen 0:f266ca250f98 848 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
Toby_Chen 0:f266ca250f98 849 if (result != STATUS_OK)
Toby_Chen 0:f266ca250f98 850 {
Toby_Chen 0:f266ca250f98 851 return result;
Toby_Chen 0:f266ca250f98 852 }
Toby_Chen 0:f266ca250f98 853
Toby_Chen 0:f266ca250f98 854 // Transmit the buffer and receive the response, validate CRC_A.
Toby_Chen 0:f266ca250f98 855 return PCD_TransceiveData(buffer, 4, buffer, bufferSize, NULL, 0, true);
Toby_Chen 0:f266ca250f98 856 } // End MIFARE_Read()
Toby_Chen 0:f266ca250f98 857
Toby_Chen 0:f266ca250f98 858 /*
Toby_Chen 0:f266ca250f98 859 * Writes 16 bytes to the active PICC.
Toby_Chen 0:f266ca250f98 860 */
Toby_Chen 0:f266ca250f98 861 uint8_t MFRC522::MIFARE_Write(uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize)
Toby_Chen 0:f266ca250f98 862 {
Toby_Chen 0:f266ca250f98 863 uint8_t result;
Toby_Chen 0:f266ca250f98 864
Toby_Chen 0:f266ca250f98 865 // Sanity check
Toby_Chen 0:f266ca250f98 866 if (buffer == NULL || bufferSize < 16)
Toby_Chen 0:f266ca250f98 867 {
Toby_Chen 0:f266ca250f98 868 return STATUS_INVALID;
Toby_Chen 0:f266ca250f98 869 }
Toby_Chen 0:f266ca250f98 870
Toby_Chen 0:f266ca250f98 871 // Mifare Classic protocol requires two communications to perform a write.
Toby_Chen 0:f266ca250f98 872 // Step 1: Tell the PICC we want to write to block blockAddr.
Toby_Chen 0:f266ca250f98 873 uint8_t cmdBuffer[2];
Toby_Chen 0:f266ca250f98 874 cmdBuffer[0] = PICC_CMD_MF_WRITE;
Toby_Chen 0:f266ca250f98 875 cmdBuffer[1] = blockAddr;
Toby_Chen 0:f266ca250f98 876 // Adds CRC_A and checks that the response is MF_ACK.
Toby_Chen 0:f266ca250f98 877 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
Toby_Chen 0:f266ca250f98 878 if (result != STATUS_OK)
Toby_Chen 0:f266ca250f98 879 {
Toby_Chen 0:f266ca250f98 880 return result;
Toby_Chen 0:f266ca250f98 881 }
Toby_Chen 0:f266ca250f98 882
Toby_Chen 0:f266ca250f98 883 // Step 2: Transfer the data
Toby_Chen 0:f266ca250f98 884 // Adds CRC_A and checks that the response is MF_ACK.
Toby_Chen 0:f266ca250f98 885 result = PCD_MIFARE_Transceive(buffer, bufferSize);
Toby_Chen 0:f266ca250f98 886 if (result != STATUS_OK)
Toby_Chen 0:f266ca250f98 887 {
Toby_Chen 0:f266ca250f98 888 return result;
Toby_Chen 0:f266ca250f98 889 }
Toby_Chen 0:f266ca250f98 890
Toby_Chen 0:f266ca250f98 891 return STATUS_OK;
Toby_Chen 0:f266ca250f98 892 } // End MIFARE_Write()
Toby_Chen 0:f266ca250f98 893
Toby_Chen 0:f266ca250f98 894 /*
Toby_Chen 0:f266ca250f98 895 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
Toby_Chen 0:f266ca250f98 896 */
Toby_Chen 0:f266ca250f98 897 uint8_t MFRC522::MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize)
Toby_Chen 0:f266ca250f98 898 {
Toby_Chen 0:f266ca250f98 899 uint8_t result;
Toby_Chen 0:f266ca250f98 900
Toby_Chen 0:f266ca250f98 901 // Sanity check
Toby_Chen 0:f266ca250f98 902 if (buffer == NULL || bufferSize < 4)
Toby_Chen 0:f266ca250f98 903 {
Toby_Chen 0:f266ca250f98 904 return STATUS_INVALID;
Toby_Chen 0:f266ca250f98 905 }
Toby_Chen 0:f266ca250f98 906
Toby_Chen 0:f266ca250f98 907 // Build commmand buffer
Toby_Chen 0:f266ca250f98 908 uint8_t cmdBuffer[6];
Toby_Chen 0:f266ca250f98 909 cmdBuffer[0] = PICC_CMD_UL_WRITE;
Toby_Chen 0:f266ca250f98 910 cmdBuffer[1] = page;
Toby_Chen 0:f266ca250f98 911 memcpy(&cmdBuffer[2], buffer, 4);
Toby_Chen 0:f266ca250f98 912
Toby_Chen 0:f266ca250f98 913 // Perform the write
Toby_Chen 0:f266ca250f98 914 result = PCD_MIFARE_Transceive(cmdBuffer, 6); // Adds CRC_A and checks that the response is MF_ACK.
Toby_Chen 0:f266ca250f98 915 if (result != STATUS_OK)
Toby_Chen 0:f266ca250f98 916 {
Toby_Chen 0:f266ca250f98 917 return result;
Toby_Chen 0:f266ca250f98 918 }
Toby_Chen 0:f266ca250f98 919
Toby_Chen 0:f266ca250f98 920 return STATUS_OK;
Toby_Chen 0:f266ca250f98 921 } // End MIFARE_Ultralight_Write()
Toby_Chen 0:f266ca250f98 922
Toby_Chen 0:f266ca250f98 923 /*
Toby_Chen 0:f266ca250f98 924 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
Toby_Chen 0:f266ca250f98 925 */
Toby_Chen 0:f266ca250f98 926 uint8_t MFRC522::MIFARE_Decrement(uint8_t blockAddr, uint32_t delta)
Toby_Chen 0:f266ca250f98 927 {
Toby_Chen 0:f266ca250f98 928 return MIFARE_TwoStepHelper(PICC_CMD_MF_DECREMENT, blockAddr, delta);
Toby_Chen 0:f266ca250f98 929 } // End MIFARE_Decrement()
Toby_Chen 0:f266ca250f98 930
Toby_Chen 0:f266ca250f98 931 /*
Toby_Chen 0:f266ca250f98 932 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
Toby_Chen 0:f266ca250f98 933 */
Toby_Chen 0:f266ca250f98 934 uint8_t MFRC522::MIFARE_Increment(uint8_t blockAddr, uint32_t delta)
Toby_Chen 0:f266ca250f98 935 {
Toby_Chen 0:f266ca250f98 936 return MIFARE_TwoStepHelper(PICC_CMD_MF_INCREMENT, blockAddr, delta);
Toby_Chen 0:f266ca250f98 937 } // End MIFARE_Increment()
Toby_Chen 0:f266ca250f98 938
Toby_Chen 0:f266ca250f98 939 /**
Toby_Chen 0:f266ca250f98 940 * MIFARE Restore copies the value of the addressed block into a volatile memory.
Toby_Chen 0:f266ca250f98 941 */
Toby_Chen 0:f266ca250f98 942 uint8_t MFRC522::MIFARE_Restore(uint8_t blockAddr)
Toby_Chen 0:f266ca250f98 943 {
Toby_Chen 0:f266ca250f98 944 // The datasheet describes Restore as a two step operation, but does not explain what data to transfer in step 2.
Toby_Chen 0:f266ca250f98 945 // Doing only a single step does not work, so I chose to transfer 0L in step two.
Toby_Chen 0:f266ca250f98 946 return MIFARE_TwoStepHelper(PICC_CMD_MF_RESTORE, blockAddr, 0L);
Toby_Chen 0:f266ca250f98 947 } // End MIFARE_Restore()
Toby_Chen 0:f266ca250f98 948
Toby_Chen 0:f266ca250f98 949 /*
Toby_Chen 0:f266ca250f98 950 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
Toby_Chen 0:f266ca250f98 951 */
Toby_Chen 0:f266ca250f98 952 uint8_t MFRC522::MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data)
Toby_Chen 0:f266ca250f98 953 {
Toby_Chen 0:f266ca250f98 954 uint8_t result;
Toby_Chen 0:f266ca250f98 955 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
Toby_Chen 0:f266ca250f98 956
Toby_Chen 0:f266ca250f98 957 // Step 1: Tell the PICC the command and block address
Toby_Chen 0:f266ca250f98 958 cmdBuffer[0] = command;
Toby_Chen 0:f266ca250f98 959 cmdBuffer[1] = blockAddr;
Toby_Chen 0:f266ca250f98 960
Toby_Chen 0:f266ca250f98 961 // Adds CRC_A and checks that the response is MF_ACK.
Toby_Chen 0:f266ca250f98 962 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
Toby_Chen 0:f266ca250f98 963 if (result != STATUS_OK)
Toby_Chen 0:f266ca250f98 964 {
Toby_Chen 0:f266ca250f98 965 return result;
Toby_Chen 0:f266ca250f98 966 }
Toby_Chen 0:f266ca250f98 967
Toby_Chen 0:f266ca250f98 968 // Step 2: Transfer the data
Toby_Chen 0:f266ca250f98 969 // Adds CRC_A and accept timeout as success.
Toby_Chen 0:f266ca250f98 970 result = PCD_MIFARE_Transceive((uint8_t *) &data, 4, true);
Toby_Chen 0:f266ca250f98 971 if (result != STATUS_OK)
Toby_Chen 0:f266ca250f98 972 {
Toby_Chen 0:f266ca250f98 973 return result;
Toby_Chen 0:f266ca250f98 974 }
Toby_Chen 0:f266ca250f98 975
Toby_Chen 0:f266ca250f98 976 return STATUS_OK;
Toby_Chen 0:f266ca250f98 977 } // End MIFARE_TwoStepHelper()
Toby_Chen 0:f266ca250f98 978
Toby_Chen 0:f266ca250f98 979 /*
Toby_Chen 0:f266ca250f98 980 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
Toby_Chen 0:f266ca250f98 981 */
Toby_Chen 0:f266ca250f98 982 uint8_t MFRC522::MIFARE_Transfer(uint8_t blockAddr)
Toby_Chen 0:f266ca250f98 983 {
Toby_Chen 0:f266ca250f98 984 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
Toby_Chen 0:f266ca250f98 985
Toby_Chen 0:f266ca250f98 986 // Tell the PICC we want to transfer the result into block blockAddr.
Toby_Chen 0:f266ca250f98 987 cmdBuffer[0] = PICC_CMD_MF_TRANSFER;
Toby_Chen 0:f266ca250f98 988 cmdBuffer[1] = blockAddr;
Toby_Chen 0:f266ca250f98 989
Toby_Chen 0:f266ca250f98 990 // Adds CRC_A and checks that the response is MF_ACK.
Toby_Chen 0:f266ca250f98 991 return PCD_MIFARE_Transceive(cmdBuffer, 2);
Toby_Chen 0:f266ca250f98 992 } // End MIFARE_Transfer()
Toby_Chen 0:f266ca250f98 993
Toby_Chen 0:f266ca250f98 994
Toby_Chen 0:f266ca250f98 995 /////////////////////////////////////////////////////////////////////////////////////
Toby_Chen 0:f266ca250f98 996 // Support functions
Toby_Chen 0:f266ca250f98 997 /////////////////////////////////////////////////////////////////////////////////////
Toby_Chen 0:f266ca250f98 998
Toby_Chen 0:f266ca250f98 999 /*
Toby_Chen 0:f266ca250f98 1000 * Wrapper for MIFARE protocol communication.
Toby_Chen 0:f266ca250f98 1001 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
Toby_Chen 0:f266ca250f98 1002 */
Toby_Chen 0:f266ca250f98 1003 uint8_t MFRC522::PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout)
Toby_Chen 0:f266ca250f98 1004 {
Toby_Chen 0:f266ca250f98 1005 uint8_t result;
Toby_Chen 0:f266ca250f98 1006 uint8_t cmdBuffer[18]; // We need room for 16 bytes data and 2 bytes CRC_A.
Toby_Chen 0:f266ca250f98 1007
Toby_Chen 0:f266ca250f98 1008 // Sanity check
Toby_Chen 0:f266ca250f98 1009 if (sendData == NULL || sendLen > 16)
Toby_Chen 0:f266ca250f98 1010 {
Toby_Chen 0:f266ca250f98 1011 return STATUS_INVALID;
Toby_Chen 0:f266ca250f98 1012 }
Toby_Chen 0:f266ca250f98 1013
Toby_Chen 0:f266ca250f98 1014 // Copy sendData[] to cmdBuffer[] and add CRC_A
Toby_Chen 0:f266ca250f98 1015 memcpy(cmdBuffer, sendData, sendLen);
Toby_Chen 0:f266ca250f98 1016 result = PCD_CalculateCRC(cmdBuffer, sendLen, &cmdBuffer[sendLen]);
Toby_Chen 0:f266ca250f98 1017 if (result != STATUS_OK)
Toby_Chen 0:f266ca250f98 1018 {
Toby_Chen 0:f266ca250f98 1019 return result;
Toby_Chen 0:f266ca250f98 1020 }
Toby_Chen 0:f266ca250f98 1021
Toby_Chen 0:f266ca250f98 1022 sendLen += 2;
Toby_Chen 0:f266ca250f98 1023
Toby_Chen 0:f266ca250f98 1024 // Transceive the data, store the reply in cmdBuffer[]
Toby_Chen 0:f266ca250f98 1025 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
Toby_Chen 0:f266ca250f98 1026 uint8_t cmdBufferSize = sizeof(cmdBuffer);
Toby_Chen 0:f266ca250f98 1027 uint8_t validBits = 0;
Toby_Chen 0:f266ca250f98 1028 result = PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, cmdBuffer, sendLen, cmdBuffer, &cmdBufferSize, &validBits);
Toby_Chen 0:f266ca250f98 1029 if (acceptTimeout && result == STATUS_TIMEOUT)
Toby_Chen 0:f266ca250f98 1030 {
Toby_Chen 0:f266ca250f98 1031 return STATUS_OK;
Toby_Chen 0:f266ca250f98 1032 }
Toby_Chen 0:f266ca250f98 1033
Toby_Chen 0:f266ca250f98 1034 if (result != STATUS_OK)
Toby_Chen 0:f266ca250f98 1035 {
Toby_Chen 0:f266ca250f98 1036 return result;
Toby_Chen 0:f266ca250f98 1037 }
Toby_Chen 0:f266ca250f98 1038
Toby_Chen 0:f266ca250f98 1039 // The PICC must reply with a 4 bit ACK
Toby_Chen 0:f266ca250f98 1040 if (cmdBufferSize != 1 || validBits != 4)
Toby_Chen 0:f266ca250f98 1041 {
Toby_Chen 0:f266ca250f98 1042 return STATUS_ERROR;
Toby_Chen 0:f266ca250f98 1043 }
Toby_Chen 0:f266ca250f98 1044
Toby_Chen 0:f266ca250f98 1045 if (cmdBuffer[0] != MF_ACK)
Toby_Chen 0:f266ca250f98 1046 {
Toby_Chen 0:f266ca250f98 1047 return STATUS_MIFARE_NACK;
Toby_Chen 0:f266ca250f98 1048 }
Toby_Chen 0:f266ca250f98 1049
Toby_Chen 0:f266ca250f98 1050 return STATUS_OK;
Toby_Chen 0:f266ca250f98 1051 } // End PCD_MIFARE_Transceive()
Toby_Chen 0:f266ca250f98 1052
Toby_Chen 0:f266ca250f98 1053
Toby_Chen 0:f266ca250f98 1054 /*
Toby_Chen 0:f266ca250f98 1055 * Translates the SAK (Select Acknowledge) to a PICC type.
Toby_Chen 0:f266ca250f98 1056 */
Toby_Chen 0:f266ca250f98 1057 uint8_t MFRC522::PICC_GetType(uint8_t sak)
Toby_Chen 0:f266ca250f98 1058 {
Toby_Chen 0:f266ca250f98 1059 uint8_t retType = PICC_TYPE_UNKNOWN;
Toby_Chen 0:f266ca250f98 1060
Toby_Chen 0:f266ca250f98 1061 if (sak & 0x04)
Toby_Chen 0:f266ca250f98 1062 { // UID not complete
Toby_Chen 0:f266ca250f98 1063 retType = PICC_TYPE_NOT_COMPLETE;
Toby_Chen 0:f266ca250f98 1064 }
Toby_Chen 0:f266ca250f98 1065 else
Toby_Chen 0:f266ca250f98 1066 {
Toby_Chen 0:f266ca250f98 1067 switch (sak)
Toby_Chen 0:f266ca250f98 1068 {
Toby_Chen 0:f266ca250f98 1069 case 0x09: retType = PICC_TYPE_MIFARE_MINI; break;
Toby_Chen 0:f266ca250f98 1070 case 0x08: retType = PICC_TYPE_MIFARE_1K; break;
Toby_Chen 0:f266ca250f98 1071 case 0x18: retType = PICC_TYPE_MIFARE_4K; break;
Toby_Chen 0:f266ca250f98 1072 case 0x00: retType = PICC_TYPE_MIFARE_UL; break;
Toby_Chen 0:f266ca250f98 1073 case 0x10:
Toby_Chen 0:f266ca250f98 1074 case 0x11: retType = PICC_TYPE_MIFARE_PLUS; break;
Toby_Chen 0:f266ca250f98 1075 case 0x01: retType = PICC_TYPE_TNP3XXX; break;
Toby_Chen 0:f266ca250f98 1076 default:
Toby_Chen 0:f266ca250f98 1077 if (sak & 0x20)
Toby_Chen 0:f266ca250f98 1078 {
Toby_Chen 0:f266ca250f98 1079 retType = PICC_TYPE_ISO_14443_4;
Toby_Chen 0:f266ca250f98 1080 }
Toby_Chen 0:f266ca250f98 1081 else if (sak & 0x40)
Toby_Chen 0:f266ca250f98 1082 {
Toby_Chen 0:f266ca250f98 1083 retType = PICC_TYPE_ISO_18092;
Toby_Chen 0:f266ca250f98 1084 }
Toby_Chen 0:f266ca250f98 1085 break;
Toby_Chen 0:f266ca250f98 1086 }
Toby_Chen 0:f266ca250f98 1087 }
Toby_Chen 0:f266ca250f98 1088
Toby_Chen 0:f266ca250f98 1089 return (retType);
Toby_Chen 0:f266ca250f98 1090 } // End PICC_GetType()
Toby_Chen 0:f266ca250f98 1091
Toby_Chen 0:f266ca250f98 1092 /*
Toby_Chen 0:f266ca250f98 1093 * Returns a string pointer to the PICC type name.
Toby_Chen 0:f266ca250f98 1094 */
Toby_Chen 0:f266ca250f98 1095 char* MFRC522::PICC_GetTypeName(uint8_t piccType)
Toby_Chen 0:f266ca250f98 1096 {
Toby_Chen 0:f266ca250f98 1097 if(piccType == PICC_TYPE_NOT_COMPLETE)
Toby_Chen 0:f266ca250f98 1098 {
Toby_Chen 0:f266ca250f98 1099 piccType = MFRC522_MaxPICCs - 1;
Toby_Chen 0:f266ca250f98 1100 }
Toby_Chen 0:f266ca250f98 1101
Toby_Chen 0:f266ca250f98 1102 return((char *) _TypeNamePICC[piccType]);
Toby_Chen 0:f266ca250f98 1103 } // End PICC_GetTypeName()
Toby_Chen 0:f266ca250f98 1104
Toby_Chen 0:f266ca250f98 1105 /*
Toby_Chen 0:f266ca250f98 1106 * Returns a string pointer to a status code name.
Toby_Chen 0:f266ca250f98 1107 */
Toby_Chen 0:f266ca250f98 1108 char* MFRC522::GetStatusCodeName(uint8_t code)
Toby_Chen 0:f266ca250f98 1109 {
Toby_Chen 0:f266ca250f98 1110 return((char *) _ErrorMessage[code]);
Toby_Chen 0:f266ca250f98 1111 } // End GetStatusCodeName()
Toby_Chen 0:f266ca250f98 1112
Toby_Chen 0:f266ca250f98 1113 /*
Toby_Chen 0:f266ca250f98 1114 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
Toby_Chen 0:f266ca250f98 1115 */
Toby_Chen 0:f266ca250f98 1116 void MFRC522::MIFARE_SetAccessBits(uint8_t *accessBitBuffer,
Toby_Chen 0:f266ca250f98 1117 uint8_t g0,
Toby_Chen 0:f266ca250f98 1118 uint8_t g1,
Toby_Chen 0:f266ca250f98 1119 uint8_t g2,
Toby_Chen 0:f266ca250f98 1120 uint8_t g3)
Toby_Chen 0:f266ca250f98 1121 {
Toby_Chen 0:f266ca250f98 1122 uint8_t c1 = ((g3 & 4) << 1) | ((g2 & 4) << 0) | ((g1 & 4) >> 1) | ((g0 & 4) >> 2);
Toby_Chen 0:f266ca250f98 1123 uint8_t c2 = ((g3 & 2) << 2) | ((g2 & 2) << 1) | ((g1 & 2) << 0) | ((g0 & 2) >> 1);
Toby_Chen 0:f266ca250f98 1124 uint8_t c3 = ((g3 & 1) << 3) | ((g2 & 1) << 2) | ((g1 & 1) << 1) | ((g0 & 1) << 0);
Toby_Chen 0:f266ca250f98 1125
Toby_Chen 0:f266ca250f98 1126 accessBitBuffer[0] = (~c2 & 0xF) << 4 | (~c1 & 0xF);
Toby_Chen 0:f266ca250f98 1127 accessBitBuffer[1] = c1 << 4 | (~c3 & 0xF);
Toby_Chen 0:f266ca250f98 1128 accessBitBuffer[2] = c3 << 4 | c2;
Toby_Chen 0:f266ca250f98 1129 } // End MIFARE_SetAccessBits()
Toby_Chen 0:f266ca250f98 1130
Toby_Chen 0:f266ca250f98 1131 /////////////////////////////////////////////////////////////////////////////////////
Toby_Chen 0:f266ca250f98 1132 // Convenience functions - does not add extra functionality
Toby_Chen 0:f266ca250f98 1133 /////////////////////////////////////////////////////////////////////////////////////
Toby_Chen 0:f266ca250f98 1134
Toby_Chen 0:f266ca250f98 1135 /*
Toby_Chen 0:f266ca250f98 1136 * Returns true if a PICC responds to PICC_CMD_REQA.
Toby_Chen 0:f266ca250f98 1137 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
Toby_Chen 0:f266ca250f98 1138 */
Toby_Chen 0:f266ca250f98 1139 bool MFRC522::PICC_IsNewCardPresent(void)
Toby_Chen 0:f266ca250f98 1140 {
Toby_Chen 0:f266ca250f98 1141 uint8_t bufferATQA[2];
Toby_Chen 0:f266ca250f98 1142 uint8_t bufferSize = sizeof(bufferATQA);
Toby_Chen 0:f266ca250f98 1143 uint8_t result = PICC_RequestA(bufferATQA, &bufferSize);
Toby_Chen 0:f266ca250f98 1144 return ((result == STATUS_OK) || (result == STATUS_COLLISION));
Toby_Chen 0:f266ca250f98 1145 } // End PICC_IsNewCardPresent()
Toby_Chen 0:f266ca250f98 1146
Toby_Chen 0:f266ca250f98 1147 /*
Toby_Chen 0:f266ca250f98 1148 * Simple wrapper around PICC_Select.
Toby_Chen 0:f266ca250f98 1149 */
Toby_Chen 0:f266ca250f98 1150 bool MFRC522::PICC_ReadCardSerial(void)
Toby_Chen 0:f266ca250f98 1151 {
Toby_Chen 0:f266ca250f98 1152 uint8_t result = PICC_Select(&uid);
Toby_Chen 0:f266ca250f98 1153 return (result == STATUS_OK);
Toby_Chen 0:f266ca250f98 1154 } // End PICC_ReadCardSerial()