Additional font macro
Components/stmpe811/stmpe811.c@1:a6fd0931a9e9, 2016-02-05 (annotated)
- Committer:
- SomeRandomBloke
- Date:
- Fri Feb 05 09:20:30 2016 +0000
- Revision:
- 1:a6fd0931a9e9
- Parent:
- 0:e1d164542663
Added additional font macro
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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bcostm | 0:e1d164542663 | 1 | /** |
bcostm | 0:e1d164542663 | 2 | ****************************************************************************** |
bcostm | 0:e1d164542663 | 3 | * @file stmpe811.c |
bcostm | 0:e1d164542663 | 4 | * @author MCD Application Team |
bcostm | 0:e1d164542663 | 5 | * @version V2.0.0 |
bcostm | 0:e1d164542663 | 6 | * @date 15-December-2014 |
bcostm | 0:e1d164542663 | 7 | * @brief This file provides a set of functions needed to manage the STMPE811 |
bcostm | 0:e1d164542663 | 8 | * IO Expander devices. |
bcostm | 0:e1d164542663 | 9 | ****************************************************************************** |
bcostm | 0:e1d164542663 | 10 | * @attention |
bcostm | 0:e1d164542663 | 11 | * |
bcostm | 0:e1d164542663 | 12 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
bcostm | 0:e1d164542663 | 13 | * |
bcostm | 0:e1d164542663 | 14 | * Redistribution and use in source and binary forms, with or without modification, |
bcostm | 0:e1d164542663 | 15 | * are permitted provided that the following conditions are met: |
bcostm | 0:e1d164542663 | 16 | * 1. Redistributions of source code must retain the above copyright notice, |
bcostm | 0:e1d164542663 | 17 | * this list of conditions and the following disclaimer. |
bcostm | 0:e1d164542663 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
bcostm | 0:e1d164542663 | 19 | * this list of conditions and the following disclaimer in the documentation |
bcostm | 0:e1d164542663 | 20 | * and/or other materials provided with the distribution. |
bcostm | 0:e1d164542663 | 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
bcostm | 0:e1d164542663 | 22 | * may be used to endorse or promote products derived from this software |
bcostm | 0:e1d164542663 | 23 | * without specific prior written permission. |
bcostm | 0:e1d164542663 | 24 | * |
bcostm | 0:e1d164542663 | 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
bcostm | 0:e1d164542663 | 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
bcostm | 0:e1d164542663 | 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
bcostm | 0:e1d164542663 | 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
bcostm | 0:e1d164542663 | 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
bcostm | 0:e1d164542663 | 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
bcostm | 0:e1d164542663 | 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
bcostm | 0:e1d164542663 | 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
bcostm | 0:e1d164542663 | 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
bcostm | 0:e1d164542663 | 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
bcostm | 0:e1d164542663 | 35 | * |
bcostm | 0:e1d164542663 | 36 | ****************************************************************************** |
bcostm | 0:e1d164542663 | 37 | */ |
bcostm | 0:e1d164542663 | 38 | |
bcostm | 0:e1d164542663 | 39 | /* Includes ------------------------------------------------------------------*/ |
bcostm | 0:e1d164542663 | 40 | #include "stmpe811.h" |
bcostm | 0:e1d164542663 | 41 | |
bcostm | 0:e1d164542663 | 42 | /** @addtogroup BSP |
bcostm | 0:e1d164542663 | 43 | * @{ |
bcostm | 0:e1d164542663 | 44 | */ |
bcostm | 0:e1d164542663 | 45 | |
bcostm | 0:e1d164542663 | 46 | /** @addtogroup Components |
bcostm | 0:e1d164542663 | 47 | * @{ |
bcostm | 0:e1d164542663 | 48 | */ |
bcostm | 0:e1d164542663 | 49 | |
bcostm | 0:e1d164542663 | 50 | /** @defgroup STMPE811 |
bcostm | 0:e1d164542663 | 51 | * @{ |
bcostm | 0:e1d164542663 | 52 | */ |
bcostm | 0:e1d164542663 | 53 | |
bcostm | 0:e1d164542663 | 54 | /** @defgroup STMPE811_Private_Types_Definitions |
bcostm | 0:e1d164542663 | 55 | * @{ |
bcostm | 0:e1d164542663 | 56 | */ |
bcostm | 0:e1d164542663 | 57 | |
bcostm | 0:e1d164542663 | 58 | /** @defgroup STMPE811_Private_Defines |
bcostm | 0:e1d164542663 | 59 | * @{ |
bcostm | 0:e1d164542663 | 60 | */ |
bcostm | 0:e1d164542663 | 61 | #define STMPE811_MAX_INSTANCE 2 |
bcostm | 0:e1d164542663 | 62 | /** |
bcostm | 0:e1d164542663 | 63 | * @} |
bcostm | 0:e1d164542663 | 64 | */ |
bcostm | 0:e1d164542663 | 65 | |
bcostm | 0:e1d164542663 | 66 | /** @defgroup STMPE811_Private_Macros |
bcostm | 0:e1d164542663 | 67 | * @{ |
bcostm | 0:e1d164542663 | 68 | */ |
bcostm | 0:e1d164542663 | 69 | /** |
bcostm | 0:e1d164542663 | 70 | * @} |
bcostm | 0:e1d164542663 | 71 | */ |
bcostm | 0:e1d164542663 | 72 | |
bcostm | 0:e1d164542663 | 73 | /** @defgroup STMPE811_Private_Variables |
bcostm | 0:e1d164542663 | 74 | * @{ |
bcostm | 0:e1d164542663 | 75 | */ |
bcostm | 0:e1d164542663 | 76 | |
bcostm | 0:e1d164542663 | 77 | /* Touch screen driver structure initialization */ |
bcostm | 0:e1d164542663 | 78 | TS_DrvTypeDef stmpe811_ts_drv = |
bcostm | 0:e1d164542663 | 79 | { |
bcostm | 0:e1d164542663 | 80 | stmpe811_Init, |
bcostm | 0:e1d164542663 | 81 | stmpe811_ReadID, |
bcostm | 0:e1d164542663 | 82 | stmpe811_Reset, |
bcostm | 0:e1d164542663 | 83 | stmpe811_TS_Start, |
bcostm | 0:e1d164542663 | 84 | stmpe811_TS_DetectTouch, |
bcostm | 0:e1d164542663 | 85 | stmpe811_TS_GetXY, |
bcostm | 0:e1d164542663 | 86 | stmpe811_TS_EnableIT, |
bcostm | 0:e1d164542663 | 87 | stmpe811_TS_ClearIT, |
bcostm | 0:e1d164542663 | 88 | stmpe811_TS_ITStatus, |
bcostm | 0:e1d164542663 | 89 | stmpe811_TS_DisableIT, |
bcostm | 0:e1d164542663 | 90 | }; |
bcostm | 0:e1d164542663 | 91 | |
bcostm | 0:e1d164542663 | 92 | /* IO driver structure initialization */ |
bcostm | 0:e1d164542663 | 93 | IO_DrvTypeDef stmpe811_io_drv = |
bcostm | 0:e1d164542663 | 94 | { |
bcostm | 0:e1d164542663 | 95 | stmpe811_Init, |
bcostm | 0:e1d164542663 | 96 | stmpe811_ReadID, |
bcostm | 0:e1d164542663 | 97 | stmpe811_Reset, |
bcostm | 0:e1d164542663 | 98 | stmpe811_IO_Start, |
bcostm | 0:e1d164542663 | 99 | stmpe811_IO_Config, |
bcostm | 0:e1d164542663 | 100 | stmpe811_IO_WritePin, |
bcostm | 0:e1d164542663 | 101 | stmpe811_IO_ReadPin, |
bcostm | 0:e1d164542663 | 102 | stmpe811_IO_EnableIT, |
bcostm | 0:e1d164542663 | 103 | stmpe811_IO_DisableIT, |
bcostm | 0:e1d164542663 | 104 | stmpe811_IO_ITStatus, |
bcostm | 0:e1d164542663 | 105 | stmpe811_IO_ClearIT, |
bcostm | 0:e1d164542663 | 106 | }; |
bcostm | 0:e1d164542663 | 107 | |
bcostm | 0:e1d164542663 | 108 | /* stmpe811 instances by address */ |
bcostm | 0:e1d164542663 | 109 | uint8_t stmpe811[STMPE811_MAX_INSTANCE] = {0}; |
bcostm | 0:e1d164542663 | 110 | /** |
bcostm | 0:e1d164542663 | 111 | * @} |
bcostm | 0:e1d164542663 | 112 | */ |
bcostm | 0:e1d164542663 | 113 | |
bcostm | 0:e1d164542663 | 114 | /** @defgroup STMPE811_Private_Function_Prototypes |
bcostm | 0:e1d164542663 | 115 | * @{ |
bcostm | 0:e1d164542663 | 116 | */ |
bcostm | 0:e1d164542663 | 117 | static uint8_t stmpe811_GetInstance(uint16_t DeviceAddr); |
bcostm | 0:e1d164542663 | 118 | /** |
bcostm | 0:e1d164542663 | 119 | * @} |
bcostm | 0:e1d164542663 | 120 | */ |
bcostm | 0:e1d164542663 | 121 | |
bcostm | 0:e1d164542663 | 122 | /** @defgroup STMPE811_Private_Functions |
bcostm | 0:e1d164542663 | 123 | * @{ |
bcostm | 0:e1d164542663 | 124 | */ |
bcostm | 0:e1d164542663 | 125 | |
bcostm | 0:e1d164542663 | 126 | /** |
bcostm | 0:e1d164542663 | 127 | * @brief Initialize the stmpe811 and configure the needed hardware resources |
bcostm | 0:e1d164542663 | 128 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 129 | * @retval None |
bcostm | 0:e1d164542663 | 130 | */ |
bcostm | 0:e1d164542663 | 131 | void stmpe811_Init(uint16_t DeviceAddr) |
bcostm | 0:e1d164542663 | 132 | { |
bcostm | 0:e1d164542663 | 133 | uint8_t instance; |
bcostm | 0:e1d164542663 | 134 | uint8_t empty; |
bcostm | 0:e1d164542663 | 135 | |
bcostm | 0:e1d164542663 | 136 | /* Check if device instance already exists */ |
bcostm | 0:e1d164542663 | 137 | instance = stmpe811_GetInstance(DeviceAddr); |
bcostm | 0:e1d164542663 | 138 | |
bcostm | 0:e1d164542663 | 139 | /* To prevent double initialization */ |
bcostm | 0:e1d164542663 | 140 | if(instance == 0xFF) |
bcostm | 0:e1d164542663 | 141 | { |
bcostm | 0:e1d164542663 | 142 | /* Look for empty instance */ |
bcostm | 0:e1d164542663 | 143 | empty = stmpe811_GetInstance(0); |
bcostm | 0:e1d164542663 | 144 | |
bcostm | 0:e1d164542663 | 145 | if(empty < STMPE811_MAX_INSTANCE) |
bcostm | 0:e1d164542663 | 146 | { |
bcostm | 0:e1d164542663 | 147 | /* Register the current device instance */ |
bcostm | 0:e1d164542663 | 148 | stmpe811[empty] = DeviceAddr; |
bcostm | 0:e1d164542663 | 149 | |
bcostm | 0:e1d164542663 | 150 | /* Initialize IO BUS layer */ |
bcostm | 0:e1d164542663 | 151 | IOE_Init(); |
bcostm | 0:e1d164542663 | 152 | |
bcostm | 0:e1d164542663 | 153 | /* Generate stmpe811 Software reset */ |
bcostm | 0:e1d164542663 | 154 | stmpe811_Reset(DeviceAddr); |
bcostm | 0:e1d164542663 | 155 | } |
bcostm | 0:e1d164542663 | 156 | } |
bcostm | 0:e1d164542663 | 157 | } |
bcostm | 0:e1d164542663 | 158 | |
bcostm | 0:e1d164542663 | 159 | /** |
bcostm | 0:e1d164542663 | 160 | * @brief Reset the stmpe811 by Software. |
bcostm | 0:e1d164542663 | 161 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 162 | * @retval None |
bcostm | 0:e1d164542663 | 163 | */ |
bcostm | 0:e1d164542663 | 164 | void stmpe811_Reset(uint16_t DeviceAddr) |
bcostm | 0:e1d164542663 | 165 | { |
bcostm | 0:e1d164542663 | 166 | /* Power Down the stmpe811 */ |
bcostm | 0:e1d164542663 | 167 | IOE_Write(DeviceAddr, STMPE811_REG_SYS_CTRL1, 2); |
bcostm | 0:e1d164542663 | 168 | |
bcostm | 0:e1d164542663 | 169 | /* Wait for a delay to ensure registers erasing */ |
bcostm | 0:e1d164542663 | 170 | IOE_Delay(10); |
bcostm | 0:e1d164542663 | 171 | |
bcostm | 0:e1d164542663 | 172 | /* Power On the Codec after the power off => all registers are reinitialized */ |
bcostm | 0:e1d164542663 | 173 | IOE_Write(DeviceAddr, STMPE811_REG_SYS_CTRL1, 0); |
bcostm | 0:e1d164542663 | 174 | |
bcostm | 0:e1d164542663 | 175 | /* Wait for a delay to ensure registers erasing */ |
bcostm | 0:e1d164542663 | 176 | IOE_Delay(2); |
bcostm | 0:e1d164542663 | 177 | } |
bcostm | 0:e1d164542663 | 178 | |
bcostm | 0:e1d164542663 | 179 | /** |
bcostm | 0:e1d164542663 | 180 | * @brief Read the stmpe811 IO Expander device ID. |
bcostm | 0:e1d164542663 | 181 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 182 | * @retval The Device ID (two bytes). |
bcostm | 0:e1d164542663 | 183 | */ |
bcostm | 0:e1d164542663 | 184 | uint16_t stmpe811_ReadID(uint16_t DeviceAddr) |
bcostm | 0:e1d164542663 | 185 | { |
bcostm | 0:e1d164542663 | 186 | /* Initialize IO BUS layer */ |
bcostm | 0:e1d164542663 | 187 | IOE_Init(); |
bcostm | 0:e1d164542663 | 188 | |
bcostm | 0:e1d164542663 | 189 | /* Return the device ID value */ |
bcostm | 0:e1d164542663 | 190 | return ((IOE_Read(DeviceAddr, STMPE811_REG_CHP_ID_LSB) << 8) |\ |
bcostm | 0:e1d164542663 | 191 | (IOE_Read(DeviceAddr, STMPE811_REG_CHP_ID_MSB))); |
bcostm | 0:e1d164542663 | 192 | } |
bcostm | 0:e1d164542663 | 193 | |
bcostm | 0:e1d164542663 | 194 | /** |
bcostm | 0:e1d164542663 | 195 | * @brief Enable the Global interrupt. |
bcostm | 0:e1d164542663 | 196 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 197 | * @retval None |
bcostm | 0:e1d164542663 | 198 | */ |
bcostm | 0:e1d164542663 | 199 | void stmpe811_EnableGlobalIT(uint16_t DeviceAddr) |
bcostm | 0:e1d164542663 | 200 | { |
bcostm | 0:e1d164542663 | 201 | uint8_t tmp = 0; |
bcostm | 0:e1d164542663 | 202 | |
bcostm | 0:e1d164542663 | 203 | /* Read the Interrupt Control register */ |
bcostm | 0:e1d164542663 | 204 | tmp = IOE_Read(DeviceAddr, STMPE811_REG_INT_CTRL); |
bcostm | 0:e1d164542663 | 205 | |
bcostm | 0:e1d164542663 | 206 | /* Set the global interrupts to be Enabled */ |
bcostm | 0:e1d164542663 | 207 | tmp |= (uint8_t)STMPE811_GIT_EN; |
bcostm | 0:e1d164542663 | 208 | |
bcostm | 0:e1d164542663 | 209 | /* Write Back the Interrupt Control register */ |
bcostm | 0:e1d164542663 | 210 | IOE_Write(DeviceAddr, STMPE811_REG_INT_CTRL, tmp); |
bcostm | 0:e1d164542663 | 211 | } |
bcostm | 0:e1d164542663 | 212 | |
bcostm | 0:e1d164542663 | 213 | /** |
bcostm | 0:e1d164542663 | 214 | * @brief Disable the Global interrupt. |
bcostm | 0:e1d164542663 | 215 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 216 | * @retval None |
bcostm | 0:e1d164542663 | 217 | */ |
bcostm | 0:e1d164542663 | 218 | void stmpe811_DisableGlobalIT(uint16_t DeviceAddr) |
bcostm | 0:e1d164542663 | 219 | { |
bcostm | 0:e1d164542663 | 220 | uint8_t tmp = 0; |
bcostm | 0:e1d164542663 | 221 | |
bcostm | 0:e1d164542663 | 222 | /* Read the Interrupt Control register */ |
bcostm | 0:e1d164542663 | 223 | tmp = IOE_Read(DeviceAddr, STMPE811_REG_INT_CTRL); |
bcostm | 0:e1d164542663 | 224 | |
bcostm | 0:e1d164542663 | 225 | /* Set the global interrupts to be Disabled */ |
bcostm | 0:e1d164542663 | 226 | tmp &= ~(uint8_t)STMPE811_GIT_EN; |
bcostm | 0:e1d164542663 | 227 | |
bcostm | 0:e1d164542663 | 228 | /* Write Back the Interrupt Control register */ |
bcostm | 0:e1d164542663 | 229 | IOE_Write(DeviceAddr, STMPE811_REG_INT_CTRL, tmp); |
bcostm | 0:e1d164542663 | 230 | |
bcostm | 0:e1d164542663 | 231 | } |
bcostm | 0:e1d164542663 | 232 | |
bcostm | 0:e1d164542663 | 233 | /** |
bcostm | 0:e1d164542663 | 234 | * @brief Enable the interrupt mode for the selected IT source |
bcostm | 0:e1d164542663 | 235 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 236 | * @param Source: The interrupt source to be configured, could be: |
bcostm | 0:e1d164542663 | 237 | * @arg STMPE811_GIT_IO: IO interrupt |
bcostm | 0:e1d164542663 | 238 | * @arg STMPE811_GIT_ADC : ADC interrupt |
bcostm | 0:e1d164542663 | 239 | * @arg STMPE811_GIT_FE : Touch Screen Controller FIFO Error interrupt |
bcostm | 0:e1d164542663 | 240 | * @arg STMPE811_GIT_FF : Touch Screen Controller FIFO Full interrupt |
bcostm | 0:e1d164542663 | 241 | * @arg STMPE811_GIT_FOV : Touch Screen Controller FIFO Overrun interrupt |
bcostm | 0:e1d164542663 | 242 | * @arg STMPE811_GIT_FTH : Touch Screen Controller FIFO Threshold interrupt |
bcostm | 0:e1d164542663 | 243 | * @arg STMPE811_GIT_TOUCH : Touch Screen Controller Touch Detected interrupt |
bcostm | 0:e1d164542663 | 244 | * @retval None |
bcostm | 0:e1d164542663 | 245 | */ |
bcostm | 0:e1d164542663 | 246 | void stmpe811_EnableITSource(uint16_t DeviceAddr, uint8_t Source) |
bcostm | 0:e1d164542663 | 247 | { |
bcostm | 0:e1d164542663 | 248 | uint8_t tmp = 0; |
bcostm | 0:e1d164542663 | 249 | |
bcostm | 0:e1d164542663 | 250 | /* Get the current value of the INT_EN register */ |
bcostm | 0:e1d164542663 | 251 | tmp = IOE_Read(DeviceAddr, STMPE811_REG_INT_EN); |
bcostm | 0:e1d164542663 | 252 | |
bcostm | 0:e1d164542663 | 253 | /* Set the interrupts to be Enabled */ |
bcostm | 0:e1d164542663 | 254 | tmp |= Source; |
bcostm | 0:e1d164542663 | 255 | |
bcostm | 0:e1d164542663 | 256 | /* Set the register */ |
bcostm | 0:e1d164542663 | 257 | IOE_Write(DeviceAddr, STMPE811_REG_INT_EN, tmp); |
bcostm | 0:e1d164542663 | 258 | } |
bcostm | 0:e1d164542663 | 259 | |
bcostm | 0:e1d164542663 | 260 | /** |
bcostm | 0:e1d164542663 | 261 | * @brief Disable the interrupt mode for the selected IT source |
bcostm | 0:e1d164542663 | 262 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 263 | * @param Source: The interrupt source to be configured, could be: |
bcostm | 0:e1d164542663 | 264 | * @arg STMPE811_GIT_IO: IO interrupt |
bcostm | 0:e1d164542663 | 265 | * @arg STMPE811_GIT_ADC : ADC interrupt |
bcostm | 0:e1d164542663 | 266 | * @arg STMPE811_GIT_FE : Touch Screen Controller FIFO Error interrupt |
bcostm | 0:e1d164542663 | 267 | * @arg STMPE811_GIT_FF : Touch Screen Controller FIFO Full interrupt |
bcostm | 0:e1d164542663 | 268 | * @arg STMPE811_GIT_FOV : Touch Screen Controller FIFO Overrun interrupt |
bcostm | 0:e1d164542663 | 269 | * @arg STMPE811_GIT_FTH : Touch Screen Controller FIFO Threshold interrupt |
bcostm | 0:e1d164542663 | 270 | * @arg STMPE811_GIT_TOUCH : Touch Screen Controller Touch Detected interrupt |
bcostm | 0:e1d164542663 | 271 | * @retval None |
bcostm | 0:e1d164542663 | 272 | */ |
bcostm | 0:e1d164542663 | 273 | void stmpe811_DisableITSource(uint16_t DeviceAddr, uint8_t Source) |
bcostm | 0:e1d164542663 | 274 | { |
bcostm | 0:e1d164542663 | 275 | uint8_t tmp = 0; |
bcostm | 0:e1d164542663 | 276 | |
bcostm | 0:e1d164542663 | 277 | /* Get the current value of the INT_EN register */ |
bcostm | 0:e1d164542663 | 278 | tmp = IOE_Read(DeviceAddr, STMPE811_REG_INT_EN); |
bcostm | 0:e1d164542663 | 279 | |
bcostm | 0:e1d164542663 | 280 | /* Set the interrupts to be Enabled */ |
bcostm | 0:e1d164542663 | 281 | tmp &= ~Source; |
bcostm | 0:e1d164542663 | 282 | |
bcostm | 0:e1d164542663 | 283 | /* Set the register */ |
bcostm | 0:e1d164542663 | 284 | IOE_Write(DeviceAddr, STMPE811_REG_INT_EN, tmp); |
bcostm | 0:e1d164542663 | 285 | } |
bcostm | 0:e1d164542663 | 286 | |
bcostm | 0:e1d164542663 | 287 | /** |
bcostm | 0:e1d164542663 | 288 | * @brief Set the global interrupt Polarity. |
bcostm | 0:e1d164542663 | 289 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 290 | * @param Polarity: the IT mode polarity, could be one of the following values: |
bcostm | 0:e1d164542663 | 291 | * @arg STMPE811_POLARITY_LOW: Interrupt line is active Low/Falling edge |
bcostm | 0:e1d164542663 | 292 | * @arg STMPE811_POLARITY_HIGH: Interrupt line is active High/Rising edge |
bcostm | 0:e1d164542663 | 293 | * @retval None |
bcostm | 0:e1d164542663 | 294 | */ |
bcostm | 0:e1d164542663 | 295 | void stmpe811_SetITPolarity(uint16_t DeviceAddr, uint8_t Polarity) |
bcostm | 0:e1d164542663 | 296 | { |
bcostm | 0:e1d164542663 | 297 | uint8_t tmp = 0; |
bcostm | 0:e1d164542663 | 298 | |
bcostm | 0:e1d164542663 | 299 | /* Get the current register value */ |
bcostm | 0:e1d164542663 | 300 | tmp = IOE_Read(DeviceAddr, STMPE811_REG_INT_CTRL); |
bcostm | 0:e1d164542663 | 301 | |
bcostm | 0:e1d164542663 | 302 | /* Mask the polarity bits */ |
bcostm | 0:e1d164542663 | 303 | tmp &= ~(uint8_t)0x04; |
bcostm | 0:e1d164542663 | 304 | |
bcostm | 0:e1d164542663 | 305 | /* Modify the Interrupt Output line configuration */ |
bcostm | 0:e1d164542663 | 306 | tmp |= Polarity; |
bcostm | 0:e1d164542663 | 307 | |
bcostm | 0:e1d164542663 | 308 | /* Set the new register value */ |
bcostm | 0:e1d164542663 | 309 | IOE_Write(DeviceAddr, STMPE811_REG_INT_CTRL, tmp); |
bcostm | 0:e1d164542663 | 310 | |
bcostm | 0:e1d164542663 | 311 | } |
bcostm | 0:e1d164542663 | 312 | |
bcostm | 0:e1d164542663 | 313 | /** |
bcostm | 0:e1d164542663 | 314 | * @brief Set the global interrupt Type. |
bcostm | 0:e1d164542663 | 315 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 316 | * @param Type: Interrupt line activity type, could be one of the following values: |
bcostm | 0:e1d164542663 | 317 | * @arg STMPE811_TYPE_LEVEL: Interrupt line is active in level model |
bcostm | 0:e1d164542663 | 318 | * @arg STMPE811_TYPE_EDGE: Interrupt line is active in edge model |
bcostm | 0:e1d164542663 | 319 | * @retval None |
bcostm | 0:e1d164542663 | 320 | */ |
bcostm | 0:e1d164542663 | 321 | void stmpe811_SetITType(uint16_t DeviceAddr, uint8_t Type) |
bcostm | 0:e1d164542663 | 322 | { |
bcostm | 0:e1d164542663 | 323 | uint8_t tmp = 0; |
bcostm | 0:e1d164542663 | 324 | |
bcostm | 0:e1d164542663 | 325 | /* Get the current register value */ |
bcostm | 0:e1d164542663 | 326 | tmp = IOE_Read(DeviceAddr, STMPE811_REG_INT_CTRL); |
bcostm | 0:e1d164542663 | 327 | |
bcostm | 0:e1d164542663 | 328 | /* Mask the type bits */ |
bcostm | 0:e1d164542663 | 329 | tmp &= ~(uint8_t)0x02; |
bcostm | 0:e1d164542663 | 330 | |
bcostm | 0:e1d164542663 | 331 | /* Modify the Interrupt Output line configuration */ |
bcostm | 0:e1d164542663 | 332 | tmp |= Type; |
bcostm | 0:e1d164542663 | 333 | |
bcostm | 0:e1d164542663 | 334 | /* Set the new register value */ |
bcostm | 0:e1d164542663 | 335 | IOE_Write(DeviceAddr, STMPE811_REG_INT_CTRL, tmp); |
bcostm | 0:e1d164542663 | 336 | |
bcostm | 0:e1d164542663 | 337 | } |
bcostm | 0:e1d164542663 | 338 | |
bcostm | 0:e1d164542663 | 339 | /** |
bcostm | 0:e1d164542663 | 340 | * @brief Check the selected Global interrupt source pending bit |
bcostm | 0:e1d164542663 | 341 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 342 | * @param Source: the Global interrupt source to be checked, could be: |
bcostm | 0:e1d164542663 | 343 | * @arg STMPE811_GIT_IO: IO interrupt |
bcostm | 0:e1d164542663 | 344 | * @arg STMPE811_GIT_ADC : ADC interrupt |
bcostm | 0:e1d164542663 | 345 | * @arg STMPE811_GIT_FE : Touch Screen Controller FIFO Error interrupt |
bcostm | 0:e1d164542663 | 346 | * @arg STMPE811_GIT_FF : Touch Screen Controller FIFO Full interrupt |
bcostm | 0:e1d164542663 | 347 | * @arg STMPE811_GIT_FOV : Touch Screen Controller FIFO Overrun interrupt |
bcostm | 0:e1d164542663 | 348 | * @arg STMPE811_GIT_FTH : Touch Screen Controller FIFO Threshold interrupt |
bcostm | 0:e1d164542663 | 349 | * @arg STMPE811_GIT_TOUCH : Touch Screen Controller Touch Detected interrupt |
bcostm | 0:e1d164542663 | 350 | * @retval The checked Global interrupt source status. |
bcostm | 0:e1d164542663 | 351 | */ |
bcostm | 0:e1d164542663 | 352 | uint8_t stmpe811_GlobalITStatus(uint16_t DeviceAddr, uint8_t Source) |
bcostm | 0:e1d164542663 | 353 | { |
bcostm | 0:e1d164542663 | 354 | /* Return the global IT source status */ |
bcostm | 0:e1d164542663 | 355 | return((IOE_Read(DeviceAddr, STMPE811_REG_INT_STA) & Source) == Source); |
bcostm | 0:e1d164542663 | 356 | } |
bcostm | 0:e1d164542663 | 357 | |
bcostm | 0:e1d164542663 | 358 | /** |
bcostm | 0:e1d164542663 | 359 | * @brief Return the Global interrupts status |
bcostm | 0:e1d164542663 | 360 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 361 | * @param Source: the Global interrupt source to be checked, could be: |
bcostm | 0:e1d164542663 | 362 | * @arg STMPE811_GIT_IO: IO interrupt |
bcostm | 0:e1d164542663 | 363 | * @arg STMPE811_GIT_ADC : ADC interrupt |
bcostm | 0:e1d164542663 | 364 | * @arg STMPE811_GIT_FE : Touch Screen Controller FIFO Error interrupt |
bcostm | 0:e1d164542663 | 365 | * @arg STMPE811_GIT_FF : Touch Screen Controller FIFO Full interrupt |
bcostm | 0:e1d164542663 | 366 | * @arg STMPE811_GIT_FOV : Touch Screen Controller FIFO Overrun interrupt |
bcostm | 0:e1d164542663 | 367 | * @arg STMPE811_GIT_FTH : Touch Screen Controller FIFO Threshold interrupt |
bcostm | 0:e1d164542663 | 368 | * @arg STMPE811_GIT_TOUCH : Touch Screen Controller Touch Detected interrupt |
bcostm | 0:e1d164542663 | 369 | * @retval The checked Global interrupt source status. |
bcostm | 0:e1d164542663 | 370 | */ |
bcostm | 0:e1d164542663 | 371 | uint8_t stmpe811_ReadGITStatus(uint16_t DeviceAddr, uint8_t Source) |
bcostm | 0:e1d164542663 | 372 | { |
bcostm | 0:e1d164542663 | 373 | /* Return the global IT source status */ |
bcostm | 0:e1d164542663 | 374 | return((IOE_Read(DeviceAddr, STMPE811_REG_INT_STA) & Source)); |
bcostm | 0:e1d164542663 | 375 | } |
bcostm | 0:e1d164542663 | 376 | |
bcostm | 0:e1d164542663 | 377 | /** |
bcostm | 0:e1d164542663 | 378 | * @brief Clear the selected Global interrupt pending bit(s) |
bcostm | 0:e1d164542663 | 379 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 380 | * @param Source: the Global interrupt source to be cleared, could be any combination |
bcostm | 0:e1d164542663 | 381 | * of the following values: |
bcostm | 0:e1d164542663 | 382 | * @arg STMPE811_GIT_IO: IO interrupt |
bcostm | 0:e1d164542663 | 383 | * @arg STMPE811_GIT_ADC : ADC interrupt |
bcostm | 0:e1d164542663 | 384 | * @arg STMPE811_GIT_FE : Touch Screen Controller FIFO Error interrupt |
bcostm | 0:e1d164542663 | 385 | * @arg STMPE811_GIT_FF : Touch Screen Controller FIFO Full interrupt |
bcostm | 0:e1d164542663 | 386 | * @arg STMPE811_GIT_FOV : Touch Screen Controller FIFO Overrun interrupt |
bcostm | 0:e1d164542663 | 387 | * @arg STMPE811_GIT_FTH : Touch Screen Controller FIFO Threshold interrupt |
bcostm | 0:e1d164542663 | 388 | * @arg STMPE811_GIT_TOUCH : Touch Screen Controller Touch Detected interrupt |
bcostm | 0:e1d164542663 | 389 | * @retval None |
bcostm | 0:e1d164542663 | 390 | */ |
bcostm | 0:e1d164542663 | 391 | void stmpe811_ClearGlobalIT(uint16_t DeviceAddr, uint8_t Source) |
bcostm | 0:e1d164542663 | 392 | { |
bcostm | 0:e1d164542663 | 393 | /* Write 1 to the bits that have to be cleared */ |
bcostm | 0:e1d164542663 | 394 | IOE_Write(DeviceAddr, STMPE811_REG_INT_STA, Source); |
bcostm | 0:e1d164542663 | 395 | } |
bcostm | 0:e1d164542663 | 396 | |
bcostm | 0:e1d164542663 | 397 | /** |
bcostm | 0:e1d164542663 | 398 | * @brief Start the IO functionality use and disable the AF for selected IO pin(s). |
bcostm | 0:e1d164542663 | 399 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 400 | * @param IO_Pin: The IO pin(s) to put in AF. This parameter can be one |
bcostm | 0:e1d164542663 | 401 | * of the following values: |
bcostm | 0:e1d164542663 | 402 | * @arg STMPE811_PIN_x: where x can be from 0 to 7. |
bcostm | 0:e1d164542663 | 403 | * @retval None |
bcostm | 0:e1d164542663 | 404 | */ |
bcostm | 0:e1d164542663 | 405 | void stmpe811_IO_Start(uint16_t DeviceAddr, uint32_t IO_Pin) |
bcostm | 0:e1d164542663 | 406 | { |
bcostm | 0:e1d164542663 | 407 | uint8_t mode; |
bcostm | 0:e1d164542663 | 408 | |
bcostm | 0:e1d164542663 | 409 | /* Get the current register value */ |
bcostm | 0:e1d164542663 | 410 | mode = IOE_Read(DeviceAddr, STMPE811_REG_SYS_CTRL2); |
bcostm | 0:e1d164542663 | 411 | |
bcostm | 0:e1d164542663 | 412 | /* Set the Functionalities to be Disabled */ |
bcostm | 0:e1d164542663 | 413 | mode &= ~(STMPE811_IO_FCT | STMPE811_ADC_FCT); |
bcostm | 0:e1d164542663 | 414 | |
bcostm | 0:e1d164542663 | 415 | /* Write the new register value */ |
bcostm | 0:e1d164542663 | 416 | IOE_Write(DeviceAddr, STMPE811_REG_SYS_CTRL2, mode); |
bcostm | 0:e1d164542663 | 417 | |
bcostm | 0:e1d164542663 | 418 | /* Disable AF for the selected IO pin(s) */ |
bcostm | 0:e1d164542663 | 419 | stmpe811_IO_DisableAF(DeviceAddr, (uint8_t)IO_Pin); |
bcostm | 0:e1d164542663 | 420 | } |
bcostm | 0:e1d164542663 | 421 | |
bcostm | 0:e1d164542663 | 422 | /** |
bcostm | 0:e1d164542663 | 423 | * @brief Configures the IO pin(s) according to IO mode structure value. |
bcostm | 0:e1d164542663 | 424 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 425 | * @param IO_Pin: The output pin to be set or reset. This parameter can be one |
bcostm | 0:e1d164542663 | 426 | * of the following values: |
bcostm | 0:e1d164542663 | 427 | * @arg STMPE811_PIN_x: where x can be from 0 to 7. |
bcostm | 0:e1d164542663 | 428 | * @param IO_Mode: The IO pin mode to configure, could be one of the following values: |
bcostm | 0:e1d164542663 | 429 | * @arg IO_MODE_INPUT |
bcostm | 0:e1d164542663 | 430 | * @arg IO_MODE_OUTPUT |
bcostm | 0:e1d164542663 | 431 | * @arg IO_MODE_IT_RISING_EDGE |
bcostm | 0:e1d164542663 | 432 | * @arg IO_MODE_IT_FALLING_EDGE |
bcostm | 0:e1d164542663 | 433 | * @arg IO_MODE_IT_LOW_LEVEL |
bcostm | 0:e1d164542663 | 434 | * @arg IO_MODE_IT_HIGH_LEVEL |
bcostm | 0:e1d164542663 | 435 | * @retval 0 if no error, IO_Mode if error |
bcostm | 0:e1d164542663 | 436 | */ |
bcostm | 0:e1d164542663 | 437 | uint8_t stmpe811_IO_Config(uint16_t DeviceAddr, uint32_t IO_Pin, IO_ModeTypedef IO_Mode) |
bcostm | 0:e1d164542663 | 438 | { |
bcostm | 0:e1d164542663 | 439 | uint8_t error_code = 0; |
bcostm | 0:e1d164542663 | 440 | |
bcostm | 0:e1d164542663 | 441 | /* Configure IO pin according to selected IO mode */ |
bcostm | 0:e1d164542663 | 442 | switch(IO_Mode) |
bcostm | 0:e1d164542663 | 443 | { |
bcostm | 0:e1d164542663 | 444 | case IO_MODE_INPUT: /* Input mode */ |
bcostm | 0:e1d164542663 | 445 | stmpe811_IO_InitPin(DeviceAddr, IO_Pin, STMPE811_DIRECTION_IN); |
bcostm | 0:e1d164542663 | 446 | break; |
bcostm | 0:e1d164542663 | 447 | |
bcostm | 0:e1d164542663 | 448 | case IO_MODE_OUTPUT: /* Output mode */ |
bcostm | 0:e1d164542663 | 449 | stmpe811_IO_InitPin(DeviceAddr, IO_Pin, STMPE811_DIRECTION_OUT); |
bcostm | 0:e1d164542663 | 450 | break; |
bcostm | 0:e1d164542663 | 451 | |
bcostm | 0:e1d164542663 | 452 | case IO_MODE_IT_RISING_EDGE: /* Interrupt rising edge mode */ |
bcostm | 0:e1d164542663 | 453 | stmpe811_IO_EnableIT(DeviceAddr); |
bcostm | 0:e1d164542663 | 454 | stmpe811_IO_EnablePinIT(DeviceAddr, IO_Pin); |
bcostm | 0:e1d164542663 | 455 | stmpe811_IO_InitPin(DeviceAddr, IO_Pin, STMPE811_DIRECTION_IN); |
bcostm | 0:e1d164542663 | 456 | stmpe811_SetITType(DeviceAddr, STMPE811_TYPE_EDGE); |
bcostm | 0:e1d164542663 | 457 | stmpe811_IO_SetEdgeMode(DeviceAddr, IO_Pin, STMPE811_EDGE_RISING); |
bcostm | 0:e1d164542663 | 458 | break; |
bcostm | 0:e1d164542663 | 459 | |
bcostm | 0:e1d164542663 | 460 | case IO_MODE_IT_FALLING_EDGE: /* Interrupt falling edge mode */ |
bcostm | 0:e1d164542663 | 461 | stmpe811_IO_EnableIT(DeviceAddr); |
bcostm | 0:e1d164542663 | 462 | stmpe811_IO_EnablePinIT(DeviceAddr, IO_Pin); |
bcostm | 0:e1d164542663 | 463 | stmpe811_IO_InitPin(DeviceAddr, IO_Pin, STMPE811_DIRECTION_IN); |
bcostm | 0:e1d164542663 | 464 | stmpe811_SetITType(DeviceAddr, STMPE811_TYPE_EDGE); |
bcostm | 0:e1d164542663 | 465 | stmpe811_IO_SetEdgeMode(DeviceAddr, IO_Pin, STMPE811_EDGE_FALLING); |
bcostm | 0:e1d164542663 | 466 | break; |
bcostm | 0:e1d164542663 | 467 | |
bcostm | 0:e1d164542663 | 468 | case IO_MODE_IT_LOW_LEVEL: /* Low level interrupt mode */ |
bcostm | 0:e1d164542663 | 469 | stmpe811_IO_EnableIT(DeviceAddr); |
bcostm | 0:e1d164542663 | 470 | stmpe811_IO_EnablePinIT(DeviceAddr, IO_Pin); |
bcostm | 0:e1d164542663 | 471 | stmpe811_IO_InitPin(DeviceAddr, IO_Pin, STMPE811_DIRECTION_IN); |
bcostm | 0:e1d164542663 | 472 | stmpe811_SetITType(DeviceAddr, STMPE811_TYPE_LEVEL); |
bcostm | 0:e1d164542663 | 473 | stmpe811_SetITPolarity(DeviceAddr, STMPE811_POLARITY_LOW); |
bcostm | 0:e1d164542663 | 474 | break; |
bcostm | 0:e1d164542663 | 475 | |
bcostm | 0:e1d164542663 | 476 | case IO_MODE_IT_HIGH_LEVEL: /* High level interrupt mode */ |
bcostm | 0:e1d164542663 | 477 | stmpe811_IO_EnableIT(DeviceAddr); |
bcostm | 0:e1d164542663 | 478 | stmpe811_IO_EnablePinIT(DeviceAddr, IO_Pin); |
bcostm | 0:e1d164542663 | 479 | stmpe811_IO_InitPin(DeviceAddr, IO_Pin, STMPE811_DIRECTION_IN); |
bcostm | 0:e1d164542663 | 480 | stmpe811_SetITType(DeviceAddr, STMPE811_TYPE_LEVEL); |
bcostm | 0:e1d164542663 | 481 | stmpe811_SetITPolarity(DeviceAddr, STMPE811_POLARITY_HIGH); |
bcostm | 0:e1d164542663 | 482 | break; |
bcostm | 0:e1d164542663 | 483 | |
bcostm | 0:e1d164542663 | 484 | default: |
bcostm | 0:e1d164542663 | 485 | error_code = (uint8_t) IO_Mode; |
bcostm | 0:e1d164542663 | 486 | break; |
bcostm | 0:e1d164542663 | 487 | } |
bcostm | 0:e1d164542663 | 488 | return error_code; |
bcostm | 0:e1d164542663 | 489 | } |
bcostm | 0:e1d164542663 | 490 | |
bcostm | 0:e1d164542663 | 491 | /** |
bcostm | 0:e1d164542663 | 492 | * @brief Initialize the selected IO pin direction. |
bcostm | 0:e1d164542663 | 493 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 494 | * @param IO_Pin: The IO pin to be configured. This parameter could be any |
bcostm | 0:e1d164542663 | 495 | * combination of the following values: |
bcostm | 0:e1d164542663 | 496 | * @arg STMPE811_PIN_x: Where x can be from 0 to 7. |
bcostm | 0:e1d164542663 | 497 | * @param Direction: could be STMPE811_DIRECTION_IN or STMPE811_DIRECTION_OUT. |
bcostm | 0:e1d164542663 | 498 | * @retval None |
bcostm | 0:e1d164542663 | 499 | */ |
bcostm | 0:e1d164542663 | 500 | void stmpe811_IO_InitPin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Direction) |
bcostm | 0:e1d164542663 | 501 | { |
bcostm | 0:e1d164542663 | 502 | uint8_t tmp = 0; |
bcostm | 0:e1d164542663 | 503 | |
bcostm | 0:e1d164542663 | 504 | /* Get all the Pins direction */ |
bcostm | 0:e1d164542663 | 505 | tmp = IOE_Read(DeviceAddr, STMPE811_REG_IO_DIR); |
bcostm | 0:e1d164542663 | 506 | |
bcostm | 0:e1d164542663 | 507 | /* Set the selected pin direction */ |
bcostm | 0:e1d164542663 | 508 | if (Direction != STMPE811_DIRECTION_IN) |
bcostm | 0:e1d164542663 | 509 | { |
bcostm | 0:e1d164542663 | 510 | tmp |= (uint8_t)IO_Pin; |
bcostm | 0:e1d164542663 | 511 | } |
bcostm | 0:e1d164542663 | 512 | else |
bcostm | 0:e1d164542663 | 513 | { |
bcostm | 0:e1d164542663 | 514 | tmp &= ~(uint8_t)IO_Pin; |
bcostm | 0:e1d164542663 | 515 | } |
bcostm | 0:e1d164542663 | 516 | |
bcostm | 0:e1d164542663 | 517 | /* Write the register new value */ |
bcostm | 0:e1d164542663 | 518 | IOE_Write(DeviceAddr, STMPE811_REG_IO_DIR, tmp); |
bcostm | 0:e1d164542663 | 519 | } |
bcostm | 0:e1d164542663 | 520 | |
bcostm | 0:e1d164542663 | 521 | /** |
bcostm | 0:e1d164542663 | 522 | * @brief Disable the AF for the selected IO pin(s). |
bcostm | 0:e1d164542663 | 523 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 524 | * @param IO_Pin: The IO pin to be configured. This parameter could be any |
bcostm | 0:e1d164542663 | 525 | * combination of the following values: |
bcostm | 0:e1d164542663 | 526 | * @arg STMPE811_PIN_x: Where x can be from 0 to 7. |
bcostm | 0:e1d164542663 | 527 | * @retval None |
bcostm | 0:e1d164542663 | 528 | */ |
bcostm | 0:e1d164542663 | 529 | void stmpe811_IO_DisableAF(uint16_t DeviceAddr, uint32_t IO_Pin) |
bcostm | 0:e1d164542663 | 530 | { |
bcostm | 0:e1d164542663 | 531 | uint8_t tmp = 0; |
bcostm | 0:e1d164542663 | 532 | |
bcostm | 0:e1d164542663 | 533 | /* Get the current state of the IO_AF register */ |
bcostm | 0:e1d164542663 | 534 | tmp = IOE_Read(DeviceAddr, STMPE811_REG_IO_AF); |
bcostm | 0:e1d164542663 | 535 | |
bcostm | 0:e1d164542663 | 536 | /* Enable the selected pins alternate function */ |
bcostm | 0:e1d164542663 | 537 | tmp |= (uint8_t)IO_Pin; |
bcostm | 0:e1d164542663 | 538 | |
bcostm | 0:e1d164542663 | 539 | /* Write back the new value in IO AF register */ |
bcostm | 0:e1d164542663 | 540 | IOE_Write(DeviceAddr, STMPE811_REG_IO_AF, tmp); |
bcostm | 0:e1d164542663 | 541 | |
bcostm | 0:e1d164542663 | 542 | } |
bcostm | 0:e1d164542663 | 543 | |
bcostm | 0:e1d164542663 | 544 | /** |
bcostm | 0:e1d164542663 | 545 | * @brief Enable the AF for the selected IO pin(s). |
bcostm | 0:e1d164542663 | 546 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 547 | * @param IO_Pin: The IO pin to be configured. This parameter could be any |
bcostm | 0:e1d164542663 | 548 | * combination of the following values: |
bcostm | 0:e1d164542663 | 549 | * @arg STMPE811_PIN_x: Where x can be from 0 to 7. |
bcostm | 0:e1d164542663 | 550 | * @retval None |
bcostm | 0:e1d164542663 | 551 | */ |
bcostm | 0:e1d164542663 | 552 | void stmpe811_IO_EnableAF(uint16_t DeviceAddr, uint32_t IO_Pin) |
bcostm | 0:e1d164542663 | 553 | { |
bcostm | 0:e1d164542663 | 554 | uint8_t tmp = 0; |
bcostm | 0:e1d164542663 | 555 | |
bcostm | 0:e1d164542663 | 556 | /* Get the current register value */ |
bcostm | 0:e1d164542663 | 557 | tmp = IOE_Read(DeviceAddr, STMPE811_REG_IO_AF); |
bcostm | 0:e1d164542663 | 558 | |
bcostm | 0:e1d164542663 | 559 | /* Enable the selected pins alternate function */ |
bcostm | 0:e1d164542663 | 560 | tmp &= ~(uint8_t)IO_Pin; |
bcostm | 0:e1d164542663 | 561 | |
bcostm | 0:e1d164542663 | 562 | /* Write back the new register value */ |
bcostm | 0:e1d164542663 | 563 | IOE_Write(DeviceAddr, STMPE811_REG_IO_AF, tmp); |
bcostm | 0:e1d164542663 | 564 | } |
bcostm | 0:e1d164542663 | 565 | |
bcostm | 0:e1d164542663 | 566 | /** |
bcostm | 0:e1d164542663 | 567 | * @brief Configure the Edge for which a transition is detectable for the |
bcostm | 0:e1d164542663 | 568 | * selected pin. |
bcostm | 0:e1d164542663 | 569 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 570 | * @param IO_Pin: The IO pin to be configured. This parameter could be any |
bcostm | 0:e1d164542663 | 571 | * combination of the following values: |
bcostm | 0:e1d164542663 | 572 | * @arg STMPE811_PIN_x: Where x can be from 0 to 7. |
bcostm | 0:e1d164542663 | 573 | * @param Edge: The edge which will be detected. This parameter can be one or |
bcostm | 0:e1d164542663 | 574 | * a combination of following values: STMPE811_EDGE_FALLING and STMPE811_EDGE_RISING . |
bcostm | 0:e1d164542663 | 575 | * @retval None |
bcostm | 0:e1d164542663 | 576 | */ |
bcostm | 0:e1d164542663 | 577 | void stmpe811_IO_SetEdgeMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Edge) |
bcostm | 0:e1d164542663 | 578 | { |
bcostm | 0:e1d164542663 | 579 | uint8_t tmp1 = 0, tmp2 = 0; |
bcostm | 0:e1d164542663 | 580 | |
bcostm | 0:e1d164542663 | 581 | /* Get the current registers values */ |
bcostm | 0:e1d164542663 | 582 | tmp1 = IOE_Read(DeviceAddr, STMPE811_REG_IO_FE); |
bcostm | 0:e1d164542663 | 583 | tmp2 = IOE_Read(DeviceAddr, STMPE811_REG_IO_RE); |
bcostm | 0:e1d164542663 | 584 | |
bcostm | 0:e1d164542663 | 585 | /* Disable the Falling Edge */ |
bcostm | 0:e1d164542663 | 586 | tmp1 &= ~(uint8_t)IO_Pin; |
bcostm | 0:e1d164542663 | 587 | |
bcostm | 0:e1d164542663 | 588 | /* Disable the Falling Edge */ |
bcostm | 0:e1d164542663 | 589 | tmp2 &= ~(uint8_t)IO_Pin; |
bcostm | 0:e1d164542663 | 590 | |
bcostm | 0:e1d164542663 | 591 | /* Enable the Falling edge if selected */ |
bcostm | 0:e1d164542663 | 592 | if (Edge & STMPE811_EDGE_FALLING) |
bcostm | 0:e1d164542663 | 593 | { |
bcostm | 0:e1d164542663 | 594 | tmp1 |= (uint8_t)IO_Pin; |
bcostm | 0:e1d164542663 | 595 | } |
bcostm | 0:e1d164542663 | 596 | |
bcostm | 0:e1d164542663 | 597 | /* Enable the Rising edge if selected */ |
bcostm | 0:e1d164542663 | 598 | if (Edge & STMPE811_EDGE_RISING) |
bcostm | 0:e1d164542663 | 599 | { |
bcostm | 0:e1d164542663 | 600 | tmp2 |= (uint8_t)IO_Pin; |
bcostm | 0:e1d164542663 | 601 | } |
bcostm | 0:e1d164542663 | 602 | |
bcostm | 0:e1d164542663 | 603 | /* Write back the new registers values */ |
bcostm | 0:e1d164542663 | 604 | IOE_Write(DeviceAddr, STMPE811_REG_IO_FE, tmp1); |
bcostm | 0:e1d164542663 | 605 | IOE_Write(DeviceAddr, STMPE811_REG_IO_RE, tmp2); |
bcostm | 0:e1d164542663 | 606 | } |
bcostm | 0:e1d164542663 | 607 | |
bcostm | 0:e1d164542663 | 608 | /** |
bcostm | 0:e1d164542663 | 609 | * @brief Write a new IO pin state. |
bcostm | 0:e1d164542663 | 610 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 611 | * @param IO_Pin: The output pin to be set or reset. This parameter can be one |
bcostm | 0:e1d164542663 | 612 | * of the following values: |
bcostm | 0:e1d164542663 | 613 | * @arg STMPE811_PIN_x: where x can be from 0 to 7. |
bcostm | 0:e1d164542663 | 614 | * @param PinState: The new IO pin state. |
bcostm | 0:e1d164542663 | 615 | * @retval None |
bcostm | 0:e1d164542663 | 616 | */ |
bcostm | 0:e1d164542663 | 617 | void stmpe811_IO_WritePin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t PinState) |
bcostm | 0:e1d164542663 | 618 | { |
bcostm | 0:e1d164542663 | 619 | /* Apply the bit value to the selected pin */ |
bcostm | 0:e1d164542663 | 620 | if (PinState != 0) |
bcostm | 0:e1d164542663 | 621 | { |
bcostm | 0:e1d164542663 | 622 | /* Set the register */ |
bcostm | 0:e1d164542663 | 623 | IOE_Write(DeviceAddr, STMPE811_REG_IO_SET_PIN, (uint8_t)IO_Pin); |
bcostm | 0:e1d164542663 | 624 | } |
bcostm | 0:e1d164542663 | 625 | else |
bcostm | 0:e1d164542663 | 626 | { |
bcostm | 0:e1d164542663 | 627 | /* Set the register */ |
bcostm | 0:e1d164542663 | 628 | IOE_Write(DeviceAddr, STMPE811_REG_IO_CLR_PIN, (uint8_t)IO_Pin); |
bcostm | 0:e1d164542663 | 629 | } |
bcostm | 0:e1d164542663 | 630 | } |
bcostm | 0:e1d164542663 | 631 | |
bcostm | 0:e1d164542663 | 632 | /** |
bcostm | 0:e1d164542663 | 633 | * @brief Return the state of the selected IO pin(s). |
bcostm | 0:e1d164542663 | 634 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 635 | * @param IO_Pin: The output pin to be set or reset. This parameter can be one |
bcostm | 0:e1d164542663 | 636 | * of the following values: |
bcostm | 0:e1d164542663 | 637 | * @arg STMPE811_PIN_x: where x can be from 0 to 7. |
bcostm | 0:e1d164542663 | 638 | * @retval IO pin(s) state. |
bcostm | 0:e1d164542663 | 639 | */ |
bcostm | 0:e1d164542663 | 640 | uint32_t stmpe811_IO_ReadPin(uint16_t DeviceAddr, uint32_t IO_Pin) |
bcostm | 0:e1d164542663 | 641 | { |
bcostm | 0:e1d164542663 | 642 | return((uint32_t)(IOE_Read(DeviceAddr, STMPE811_REG_IO_MP_STA) & (uint8_t)IO_Pin)); |
bcostm | 0:e1d164542663 | 643 | } |
bcostm | 0:e1d164542663 | 644 | |
bcostm | 0:e1d164542663 | 645 | /** |
bcostm | 0:e1d164542663 | 646 | * @brief Enable the global IO interrupt source. |
bcostm | 0:e1d164542663 | 647 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 648 | * @retval None |
bcostm | 0:e1d164542663 | 649 | */ |
bcostm | 0:e1d164542663 | 650 | void stmpe811_IO_EnableIT(uint16_t DeviceAddr) |
bcostm | 0:e1d164542663 | 651 | { |
bcostm | 0:e1d164542663 | 652 | IOE_ITConfig(); |
bcostm | 0:e1d164542663 | 653 | |
bcostm | 0:e1d164542663 | 654 | /* Enable global IO IT source */ |
bcostm | 0:e1d164542663 | 655 | stmpe811_EnableITSource(DeviceAddr, STMPE811_GIT_IO); |
bcostm | 0:e1d164542663 | 656 | |
bcostm | 0:e1d164542663 | 657 | /* Enable global interrupt */ |
bcostm | 0:e1d164542663 | 658 | stmpe811_EnableGlobalIT(DeviceAddr); |
bcostm | 0:e1d164542663 | 659 | } |
bcostm | 0:e1d164542663 | 660 | |
bcostm | 0:e1d164542663 | 661 | /** |
bcostm | 0:e1d164542663 | 662 | * @brief Disable the global IO interrupt source. |
bcostm | 0:e1d164542663 | 663 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 664 | * @retval None |
bcostm | 0:e1d164542663 | 665 | */ |
bcostm | 0:e1d164542663 | 666 | void stmpe811_IO_DisableIT(uint16_t DeviceAddr) |
bcostm | 0:e1d164542663 | 667 | { |
bcostm | 0:e1d164542663 | 668 | /* Disable the global interrupt */ |
bcostm | 0:e1d164542663 | 669 | stmpe811_DisableGlobalIT(DeviceAddr); |
bcostm | 0:e1d164542663 | 670 | |
bcostm | 0:e1d164542663 | 671 | /* Disable global IO IT source */ |
bcostm | 0:e1d164542663 | 672 | stmpe811_DisableITSource(DeviceAddr, STMPE811_GIT_IO); |
bcostm | 0:e1d164542663 | 673 | } |
bcostm | 0:e1d164542663 | 674 | |
bcostm | 0:e1d164542663 | 675 | /** |
bcostm | 0:e1d164542663 | 676 | * @brief Enable interrupt mode for the selected IO pin(s). |
bcostm | 0:e1d164542663 | 677 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 678 | * @param IO_Pin: The IO interrupt to be enabled. This parameter could be any |
bcostm | 0:e1d164542663 | 679 | * combination of the following values: |
bcostm | 0:e1d164542663 | 680 | * @arg STMPE811_PIN_x: where x can be from 0 to 7. |
bcostm | 0:e1d164542663 | 681 | * @retval None |
bcostm | 0:e1d164542663 | 682 | */ |
bcostm | 0:e1d164542663 | 683 | void stmpe811_IO_EnablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin) |
bcostm | 0:e1d164542663 | 684 | { |
bcostm | 0:e1d164542663 | 685 | uint8_t tmp = 0; |
bcostm | 0:e1d164542663 | 686 | |
bcostm | 0:e1d164542663 | 687 | /* Get the IO interrupt state */ |
bcostm | 0:e1d164542663 | 688 | tmp = IOE_Read(DeviceAddr, STMPE811_REG_IO_INT_EN); |
bcostm | 0:e1d164542663 | 689 | |
bcostm | 0:e1d164542663 | 690 | /* Set the interrupts to be enabled */ |
bcostm | 0:e1d164542663 | 691 | tmp |= (uint8_t)IO_Pin; |
bcostm | 0:e1d164542663 | 692 | |
bcostm | 0:e1d164542663 | 693 | /* Write the register new value */ |
bcostm | 0:e1d164542663 | 694 | IOE_Write(DeviceAddr, STMPE811_REG_IO_INT_EN, tmp); |
bcostm | 0:e1d164542663 | 695 | } |
bcostm | 0:e1d164542663 | 696 | |
bcostm | 0:e1d164542663 | 697 | /** |
bcostm | 0:e1d164542663 | 698 | * @brief Disable interrupt mode for the selected IO pin(s). |
bcostm | 0:e1d164542663 | 699 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 700 | * @param IO_Pin: The IO interrupt to be disabled. This parameter could be any |
bcostm | 0:e1d164542663 | 701 | * combination of the following values: |
bcostm | 0:e1d164542663 | 702 | * @arg STMPE811_PIN_x: where x can be from 0 to 7. |
bcostm | 0:e1d164542663 | 703 | * @retval None |
bcostm | 0:e1d164542663 | 704 | */ |
bcostm | 0:e1d164542663 | 705 | void stmpe811_IO_DisablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin) |
bcostm | 0:e1d164542663 | 706 | { |
bcostm | 0:e1d164542663 | 707 | uint8_t tmp = 0; |
bcostm | 0:e1d164542663 | 708 | |
bcostm | 0:e1d164542663 | 709 | /* Get the IO interrupt state */ |
bcostm | 0:e1d164542663 | 710 | tmp = IOE_Read(DeviceAddr, STMPE811_REG_IO_INT_EN); |
bcostm | 0:e1d164542663 | 711 | |
bcostm | 0:e1d164542663 | 712 | /* Set the interrupts to be Disabled */ |
bcostm | 0:e1d164542663 | 713 | tmp &= ~(uint8_t)IO_Pin; |
bcostm | 0:e1d164542663 | 714 | |
bcostm | 0:e1d164542663 | 715 | /* Write the register new value */ |
bcostm | 0:e1d164542663 | 716 | IOE_Write(DeviceAddr, STMPE811_REG_IO_INT_EN, tmp); |
bcostm | 0:e1d164542663 | 717 | } |
bcostm | 0:e1d164542663 | 718 | |
bcostm | 0:e1d164542663 | 719 | /** |
bcostm | 0:e1d164542663 | 720 | * @brief Check the status of the selected IO interrupt pending bit |
bcostm | 0:e1d164542663 | 721 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 722 | * @param IO_Pin: The IO interrupt to be checked could be: |
bcostm | 0:e1d164542663 | 723 | * @arg STMPE811_PIN_x Where x can be from 0 to 7. |
bcostm | 0:e1d164542663 | 724 | * @retval Status of the checked IO pin(s). |
bcostm | 0:e1d164542663 | 725 | */ |
bcostm | 0:e1d164542663 | 726 | uint32_t stmpe811_IO_ITStatus(uint16_t DeviceAddr, uint32_t IO_Pin) |
bcostm | 0:e1d164542663 | 727 | { |
bcostm | 0:e1d164542663 | 728 | /* Get the Interrupt status */ |
bcostm | 0:e1d164542663 | 729 | return(IOE_Read(DeviceAddr, STMPE811_REG_IO_INT_STA) & (uint8_t)IO_Pin); |
bcostm | 0:e1d164542663 | 730 | } |
bcostm | 0:e1d164542663 | 731 | |
bcostm | 0:e1d164542663 | 732 | /** |
bcostm | 0:e1d164542663 | 733 | * @brief Clear the selected IO interrupt pending bit(s). |
bcostm | 0:e1d164542663 | 734 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 735 | * @param IO_Pin: the IO interrupt to be cleared, could be: |
bcostm | 0:e1d164542663 | 736 | * @arg STMPE811_PIN_x: Where x can be from 0 to 7. |
bcostm | 0:e1d164542663 | 737 | * @retval None |
bcostm | 0:e1d164542663 | 738 | */ |
bcostm | 0:e1d164542663 | 739 | void stmpe811_IO_ClearIT(uint16_t DeviceAddr, uint32_t IO_Pin) |
bcostm | 0:e1d164542663 | 740 | { |
bcostm | 0:e1d164542663 | 741 | /* Clear the global IO IT pending bit */ |
bcostm | 0:e1d164542663 | 742 | stmpe811_ClearGlobalIT(DeviceAddr, STMPE811_GIT_IO); |
bcostm | 0:e1d164542663 | 743 | |
bcostm | 0:e1d164542663 | 744 | /* Clear the IO IT pending bit(s) */ |
bcostm | 0:e1d164542663 | 745 | IOE_Write(DeviceAddr, STMPE811_REG_IO_INT_STA, (uint8_t)IO_Pin); |
bcostm | 0:e1d164542663 | 746 | |
bcostm | 0:e1d164542663 | 747 | /* Clear the Edge detection pending bit*/ |
bcostm | 0:e1d164542663 | 748 | IOE_Write(DeviceAddr, STMPE811_REG_IO_ED, (uint8_t)IO_Pin); |
bcostm | 0:e1d164542663 | 749 | |
bcostm | 0:e1d164542663 | 750 | /* Clear the Rising edge pending bit */ |
bcostm | 0:e1d164542663 | 751 | IOE_Write(DeviceAddr, STMPE811_REG_IO_RE, (uint8_t)IO_Pin); |
bcostm | 0:e1d164542663 | 752 | |
bcostm | 0:e1d164542663 | 753 | /* Clear the Falling edge pending bit */ |
bcostm | 0:e1d164542663 | 754 | IOE_Write(DeviceAddr, STMPE811_REG_IO_FE, (uint8_t)IO_Pin); |
bcostm | 0:e1d164542663 | 755 | } |
bcostm | 0:e1d164542663 | 756 | |
bcostm | 0:e1d164542663 | 757 | /** |
bcostm | 0:e1d164542663 | 758 | * @brief Configures the touch Screen Controller (Single point detection) |
bcostm | 0:e1d164542663 | 759 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 760 | * @retval None. |
bcostm | 0:e1d164542663 | 761 | */ |
bcostm | 0:e1d164542663 | 762 | void stmpe811_TS_Start(uint16_t DeviceAddr) |
bcostm | 0:e1d164542663 | 763 | { |
bcostm | 0:e1d164542663 | 764 | uint8_t mode; |
bcostm | 0:e1d164542663 | 765 | |
bcostm | 0:e1d164542663 | 766 | /* Get the current register value */ |
bcostm | 0:e1d164542663 | 767 | mode = IOE_Read(DeviceAddr, STMPE811_REG_SYS_CTRL2); |
bcostm | 0:e1d164542663 | 768 | |
bcostm | 0:e1d164542663 | 769 | /* Set the Functionalities to be Enabled */ |
bcostm | 0:e1d164542663 | 770 | mode &= ~(STMPE811_IO_FCT); |
bcostm | 0:e1d164542663 | 771 | |
bcostm | 0:e1d164542663 | 772 | /* Write the new register value */ |
bcostm | 0:e1d164542663 | 773 | IOE_Write(DeviceAddr, STMPE811_REG_SYS_CTRL2, mode); |
bcostm | 0:e1d164542663 | 774 | |
bcostm | 0:e1d164542663 | 775 | /* Select TSC pins in TSC alternate mode */ |
bcostm | 0:e1d164542663 | 776 | stmpe811_IO_EnableAF(DeviceAddr, STMPE811_TOUCH_IO_ALL); |
bcostm | 0:e1d164542663 | 777 | |
bcostm | 0:e1d164542663 | 778 | /* Set the Functionalities to be Enabled */ |
bcostm | 0:e1d164542663 | 779 | mode &= ~(STMPE811_TS_FCT | STMPE811_ADC_FCT); |
bcostm | 0:e1d164542663 | 780 | |
bcostm | 0:e1d164542663 | 781 | /* Set the new register value */ |
bcostm | 0:e1d164542663 | 782 | IOE_Write(DeviceAddr, STMPE811_REG_SYS_CTRL2, mode); |
bcostm | 0:e1d164542663 | 783 | |
bcostm | 0:e1d164542663 | 784 | /* Select Sample Time, bit number and ADC Reference */ |
bcostm | 0:e1d164542663 | 785 | IOE_Write(DeviceAddr, STMPE811_REG_ADC_CTRL1, 0x49); |
bcostm | 0:e1d164542663 | 786 | |
bcostm | 0:e1d164542663 | 787 | /* Wait for 2 ms */ |
bcostm | 0:e1d164542663 | 788 | IOE_Delay(2); |
bcostm | 0:e1d164542663 | 789 | |
bcostm | 0:e1d164542663 | 790 | /* Select the ADC clock speed: 3.25 MHz */ |
bcostm | 0:e1d164542663 | 791 | IOE_Write(DeviceAddr, STMPE811_REG_ADC_CTRL2, 0x01); |
bcostm | 0:e1d164542663 | 792 | |
bcostm | 0:e1d164542663 | 793 | /* Select 2 nF filter capacitor */ |
bcostm | 0:e1d164542663 | 794 | /* Configuration: |
bcostm | 0:e1d164542663 | 795 | - Touch average control : 4 samples |
bcostm | 0:e1d164542663 | 796 | - Touch delay time : 500 uS |
bcostm | 0:e1d164542663 | 797 | - Panel driver setting time: 500 uS |
bcostm | 0:e1d164542663 | 798 | */ |
bcostm | 0:e1d164542663 | 799 | IOE_Write(DeviceAddr, STMPE811_REG_TSC_CFG, 0x9A); |
bcostm | 0:e1d164542663 | 800 | |
bcostm | 0:e1d164542663 | 801 | /* Configure the Touch FIFO threshold: single point reading */ |
bcostm | 0:e1d164542663 | 802 | IOE_Write(DeviceAddr, STMPE811_REG_FIFO_TH, 0x01); |
bcostm | 0:e1d164542663 | 803 | |
bcostm | 0:e1d164542663 | 804 | /* Clear the FIFO memory content. */ |
bcostm | 0:e1d164542663 | 805 | IOE_Write(DeviceAddr, STMPE811_REG_FIFO_STA, 0x01); |
bcostm | 0:e1d164542663 | 806 | |
bcostm | 0:e1d164542663 | 807 | /* Put the FIFO back into operation mode */ |
bcostm | 0:e1d164542663 | 808 | IOE_Write(DeviceAddr, STMPE811_REG_FIFO_STA, 0x00); |
bcostm | 0:e1d164542663 | 809 | |
bcostm | 0:e1d164542663 | 810 | /* Set the range and accuracy pf the pressure measurement (Z) : |
bcostm | 0:e1d164542663 | 811 | - Fractional part :7 |
bcostm | 0:e1d164542663 | 812 | - Whole part :1 |
bcostm | 0:e1d164542663 | 813 | */ |
bcostm | 0:e1d164542663 | 814 | IOE_Write(DeviceAddr, STMPE811_REG_TSC_FRACT_XYZ, 0x01); |
bcostm | 0:e1d164542663 | 815 | |
bcostm | 0:e1d164542663 | 816 | /* Set the driving capability (limit) of the device for TSC pins: 50mA */ |
bcostm | 0:e1d164542663 | 817 | IOE_Write(DeviceAddr, STMPE811_REG_TSC_I_DRIVE, 0x01); |
bcostm | 0:e1d164542663 | 818 | |
bcostm | 0:e1d164542663 | 819 | /* Touch screen control configuration (enable TSC): |
bcostm | 0:e1d164542663 | 820 | - No window tracking index |
bcostm | 0:e1d164542663 | 821 | - XYZ acquisition mode |
bcostm | 0:e1d164542663 | 822 | */ |
bcostm | 0:e1d164542663 | 823 | IOE_Write(DeviceAddr, STMPE811_REG_TSC_CTRL, 0x01); |
bcostm | 0:e1d164542663 | 824 | |
bcostm | 0:e1d164542663 | 825 | /* Clear all the status pending bits if any */ |
bcostm | 0:e1d164542663 | 826 | IOE_Write(DeviceAddr, STMPE811_REG_INT_STA, 0xFF); |
bcostm | 0:e1d164542663 | 827 | |
bcostm | 0:e1d164542663 | 828 | /* Wait for 2 ms delay */ |
bcostm | 0:e1d164542663 | 829 | IOE_Delay(2); |
bcostm | 0:e1d164542663 | 830 | } |
bcostm | 0:e1d164542663 | 831 | |
bcostm | 0:e1d164542663 | 832 | /** |
bcostm | 0:e1d164542663 | 833 | * @brief Return if there is touch detected or not. |
bcostm | 0:e1d164542663 | 834 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 835 | * @retval Touch detected state. |
bcostm | 0:e1d164542663 | 836 | */ |
bcostm | 0:e1d164542663 | 837 | uint8_t stmpe811_TS_DetectTouch(uint16_t DeviceAddr) |
bcostm | 0:e1d164542663 | 838 | { |
bcostm | 0:e1d164542663 | 839 | uint8_t state; |
bcostm | 0:e1d164542663 | 840 | uint8_t ret = 0; |
bcostm | 0:e1d164542663 | 841 | |
bcostm | 0:e1d164542663 | 842 | state = ((IOE_Read(DeviceAddr, STMPE811_REG_TSC_CTRL) & (uint8_t)STMPE811_TS_CTRL_STATUS) == (uint8_t)0x80); |
bcostm | 0:e1d164542663 | 843 | |
bcostm | 0:e1d164542663 | 844 | if(state > 0) |
bcostm | 0:e1d164542663 | 845 | { |
bcostm | 0:e1d164542663 | 846 | if(IOE_Read(DeviceAddr, STMPE811_REG_FIFO_SIZE) > 0) |
bcostm | 0:e1d164542663 | 847 | { |
bcostm | 0:e1d164542663 | 848 | ret = 1; |
bcostm | 0:e1d164542663 | 849 | } |
bcostm | 0:e1d164542663 | 850 | } |
bcostm | 0:e1d164542663 | 851 | else |
bcostm | 0:e1d164542663 | 852 | { |
bcostm | 0:e1d164542663 | 853 | /* Reset FIFO */ |
bcostm | 0:e1d164542663 | 854 | IOE_Write(DeviceAddr, STMPE811_REG_FIFO_STA, 0x01); |
bcostm | 0:e1d164542663 | 855 | /* Enable the FIFO again */ |
bcostm | 0:e1d164542663 | 856 | IOE_Write(DeviceAddr, STMPE811_REG_FIFO_STA, 0x00); |
bcostm | 0:e1d164542663 | 857 | } |
bcostm | 0:e1d164542663 | 858 | |
bcostm | 0:e1d164542663 | 859 | return ret; |
bcostm | 0:e1d164542663 | 860 | } |
bcostm | 0:e1d164542663 | 861 | |
bcostm | 0:e1d164542663 | 862 | /** |
bcostm | 0:e1d164542663 | 863 | * @brief Get the touch screen X and Y positions values |
bcostm | 0:e1d164542663 | 864 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 865 | * @param X: Pointer to X position value |
bcostm | 0:e1d164542663 | 866 | * @param Y: Pointer to Y position value |
bcostm | 0:e1d164542663 | 867 | * @retval None. |
bcostm | 0:e1d164542663 | 868 | */ |
bcostm | 0:e1d164542663 | 869 | void stmpe811_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y) |
bcostm | 0:e1d164542663 | 870 | { |
bcostm | 0:e1d164542663 | 871 | uint8_t dataXYZ[4]; |
bcostm | 0:e1d164542663 | 872 | uint32_t uldataXYZ; |
bcostm | 0:e1d164542663 | 873 | |
bcostm | 0:e1d164542663 | 874 | IOE_ReadMultiple(DeviceAddr, STMPE811_REG_TSC_DATA_NON_INC, dataXYZ, sizeof(dataXYZ)) ; |
bcostm | 0:e1d164542663 | 875 | |
bcostm | 0:e1d164542663 | 876 | /* Calculate positions values */ |
bcostm | 0:e1d164542663 | 877 | uldataXYZ = (dataXYZ[0] << 24)|(dataXYZ[1] << 16)|(dataXYZ[2] << 8)|(dataXYZ[3] << 0); |
bcostm | 0:e1d164542663 | 878 | *X = (uldataXYZ >> 20) & 0x00000FFF; |
bcostm | 0:e1d164542663 | 879 | *Y = (uldataXYZ >> 8) & 0x00000FFF; |
bcostm | 0:e1d164542663 | 880 | |
bcostm | 0:e1d164542663 | 881 | /* Reset FIFO */ |
bcostm | 0:e1d164542663 | 882 | IOE_Write(DeviceAddr, STMPE811_REG_FIFO_STA, 0x01); |
bcostm | 0:e1d164542663 | 883 | /* Enable the FIFO again */ |
bcostm | 0:e1d164542663 | 884 | IOE_Write(DeviceAddr, STMPE811_REG_FIFO_STA, 0x00); |
bcostm | 0:e1d164542663 | 885 | } |
bcostm | 0:e1d164542663 | 886 | |
bcostm | 0:e1d164542663 | 887 | /** |
bcostm | 0:e1d164542663 | 888 | * @brief Configure the selected source to generate a global interrupt or not |
bcostm | 0:e1d164542663 | 889 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 890 | * @retval None |
bcostm | 0:e1d164542663 | 891 | */ |
bcostm | 0:e1d164542663 | 892 | void stmpe811_TS_EnableIT(uint16_t DeviceAddr) |
bcostm | 0:e1d164542663 | 893 | { |
bcostm | 0:e1d164542663 | 894 | IOE_ITConfig(); |
bcostm | 0:e1d164542663 | 895 | |
bcostm | 0:e1d164542663 | 896 | /* Enable global TS IT source */ |
bcostm | 0:e1d164542663 | 897 | stmpe811_EnableITSource(DeviceAddr, STMPE811_TS_IT); |
bcostm | 0:e1d164542663 | 898 | |
bcostm | 0:e1d164542663 | 899 | /* Enable global interrupt */ |
bcostm | 0:e1d164542663 | 900 | stmpe811_EnableGlobalIT(DeviceAddr); |
bcostm | 0:e1d164542663 | 901 | } |
bcostm | 0:e1d164542663 | 902 | |
bcostm | 0:e1d164542663 | 903 | /** |
bcostm | 0:e1d164542663 | 904 | * @brief Configure the selected source to generate a global interrupt or not |
bcostm | 0:e1d164542663 | 905 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 906 | * @retval None |
bcostm | 0:e1d164542663 | 907 | */ |
bcostm | 0:e1d164542663 | 908 | void stmpe811_TS_DisableIT(uint16_t DeviceAddr) |
bcostm | 0:e1d164542663 | 909 | { |
bcostm | 0:e1d164542663 | 910 | /* Disable global interrupt */ |
bcostm | 0:e1d164542663 | 911 | stmpe811_DisableGlobalIT(DeviceAddr); |
bcostm | 0:e1d164542663 | 912 | |
bcostm | 0:e1d164542663 | 913 | /* Disable global TS IT source */ |
bcostm | 0:e1d164542663 | 914 | stmpe811_DisableITSource(DeviceAddr, STMPE811_TS_IT); |
bcostm | 0:e1d164542663 | 915 | } |
bcostm | 0:e1d164542663 | 916 | |
bcostm | 0:e1d164542663 | 917 | /** |
bcostm | 0:e1d164542663 | 918 | * @brief Configure the selected source to generate a global interrupt or not |
bcostm | 0:e1d164542663 | 919 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 920 | * @retval TS interrupts status |
bcostm | 0:e1d164542663 | 921 | */ |
bcostm | 0:e1d164542663 | 922 | uint8_t stmpe811_TS_ITStatus(uint16_t DeviceAddr) |
bcostm | 0:e1d164542663 | 923 | { |
bcostm | 0:e1d164542663 | 924 | /* Return TS interrupts status */ |
bcostm | 0:e1d164542663 | 925 | return(stmpe811_ReadGITStatus(DeviceAddr, STMPE811_TS_IT)); |
bcostm | 0:e1d164542663 | 926 | } |
bcostm | 0:e1d164542663 | 927 | |
bcostm | 0:e1d164542663 | 928 | /** |
bcostm | 0:e1d164542663 | 929 | * @brief Configure the selected source to generate a global interrupt or not |
bcostm | 0:e1d164542663 | 930 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 931 | * @retval None |
bcostm | 0:e1d164542663 | 932 | */ |
bcostm | 0:e1d164542663 | 933 | void stmpe811_TS_ClearIT(uint16_t DeviceAddr) |
bcostm | 0:e1d164542663 | 934 | { |
bcostm | 0:e1d164542663 | 935 | /* Clear the global TS IT source */ |
bcostm | 0:e1d164542663 | 936 | stmpe811_ClearGlobalIT(DeviceAddr, STMPE811_TS_IT); |
bcostm | 0:e1d164542663 | 937 | } |
bcostm | 0:e1d164542663 | 938 | |
bcostm | 0:e1d164542663 | 939 | /** |
bcostm | 0:e1d164542663 | 940 | * @brief Check if the device instance of the selected address is already registered |
bcostm | 0:e1d164542663 | 941 | * and return its index |
bcostm | 0:e1d164542663 | 942 | * @param DeviceAddr: Device address on communication Bus. |
bcostm | 0:e1d164542663 | 943 | * @retval Index of the device instance if registered, 0xFF if not. |
bcostm | 0:e1d164542663 | 944 | */ |
bcostm | 0:e1d164542663 | 945 | static uint8_t stmpe811_GetInstance(uint16_t DeviceAddr) |
bcostm | 0:e1d164542663 | 946 | { |
bcostm | 0:e1d164542663 | 947 | uint8_t idx = 0; |
bcostm | 0:e1d164542663 | 948 | |
bcostm | 0:e1d164542663 | 949 | /* Check all the registered instances */ |
bcostm | 0:e1d164542663 | 950 | for(idx = 0; idx < STMPE811_MAX_INSTANCE ; idx ++) |
bcostm | 0:e1d164542663 | 951 | { |
bcostm | 0:e1d164542663 | 952 | if(stmpe811[idx] == DeviceAddr) |
bcostm | 0:e1d164542663 | 953 | { |
bcostm | 0:e1d164542663 | 954 | return idx; |
bcostm | 0:e1d164542663 | 955 | } |
bcostm | 0:e1d164542663 | 956 | } |
bcostm | 0:e1d164542663 | 957 | |
bcostm | 0:e1d164542663 | 958 | return 0xFF; |
bcostm | 0:e1d164542663 | 959 | } |
bcostm | 0:e1d164542663 | 960 | |
bcostm | 0:e1d164542663 | 961 | /** |
bcostm | 0:e1d164542663 | 962 | * @} |
bcostm | 0:e1d164542663 | 963 | */ |
bcostm | 0:e1d164542663 | 964 | |
bcostm | 0:e1d164542663 | 965 | /** |
bcostm | 0:e1d164542663 | 966 | * @} |
bcostm | 0:e1d164542663 | 967 | */ |
bcostm | 0:e1d164542663 | 968 | |
bcostm | 0:e1d164542663 | 969 | /** |
bcostm | 0:e1d164542663 | 970 | * @} |
bcostm | 0:e1d164542663 | 971 | */ |
bcostm | 0:e1d164542663 | 972 | |
bcostm | 0:e1d164542663 | 973 | /** |
bcostm | 0:e1d164542663 | 974 | * @} |
bcostm | 0:e1d164542663 | 975 | */ |
bcostm | 0:e1d164542663 | 976 | |
bcostm | 0:e1d164542663 | 977 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |