core_cm4.h

00001 /**************************************************************************//**
00002  * @file     core_cm4.h
00003  * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
00004  * @version  V3.02
00005  * @date     16. July 2012
00006  *
00007  * @note
00008  * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
00009  *
00010  * @par
00011  * ARM Limited (ARM) is supplying this software for use with Cortex-M
00012  * processor based microcontrollers.  This file can be freely distributed
00013  * within development tools that are supporting such ARM based processors.
00014  *
00015  * @par
00016  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
00017  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
00018  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
00019  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
00020  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
00021  *
00022  ******************************************************************************/
00023 #if defined ( __ICCARM__ )
00024  #pragma system_include  /* treat file as system include file for MISRA check */
00025 #endif
00026 
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030 
00031 #ifndef __CORE_CM4_H_GENERIC
00032 #define __CORE_CM4_H_GENERIC
00033 
00034 /** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
00035   CMSIS violates the following MISRA-C:2004 rules:
00036 
00037    \li Required Rule 8.5, object/function definition in header file.<br>
00038      Function definitions in header files are used to allow 'inlining'.
00039 
00040    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
00041      Unions are used for effective representation of core registers.
00042 
00043    \li Advisory Rule 19.7, Function-like macro defined.<br>
00044      Function-like macros are used to allow more efficient code.
00045  */
00046 
00047 
00048 /*******************************************************************************
00049  *                 CMSIS definitions
00050  ******************************************************************************/
00051 /** \ingroup Cortex_M4
00052   @{
00053  */
00054 
00055 /*  CMSIS CM4 definitions */
00056 #define __CM4_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
00057 #define __CM4_CMSIS_VERSION_SUB   (0x01)                                   /*!< [15:0]  CMSIS HAL sub version    */
00058 #define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
00059                                     __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
00060 
00061 #define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
00062 
00063 
00064 #if   defined ( __CC_ARM )
00065   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
00066   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
00067   #define __STATIC_INLINE  static __inline
00068 
00069 #elif defined ( __ICCARM__ )
00070   #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
00071   #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
00072   #define __STATIC_INLINE  static inline
00073 
00074 #elif defined ( __TMS470__ )
00075   #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
00076   #define __STATIC_INLINE  static inline
00077 
00078 #elif defined ( __GNUC__ )
00079   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
00080   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
00081   #define __STATIC_INLINE  static inline
00082 
00083 #elif defined ( __TASKING__ )
00084   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
00085   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
00086   #define __STATIC_INLINE  static inline
00087 
00088 #endif
00089 
00090 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
00091 */
00092 #if defined ( __CC_ARM )
00093   #if defined __TARGET_FPU_VFP
00094     #if (__FPU_PRESENT == 1)
00095       #define __FPU_USED       1
00096     #else
00097       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00098       #define __FPU_USED       0
00099     #endif
00100   #else
00101     #define __FPU_USED         0
00102   #endif
00103 
00104 #elif defined ( __ICCARM__ )
00105   #if defined __ARMVFP__
00106     #if (__FPU_PRESENT == 1)
00107       #define __FPU_USED       1
00108     #else
00109       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00110       #define __FPU_USED       0
00111     #endif
00112   #else
00113     #define __FPU_USED         0
00114   #endif
00115 
00116 #elif defined ( __TMS470__ )
00117   #if defined __TI_VFP_SUPPORT__
00118     #if (__FPU_PRESENT == 1)
00119       #define __FPU_USED       1
00120     #else
00121       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00122       #define __FPU_USED       0
00123     #endif
00124   #else
00125     #define __FPU_USED         0
00126   #endif
00127 
00128 #elif defined ( __GNUC__ )
00129   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
00130     #if (__FPU_PRESENT == 1)
00131       #define __FPU_USED       1
00132     #else
00133       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00134       #define __FPU_USED       0
00135     #endif
00136   #else
00137     #define __FPU_USED         0
00138   #endif
00139 
00140 #elif defined ( __TASKING__ )
00141   #if defined __FPU_VFP__
00142     #if (__FPU_PRESENT == 1)
00143       #define __FPU_USED       1
00144     #else
00145       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00146       #define __FPU_USED       0
00147     #endif
00148   #else
00149     #define __FPU_USED         0
00150   #endif
00151 #endif
00152 
00153 #include <stdint.h>                      /* standard types definitions                      */
00154 #include <core_cmInstr.h>                /* Core Instruction Access                         */
00155 #include <core_cmFunc.h>                 /* Core Function Access                            */
00156 #include <core_cm4_simd.h>               /* Compiler specific SIMD Intrinsics               */
00157 
00158 #endif /* __CORE_CM4_H_GENERIC */
00159 
00160 #ifndef __CMSIS_GENERIC
00161 
00162 #ifndef __CORE_CM4_H_DEPENDANT
00163 #define __CORE_CM4_H_DEPENDANT
00164 
00165 /* check device defines and use defaults */
00166 #if defined __CHECK_DEVICE_DEFINES
00167   #ifndef __CM4_REV
00168     #define __CM4_REV               0x0000
00169     #warning "__CM4_REV not defined in device header file; using default!"
00170   #endif
00171 
00172   #ifndef __FPU_PRESENT
00173     #define __FPU_PRESENT             0
00174     #warning "__FPU_PRESENT not defined in device header file; using default!"
00175   #endif
00176 
00177   #ifndef __MPU_PRESENT
00178     #define __MPU_PRESENT             0
00179     #warning "__MPU_PRESENT not defined in device header file; using default!"
00180   #endif
00181 
00182   #ifndef __NVIC_PRIO_BITS
00183     #define __NVIC_PRIO_BITS          4
00184     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
00185   #endif
00186 
00187   #ifndef __Vendor_SysTickConfig
00188     #define __Vendor_SysTickConfig    0
00189     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
00190   #endif
00191 #endif
00192 
00193 /* IO definitions (access restrictions to peripheral registers) */
00194 /**
00195     \defgroup CMSIS_glob_defs CMSIS Global Defines
00196 
00197     <strong>IO Type Qualifiers</strong> are used
00198     \li to specify the access to peripheral variables.
00199     \li for automatic generation of peripheral register debug information.
00200 */
00201 #ifdef __cplusplus
00202   #define   __I     volatile             /*!< Defines 'read only' permissions                 */
00203 #else
00204   #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
00205 #endif
00206 #define     __O     volatile             /*!< Defines 'write only' permissions                */
00207 #define     __IO    volatile             /*!< Defines 'read / write' permissions              */
00208 
00209 /*@} end of group Cortex_M4 */
00210 
00211 
00212 
00213 /*******************************************************************************
00214  *                 Register Abstraction
00215   Core Register contain:
00216   - Core Register
00217   - Core NVIC Register
00218   - Core SCB Register
00219   - Core SysTick Register
00220   - Core Debug Register
00221   - Core MPU Register
00222   - Core FPU Register
00223  ******************************************************************************/
00224 /** \defgroup CMSIS_core_register Defines and Type Definitions
00225     \brief Type definitions and defines for Cortex-M processor based devices.
00226 */
00227 
00228 /** \ingroup    CMSIS_core_register
00229     \defgroup   CMSIS_CORE  Status and Control Registers
00230     \brief  Core Register type definitions.
00231   @{
00232  */
00233 
00234 /** \brief  Union type to access the Application Program Status Register (APSR).
00235  */
00236 typedef union
00237 {
00238   struct
00239   {
00240 #if (__CORTEX_M != 0x04)
00241     uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
00242 #else
00243     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
00244     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
00245     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
00246 #endif
00247     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
00248     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
00249     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
00250     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
00251     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
00252   } b;                                   /*!< Structure used for bit  access                  */
00253   uint32_t w;                            /*!< Type      used for word access                  */
00254 } APSR_Type;
00255 
00256 
00257 /** \brief  Union type to access the Interrupt Program Status Register (IPSR).
00258  */
00259 typedef union
00260 {
00261   struct
00262   {
00263     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
00264     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
00265   } b;                                   /*!< Structure used for bit  access                  */
00266   uint32_t w;                            /*!< Type      used for word access                  */
00267 } IPSR_Type;
00268 
00269 
00270 /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
00271  */
00272 typedef union
00273 {
00274   struct
00275   {
00276     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
00277 #if (__CORTEX_M != 0x04)
00278     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
00279 #else
00280     uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
00281     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
00282     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
00283 #endif
00284     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
00285     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
00286     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
00287     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
00288     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
00289     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
00290     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
00291   } b;                                   /*!< Structure used for bit  access                  */
00292   uint32_t w;                            /*!< Type      used for word access                  */
00293 } xPSR_Type;
00294 
00295 
00296 /** \brief  Union type to access the Control Registers (CONTROL).
00297  */
00298 typedef union
00299 {
00300   struct
00301   {
00302     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
00303     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
00304     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
00305     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
00306   } b;                                   /*!< Structure used for bit  access                  */
00307   uint32_t w;                            /*!< Type      used for word access                  */
00308 } CONTROL_Type;
00309 
00310 /*@} end of group CMSIS_CORE */
00311 
00312 
00313 /** \ingroup    CMSIS_core_register
00314     \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
00315     \brief      Type definitions for the NVIC Registers
00316   @{
00317  */
00318 
00319 /** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
00320  */
00321 typedef struct
00322 {
00323   __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
00324        uint32_t RESERVED0[24];
00325   __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
00326        uint32_t RSERVED1[24];
00327   __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
00328        uint32_t RESERVED2[24];
00329   __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
00330        uint32_t RESERVED3[24];
00331   __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
00332        uint32_t RESERVED4[56];
00333   __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
00334        uint32_t RESERVED5[644];
00335   __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
00336 }  NVIC_Type;
00337 
00338 /* Software Triggered Interrupt Register Definitions */
00339 #define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
00340 #define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
00341 
00342 /*@} end of group CMSIS_NVIC */
00343 
00344 
00345 /** \ingroup  CMSIS_core_register
00346     \defgroup CMSIS_SCB     System Control Block (SCB)
00347     \brief      Type definitions for the System Control Block Registers
00348   @{
00349  */
00350 
00351 /** \brief  Structure type to access the System Control Block (SCB).
00352  */
00353 typedef struct
00354 {
00355   __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
00356   __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
00357   __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
00358   __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
00359   __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
00360   __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
00361   __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
00362   __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
00363   __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
00364   __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
00365   __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
00366   __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
00367   __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
00368   __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
00369   __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
00370   __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
00371   __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
00372   __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
00373   __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
00374        uint32_t RESERVED0[5];
00375   __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
00376 } SCB_Type;
00377 
00378 /* SCB CPUID Register Definitions */
00379 #define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
00380 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
00381 
00382 #define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
00383 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
00384 
00385 #define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
00386 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
00387 
00388 #define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
00389 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
00390 
00391 #define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
00392 #define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
00393 
00394 /* SCB Interrupt Control State Register Definitions */
00395 #define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
00396 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
00397 
00398 #define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
00399 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
00400 
00401 #define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
00402 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
00403 
00404 #define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
00405 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
00406 
00407 #define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
00408 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
00409 
00410 #define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
00411 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
00412 
00413 #define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
00414 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
00415 
00416 #define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
00417 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
00418 
00419 #define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
00420 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
00421 
00422 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
00423 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
00424 
00425 /* SCB Vector Table Offset Register Definitions */
00426 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
00427 #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
00428 
00429 /* SCB Application Interrupt and Reset Control Register Definitions */
00430 #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
00431 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
00432 
00433 #define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
00434 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
00435 
00436 #define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
00437 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
00438 
00439 #define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
00440 #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
00441 
00442 #define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
00443 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
00444 
00445 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
00446 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
00447 
00448 #define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
00449 #define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
00450 
00451 /* SCB System Control Register Definitions */
00452 #define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
00453 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
00454 
00455 #define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
00456 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
00457 
00458 #define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
00459 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
00460 
00461 /* SCB Configuration Control Register Definitions */
00462 #define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
00463 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
00464 
00465 #define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
00466 #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
00467 
00468 #define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
00469 #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
00470 
00471 #define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
00472 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
00473 
00474 #define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
00475 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
00476 
00477 #define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
00478 #define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
00479 
00480 /* SCB System Handler Control and State Register Definitions */
00481 #define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
00482 #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
00483 
00484 #define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
00485 #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
00486 
00487 #define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
00488 #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
00489 
00490 #define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
00491 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
00492 
00493 #define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
00494 #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
00495 
00496 #define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
00497 #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
00498 
00499 #define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
00500 #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
00501 
00502 #define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
00503 #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
00504 
00505 #define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
00506 #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
00507 
00508 #define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
00509 #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
00510 
00511 #define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
00512 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
00513 
00514 #define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
00515 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
00516 
00517 #define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
00518 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
00519 
00520 #define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
00521 #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
00522 
00523 /* SCB Configurable Fault Status Registers Definitions */
00524 #define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
00525 #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
00526 
00527 #define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
00528 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
00529 
00530 #define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
00531 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
00532 
00533 /* SCB Hard Fault Status Registers Definitions */
00534 #define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
00535 #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
00536 
00537 #define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
00538 #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
00539 
00540 #define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
00541 #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
00542 
00543 /* SCB Debug Fault Status Register Definitions */
00544 #define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
00545 #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
00546 
00547 #define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
00548 #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
00549 
00550 #define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
00551 #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
00552 
00553 #define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
00554 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
00555 
00556 #define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
00557 #define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
00558 
00559 /*@} end of group CMSIS_SCB */
00560 
00561 
00562 /** \ingroup  CMSIS_core_register
00563     \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
00564     \brief      Type definitions for the System Control and ID Register not in the SCB
00565   @{
00566  */
00567 
00568 /** \brief  Structure type to access the System Control and ID Register not in the SCB.
00569  */
00570 typedef struct
00571 {
00572        uint32_t RESERVED0[1];
00573   __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
00574   __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
00575 } SCnSCB_Type;
00576 
00577 /* Interrupt Controller Type Register Definitions */
00578 #define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
00579 #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
00580 
00581 /* Auxiliary Control Register Definitions */
00582 #define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
00583 #define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
00584 
00585 #define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
00586 #define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
00587 
00588 #define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
00589 #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
00590 
00591 #define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
00592 #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
00593 
00594 #define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
00595 #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
00596 
00597 /*@} end of group CMSIS_SCnotSCB */
00598 
00599 
00600 /** \ingroup  CMSIS_core_register
00601     \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
00602     \brief      Type definitions for the System Timer Registers.
00603   @{
00604  */
00605 
00606 /** \brief  Structure type to access the System Timer (SysTick).
00607  */
00608 typedef struct
00609 {
00610   __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
00611   __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
00612   __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
00613   __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
00614 } SysTick_Type;
00615 
00616 /* SysTick Control / Status Register Definitions */
00617 #define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
00618 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
00619 
00620 #define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
00621 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
00622 
00623 #define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
00624 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
00625 
00626 #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
00627 #define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
00628 
00629 /* SysTick Reload Register Definitions */
00630 #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
00631 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
00632 
00633 /* SysTick Current Register Definitions */
00634 #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
00635 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
00636 
00637 /* SysTick Calibration Register Definitions */
00638 #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
00639 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
00640 
00641 #define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
00642 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
00643 
00644 #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
00645 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
00646 
00647 /*@} end of group CMSIS_SysTick */
00648 
00649 
00650 /** \ingroup  CMSIS_core_register
00651     \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
00652     \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
00653   @{
00654  */
00655 
00656 /** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
00657  */
00658 typedef struct
00659 {
00660   __O  union
00661   {
00662     __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
00663     __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
00664     __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
00665   }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
00666        uint32_t RESERVED0[864];
00667   __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
00668        uint32_t RESERVED1[15];
00669   __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
00670        uint32_t RESERVED2[15];
00671   __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
00672        uint32_t RESERVED3[29];
00673   __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
00674   __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
00675   __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
00676        uint32_t RESERVED4[43];
00677   __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
00678   __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
00679        uint32_t RESERVED5[6];
00680   __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
00681   __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
00682   __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
00683   __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
00684   __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
00685   __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
00686   __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
00687   __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
00688   __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
00689   __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
00690   __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
00691   __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
00692 } ITM_Type;
00693 
00694 /* ITM Trace Privilege Register Definitions */
00695 #define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
00696 #define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
00697 
00698 /* ITM Trace Control Register Definitions */
00699 #define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
00700 #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
00701 
00702 #define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
00703 #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
00704 
00705 #define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
00706 #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
00707 
00708 #define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
00709 #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
00710 
00711 #define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
00712 #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
00713 
00714 #define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
00715 #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
00716 
00717 #define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
00718 #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
00719 
00720 #define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
00721 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
00722 
00723 #define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
00724 #define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
00725 
00726 /* ITM Integration Write Register Definitions */
00727 #define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
00728 #define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
00729 
00730 /* ITM Integration Read Register Definitions */
00731 #define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
00732 #define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
00733 
00734 /* ITM Integration Mode Control Register Definitions */
00735 #define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
00736 #define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
00737 
00738 /* ITM Lock Status Register Definitions */
00739 #define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
00740 #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
00741 
00742 #define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
00743 #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
00744 
00745 #define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
00746 #define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
00747 
00748 /*@}*/ /* end of group CMSIS_ITM */
00749 
00750 
00751 /** \ingroup  CMSIS_core_register
00752     \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
00753     \brief      Type definitions for the Data Watchpoint and Trace (DWT)
00754   @{
00755  */
00756 
00757 /** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
00758  */
00759 typedef struct
00760 {
00761   __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
00762   __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
00763   __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
00764   __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
00765   __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
00766   __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
00767   __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
00768   __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
00769   __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
00770   __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
00771   __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
00772        uint32_t RESERVED0[1];
00773   __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
00774   __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
00775   __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
00776        uint32_t RESERVED1[1];
00777   __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
00778   __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
00779   __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
00780        uint32_t RESERVED2[1];
00781   __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
00782   __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
00783   __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
00784 } DWT_Type;
00785 
00786 /* DWT Control Register Definitions */
00787 #define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
00788 #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
00789 
00790 #define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
00791 #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
00792 
00793 #define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
00794 #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
00795 
00796 #define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
00797 #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
00798 
00799 #define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
00800 #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
00801 
00802 #define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
00803 #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
00804 
00805 #define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
00806 #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
00807 
00808 #define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
00809 #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
00810 
00811 #define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
00812 #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
00813 
00814 #define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
00815 #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
00816 
00817 #define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
00818 #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
00819 
00820 #define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
00821 #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
00822 
00823 #define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
00824 #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
00825 
00826 #define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
00827 #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
00828 
00829 #define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
00830 #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
00831 
00832 #define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
00833 #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
00834 
00835 #define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
00836 #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
00837 
00838 #define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
00839 #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
00840 
00841 /* DWT CPI Count Register Definitions */
00842 #define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
00843 #define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
00844 
00845 /* DWT Exception Overhead Count Register Definitions */
00846 #define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
00847 #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
00848 
00849 /* DWT Sleep Count Register Definitions */
00850 #define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
00851 #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
00852 
00853 /* DWT LSU Count Register Definitions */
00854 #define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
00855 #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
00856 
00857 /* DWT Folded-instruction Count Register Definitions */
00858 #define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
00859 #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
00860 
00861 /* DWT Comparator Mask Register Definitions */
00862 #define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
00863 #define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
00864 
00865 /* DWT Comparator Function Register Definitions */
00866 #define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
00867 #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
00868 
00869 #define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
00870 #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
00871 
00872 #define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
00873 #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
00874 
00875 #define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
00876 #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
00877 
00878 #define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
00879 #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
00880 
00881 #define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
00882 #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
00883 
00884 #define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
00885 #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
00886 
00887 #define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
00888 #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
00889 
00890 #define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
00891 #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
00892 
00893 /*@}*/ /* end of group CMSIS_DWT */
00894 
00895 
00896 /** \ingroup  CMSIS_core_register
00897     \defgroup CMSIS_TPI     Trace Port Interface (TPI)
00898     \brief      Type definitions for the Trace Port Interface (TPI)
00899   @{
00900  */
00901 
00902 /** \brief  Structure type to access the Trace Port Interface Register (TPI).
00903  */
00904 typedef struct
00905 {
00906   __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
00907   __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
00908        uint32_t RESERVED0[2];
00909   __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
00910        uint32_t RESERVED1[55];
00911   __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
00912        uint32_t RESERVED2[131];
00913   __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
00914   __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
00915   __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
00916        uint32_t RESERVED3[759];
00917   __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
00918   __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
00919   __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
00920        uint32_t RESERVED4[1];
00921   __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
00922   __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
00923   __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
00924        uint32_t RESERVED5[39];
00925   __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
00926   __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
00927        uint32_t RESERVED7[8];
00928   __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
00929   __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
00930 } TPI_Type;
00931 
00932 /* TPI Asynchronous Clock Prescaler Register Definitions */
00933 #define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
00934 #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
00935 
00936 /* TPI Selected Pin Protocol Register Definitions */
00937 #define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
00938 #define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
00939 
00940 /* TPI Formatter and Flush Status Register Definitions */
00941 #define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
00942 #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
00943 
00944 #define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
00945 #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
00946 
00947 #define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
00948 #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
00949 
00950 #define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
00951 #define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
00952 
00953 /* TPI Formatter and Flush Control Register Definitions */
00954 #define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
00955 #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
00956 
00957 #define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
00958 #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
00959 
00960 /* TPI TRIGGER Register Definitions */
00961 #define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
00962 #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
00963 
00964 /* TPI Integration ETM Data Register Definitions (FIFO0) */
00965 #define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
00966 #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
00967 
00968 #define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
00969 #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
00970 
00971 #define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
00972 #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
00973 
00974 #define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
00975 #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
00976 
00977 #define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
00978 #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
00979 
00980 #define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
00981 #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
00982 
00983 #define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
00984 #define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
00985 
00986 /* TPI ITATBCTR2 Register Definitions */
00987 #define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
00988 #define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
00989 
00990 /* TPI Integration ITM Data Register Definitions (FIFO1) */
00991 #define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
00992 #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
00993 
00994 #define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
00995 #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
00996 
00997 #define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
00998 #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
00999 
01000 #define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
01001 #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
01002 
01003 #define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
01004 #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
01005 
01006 #define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
01007 #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
01008 
01009 #define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
01010 #define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
01011 
01012 /* TPI ITATBCTR0 Register Definitions */
01013 #define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
01014 #define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
01015 
01016 /* TPI Integration Mode Control Register Definitions */
01017 #define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
01018 #define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
01019 
01020 /* TPI DEVID Register Definitions */
01021 #define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
01022 #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
01023 
01024 #define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
01025 #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
01026 
01027 #define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
01028 #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
01029 
01030 #define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
01031 #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
01032 
01033 #define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
01034 #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
01035 
01036 #define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
01037 #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
01038 
01039 /* TPI DEVTYPE Register Definitions */
01040 #define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
01041 #define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
01042 
01043 #define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
01044 #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
01045 
01046 /*@}*/ /* end of group CMSIS_TPI */
01047 
01048 
01049 #if (__MPU_PRESENT == 1)
01050 /** \ingroup  CMSIS_core_register
01051     \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
01052     \brief      Type definitions for the Memory Protection Unit (MPU)
01053   @{
01054  */
01055 
01056 /** \brief  Structure type to access the Memory Protection Unit (MPU).
01057  */
01058 typedef struct
01059 {
01060   __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
01061   __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
01062   __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
01063   __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
01064   __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
01065   __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
01066   __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
01067   __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
01068   __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
01069   __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
01070   __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
01071 } MPU_Type;
01072 
01073 /* MPU Type Register */
01074 #define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
01075 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
01076 
01077 #define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
01078 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
01079 
01080 #define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
01081 #define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
01082 
01083 /* MPU Control Register */
01084 #define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
01085 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
01086 
01087 #define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
01088 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
01089 
01090 #define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
01091 #define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
01092 
01093 /* MPU Region Number Register */
01094 #define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
01095 #define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
01096 
01097 /* MPU Region Base Address Register */
01098 #define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
01099 #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
01100 
01101 #define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
01102 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
01103 
01104 #define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
01105 #define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
01106 
01107 /* MPU Region Attribute and Size Register */
01108 #define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
01109 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
01110 
01111 #define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
01112 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
01113 
01114 #define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
01115 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
01116 
01117 #define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
01118 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
01119 
01120 #define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
01121 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
01122 
01123 #define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
01124 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
01125 
01126 #define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
01127 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
01128 
01129 #define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
01130 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
01131 
01132 #define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
01133 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
01134 
01135 #define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
01136 #define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
01137 
01138 /*@} end of group CMSIS_MPU */
01139 #endif
01140 
01141 
01142 #if (__FPU_PRESENT == 1)
01143 /** \ingroup  CMSIS_core_register
01144     \defgroup CMSIS_FPU     Floating Point Unit (FPU)
01145     \brief      Type definitions for the Floating Point Unit (FPU)
01146   @{
01147  */
01148 
01149 /** \brief  Structure type to access the Floating Point Unit (FPU).
01150  */
01151 typedef struct
01152 {
01153        uint32_t RESERVED0[1];
01154   __IO uint32_t FPCCR ;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
01155   __IO uint32_t FPCAR ;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
01156   __IO uint32_t FPDSCR ;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
01157   __I  uint32_t MVFR0 ;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
01158   __I  uint32_t MVFR1 ;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
01159 } FPU_Type;
01160 
01161 /* Floating-Point Context Control Register */
01162 #define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
01163 #define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
01164 
01165 #define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
01166 #define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
01167 
01168 #define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
01169 #define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
01170 
01171 #define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
01172 #define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
01173 
01174 #define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
01175 #define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
01176 
01177 #define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
01178 #define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
01179 
01180 #define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
01181 #define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
01182 
01183 #define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
01184 #define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
01185 
01186 #define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
01187 #define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
01188 
01189 /* Floating-Point Context Address Register */
01190 #define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
01191 #define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
01192 
01193 /* Floating-Point Default Status Control Register */
01194 #define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
01195 #define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
01196 
01197 #define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
01198 #define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
01199 
01200 #define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
01201 #define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
01202 
01203 #define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
01204 #define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
01205 
01206 /* Media and FP Feature Register 0 */
01207 #define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
01208 #define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
01209 
01210 #define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
01211 #define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
01212 
01213 #define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
01214 #define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
01215 
01216 #define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
01217 #define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
01218 
01219 #define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
01220 #define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
01221 
01222 #define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
01223 #define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
01224 
01225 #define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
01226 #define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
01227 
01228 #define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
01229 #define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
01230 
01231 /* Media and FP Feature Register 1 */
01232 #define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
01233 #define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
01234 
01235 #define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
01236 #define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
01237 
01238 #define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
01239 #define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
01240 
01241 #define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
01242 #define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
01243 
01244 /*@} end of group CMSIS_FPU */
01245 #endif
01246 
01247 
01248 /** \ingroup  CMSIS_core_register
01249     \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
01250     \brief      Type definitions for the Core Debug Registers
01251   @{
01252  */
01253 
01254 /** \brief  Structure type to access the Core Debug Register (CoreDebug).
01255  */
01256 typedef struct
01257 {
01258   __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
01259   __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
01260   __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
01261   __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
01262 } CoreDebug_Type;
01263 
01264 /* Debug Halting Control and Status Register */
01265 #define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
01266 #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
01267 
01268 #define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
01269 #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
01270 
01271 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
01272 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
01273 
01274 #define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
01275 #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
01276 
01277 #define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
01278 #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
01279 
01280 #define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
01281 #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
01282 
01283 #define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
01284 #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
01285 
01286 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
01287 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
01288 
01289 #define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
01290 #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
01291 
01292 #define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
01293 #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
01294 
01295 #define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
01296 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
01297 
01298 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
01299 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
01300 
01301 /* Debug Core Register Selector Register */
01302 #define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
01303 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
01304 
01305 #define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
01306 #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
01307 
01308 /* Debug Exception and Monitor Control Register */
01309 #define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
01310 #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
01311 
01312 #define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
01313 #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
01314 
01315 #define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
01316 #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
01317 
01318 #define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
01319 #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
01320 
01321 #define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
01322 #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
01323 
01324 #define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
01325 #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
01326 
01327 #define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
01328 #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
01329 
01330 #define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
01331 #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
01332 
01333 #define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
01334 #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
01335 
01336 #define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
01337 #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
01338 
01339 #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
01340 #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
01341 
01342 #define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
01343 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
01344 
01345 #define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
01346 #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
01347 
01348 /*@} end of group CMSIS_CoreDebug */
01349 
01350 
01351 /** \ingroup    CMSIS_core_register
01352     \defgroup   CMSIS_core_base     Core Definitions
01353     \brief      Definitions for base addresses, unions, and structures.
01354   @{
01355  */
01356 
01357 /* Memory mapping of Cortex-M4 Hardware */
01358 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
01359 #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
01360 #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
01361 #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
01362 #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
01363 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
01364 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
01365 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
01366 
01367 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
01368 #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
01369 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
01370 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
01371 #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
01372 #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
01373 #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
01374 #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
01375 
01376 #if (__MPU_PRESENT == 1)
01377   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
01378   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
01379 #endif
01380 
01381 #if (__FPU_PRESENT == 1)
01382   #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
01383   #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
01384 #endif
01385 
01386 /*@} */
01387 
01388 
01389 
01390 /*******************************************************************************
01391  *                Hardware Abstraction Layer
01392   Core Function Interface contains:
01393   - Core NVIC Functions
01394   - Core SysTick Functions
01395   - Core Debug Functions
01396   - Core Register Access Functions
01397  ******************************************************************************/
01398 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
01399 */
01400 
01401 
01402 
01403 /* ##########################   NVIC functions  #################################### */
01404 /** \ingroup  CMSIS_Core_FunctionInterface
01405     \defgroup CMSIS_Core_NVICFunctions NVIC Functions
01406     \brief      Functions that manage interrupts and exceptions via the NVIC.
01407     @{
01408  */
01409 
01410 /** \brief  Set Priority Grouping
01411 
01412   The function sets the priority grouping field using the required unlock sequence.
01413   The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
01414   Only values from 0..7 are used.
01415   In case of a conflict between priority grouping and available
01416   priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
01417 
01418     \param [in]      PriorityGroup  Priority grouping field.
01419  */
01420 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
01421 {
01422   uint32_t reg_value;
01423   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
01424 
01425   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
01426   reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
01427   reg_value  =  (reg_value                                 |
01428                 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
01429                 (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
01430   SCB->AIRCR =  reg_value;
01431 }
01432 
01433 
01434 /** \brief  Get Priority Grouping
01435 
01436   The function reads the priority grouping field from the NVIC Interrupt Controller.
01437 
01438     \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
01439  */
01440 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
01441 {
01442   return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
01443 }
01444 
01445 
01446 /** \brief  Enable External Interrupt
01447 
01448     The function enables a device-specific interrupt in the NVIC interrupt controller.
01449 
01450     \param [in]      IRQn  External interrupt number. Value cannot be negative.
01451  */
01452 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type  IRQn)
01453 {
01454 /*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
01455   NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
01456 }
01457 
01458 
01459 /** \brief  Disable External Interrupt
01460 
01461     The function disables a device-specific interrupt in the NVIC interrupt controller.
01462 
01463     \param [in]      IRQn  External interrupt number. Value cannot be negative.
01464  */
01465 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type  IRQn)
01466 {
01467   NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
01468 }
01469 
01470 
01471 /** \brief  Get Pending Interrupt
01472 
01473     The function reads the pending register in the NVIC and returns the pending bit
01474     for the specified interrupt.
01475 
01476     \param [in]      IRQn  Interrupt number.
01477 
01478     \return             0  Interrupt status is not pending.
01479     \return             1  Interrupt status is pending.
01480  */
01481 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type  IRQn)
01482 {
01483   return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
01484 }
01485 
01486 
01487 /** \brief  Set Pending Interrupt
01488 
01489     The function sets the pending bit of an external interrupt.
01490 
01491     \param [in]      IRQn  Interrupt number. Value cannot be negative.
01492  */
01493 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type  IRQn)
01494 {
01495   NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
01496 }
01497 
01498 
01499 /** \brief  Clear Pending Interrupt
01500 
01501     The function clears the pending bit of an external interrupt.
01502 
01503     \param [in]      IRQn  External interrupt number. Value cannot be negative.
01504  */
01505 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type  IRQn)
01506 {
01507   NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
01508 }
01509 
01510 
01511 /** \brief  Get Active Interrupt
01512 
01513     The function reads the active register in NVIC and returns the active bit.
01514 
01515     \param [in]      IRQn  Interrupt number.
01516 
01517     \return             0  Interrupt status is not active.
01518     \return             1  Interrupt status is active.
01519  */
01520 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type  IRQn)
01521 {
01522   return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
01523 }
01524 
01525 
01526 /** \brief  Set Interrupt Priority
01527 
01528     The function sets the priority of an interrupt.
01529 
01530     \note The priority cannot be set for every core interrupt.
01531 
01532     \param [in]      IRQn  Interrupt number.
01533     \param [in]  priority  Priority to set.
01534  */
01535 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type  IRQn, uint32_t priority)
01536 {
01537   if(IRQn < 0) {
01538     SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
01539   else {
01540     NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
01541 }
01542 
01543 
01544 /** \brief  Get Interrupt Priority
01545 
01546     The function reads the priority of an interrupt. The interrupt
01547     number can be positive to specify an external (device specific)
01548     interrupt, or negative to specify an internal (core) interrupt.
01549 
01550 
01551     \param [in]   IRQn  Interrupt number.
01552     \return             Interrupt Priority. Value is aligned automatically to the implemented
01553                         priority bits of the microcontroller.
01554  */
01555 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type  IRQn)
01556 {
01557 
01558   if(IRQn < 0) {
01559     return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
01560   else {
01561     return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
01562 }
01563 
01564 
01565 /** \brief  Encode Priority
01566 
01567     The function encodes the priority for an interrupt with the given priority group,
01568     preemptive priority value, and subpriority value.
01569     In case of a conflict between priority grouping and available
01570     priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
01571 
01572     \param [in]     PriorityGroup  Used priority group.
01573     \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
01574     \param [in]       SubPriority  Subpriority value (starting from 0).
01575     \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
01576  */
01577 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
01578 {
01579   uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
01580   uint32_t PreemptPriorityBits;
01581   uint32_t SubPriorityBits;
01582 
01583   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
01584   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
01585 
01586   return (
01587            ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
01588            ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
01589          );
01590 }
01591 
01592 
01593 /** \brief  Decode Priority
01594 
01595     The function decodes an interrupt priority value with a given priority group to
01596     preemptive priority value and subpriority value.
01597     In case of a conflict between priority grouping and available
01598     priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
01599 
01600     \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
01601     \param [in]     PriorityGroup  Used priority group.
01602     \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
01603     \param [out]     pSubPriority  Subpriority value (starting from 0).
01604  */
01605 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
01606 {
01607   uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
01608   uint32_t PreemptPriorityBits;
01609   uint32_t SubPriorityBits;
01610 
01611   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
01612   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
01613 
01614   *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
01615   *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
01616 }
01617 
01618 
01619 /** \brief  System Reset
01620 
01621     The function initiates a system reset request to reset the MCU.
01622  */
01623 __STATIC_INLINE void NVIC_SystemReset(void)
01624 {
01625   __DSB();                                                     /* Ensure all outstanding memory accesses included
01626                                                                   buffered write are completed before reset */
01627   SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
01628                  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
01629                  SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
01630   __DSB();                                                     /* Ensure completion of memory access */
01631   while(1);                                                    /* wait until reset */
01632 }
01633 
01634 /*@} end of CMSIS_Core_NVICFunctions */
01635 
01636 
01637 
01638 /* ##################################    SysTick function  ############################################ */
01639 /** \ingroup  CMSIS_Core_FunctionInterface
01640     \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
01641     \brief      Functions that configure the System.
01642   @{
01643  */
01644 
01645 #if (__Vendor_SysTickConfig == 0)
01646 
01647 /** \brief  System Tick Configuration
01648 
01649     The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
01650     Counter is in free running mode to generate periodic interrupts.
01651 
01652     \param [in]  ticks  Number of ticks between two interrupts.
01653 
01654     \return          0  Function succeeded.
01655     \return          1  Function failed.
01656 
01657     \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
01658     function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
01659     must contain a vendor-specific implementation of this function.
01660 
01661  */
01662 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
01663 {
01664   if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
01665 
01666   SysTick->LOAD  = ticks - 1;                                  /* set reload register */
01667   NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
01668   SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
01669   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
01670                    SysTick_CTRL_TICKINT_Msk   |
01671                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
01672   return (0);                                                  /* Function successful */
01673 }
01674 
01675 #endif
01676 
01677 /*@} end of CMSIS_Core_SysTickFunctions */
01678 
01679 
01680 
01681 /* ##################################### Debug In/Output function ########################################### */
01682 /** \ingroup  CMSIS_Core_FunctionInterface
01683     \defgroup CMSIS_core_DebugFunctions ITM Functions
01684     \brief   Functions that access the ITM debug interface.
01685   @{
01686  */
01687 
01688 extern volatile int32_t ITM_RxBuffer ;                    /*!< External variable to receive characters.                         */
01689 #define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
01690 
01691 
01692 /** \brief  ITM Send Character
01693 
01694     The function transmits a character via the ITM channel 0, and
01695     \li Just returns when no debugger is connected that has booked the output.
01696     \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
01697 
01698     \param [in]     ch  Character to transmit.
01699 
01700     \returns            Character to transmit.
01701  */
01702 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
01703 {
01704   if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
01705       (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
01706   {
01707     while (ITM->PORT[0].u32 == 0);
01708     ITM->PORT[0].u8 = (uint8_t) ch;
01709   }
01710   return (ch);
01711 }
01712 
01713 
01714 /** \brief  ITM Receive Character
01715 
01716     The function inputs a character via the external variable \ref ITM_RxBuffer.
01717 
01718     \return             Received character.
01719     \return         -1  No character pending.
01720  */
01721 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
01722   int32_t ch = -1;                           /* no character available */
01723 
01724   if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
01725     ch = ITM_RxBuffer ;
01726     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
01727   }
01728 
01729   return (ch);
01730 }
01731 
01732 
01733 /** \brief  ITM Check Character
01734 
01735     The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
01736 
01737     \return          0  No character available.
01738     \return          1  Character available.
01739  */
01740 __STATIC_INLINE int32_t ITM_CheckChar (void) {
01741 
01742   if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
01743     return (0);                                 /* no character available */
01744   } else {
01745     return (1);                                 /*    character available */
01746   }
01747 }
01748 
01749 /*@} end of CMSIS_core_DebugFunctions */
01750 
01751 #endif /* __CORE_CM4_H_DEPENDANT */
01752 
01753 #endif /* __CMSIS_GENERIC */
01754 
01755 #ifdef __cplusplus
01756 }
01757 #endif