RCC_Private_Functions
[RCC]

Configures the ADC clock (ADCCLK).

Parameters:

RCC_PCLK2,:

defines the ADC clock divider. This clock is derived from the APB2 clock (PCLK2). This parameter can be one of the following values: RCC_PCLK2_Div2: ADC clock = PCLK2/2 RCC_PCLK2_Div4: ADC clock = PCLK2/4 RCC_PCLK2_Div6: ADC clock = PCLK2/6 RCC_PCLK2_Div8: ADC clock = PCLK2/8

Return values:

None

Definition at line 766 of file stm32f10x_rcc.c.

Adjusts the Internal High Speed oscillator (HSI) calibration value.

Parameters:

HSICalibrationValue,:

specifies the calibration trimming value. This parameter must be a number between 0 and 0x1F.

Return values:

None

Definition at line 334 of file stm32f10x_rcc.c.

Enables or disables the AHB peripheral clock.

Parameters:

RCC_AHBPeriph,:

specifies the AHB peripheral to gates its clock.

For STM32_Connectivity_line_devices, this parameter can be any combination of the following values:

• RCC_AHBPeriph_DMA1
• RCC_AHBPeriph_DMA2
• RCC_AHBPeriph_SRAM
• RCC_AHBPeriph_FLITF
• RCC_AHBPeriph_CRC
• RCC_AHBPeriph_OTG_FS
• RCC_AHBPeriph_ETH_MAC
• RCC_AHBPeriph_ETH_MAC_Tx
• RCC_AHBPeriph_ETH_MAC_Rx

For other_STM32_devices, this parameter can be any combination of the following values:

• RCC_AHBPeriph_DMA1
• RCC_AHBPeriph_DMA2
• RCC_AHBPeriph_SRAM
• RCC_AHBPeriph_FLITF
• RCC_AHBPeriph_CRC
• RCC_AHBPeriph_FSMC
• RCC_AHBPeriph_SDIO

Note:

SRAM and FLITF clock can be disabled only during sleep mode.

Parameters:

NewState,:

new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 1064 of file stm32f10x_rcc.c.

Forces or releases AHB peripheral reset.

Note:

This function applies only to STM32 Connectivity line devices.

Parameters:

RCC_AHBPeriph,:	specifies the AHB peripheral to reset. This parameter can be any combination of the following values: RCC_AHBPeriph_OTG_FS RCC_AHBPeriph_ETH_MAC
NewState,:	new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 1153 of file stm32f10x_rcc.c.

Enables or disables the Low Speed APB (APB1) peripheral clock.

Parameters:

RCC_APB1Periph,:

specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values: RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14

NewState,:

new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 1126 of file stm32f10x_rcc.c.

Forces or releases Low Speed APB (APB1) peripheral reset.

Parameters:

RCC_APB1Periph,:

specifies the APB1 peripheral to reset. This parameter can be any combination of the following values: RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14

NewState,:

new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 1216 of file stm32f10x_rcc.c.

Enables or disables the High Speed APB (APB2) peripheral clock.

Parameters:

RCC_APB2Periph,:

specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values: RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11

NewState,:

new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 1095 of file stm32f10x_rcc.c.

Forces or releases High Speed APB (APB2) peripheral reset.

Parameters:

RCC_APB2Periph,:

specifies the APB2 peripheral to reset. This parameter can be any combination of the following values: RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11

NewState,:

new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 1185 of file stm32f10x_rcc.c.

Forces or releases the Backup domain reset.

Parameters:

NewState,:

new state of the Backup domain reset. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 1237 of file stm32f10x_rcc.c.

Clears the RCC reset flags.

Note:

The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST

Parameters:

None

Return values:

None

Definition at line 1371 of file stm32f10x_rcc.c.

Clears the RCC's interrupt pending bits.

Parameters:

RCC_IT,:

specifies the interrupt pending bit to clear.

For STM32_Connectivity_line_devices, this parameter can be any combination of the following values:

• RCC_IT_LSIRDY: LSI ready interrupt
• RCC_IT_LSERDY: LSE ready interrupt
• RCC_IT_HSIRDY: HSI ready interrupt
• RCC_IT_HSERDY: HSE ready interrupt
• RCC_IT_PLLRDY: PLL ready interrupt
• RCC_IT_PLL2RDY: PLL2 ready interrupt
• RCC_IT_PLL3RDY: PLL3 ready interrupt
• RCC_IT_CSS: Clock Security System interrupt

For other_STM32_devices, this parameter can be any combination of the following values:

• RCC_IT_LSIRDY: LSI ready interrupt
• RCC_IT_LSERDY: LSE ready interrupt
• RCC_IT_HSIRDY: HSI ready interrupt
• RCC_IT_HSERDY: HSE ready interrupt
• RCC_IT_PLLRDY: PLL ready interrupt

• RCC_IT_CSS: Clock Security System interrupt

  Return values:

  None

Definition at line 1448 of file stm32f10x_rcc.c.

Enables or disables the Clock Security System.

Parameters:

NewState,:

new state of the Clock Security System.. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 1250 of file stm32f10x_rcc.c.

Resets the RCC clock configuration to the default reset state.

Parameters:

None

Return values:

None

Definition at line 217 of file stm32f10x_rcc.c.

Returns the frequencies of different on chip clocks.

Parameters:

RCC_Clocks,:

pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies.

Note:

The result of this function could be not correct when using fractional value for HSE crystal.

Return values:

None

Definition at line 908 of file stm32f10x_rcc.c.

Checks whether the specified RCC flag is set or not.

Parameters:

RCC_FLAG,:

specifies the flag to check.

For STM32_Connectivity_line_devices, this parameter can be one of the following values:

• RCC_FLAG_HSIRDY: HSI oscillator clock ready
• RCC_FLAG_HSERDY: HSE oscillator clock ready
• RCC_FLAG_PLLRDY: PLL clock ready
• RCC_FLAG_PLL2RDY: PLL2 clock ready
• RCC_FLAG_PLL3RDY: PLL3 clock ready
• RCC_FLAG_LSERDY: LSE oscillator clock ready
• RCC_FLAG_LSIRDY: LSI oscillator clock ready
• RCC_FLAG_PINRST: Pin reset
• RCC_FLAG_PORRST: POR/PDR reset
• RCC_FLAG_SFTRST: Software reset
• RCC_FLAG_IWDGRST: Independent Watchdog reset
• RCC_FLAG_WWDGRST: Window Watchdog reset
• RCC_FLAG_LPWRRST: Low Power reset

For other_STM32_devices, this parameter can be one of the following values:

• RCC_FLAG_HSIRDY: HSI oscillator clock ready
• RCC_FLAG_HSERDY: HSE oscillator clock ready
• RCC_FLAG_PLLRDY: PLL clock ready
• RCC_FLAG_LSERDY: LSE oscillator clock ready
• RCC_FLAG_LSIRDY: LSI oscillator clock ready
• RCC_FLAG_PINRST: Pin reset
• RCC_FLAG_PORRST: POR/PDR reset
• RCC_FLAG_SFTRST: Software reset
• RCC_FLAG_IWDGRST: Independent Watchdog reset
• RCC_FLAG_WWDGRST: Window Watchdog reset
• RCC_FLAG_LPWRRST: Low Power reset

Return values:

The	new state of RCC_FLAG (SET or RESET).

Definition at line 1326 of file stm32f10x_rcc.c.

Checks whether the specified RCC interrupt has occurred or not.

Parameters:

RCC_IT,:

specifies the RCC interrupt source to check.

For STM32_Connectivity_line_devices, this parameter can be one of the following values:

• RCC_IT_LSIRDY: LSI ready interrupt
• RCC_IT_LSERDY: LSE ready interrupt
• RCC_IT_HSIRDY: HSI ready interrupt
• RCC_IT_HSERDY: HSE ready interrupt
• RCC_IT_PLLRDY: PLL ready interrupt
• RCC_IT_PLL2RDY: PLL2 ready interrupt
• RCC_IT_PLL3RDY: PLL3 ready interrupt
• RCC_IT_CSS: Clock Security System interrupt

For other_STM32_devices, this parameter can be one of the following values:

• RCC_IT_LSIRDY: LSI ready interrupt
• RCC_IT_LSERDY: LSE ready interrupt
• RCC_IT_HSIRDY: HSI ready interrupt
• RCC_IT_HSERDY: HSE ready interrupt
• RCC_IT_PLLRDY: PLL ready interrupt
• RCC_IT_CSS: Clock Security System interrupt

Return values:

The	new state of RCC_IT (SET or RESET).

Definition at line 1402 of file stm32f10x_rcc.c.

Returns the clock source used as system clock.

Parameters:

None

Return values:

The	clock source used as system clock. The returned value can be one of the following: 0x00: HSI used as system clock 0x04: HSE used as system clock 0x08: PLL used as system clock

Definition at line 587 of file stm32f10x_rcc.c.

Configures the AHB clock (HCLK).

Parameters:

RCC_SYSCLK,:

defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values: RCC_SYSCLK_Div1: AHB clock = SYSCLK RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 RCC_SYSCLK_Div512: AHB clock = SYSCLK/512

Return values:

None

Definition at line 608 of file stm32f10x_rcc.c.

Configures the External High Speed oscillator (HSE).

Note:

HSE can not be stopped if it is used directly or through the PLL as system clock.

Parameters:

RCC_HSE,:

specifies the new state of the HSE. This parameter can be one of the following values: RCC_HSE_OFF: HSE oscillator OFF RCC_HSE_ON: HSE oscillator ON RCC_HSE_Bypass: HSE oscillator bypassed with external clock

Return values:

None

Definition at line 270 of file stm32f10x_rcc.c.

Enables or disables the Internal High Speed oscillator (HSI).

Note:

HSI can not be stopped if it is used directly or through the PLL as system clock.

Parameters:

NewState,:

new state of the HSI. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 354 of file stm32f10x_rcc.c.

Configures the I2S2 clock source(I2S2CLK).

Note:

• This function must be called before enabling I2S2 APB clock.
• This function applies only to STM32 Connectivity line devices.

Parameters:

RCC_I2S2CLKSource,:

specifies the I2S2 clock source. This parameter can be one of the following values: RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry

Return values:

None

Definition at line 792 of file stm32f10x_rcc.c.

Configures the I2S3 clock source(I2S2CLK).

Note:

• This function must be called before enabling I2S3 APB clock.
• This function applies only to STM32 Connectivity line devices.

Parameters:

RCC_I2S3CLKSource,:

specifies the I2S3 clock source. This parameter can be one of the following values: RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry

Return values:

None

Definition at line 811 of file stm32f10x_rcc.c.

Enables or disables the specified RCC interrupts.

Parameters:

RCC_IT,:

specifies the RCC interrupt sources to be enabled or disabled.

For STM32_Connectivity_line_devices, this parameter can be any combination of the following values

• RCC_IT_LSIRDY: LSI ready interrupt
• RCC_IT_LSERDY: LSE ready interrupt
• RCC_IT_HSIRDY: HSI ready interrupt
• RCC_IT_HSERDY: HSE ready interrupt
• RCC_IT_PLLRDY: PLL ready interrupt
• RCC_IT_PLL2RDY: PLL2 ready interrupt
• RCC_IT_PLL3RDY: PLL3 ready interrupt

For other_STM32_devices, this parameter can be any combination of the following values

• RCC_IT_LSIRDY: LSI ready interrupt
• RCC_IT_LSERDY: LSE ready interrupt
• RCC_IT_HSIRDY: HSI ready interrupt
• RCC_IT_HSERDY: HSE ready interrupt
• RCC_IT_PLLRDY: PLL ready interrupt

Parameters:

NewState,:

new state of the specified RCC interrupts. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 700 of file stm32f10x_rcc.c.

Configures the External Low Speed oscillator (LSE).

Parameters:

RCC_LSE,:

specifies the new state of the LSE. This parameter can be one of the following values: RCC_LSE_OFF: LSE oscillator OFF RCC_LSE_ON: LSE oscillator ON RCC_LSE_Bypass: LSE oscillator bypassed with external clock

Return values:

None

Definition at line 829 of file stm32f10x_rcc.c.

Enables or disables the Internal Low Speed oscillator (LSI).

Note:

LSI can not be disabled if the IWDG is running.

Parameters:

NewState,:

new state of the LSI. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 862 of file stm32f10x_rcc.c.

Selects the clock source to output on MCO pin.

Parameters:

RCC_MCO,:

specifies the clock source to output.

For STM32_Connectivity_line_devices, this parameter can be one of the following values:

• RCC_MCO_NoClock: No clock selected
• RCC_MCO_SYSCLK: System clock selected
• RCC_MCO_HSI: HSI oscillator clock selected
• RCC_MCO_HSE: HSE oscillator clock selected
• RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
• RCC_MCO_PLL2CLK: PLL2 clock selected
• RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected
• RCC_MCO_XT1: External 3-25 MHz oscillator clock selected
• RCC_MCO_PLL3CLK: PLL3 clock selected

For other_STM32_devices, this parameter can be one of the following values:

• RCC_MCO_NoClock: No clock selected
• RCC_MCO_SYSCLK: System clock selected
• RCC_MCO_HSI: HSI oscillator clock selected
• RCC_MCO_HSE: HSE oscillator clock selected
• RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected

Return values:

None

Definition at line 1282 of file stm32f10x_rcc.c.

Configures the USB OTG FS clock (OTGFSCLK).

This function applies only to STM32 Connectivity line devices.

Parameters:

RCC_OTGFSCLKSource,:

specifies the USB OTG FS clock source. This clock is derived from the PLL output. This parameter can be one of the following values: RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source

Return values:

None

Definition at line 746 of file stm32f10x_rcc.c.

Configures the Low Speed APB clock (PCLK1).

Parameters:

RCC_HCLK,:

defines the APB1 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values: RCC_HCLK_Div1: APB1 clock = HCLK RCC_HCLK_Div2: APB1 clock = HCLK/2 RCC_HCLK_Div4: APB1 clock = HCLK/4 RCC_HCLK_Div8: APB1 clock = HCLK/8 RCC_HCLK_Div16: APB1 clock = HCLK/16

Return values:

None

Definition at line 634 of file stm32f10x_rcc.c.

Configures the High Speed APB clock (PCLK2).

Parameters:

RCC_HCLK,:

defines the APB2 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values: RCC_HCLK_Div1: APB2 clock = HCLK RCC_HCLK_Div2: APB2 clock = HCLK/2 RCC_HCLK_Div4: APB2 clock = HCLK/4 RCC_HCLK_Div8: APB2 clock = HCLK/8 RCC_HCLK_Div16: APB2 clock = HCLK/16

Return values:

None

Definition at line 660 of file stm32f10x_rcc.c.

Enables or disables the PLL2.

Note:

• The PLL2 can not be disabled if it is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as System clock).
• This function applies only to STM32 Connectivity line devices.

Parameters:

NewState,:

new state of the PLL2. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 505 of file stm32f10x_rcc.c.

Configures the PLL2 multiplication factor.

Note:

• This function must be used only when the PLL2 is disabled.
• This function applies only to STM32 Connectivity line devices.

Parameters:

RCC_PLL2Mul,:

specifies the PLL2 multiplication factor. This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}

Return values:

None

Definition at line 479 of file stm32f10x_rcc.c.

Enables or disables the PLL3.

Note:

This function applies only to STM32 Connectivity line devices.

Parameters:

NewState,:

new state of the PLL3. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 546 of file stm32f10x_rcc.c.

Configures the PLL3 multiplication factor.

Note:

• This function must be used only when the PLL3 is disabled.
• This function applies only to STM32 Connectivity line devices.

Parameters:

RCC_PLL3Mul,:

specifies the PLL3 multiplication factor. This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20}

Return values:

None

Definition at line 523 of file stm32f10x_rcc.c.

Enables or disables the PLL.

Note:

The PLL can not be disabled if it is used as system clock.

Parameters:

NewState,:

new state of the PLL. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 401 of file stm32f10x_rcc.c.

Configures the PLL clock source and multiplication factor.

Note:

This function must be used only when the PLL is disabled.

Parameters:

RCC_PLLSource,:

specifies the PLL entry clock source. For STM32_Connectivity_line_devices or STM32_Value_line_devices, this parameter can be one of the following values: RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry For other_STM32_devices, this parameter can be one of the following values: RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry

RCC_PLLMul,:

specifies the PLL multiplication factor. For STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5} For other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16]

Return values:

None

Definition at line 378 of file stm32f10x_rcc.c.

Configures the PREDIV1 division factor.

Note:

• This function must be used only when the PLL is disabled.
• This function applies only to STM32 Connectivity line and Value line devices.

Parameters:

RCC_PREDIV1_Source,:

specifies the PREDIV1 clock source. This parameter can be one of the following values: RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock

Note:

For STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE

Parameters:

RCC_PREDIV1_Div,:

specifies the PREDIV1 clock division factor. This parameter can be RCC_PREDIV1_Divx where x:[1,16]

Return values:

None

Definition at line 426 of file stm32f10x_rcc.c.

Configures the PREDIV2 division factor.

Note:

• This function must be used only when both PLL2 and PLL3 are disabled.
• This function applies only to STM32 Connectivity line devices.

Parameters:

RCC_PREDIV2_Div,:

specifies the PREDIV2 clock division factor. This parameter can be RCC_PREDIV2_Divx where x:[1,16]

Return values:

None

Definition at line 454 of file stm32f10x_rcc.c.

Enables or disables the RTC clock.

Note:

This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.

Parameters:

NewState,:

new state of the RTC clock. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 893 of file stm32f10x_rcc.c.

Configures the RTC clock (RTCCLK).

Note:

Once the RTC clock is selected it can't be changed unless the Backup domain is reset.

Parameters:

RCC_RTCCLKSource,:

specifies the RTC clock source. This parameter can be one of the following values: RCC_RTCCLKSource_LSE: LSE selected as RTC clock RCC_RTCCLKSource_LSI: LSI selected as RTC clock RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock

Return values:

None

Definition at line 879 of file stm32f10x_rcc.c.

Configures the system clock (SYSCLK).

Parameters:

RCC_SYSCLKSource,:

specifies the clock source used as system clock. This parameter can be one of the following values: RCC_SYSCLKSource_HSI: HSI selected as system clock RCC_SYSCLKSource_HSE: HSE selected as system clock RCC_SYSCLKSource_PLLCLK: PLL selected as system clock

Return values:

None

Definition at line 564 of file stm32f10x_rcc.c.

Configures the USB clock (USBCLK).

Parameters:

RCC_USBCLKSource,:

specifies the USB clock source. This clock is derived from the PLL output. This parameter can be one of the following values: RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB clock source RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source

Return values:

None

Definition at line 728 of file stm32f10x_rcc.c.

Waits for HSE start-up.

Parameters:

None

Return values:

An	ErrorStatus enumuration value: SUCCESS: HSE oscillator is stable and ready to use ERROR: HSE oscillator not yet ready

Definition at line 304 of file stm32f10x_rcc.c.